From 5cc0d092640b031b309b18cd5890ab0180f887d6 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Fri, 28 May 2021 09:05:20 -0700 Subject: [PATCH] clk: qcom: clk-cpu-sdxlemur: Don't limit the max register The lucid_5lpe PLL has multiple registers past 0x3C, including the ALPHA_VAL and SSC registers. Since we currently set max_register to 0x3C, this causes read failures on ALPHA_VAL in in alpha_pll_lucid_recalc_rate(). This function ignores the regmap_read() return codes, which results in the frac variable being uninitialized. The CPU PLL doesn't currently use fractional operation, so it should always be zero in HW. But the uninitialized frac variable causes random, small increases to the calculated frequency. Specifying max_register is optional, so just remove it and allow the full range we define in devicetree. Change-Id: I3549c249f2dfbad5c056de584864b0e1a3eeb912 Signed-off-by: Mike Tipton --- drivers/clk/qcom/clk-cpu-sdxlemur.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/clk-cpu-sdxlemur.c b/drivers/clk/qcom/clk-cpu-sdxlemur.c index 5c1e5d7f7c44..04ab88561051 100644 --- a/drivers/clk/qcom/clk-cpu-sdxlemur.c +++ b/drivers/clk/qcom/clk-cpu-sdxlemur.c @@ -361,7 +361,6 @@ static struct regmap_config cpu_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = 0x3C, .fast_io = true, };