From 745cefb9c49f519dc3b1d56681e8047b91dccc26 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Wed, 4 Nov 2020 16:56:52 +0530 Subject: [PATCH] ARM: dts: msm: Add mdp_intf base address in dt This change adds mdp_intf_base address entry for dsi0 and dsi1 on shima, holi and lahaina targets. Change-Id: I56c118884690237e0559e928c4828fe575adf98c --- display/holi-sde-common.dtsi | 5 +++-- display/lahaina-sde-common.dtsi | 10 ++++++---- display/shima-sde-common.dtsi | 10 ++++++---- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index ca2ba7d915f7..3e49e2ac9420 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -173,8 +173,9 @@ cell-index = <0>; frame-threshold-time-us = <1000>; reg = <0x05e94000 0x400>, - <0x05f08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0x05f08000 0x4>, + <0x05e6b800 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 9c009d960baf..66182dd3bc09 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -283,8 +283,9 @@ cell-index = <0>; frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; @@ -322,8 +323,9 @@ cell-index = <1>; frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index 8ed5332e3db4..8e003df778e8 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -241,8 +241,9 @@ cell-index = <0>; frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae6b800 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; @@ -281,8 +282,9 @@ cell-index = <1>; frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae6c000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>;