From 5d0e0faf2a2f7e209a166d376bea34a67da4127f Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 11 Nov 2020 18:30:39 +0530 Subject: [PATCH] ARM: dts: msm: Correct BAM register address on olympic This change will correct the UART nodes BAM base register address on olympic platform. Change-Id: Ib5819fea7c1201ae06bc72b8f080c40f286f5017 --- qcom/sdxlemur-blsp.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi index 997db6b37078..230b20c32b78 100644 --- a/qcom/sdxlemur-blsp.dtsi +++ b/qcom/sdxlemur-blsp.dtsi @@ -294,7 +294,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x82f000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1a_hs>; @@ -330,7 +330,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x82f000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1b_hs>; @@ -366,7 +366,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x830000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2a_hs>; @@ -402,7 +402,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x830000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2b_hs>; @@ -438,7 +438,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x831000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart3_hs>; @@ -474,7 +474,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x832000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart4a_hs>; @@ -510,7 +510,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x832000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart4b_hs>;