From 5d720d8419b04ba991399684e08d2c361d87a8bf Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Thu, 16 Jul 2020 12:14:48 +0530 Subject: [PATCH] ARM: dts: msm: add support for dcvs nodes for holi target Add support for dcvs nodes used to monitor traffic coming from cpu and scale L3 and DDR accordingly. Change-Id: I4fcababa4ea083d59990e92f769a226f6ec008b6 --- qcom/holi.dtsi | 291 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 291 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 698b5decb1ff..aea0a7b038db 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -10,6 +10,9 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + / { model = "Qualcomm Technologies, Inc. Holi"; compatible = "qcom,holi"; @@ -1034,6 +1037,294 @@ #freq-domain-cells = <2>; }; + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devfreq-icc"; + governor = "performance"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@4520300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x4520300 0x300>, <0x4520200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU5>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "performance"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc-ddr"; + governor = "performance"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 710400 MHZ_TO_MBPS( 300, 4) >, + < 940800 MHZ_TO_MBPS( 451, 4) >, + < 1190400 MHZ_TO_MBPS( 547, 4) >, + < 1478400 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS( 1017, 4) >; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 710400 MHZ_TO_MBPS( 300, 4) >, + < 1190400 MHZ_TO_MBPS( 451, 4) >, + < 1478400 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + }; + + cpu6_memlat_cpugrp: qcom,cpu6-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 1017600 MHZ_TO_MBPS( 547, 4) >, + < 1248000 MHZ_TO_MBPS(1017, 4) >, + < 1536000 MHZ_TO_MBPS(1555, 4) >, + < 1804800 MHZ_TO_MBPS(1804, 4) >, + < 2035200 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1248800 MHZ_TO_MBPS( 547, 4) >, + < 1401600 MHZ_TO_MBPS( 768, 4) >, + < 1536000 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1804800 MHZ_TO_MBPS(1804, 4) >, + < 2035200 MHZ_TO_MBPS(2092, 4) >; + }; + }; + tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>;