mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
Merge branch 'pci/ecam' into next
* pci/ecam: PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy PCI: Add MCFG quirks for X-Gene host controller PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller PCI: thunder-pem: Factor out resource lookup PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers PCI: Add MCFG quirks for Qualcomm QDF2432 host controller PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform PCI/ACPI: Check for platform-specific MCFG quirks PCI/ACPI: Extend pci_mcfg_lookup() to return ECAM config accessors arm64: PCI: Exclude ACPI "consumer" resources from host bridge windows arm64: PCI: Manage controller-specific data on per-controller basis arm64: PCI: Search ACPI namespace to ensure ECAM space is reserved arm64: PCI: Add local struct device pointers ACPI: Add acpi_resource_consumer() to find device that claims a resource
This commit is contained in:
Bjorn Helgaas
commit
5e0ad9f686
15 changed files with 719 additions and 67 deletions
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@ -162,3 +162,15 @@ struct pci_ecam_ops pci_generic_ecam_ops = {
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.write = pci_generic_config_write,
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}
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};
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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/* ECAM ops for 32-bit access only (non-compliant) */
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struct pci_ecam_ops pci_32b_ops = {
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.bus_shift = 20,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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}
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};
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#endif
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@ -133,8 +133,8 @@ config PCIE_XILINX
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config PCI_XGENE
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bool "X-Gene PCIe controller"
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depends on ARCH_XGENE
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depends on OF
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depends on ARM64
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depends on OF || (ACPI && PCI_QUIRKS)
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select PCIEPORTBUS
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help
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Say Y here if you want internal PCI support on APM X-Gene SoC.
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@ -240,14 +240,16 @@ config PCIE_QCOM
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config PCI_HOST_THUNDER_PEM
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bool "Cavium Thunder PCIe controller to off-chip devices"
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depends on OF && ARM64
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depends on ARM64
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depends on OF || (ACPI && PCI_QUIRKS)
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
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config PCI_HOST_THUNDER_ECAM
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bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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depends on OF && ARM64
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depends on ARM64
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depends on OF || (ACPI && PCI_QUIRKS)
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select PCI_HOST_COMMON
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help
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Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
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@ -15,7 +15,6 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
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@ -25,11 +24,23 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
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obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
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obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
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obj-$(CONFIG_VMD) += vmd.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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# They contain MCFG quirks to replace the generic ECAM accessors with
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# device-specific ones that are shared with the DT driver.
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# The ACPI driver is generic and should not require driver-specific
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# config options to be enabled, so we always build these drivers on
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# ARM64 and use internal ifdefs to only build the pieces we need
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# depending on whether ACPI, the DT driver, or both are enabled.
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obj-$(CONFIG_ARM64) += pcie-hisi.o
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obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
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obj-$(CONFIG_ARM64) += pci-thunder-pem.o
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obj-$(CONFIG_ARM64) += pci-xgene.o
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@ -14,6 +14,8 @@
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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static void set_val(u32 v, int where, int size, u32 *val)
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{
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int shift = (where & 3) * 8;
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@ -346,7 +348,7 @@ static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static struct pci_ecam_ops pci_thunder_ecam_ops = {
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struct pci_ecam_ops pci_thunder_ecam_ops = {
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.bus_shift = 20,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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@ -355,6 +357,8 @@ static struct pci_ecam_ops pci_thunder_ecam_ops = {
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}
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};
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#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
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static const struct of_device_id thunder_ecam_of_match[] = {
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{ .compatible = "cavium,pci-host-thunder-ecam" },
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{ },
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@ -373,3 +377,6 @@ static struct platform_driver thunder_ecam_driver = {
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.probe = thunder_ecam_probe,
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};
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builtin_platform_driver(thunder_ecam_driver);
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#endif
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#endif
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@ -18,8 +18,12 @@
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#include "../pci.h"
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#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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#define PEM_CFG_WR 0x28
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#define PEM_CFG_RD 0x30
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@ -284,35 +288,16 @@ static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static int thunder_pem_init(struct pci_config_window *cfg)
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static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
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struct resource *res_pem)
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{
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struct device *dev = cfg->parent;
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resource_size_t bar4_start;
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struct resource *res_pem;
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struct thunder_pem_pci *pem_pci;
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struct platform_device *pdev;
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/* Only OF support for now */
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if (!dev->of_node)
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return -EINVAL;
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resource_size_t bar4_start;
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pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
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if (!pem_pci)
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return -ENOMEM;
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pdev = to_platform_device(dev);
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/*
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* The second register range is the PEM bridge to the PCIe
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* bus. It has a different config access method than those
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* devices behind the bridge.
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*/
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res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res_pem) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
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if (!pem_pci->pem_reg_base)
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return -ENOMEM;
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@ -332,9 +317,69 @@ static int thunder_pem_init(struct pci_config_window *cfg)
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return 0;
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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static int thunder_pem_acpi_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct resource *res_pem;
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int ret;
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res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
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if (!res_pem)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "THRX0002", root->segment, res_pem);
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if (ret) {
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dev_err(dev, "can't get rc base address\n");
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return ret;
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}
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return thunder_pem_init(dev, cfg, res_pem);
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}
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struct pci_ecam_ops thunder_pem_ecam_ops = {
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.bus_shift = 24,
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.init = thunder_pem_acpi_init,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = thunder_pem_config_read,
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.write = thunder_pem_config_write,
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}
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};
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#endif
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#ifdef CONFIG_PCI_HOST_THUNDER_PEM
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static int thunder_pem_platform_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res_pem;
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if (!dev->of_node)
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return -EINVAL;
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/*
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* The second register range is the PEM bridge to the PCIe
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* bus. It has a different config access method than those
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* devices behind the bridge.
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*/
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res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res_pem) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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return thunder_pem_init(dev, cfg, res_pem);
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}
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static struct pci_ecam_ops pci_thunder_pem_ops = {
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.bus_shift = 24,
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.init = thunder_pem_init,
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.init = thunder_pem_platform_init,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = thunder_pem_config_read,
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@ -360,3 +405,6 @@ static struct platform_driver thunder_pem_driver = {
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.probe = thunder_pem_probe,
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};
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builtin_platform_driver(thunder_pem_driver);
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#endif
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#endif
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@ -27,6 +27,8 @@
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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@ -64,7 +66,9 @@
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/* PCIe IP version */
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#define XGENE_PCIE_IP_VER_UNKN 0
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#define XGENE_PCIE_IP_VER_1 1
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#define XGENE_PCIE_IP_VER_2 2
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#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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struct xgene_pcie_port {
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struct device_node *node;
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struct device *dev;
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@ -91,13 +95,24 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
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return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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}
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static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
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{
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struct pci_config_window *cfg;
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if (acpi_disabled)
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return (struct xgene_pcie_port *)(bus->sysdata);
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cfg = bus->sysdata;
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return (struct xgene_pcie_port *)(cfg->priv);
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}
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/*
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* When the address bit [17:16] is 2'b01, the Configuration access will be
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* treated as Type 1 and it will be forwarded to external PCIe device.
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*/
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static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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struct xgene_pcie_port *port = pcie_bus_to_port(bus);
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if (bus->number >= (bus->primary + 1))
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return port->cfg_base + AXI_EP_CFG_ACCESS;
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@ -111,7 +126,7 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
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*/
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static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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struct xgene_pcie_port *port = pcie_bus_to_port(bus);
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unsigned int b, d, f;
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u32 rtdid_val = 0;
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@ -158,7 +173,7 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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struct xgene_pcie_port *port = pcie_bus_to_port(bus);
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if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
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PCIBIOS_SUCCESSFUL)
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@ -182,13 +197,103 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
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return PCIBIOS_SUCCESSFUL;
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}
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#endif
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static struct pci_ops xgene_pcie_ops = {
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.map_bus = xgene_pcie_map_bus,
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.read = xgene_pcie_config_read32,
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.write = pci_generic_config_write32,
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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static int xgene_get_csr_resource(struct acpi_device *adev,
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struct resource *res)
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{
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struct device *dev = &adev->dev;
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struct resource_entry *entry;
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struct list_head list;
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unsigned long flags;
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int ret;
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INIT_LIST_HEAD(&list);
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flags = IORESOURCE_MEM;
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ret = acpi_dev_get_resources(adev, &list,
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acpi_dev_filter_resource_type_cb,
|
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(void *) flags);
|
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if (ret < 0) {
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dev_err(dev, "failed to parse _CRS method, error code %d\n",
|
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ret);
|
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return ret;
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}
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if (ret == 0) {
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dev_err(dev, "no IO and memory resources present in _CRS\n");
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return -EINVAL;
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}
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entry = list_first_entry(&list, struct resource_entry, node);
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*res = *entry->res;
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acpi_dev_free_resource_list(&list);
|
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return 0;
|
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}
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static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
|
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struct xgene_pcie_port *port;
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struct resource csr;
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int ret;
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|
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
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if (!port)
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return -ENOMEM;
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ret = xgene_get_csr_resource(adev, &csr);
|
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if (ret) {
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dev_err(dev, "can't get CSR resource\n");
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kfree(port);
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return ret;
|
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}
|
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port->csr_base = devm_ioremap_resource(dev, &csr);
|
||||
if (IS_ERR(port->csr_base)) {
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kfree(port);
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return -ENOMEM;
|
||||
}
|
||||
|
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port->cfg_base = cfg->win;
|
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port->version = ipversion;
|
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|
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cfg->priv = port;
|
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return 0;
|
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}
|
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|
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static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
|
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{
|
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return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
|
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}
|
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|
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struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
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.bus_shift = 16,
|
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.init = xgene_v1_pcie_ecam_init,
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.pci_ops = {
|
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.map_bus = xgene_pcie_map_bus,
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.read = xgene_pcie_config_read32,
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.write = pci_generic_config_write,
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}
|
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};
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|
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static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
|
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{
|
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return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
|
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}
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|
||||
struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
|
||||
.bus_shift = 16,
|
||||
.init = xgene_v2_pcie_ecam_init,
|
||||
.pci_ops = {
|
||||
.map_bus = xgene_pcie_map_bus,
|
||||
.read = xgene_pcie_config_read32,
|
||||
.write = pci_generic_config_write,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_XGENE)
|
||||
static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
|
||||
u32 flags, u64 size)
|
||||
{
|
||||
|
|
@ -521,6 +626,12 @@ static int xgene_pcie_setup(struct xgene_pcie_port *port,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_ops xgene_pcie_ops = {
|
||||
.map_bus = xgene_pcie_map_bus,
|
||||
.read = xgene_pcie_config_read32,
|
||||
.write = pci_generic_config_write32,
|
||||
};
|
||||
|
||||
static int xgene_pcie_probe_bridge(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -591,3 +702,4 @@ static struct platform_driver xgene_pcie_driver = {
|
|||
.probe = xgene_pcie_probe_bridge,
|
||||
};
|
||||
builtin_platform_driver(xgene_pcie_driver);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,7 +18,106 @@
|
|||
#include <linux/of_pci.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-acpi.h>
|
||||
#include <linux/pci-ecam.h>
|
||||
#include <linux/regmap.h>
|
||||
#include "../pci.h"
|
||||
|
||||
#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
|
||||
|
||||
static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
||||
int size, u32 *val)
|
||||
{
|
||||
struct pci_config_window *cfg = bus->sysdata;
|
||||
int dev = PCI_SLOT(devfn);
|
||||
|
||||
if (bus->number == cfg->busr.start) {
|
||||
/* access only one slot on each root port */
|
||||
if (dev > 0)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
else
|
||||
return pci_generic_config_read32(bus, devfn, where,
|
||||
size, val);
|
||||
}
|
||||
|
||||
return pci_generic_config_read(bus, devfn, where, size, val);
|
||||
}
|
||||
|
||||
static int hisi_pcie_acpi_wr_conf(struct pci_bus *bus, u32 devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
struct pci_config_window *cfg = bus->sysdata;
|
||||
int dev = PCI_SLOT(devfn);
|
||||
|
||||
if (bus->number == cfg->busr.start) {
|
||||
/* access only one slot on each root port */
|
||||
if (dev > 0)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
else
|
||||
return pci_generic_config_write32(bus, devfn, where,
|
||||
size, val);
|
||||
}
|
||||
|
||||
return pci_generic_config_write(bus, devfn, where, size, val);
|
||||
}
|
||||
|
||||
static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
|
||||
int where)
|
||||
{
|
||||
struct pci_config_window *cfg = bus->sysdata;
|
||||
void __iomem *reg_base = cfg->priv;
|
||||
|
||||
if (bus->number == cfg->busr.start)
|
||||
return reg_base + where;
|
||||
else
|
||||
return pci_ecam_map_bus(bus, devfn, where);
|
||||
}
|
||||
|
||||
static int hisi_pcie_init(struct pci_config_window *cfg)
|
||||
{
|
||||
struct device *dev = cfg->parent;
|
||||
struct acpi_device *adev = to_acpi_device(dev);
|
||||
struct acpi_pci_root *root = acpi_driver_data(adev);
|
||||
struct resource *res;
|
||||
void __iomem *reg_base;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Retrieve RC base and size from a HISI0081 device with _UID
|
||||
* matching our segment.
|
||||
*/
|
||||
res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
|
||||
if (!res)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't get rc base address\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
reg_base = devm_ioremap(dev, res->start, resource_size(res));
|
||||
if (!reg_base)
|
||||
return -ENOMEM;
|
||||
|
||||
cfg->priv = reg_base;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pci_ecam_ops hisi_pcie_ops = {
|
||||
.bus_shift = 20,
|
||||
.init = hisi_pcie_init,
|
||||
.pci_ops = {
|
||||
.map_bus = hisi_pcie_map_bus,
|
||||
.read = hisi_pcie_acpi_rd_conf,
|
||||
.write = hisi_pcie_acpi_wr_conf,
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HISI
|
||||
|
||||
#include "pcie-designware.h"
|
||||
|
||||
|
|
@ -227,3 +326,5 @@ static struct platform_driver hisi_pcie_driver = {
|
|||
},
|
||||
};
|
||||
builtin_platform_driver(hisi_pcie_driver);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -29,6 +29,82 @@ const u8 pci_acpi_dsm_uuid[] = {
|
|||
0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
|
||||
};
|
||||
|
||||
#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
|
||||
static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
|
||||
{
|
||||
struct device *dev = &adev->dev;
|
||||
struct resource_entry *entry;
|
||||
struct list_head list;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
INIT_LIST_HEAD(&list);
|
||||
flags = IORESOURCE_MEM;
|
||||
ret = acpi_dev_get_resources(adev, &list,
|
||||
acpi_dev_filter_resource_type_cb,
|
||||
(void *) flags);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to parse _CRS method, error code %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret == 0) {
|
||||
dev_err(dev, "no IO and memory resources present in _CRS\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
entry = list_first_entry(&list, struct resource_entry, node);
|
||||
*res = *entry->res;
|
||||
acpi_dev_free_resource_list(&list);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
|
||||
void **retval)
|
||||
{
|
||||
u16 *segment = context;
|
||||
unsigned long long uid;
|
||||
acpi_status status;
|
||||
|
||||
status = acpi_evaluate_integer(handle, "_UID", NULL, &uid);
|
||||
if (ACPI_FAILURE(status) || uid != *segment)
|
||||
return AE_CTRL_DEPTH;
|
||||
|
||||
*(acpi_handle *)retval = handle;
|
||||
return AE_CTRL_TERMINATE;
|
||||
}
|
||||
|
||||
int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
|
||||
struct resource *res)
|
||||
{
|
||||
struct acpi_device *adev;
|
||||
acpi_status status;
|
||||
acpi_handle handle;
|
||||
int ret;
|
||||
|
||||
status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle);
|
||||
if (ACPI_FAILURE(status)) {
|
||||
dev_err(dev, "can't find _HID %s device to locate resources\n",
|
||||
hid);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = acpi_bus_get_device(handle, &adev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = acpi_get_rc_addr(adev, res);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't get resource from %s\n",
|
||||
dev_name(&adev->dev));
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
|
||||
{
|
||||
acpi_status status = AE_NOT_EXIST;
|
||||
|
|
|
|||
|
|
@ -356,4 +356,9 @@ static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
|
||||
int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
|
||||
struct resource *res);
|
||||
#endif
|
||||
|
||||
#endif /* DRIVERS_PCI_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue