A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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arm64/dts:add sx9375 dts for rhodec

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Modify:SAR sensor interrupt power on
and  register configuration

Change-Id: Ic0c8c86acde7c62c9ca835628b49efb2c4b87a6e
Reviewed-on: https://gerrit.mot.com/2131892
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: <xuyanan@wingtech.com>
Reviewed-by: Lijun Chen <chenlj2@motorola.com>
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Reviewed-by: Jiacheng Ou <oujc1@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
xuyanan 2021-12-01 16:01:56 +08:00 • committed by panyq6
commit 5e21f34aa5
1 changed files with 110 additions and 0 deletions
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110
qcom/holi-rhodec-common-overlay.dtsi
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@ -95,6 +95,11 @@
qcom,init-voltage = <3300000>;
};
&pm6125_l9 {
regulator-always-on; //SAR interrupt power
qcom,init-voltage = <1800000>;
};
&tlmm {
cam_pmic_en_default: cam_pmic_en_default {
mux {
@ -440,6 +445,111 @@
};
};
&qupv3_se10_i2c {
status = "ok"
sx937x@2c {
compatible = "Semtech,sx937x";
reg = <0x2c>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&sar_int_default>;
pinctrl-1 = <&sar_int_sleep>;
interrupt-parent = <&tlmm>;
interrupts = <24 0x02>;
interrupt-names = "sx937x_irq";
Semtech,nirq-gpio = <&tlmm 24 0x02>;
//please fix me
cap_vdd-supply = <&pm6125_l9>;
/*use PH4/5/6 as the reference sensor
set it to 0xff if the ref-phases-x is not used*/
Semtech,ref-phases-a = <5>;
Semtech,ref-phases-b = <6>;
Semtech,ref-phases-c = <0xff>;
Semtech,button-flag = <0x1f>;
Semtech,reg-num = <75>;
Semtech,reg-init = <
0x8024 0x7F00
0x4004 0x70
0x8008 0x0
0x4280 0x0
0x8020 0x32
0x8028 0x876 /*AFE_PARAM_PH0*/
0x8034 0x876 /*AFE_PARAM_PH1*/
0x8040 0x876 /*AFE_PARAM_PH2*/
0x804C 0x876 /*AFE_PARAM_PH3*/
0x8058 0x876 /*AFE_PARAM_PH4*/
0x8064 0x876 /*AFE_PARAM_PH5*/
0x8070 0x876 /*AFE_PARAM_PH6*/
0x807C 0x876 /*AFE_PARAM_PH7*/
/*set CS3 to hiz, because it used as IRQ pin*/
0x8030 0xFFD9FF /*REG_AFEPH_PH0, CS4, ANT0, Bottom Left*/
0x803C 0xBFF9FF /*REG_AFEPH_PH1, CS7, ANT1, Bottom right*/
0x8048 0xFFF9FD /*REG_AFEPH_PH2, CS0, ANT4, Top Left*/
0x8054 0xFEF9FF /*REG_AFEPH_PH3, CS5, ANT5, Top Middle*/
0x8060 0xF7F9FF /*REG_AFEPH_PH4, CS6, ANT6, Top Right*/
0x806C 0xFFF97F /*REG_AFEPH_PH5, CS2, ANT0/1_REF, Bottom_Ref*/
0x8078 0xBFF9FF /*REG_AFEPH_PH6, CS1, ANT4 REF, Top_Left*/
0x8084 0xFFF9EF /*REG_AFEPH_PH7, NOT USE*/
0x802C 0x0
0x8038 0x0
0x8044 0x0
0x8050 0x0
0x805C 0x0
0x8068 0x0
0x8074 0x0
0x8080 0x0
0x8098 0x6942
0x80B8 0x6942
0x80D8 0x5A39
0x80F8 0x3F3F
0x8118 0x3F3F
0x8138 0xFF
0x8158 0xFF
0x8178 0x0
0x80A0 0x0
0x80C0 0x0
0x80E0 0x0
0x8100 0x0
0x8120 0x0
0x8140 0x0
0x8160 0x0
0x8180 0x0
0x8188 0x8000015
0x818C 0x8000016
0x8190 0x0
0x8194 0x0
0x8090 0x40CF3000
0x80B0 0x7FB33000
0x80D0 0x40CD3000
0x80F0 0x68B03000
0x8110 0x30273000
0x8130 0x2AD67000
0x8150 0x2AD67000
0x8170 0x2AD67000
0x8088 0x300000
0x80A8 0x300000
0x80C8 0x300000
0x80E8 0x300000
0x8108 0x300000
0x8128 0x600000
0x8148 0x600000
0x8168 0x300000
0x808C 0x60200060
0x80AC 0x60200060
0x80CC 0x60200060
0x80EC 0x60200060
0x810C 0x60200060
0x812C 0x60200018
0x814C 0x60200018
0x816C 0x60200018
0x8024 0x7F7F
0x4280 0xF
>;
status = "ok"
};
};
&qusb_phy0 {
qcom,qusb-phy-init-seq =
/* <value reg_offset> */