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ARM: dts: msm: Mark GCC PCIE clocks as protected in YUPIK

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GCC PCIE clocks does not need to be controlled from HLOS in
YUPIK, hence mark them as protected and remove support for
PCIE GDSC's.

Change-Id: I6111c9b37d1a90f4552560334fb5e963778b2921
This commit is contained in:
Jagadeesh Kona 2021-01-07 12:15:03 +05:30
commit 5e41344a66
2 changed files with 15 additions and 16 deletions
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2
qcom/yupik-rumi.dtsi
View file

@ -169,8 +169,6 @@
&gcc {
clocks = <&bi_tcxo>,
<&sleep_clk>,
<&pcie_0_pipe_clk>,
<&pcie_1_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};

29
qcom/yupik.dtsi
View file

@ -900,14 +900,25 @@
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie_0_pipe_clk>,
<&pcie_1_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"sleep_clk",
"pcie_0_pipe_clk",
"pcie_1_pipe_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE0_PHY_RCHNG_CLK>, <GCC_PCIE1_PHY_RCHNG_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK_SRC>, <GCC_PCIE_0_PIPE_CLK>,
<GCC_PCIE_0_PIPE_CLK_SRC>, <GCC_PCIE_0_SLV_AXI_CLK>,
<GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <GCC_PCIE_1_AUX_CLK>,
<GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>,
<GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -2754,16 +2765,6 @@
#include "yupik-regulators.dtsi"
#include "yupik-thermal.dtsi"
&gcc_pcie_0_gdsc {
qcom,support-hw-trigger;
status = "ok"
};
&gcc_pcie_1_gdsc {
qcom,support-hw-trigger;
status = "ok"
};
&gcc_ufs_phy_gdsc {
qcom,support-hw-trigger;
status = "ok"