From 5e6ced2ea349ab0393b0835385212aab7806dcbe Mon Sep 17 00:00:00 2001 From: Leo Chang Date: Thu, 15 Sep 2016 13:32:05 -0700 Subject: [PATCH] [wifi 3.0] add firmware common files add firmware common files into separated project. Included firmware common htt and wmi. Included hardware common header files for napier and hawkeye Change-Id: I8724057eb9aa21f7614231d1943177e780ed16b1 CRs-fixed: 1074308 --- fw/a_osapi.h | 71 + fw/a_usb_defs.h | 97 + fw/apb_athr_wlan_map.h | 59 + fw/athdefs.h | 83 + fw/athendpack.h | 35 + fw/bin_sig.h | 44 + fw/bmi_msg.h | 385 + fw/cepci.h | 49 +- fw/dbglog.h | 88 +- fw/dbglog_id.h | 118 +- fw/efuse_reg.h | 154 + fw/enet.h | 149 + fw/epping_test.h | 124 + fw/htc.h | 422 + fw/htc_services.h | 100 + fw/htt.h | 8106 +++---- fw/htt_common.h | 93 +- fw/htt_isoc.h | 1244 + fw/ip_prot.h | 58 + fw/ipv4.h | 55 + fw/ol_fw_tx_dbg.h | 184 + fw/rtc_soc_reg.h | 1966 ++ fw/targaddrs.h | 551 +- fw/targcfg.h | 30 +- fw/wal_rx_desc.h | 159 +- fw/wlan_defs.h | 1083 +- fw/wlan_module_ids.h | 164 +- fw/wlan_tgt_def_config.h | 257 + fw/wlan_tgt_def_config_hl.h | 289 + fw/wmi.h | 134 +- fw/wmi_services.h | 468 +- fw/wmi_tlv_defs.h | 4608 ++-- fw/wmi_tlv_helper.h | 80 +- fw/wmi_unified.h | 23263 ++++++++++--------- fw/wmi_version.h | 5 +- fw/wmix.h | 111 +- hw/qca6290/v1/HALcomdef.h | 131 + hw/qca6290/v1/HALhwio.h | 490 + hw/qca6290/v1/buffer_addr_info.h | 283 + hw/qca6290/v1/ce_src_desc.h | 360 + hw/qca6290/v1/ce_stat_desc.h | 330 + hw/qca6290/v1/com_dtypes.h | 300 + hw/qca6290/v1/lithium_top_reg.h | 38 + hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h | 39 + hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h | 6821 ++++++ hw/qca6290/v1/msmhwio.h | 51 + hw/qca6290/v1/reo_destination_ring.h | 730 + hw/qca6290/v1/reo_entrance_ring.h | 722 + hw/qca6290/v1/reo_get_queue_stats.h | 305 + hw/qca6290/v1/reo_get_queue_stats_status.h | 868 + hw/qca6290/v1/reo_reg_seq_hwiobase.h | 39 + hw/qca6290/v1/reo_reg_seq_hwioreg.h | 8639 +++++++ hw/qca6290/v1/rx_attention.h | 1168 + hw/qca6290/v1/rx_mpdu_desc_info.h | 466 + hw/qca6290/v1/rx_mpdu_details.h | 87 + hw/qca6290/v1/rx_mpdu_end.h | 753 + hw/qca6290/v1/rx_mpdu_info.h | 2871 +++ hw/qca6290/v1/rx_mpdu_link_ptr.h | 61 + hw/qca6290/v1/rx_mpdu_start.h | 158 + hw/qca6290/v1/rx_msdu_desc_info.h | 514 + hw/qca6290/v1/rx_msdu_details.h | 88 + hw/qca6290/v1/rx_msdu_end.h | 1238 + hw/qca6290/v1/rx_msdu_link.h | 345 + hw/qca6290/v1/rx_msdu_start.h | 1081 + hw/qca6290/v1/rx_reo_queue.h | 1662 ++ hw/qca6290/v1/rx_reo_queue_ext.h | 360 + hw/qca6290/v1/rxpt_classify_info.h | 245 + hw/qca6290/v1/seq_hwio.h | 121 + hw/qca6290/v1/sw_xml_headers.h | 365 + hw/qca6290/v1/tcl_data_cmd.h | 890 + hw/qca6290/v1/tcl_gse_cmd.h | 408 + hw/qca6290/v1/tcl_status_ring.h | 414 + hw/qca6290/v1/tlv_hdr.h | 82 + hw/qca6290/v1/tlv_tag_def.h | 453 + hw/qca6290/v1/tx_msdu_extension.h | 827 + hw/qca6290/v1/tx_rate_stats_info.h | 458 + hw/qca6290/v1/uniform_descriptor_header.h | 229 + hw/qca6290/v1/uniform_reo_cmd_header.h | 141 + hw/qca6290/v1/uniform_reo_status_header.h | 250 + hw/qca6290/v1/wbm_buffer_ring.h | 72 + hw/qca6290/v1/wbm_link_descriptor_ring.h | 72 + hw/qca6290/v1/wbm_reg_seq_hwiobase.h | 39 + hw/qca6290/v1/wbm_reg_seq_hwioreg.h | 12394 ++++++++++ hw/qca6290/v1/wbm_release_ring.h | 1418 ++ hw/qca6290/v1/wcss_seq_hwiobase.h | 731 + hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h | 70 + hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h | 2361 ++ hw/qca6290/v1/wfss_pmm_base_struct.h | 52 + hw/qca8074/v1/HALcomdef.h | 131 + hw/qca8074/v1/HALhwio.h | 490 + hw/qca8074/v1/buffer_addr_info.h | 283 + hw/qca8074/v1/ce_src_desc.h | 360 + hw/qca8074/v1/ce_stat_desc.h | 330 + hw/qca8074/v1/com_dtypes.h | 300 + hw/qca8074/v1/lithium_top_reg.h | 38 + hw/qca8074/v1/mac_tcl_reg_seq_hwiobase.h | 39 + hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h | 6821 ++++++ hw/qca8074/v1/msmhwio.h | 51 + hw/qca8074/v1/reo_destination_ring.h | 730 + hw/qca8074/v1/reo_entrance_ring.h | 722 + hw/qca8074/v1/reo_get_queue_stats.h | 305 + hw/qca8074/v1/reo_get_queue_stats_status.h | 868 + hw/qca8074/v1/reo_reg_seq_hwiobase.h | 39 + hw/qca8074/v1/reo_reg_seq_hwioreg.h | 8639 +++++++ hw/qca8074/v1/rx_attention.h | 1168 + hw/qca8074/v1/rx_mpdu_desc_info.h | 466 + hw/qca8074/v1/rx_mpdu_details.h | 87 + hw/qca8074/v1/rx_mpdu_end.h | 753 + hw/qca8074/v1/rx_mpdu_info.h | 2871 +++ hw/qca8074/v1/rx_mpdu_link_ptr.h | 61 + hw/qca8074/v1/rx_mpdu_start.h | 158 + hw/qca8074/v1/rx_msdu_desc_info.h | 514 + hw/qca8074/v1/rx_msdu_details.h | 88 + hw/qca8074/v1/rx_msdu_end.h | 1238 + hw/qca8074/v1/rx_msdu_link.h | 345 + hw/qca8074/v1/rx_msdu_start.h | 1081 + hw/qca8074/v1/rx_reo_queue.h | 1662 ++ hw/qca8074/v1/rx_reo_queue_ext.h | 360 + hw/qca8074/v1/rxpt_classify_info.h | 245 + hw/qca8074/v1/seq_hwio.h | 121 + hw/qca8074/v1/sw_xml_headers.h | 365 + hw/qca8074/v1/tcl_data_cmd.h | 890 + hw/qca8074/v1/tcl_gse_cmd.h | 408 + hw/qca8074/v1/tcl_status_ring.h | 414 + hw/qca8074/v1/tlv_hdr.h | 82 + hw/qca8074/v1/tlv_tag_def.h | 453 + hw/qca8074/v1/tx_msdu_extension.h | 827 + hw/qca8074/v1/tx_rate_stats_info.h | 458 + hw/qca8074/v1/uniform_descriptor_header.h | 229 + hw/qca8074/v1/uniform_reo_cmd_header.h | 141 + hw/qca8074/v1/uniform_reo_status_header.h | 250 + hw/qca8074/v1/wbm_buffer_ring.h | 72 + hw/qca8074/v1/wbm_link_descriptor_ring.h | 72 + hw/qca8074/v1/wbm_reg_seq_hwiobase.h | 39 + hw/qca8074/v1/wbm_reg_seq_hwioreg.h | 12394 ++++++++++ hw/qca8074/v1/wbm_release_ring.h | 1418 ++ hw/qca8074/v1/wcss_seq_hwiobase.h | 731 + hw/qca8074/v1/wfss_ce_reg_seq_hwiobase.h | 70 + hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h | 2361 ++ hw/qca8074/v1/wfss_pmm_base_struct.h | 52 + 140 files changed, 132604 insertions(+), 18462 deletions(-) create mode 100644 fw/a_osapi.h create mode 100644 fw/a_usb_defs.h create mode 100644 fw/apb_athr_wlan_map.h create mode 100644 fw/athdefs.h create mode 100644 fw/athendpack.h create mode 100644 fw/bin_sig.h create mode 100644 fw/bmi_msg.h mode change 100755 => 100644 fw/cepci.h mode change 100755 => 100644 fw/dbglog.h mode change 100755 => 100644 fw/dbglog_id.h create mode 100644 fw/efuse_reg.h create mode 100644 fw/enet.h create mode 100644 fw/epping_test.h create mode 100644 fw/htc.h create mode 100644 fw/htc_services.h mode change 100755 => 100644 fw/htt.h mode change 100755 => 100644 fw/htt_common.h create mode 100644 fw/htt_isoc.h create mode 100644 fw/ip_prot.h create mode 100644 fw/ipv4.h create mode 100644 fw/ol_fw_tx_dbg.h create mode 100644 fw/rtc_soc_reg.h mode change 100755 => 100644 fw/targaddrs.h mode change 100755 => 100644 fw/targcfg.h mode change 100755 => 100644 fw/wal_rx_desc.h mode change 100755 => 100644 fw/wlan_defs.h mode change 100755 => 100644 fw/wlan_module_ids.h create mode 100644 fw/wlan_tgt_def_config.h create mode 100644 fw/wlan_tgt_def_config_hl.h mode change 100755 => 100644 fw/wmi.h mode change 100755 => 100644 fw/wmi_services.h mode change 100755 => 100644 fw/wmi_tlv_defs.h mode change 100755 => 100644 fw/wmi_tlv_helper.h mode change 100755 => 100644 fw/wmi_unified.h mode change 100755 => 100644 fw/wmi_version.h mode change 100755 => 100644 fw/wmix.h create mode 100644 hw/qca6290/v1/HALcomdef.h create mode 100644 hw/qca6290/v1/HALhwio.h create mode 100644 hw/qca6290/v1/buffer_addr_info.h create mode 100644 hw/qca6290/v1/ce_src_desc.h create mode 100644 hw/qca6290/v1/ce_stat_desc.h create mode 100644 hw/qca6290/v1/com_dtypes.h create mode 100644 hw/qca6290/v1/lithium_top_reg.h create mode 100644 hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h create mode 100644 hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h create mode 100644 hw/qca6290/v1/msmhwio.h create mode 100644 hw/qca6290/v1/reo_destination_ring.h create mode 100644 hw/qca6290/v1/reo_entrance_ring.h create mode 100644 hw/qca6290/v1/reo_get_queue_stats.h create mode 100644 hw/qca6290/v1/reo_get_queue_stats_status.h create mode 100644 hw/qca6290/v1/reo_reg_seq_hwiobase.h create mode 100644 hw/qca6290/v1/reo_reg_seq_hwioreg.h create mode 100644 hw/qca6290/v1/rx_attention.h create mode 100644 hw/qca6290/v1/rx_mpdu_desc_info.h create mode 100644 hw/qca6290/v1/rx_mpdu_details.h create mode 100644 hw/qca6290/v1/rx_mpdu_end.h create mode 100644 hw/qca6290/v1/rx_mpdu_info.h create mode 100644 hw/qca6290/v1/rx_mpdu_link_ptr.h create mode 100644 hw/qca6290/v1/rx_mpdu_start.h create mode 100644 hw/qca6290/v1/rx_msdu_desc_info.h create mode 100644 hw/qca6290/v1/rx_msdu_details.h create mode 100644 hw/qca6290/v1/rx_msdu_end.h create mode 100644 hw/qca6290/v1/rx_msdu_link.h create mode 100644 hw/qca6290/v1/rx_msdu_start.h create mode 100644 hw/qca6290/v1/rx_reo_queue.h create mode 100644 hw/qca6290/v1/rx_reo_queue_ext.h create mode 100644 hw/qca6290/v1/rxpt_classify_info.h create mode 100644 hw/qca6290/v1/seq_hwio.h create mode 100644 hw/qca6290/v1/sw_xml_headers.h create mode 100644 hw/qca6290/v1/tcl_data_cmd.h create mode 100644 hw/qca6290/v1/tcl_gse_cmd.h create mode 100644 hw/qca6290/v1/tcl_status_ring.h create mode 100644 hw/qca6290/v1/tlv_hdr.h create mode 100644 hw/qca6290/v1/tlv_tag_def.h create mode 100644 hw/qca6290/v1/tx_msdu_extension.h create mode 100644 hw/qca6290/v1/tx_rate_stats_info.h create mode 100644 hw/qca6290/v1/uniform_descriptor_header.h create mode 100644 hw/qca6290/v1/uniform_reo_cmd_header.h create mode 100644 hw/qca6290/v1/uniform_reo_status_header.h create mode 100644 hw/qca6290/v1/wbm_buffer_ring.h create mode 100644 hw/qca6290/v1/wbm_link_descriptor_ring.h create mode 100644 hw/qca6290/v1/wbm_reg_seq_hwiobase.h create mode 100644 hw/qca6290/v1/wbm_reg_seq_hwioreg.h create mode 100644 hw/qca6290/v1/wbm_release_ring.h create mode 100644 hw/qca6290/v1/wcss_seq_hwiobase.h create mode 100644 hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h create mode 100644 hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h create mode 100644 hw/qca6290/v1/wfss_pmm_base_struct.h create mode 100644 hw/qca8074/v1/HALcomdef.h create mode 100644 hw/qca8074/v1/HALhwio.h create mode 100644 hw/qca8074/v1/buffer_addr_info.h create mode 100644 hw/qca8074/v1/ce_src_desc.h create mode 100644 hw/qca8074/v1/ce_stat_desc.h create mode 100644 hw/qca8074/v1/com_dtypes.h create mode 100644 hw/qca8074/v1/lithium_top_reg.h create mode 100644 hw/qca8074/v1/mac_tcl_reg_seq_hwiobase.h create mode 100644 hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h create mode 100644 hw/qca8074/v1/msmhwio.h create mode 100644 hw/qca8074/v1/reo_destination_ring.h create mode 100644 hw/qca8074/v1/reo_entrance_ring.h create mode 100644 hw/qca8074/v1/reo_get_queue_stats.h create mode 100644 hw/qca8074/v1/reo_get_queue_stats_status.h create mode 100644 hw/qca8074/v1/reo_reg_seq_hwiobase.h create mode 100644 hw/qca8074/v1/reo_reg_seq_hwioreg.h create mode 100644 hw/qca8074/v1/rx_attention.h create mode 100644 hw/qca8074/v1/rx_mpdu_desc_info.h create mode 100644 hw/qca8074/v1/rx_mpdu_details.h create mode 100644 hw/qca8074/v1/rx_mpdu_end.h create mode 100644 hw/qca8074/v1/rx_mpdu_info.h create mode 100644 hw/qca8074/v1/rx_mpdu_link_ptr.h create mode 100644 hw/qca8074/v1/rx_mpdu_start.h create mode 100644 hw/qca8074/v1/rx_msdu_desc_info.h create mode 100644 hw/qca8074/v1/rx_msdu_details.h create mode 100644 hw/qca8074/v1/rx_msdu_end.h create mode 100644 hw/qca8074/v1/rx_msdu_link.h create mode 100644 hw/qca8074/v1/rx_msdu_start.h create mode 100644 hw/qca8074/v1/rx_reo_queue.h create mode 100644 hw/qca8074/v1/rx_reo_queue_ext.h create mode 100644 hw/qca8074/v1/rxpt_classify_info.h create mode 100644 hw/qca8074/v1/seq_hwio.h create mode 100644 hw/qca8074/v1/sw_xml_headers.h create mode 100644 hw/qca8074/v1/tcl_data_cmd.h create mode 100644 hw/qca8074/v1/tcl_gse_cmd.h create mode 100644 hw/qca8074/v1/tcl_status_ring.h create mode 100644 hw/qca8074/v1/tlv_hdr.h create mode 100644 hw/qca8074/v1/tlv_tag_def.h create mode 100644 hw/qca8074/v1/tx_msdu_extension.h create mode 100644 hw/qca8074/v1/tx_rate_stats_info.h create mode 100644 hw/qca8074/v1/uniform_descriptor_header.h create mode 100644 hw/qca8074/v1/uniform_reo_cmd_header.h create mode 100644 hw/qca8074/v1/uniform_reo_status_header.h create mode 100644 hw/qca8074/v1/wbm_buffer_ring.h create mode 100644 hw/qca8074/v1/wbm_link_descriptor_ring.h create mode 100644 hw/qca8074/v1/wbm_reg_seq_hwiobase.h create mode 100644 hw/qca8074/v1/wbm_reg_seq_hwioreg.h create mode 100644 hw/qca8074/v1/wbm_release_ring.h create mode 100644 hw/qca8074/v1/wcss_seq_hwiobase.h create mode 100644 hw/qca8074/v1/wfss_ce_reg_seq_hwiobase.h create mode 100644 hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h create mode 100644 hw/qca8074/v1/wfss_pmm_base_struct.h diff --git a/fw/a_osapi.h b/fw/a_osapi.h new file mode 100644 index 000000000000..0eabec0a6244 --- /dev/null +++ b/fw/a_osapi.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +/* ============================================================================== */ +/* This file contains the definitions of the basic atheros data types. */ +/* It is used to map the data types in atheros files to a platform specific */ +/* type. */ +/* */ +/* Author(s): ="Atheros" */ +/* ============================================================================== */ +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "osapi_linux.h" +#endif + +/*=== the following primitives have the same definition for all platforms ===*/ + +#define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \ + typedef char assertion_name[(predicate) ? 1 : -1] + +/* + * If N is a power of 2, then N and N-1 are orthogonal + * (N-1 has all the least-significant bits set which are zero in N) + * so N ^ (N-1) = (N << 1) - 1 + */ +#define A_COMPILE_TIME_ASSERT_IS_PWR2(assertion_name, value) \ + A_COMPILE_TIME_ASSERT (assertion_name, \ + (((value) ^ ((value)-1)) == ((value) << 1) - 1)) + +#ifndef __ubicom32__ +#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \ + os_malloc_CONSISTENT(osdev, size, pa, context, retry) +#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \ + OS_FREE_CONSISTENT(osdev, size, vaddr, pa, context) +#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context) +#else +#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \ + os_malloc_NONCONSISTENT(osdev, size, pa, context, retry) +#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \ + OS_FREE_NONCONSISTENT(osdev, size, vaddr, pa, context) +#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context) \ + OS_SYNC_SINGLE(osdev, pa, size, dir, context) +#endif /* ubicom32 */ + +#endif /* _OSAPI_H_ */ diff --git a/fw/a_usb_defs.h b/fw/a_usb_defs.h new file mode 100644 index 000000000000..1664a0a15859 --- /dev/null +++ b/fw/a_usb_defs.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ +/* + * Shared USB definitions + * + * + * + * + */ + +#ifndef __A_USB_DEFS_H__ +#define __A_USB_DEFS_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* USB endpoint definitions */ + +#define USB_EP_ADDR_APP_CTRL_IN 0x81 +#define USB_EP_ADDR_APP_DATA_IN 0x82 +#define USB_EP_ADDR_APP_DATA2_IN 0x83 +#define USB_EP_ADDR_APP_INT_IN 0x84 + +#define USB_EP_ADDR_APP_CTRL_OUT 0x01 +#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02 +#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03 +#define USB_EP_ADDR_APP_DATA_HP_OUT 0x04 + +#define USB_CONTROL_REQ_SEND_BMI_CMD 1 +#define USB_CONTROL_REQ_RECV_BMI_RESP 2 +#define USB_CONTROL_REQ_DIAG_CMD 3 +#define USB_CONTROL_REQ_DIAG_RESP 4 + +/* #define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64 */ +#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 252 + +#define HIF_BMI_MAX_TRANSFER_SIZE USB_CONTROL_MAX_BMI_TRANSFER_SIZE + +/* 512 Bytes Maxp for High Speed for BULK EP */ +#define USB_HS_BULK_MAXP_SIZE 0x200 +/* 64 Bytes Maxp for Full Speed for BULK EP */ +#define USB_FS_BULK_MAXP_SIZE 0x40 + +/* diagnostic command defnitions */ +#define USB_CTRL_DIAG_CC_READ 0 +#define USB_CTRL_DIAG_CC_WRITE 1 +#define USB_CTRL_DIAG_CC_WARM_RESET 2 + +typedef PREPACK struct { + A_UINT32 Cmd; + A_UINT32 Address; + A_UINT32 Value; + A_UINT32 _pad[1]; +} POSTPACK USB_CTRL_DIAG_CMD_WRITE; + +typedef PREPACK struct { + A_UINT32 Cmd; + A_UINT32 Address; +} POSTPACK USB_CTRL_DIAG_CMD_READ; + +typedef PREPACK struct { + A_UINT32 ReadValue; +} POSTPACK USB_CTRL_DIAG_RESP_READ; + +#define USB_CTRL_MAX_DIAG_CMD_SIZE (sizeof(USB_CTRL_DIAG_CMD_WRITE)) +#define USB_CTRL_MAX_DIAG_RESP_SIZE (sizeof(USB_CTRL_DIAG_RESP_READ)) + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif diff --git a/fw/apb_athr_wlan_map.h b/fw/apb_athr_wlan_map.h new file mode 100644 index 000000000000..3e48543f0de2 --- /dev/null +++ b/fw/apb_athr_wlan_map.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef _APB_ATHR_WLAN_MAP_H_ +#define _APB_ATHR_WLAN_MAP_H_ + +#define RTC_SOC_BASE_ADDRESS 0x00004000 +#define RTC_WMAC_BASE_ADDRESS 0x00005000 +#define MAC_COEX_BASE_ADDRESS 0x00006000 +#define BT_COEX_BASE_ADDRESS 0x00007000 +#define SOC_PCIE_BASE_ADDRESS 0x00008000 +#define SOC_CORE_BASE_ADDRESS 0x00009000 +#define WLAN_UART_BASE_ADDRESS 0x0000c000 +#define WLAN_SI_BASE_ADDRESS 0x00010000 +#define WLAN_GPIO_BASE_ADDRESS 0x00014000 +#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define WLAN_MAC_BASE_ADDRESS 0x00020000 +#define EFUSE_BASE_ADDRESS 0x00030000 +#define FPGA_REG_BASE_ADDRESS 0x00039000 +#define WLAN_UART2_BASE_ADDRESS 0x00054c00 +#define CE_WRAPPER_BASE_ADDRESS 0x00057000 +#define CE0_BASE_ADDRESS 0x00057400 +#define CE1_BASE_ADDRESS 0x00057800 +#define CE2_BASE_ADDRESS 0x00057c00 +#define CE3_BASE_ADDRESS 0x00058000 +#define CE4_BASE_ADDRESS 0x00058400 +#define CE5_BASE_ADDRESS 0x00058800 +#define CE6_BASE_ADDRESS 0x00058c00 +#define CE7_BASE_ADDRESS 0x00059000 +#define DBI_BASE_ADDRESS 0x00060000 +#define WLAN_MBOX_BASE_ADDRESS 0x00068000 +#define WLAN_DBG_UART_BASE_ADDRESS 0x00069000 +#define USB_DMA_BASE_ADDRESS 0x0006a000 + +#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */ diff --git a/fw/athdefs.h b/fw/athdefs.h new file mode 100644 index 000000000000..d1ee6cb6ab0b --- /dev/null +++ b/fw/athdefs.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la + ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED, /* Object was consumed */ + A_CLONE, /* The buffer is cloned */ + A_USB_ERROR, /* Rome USB Target error */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#endif /* __ATHDEFS_H__ */ diff --git a/fw/athendpack.h b/fw/athendpack.h new file mode 100644 index 000000000000..977909eb6e9f --- /dev/null +++ b/fw/athendpack.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ diff --git a/fw/bin_sig.h b/fw/bin_sig.h new file mode 100644 index 000000000000..d4f351632325 --- /dev/null +++ b/fw/bin_sig.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2012,2014, 2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef BIN_SIGN_H_ +#define BIN_SIGN_H_ + + +/* Signed binary MetaData */ +typedef struct { + unsigned int magic_num; + unsigned int total_len; + unsigned int rampatch_len; + unsigned int product_id; + unsigned int patch_ver; + unsigned short sign_format_ver; + unsigned short sign_algorithm; + unsigned char reserved[8]; +} SIGN_HEADER_T; + +#endif /* BIN_SIGN_H_ */ diff --git a/fw/bmi_msg.h b/fw/bmi_msg.h new file mode 100644 index 000000000000..be38713e8c96 --- /dev/null +++ b/fw/bmi_msg.h @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 +/* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 +/* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 +/* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ +/* + * Capbility to write "segmented files" is provided for two reasons + * 1) backwards compatibility for certain situations where Hosts + * have limited flexibility + * 2) because it's darn convenient. + * + * A segmented file consists of a file header followed by an arbitrary number + * of segments. Each segment contains segment metadata -- a Target address and + * a length -- followed by "length" bytes of data. A segmented file ends with + * a segment that specifies length=BMI_SGMTFILE_DONE. When a segmented file + * is sent to the Target, firmware writes each segment to the specified address. + * + * Special cases: + * 1) If a segment's metadata indicates length=BMI_SGMTFILE_EXEC, then the + * specified address is used as a function entry point for a brief function + * with prototype "(void *)(void)". That function is called immediately. + * After execution of the function completes, firmware continues with the + * next segment. No data is expected when length=BMI_SGMTFILE_EXEC. + * + * 2) If a segment's metadata indicates length=BMI_SGMTFILE_BEGINADDR, then + * the specified address is established as the application start address + * so that a subsequent BMI_DONE jumps there. + * + * 3) If a segment's metadata indicates length=BMI_SGMTFILE_BDDATA, then + * the specified address is used as the (possibly compressed) length of board + * data, which is loaded into the proper Target address as specified by + * hi_board_data. In addition, the hi_board_data_initialized flag is set. + * + * A segmented file is sent to the Target using a sequence of 1 or more + * BMI_WRITE_MEMORY commands. The first such command must have + * address=BMI_SEGMENTED_WRITE_ADDR. Subsequent BMI_WRITE_MEMORY commands + * can use an arbitrary address. In each BMI_WRITE_MEMORY command, the + * length specifies the number of data bytes transmitted (except for the + * special cases listed above). + * + * Alternatively, a segmented file may be sent to the Target using a + * BMI_LZ_STREAM_START command with address=BMI_SEGMENTED_WRITE_ADDR + * followed by a series of BMI_LZ_DATA commands that each send the next portion + * of the segmented file. + * + * The data segments may be lz77 compressed. In this case, the segmented file + * header flag, BMI_SGMTFILE_FLAG_COMPRESS, must be set. Note that segmented + * file METAdata is never compressed; only the data segments themselves are + * compressed. There is no way to mix compressed and uncompressed data segments + * in a single segmented file. Compressed (or uncompressed) segments are handled + * by both BMI_WRITE_MEMORY and by BMI_LZ_DATA commands. (Compression is an + * attribute of the segmented file rather than of the command used to transmit + * it.) + */ +#define BMI_SEGMENTED_WRITE_ADDR 0x1234 + +/* File header for a segmented file */ +struct bmi_segmented_file_header { + A_UINT32 magic_num; + A_UINT32 file_flags; +}; +#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */ +#define BMI_SGMTFILE_FLAG_COMPRESS 1 + +/* Metadata for a segmented file segment */ +struct bmi_segmented_metadata { + A_UINT32 addr; + A_UINT32 length; +}; +/* Special values for bmi_segmented_metadata.length (all have high bit set) */ +#define BMI_SGMTFILE_DONE 0xffffffff /* end of segmented data */ +#define BMI_SGMTFILE_BDDATA 0xfffffffe /* Board Data segment */ +#define BMI_SGMTFILE_BEGINADDR 0xfffffffd /* set beginning address */ +#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */ + +#define BMI_EXECUTE 4 +/* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ +/* + * Note: In order to support the segmented file feature + * (see BMI_WRITE_MEMORY), when the address specified in a + * BMI_EXECUTE command matches (same physical address) + * BMI_SEGMENTED_WRITE_ADDR, it is ignored. Instead, execution + * begins at the address specified by hi_app_start. + */ + +#define BMI_SET_APP_START 5 +/* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 +#define BMI_READ_SOC_WORD 6 +/* + * Semantics: Read a 32-bit Target SOC word. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 +#define BMI_WRITE_SOC_WORD 7 +/* + * Semantics: Write a 32-bit Target SOC word. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 +/* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * + * Response format2 (intermediate firmware, during transition): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + * + * Response format3 (newest firmware) + * struct bmi_target_info; + */ +PREPACK struct bmi_target_info { + /* size of this structure */ + A_UINT32 target_info_byte_count; + A_UINT32 target_ver; + A_UINT32 target_type; +} POSTPACK; + +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_UNKNOWN 0 +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 +#define TARGET_TYPE_AR6003 3 +#define TARGET_TYPE_AR6004 5 +#define TARGET_TYPE_AR6006 6 +#define TARGET_TYPE_AR9888 7 +#define TARGET_TYPE_AR6320 8 +#define TARGET_TYPE_AR900B 9 +/* For attach Peregrine 2.0 board target_reg_tbl only */ +#define TARGET_TYPE_AR9888V2 10 +/* For attach Rome1.0 target_reg_tbl only*/ +#define TARGET_TYPE_AR6320V1 11 +/* For Rome2.0/2.1 target_reg_tbl ID*/ +#define TARGET_TYPE_AR6320V2 12 +/* For Rome3.0 target_reg_tbl ID*/ +#define TARGET_TYPE_AR6320V3 13 +/* For Tufello1.0 target_reg_tbl ID*/ +#define TARGET_TYPE_QCA9377V1 14 +/* cascade */ +#define TARGET_TYPE_QCA9984 15 +/* dakota */ +#define TARGET_TYPE_IPQ4019 16 +/* besra */ +#define TARGET_TYPE_QCA9888 17 +/* For Adrastea target */ +#define TARGET_TYPE_ADRASTEA 19 + +extern void target_register_tbl_attach(A_UINT32 target_type); + +#define BMI_ROMPATCH_INSTALL 9 +/* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address or Value (depending on Target Type) + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 +/* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 +/* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 +/* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_LZ_STREAM_START 13 +/* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 +/* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_NVRAM_PROCESS 15 +#define BMI_NVRAM_SEG_NAME_SZ 16 +/* + * Semantics: Cause Target to search NVRAM (if any) for a + * segment with the specified name and process it according + * to NVRAM metadata. + * Request format: + * A_UINT32 command (BMI_NVRAM_PROCESS) + * A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format) + * Response format: + * A_UINT32 0, if nothing was executed; + * otherwise the value returned from the + * last NVRAM segment that was executed + */ + +#define BMI_SIGN_STREAM_START 17 +/* + * Semantics: Trigger target start/end binary signature verification + * flow. + * Request format: + * A_UINT32 command (BMI_SIGN_STREAM_START) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +/* TBDXXX: Need a better place for these */ +#define BMI_CE_NUM_TO_TARG 0 +#define BMI_CE_NUM_TO_HOST 1 + +#endif /* __BMI_MSG_H__ */ diff --git a/fw/cepci.h b/fw/cepci.h old mode 100755 new mode 100644 index a55f325be3db..5c2247eafd56 --- a/fw/cepci.h +++ b/fw/cepci.h @@ -33,7 +33,6 @@ * Structures shared between Host software and Target firmware. */ - /* * Total number of PCIe MSI interrupts requested for all interrupt sources. * PCIe standard forces this to be a power of 2. @@ -55,9 +54,6 @@ #define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */ #define MSI_ASSIGN_CE_MAX 7 - - - /* * PCI-specific Target state. Much of this may be of interest * to the Host so HOST_INTEREST->hi_interconnect_state points @@ -66,49 +62,50 @@ * required to initialize pipe_cfg_addr and svc_to_pipe_map. */ struct pcie_state_s { - A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */ - /* NB: CE_pipe_config[CE_COUNT] */ + uint32_t pipe_cfg_addr; /* Pipe configuration Target address */ + /* NB: CE_pipe_config[CE_COUNT] */ - A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */ - /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */ + uint32_t svc_to_pipe_map; /* Service to pipe map Target address */ + /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */ - A_UINT32 MSI_requested; /* number of MSI interrupts requested */ - A_UINT32 MSI_granted; /* number of MSI interrupts granted */ - A_UINT32 MSI_addr; /* Message Signalled Interrupt address */ - A_UINT32 MSI_data; /* Base data */ - A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt; - MSI data for other interrupts are - in various SoC registers */ + uint32_t MSI_requested; /* number of MSI interrupts requested */ + uint32_t MSI_granted; /* number of MSI interrupts granted */ + uint32_t MSI_addr; /* Message Signalled Interrupt address */ + uint32_t MSI_data; /* Base data */ + uint32_t MSI_fw_intr_data; /* Data for firmware interrupt; + MSI data for other interrupts are + in various SoC registers */ - A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */ - A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */ + uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */ + uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */ }; /* * PCIE_CONFIG_FLAG definitions */ - -#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 +#if defined(AR900B) #define CE_PKTLOG_PIPE 8 /* used by both host and target side */ +#endif +#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 #define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001 #define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002 #define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004 #define PCIE_CONFIG_FLAG_CLK_REQ_L1 0x0000008 -#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */ +#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */ /* * Configuration information for a Copy Engine pipe. * Passed from Host to Target during startup (one per CE). */ struct CE_pipe_config { - A_UINT32 pipenum; - A_UINT32 pipedir; - A_UINT32 nentries; - A_UINT32 nbytes_max; - A_UINT32 flags; - A_UINT32 reserved; + uint32_t pipenum; + uint32_t pipedir; + uint32_t nentries; + uint32_t nbytes_max; + uint32_t flags; + uint32_t reserved; }; #endif /* __CEPCI_H__ */ diff --git a/fw/dbglog.h b/fw/dbglog.h old mode 100755 new mode 100644 index 1be8bf13b560..d3179a7ae92e --- a/fw/dbglog.h +++ b/fw/dbglog.h @@ -32,83 +32,87 @@ #include "athstartpack.h" #endif -#include +#include "wlan_module_ids.h" #ifdef __cplusplus extern "C" { #endif #define DBGLOG_TIMESTAMP_OFFSET 0 -#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF /* Bit 0-15. Contains bit - 8-23 of the LF0 timer */ + +/* Bit 0-15. Contains bit 8-23 of the LF0 timer */ +#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF #define DBGLOG_DBGID_OFFSET 0 -#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */ -#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */ +/* Upper limit is width of mask */ +#define DBGLOG_DBGID_NUM_MAX 256 #define DBGLOG_MODULEID_OFFSET 10 -#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */ -#define DBGLOG_MODULEID_NUM_MAX 32 /* Upper limit is width of mask */ +#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */ +/* Upper limit is width of mask */ +#define DBGLOG_MODULEID_NUM_MAX 32 -#define DBGLOG_VDEVID_OFFSET 18 -#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25*/ -#define DBGLOG_VDEVID_NUM_MAX 16 +#define DBGLOG_VDEVID_OFFSET 18 +#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25 */ +#define DBGLOG_VDEVID_NUM_MAX 16 -#define DBGLOG_NUM_ARGS_OFFSET 26 -#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */ -#define DBGLOG_NUM_ARGS_MAX 9 /* it is bcoz of limitation - of corebsp MSG*() to accept max 9 arg */ +#define DBGLOG_NUM_ARGS_OFFSET 26 +#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */ -#define DBGLOG_LOG_BUFFER_SIZE 1500 -#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 +/* it is limited bcoz of limitations of corebsp MSG*() to accept max 9 arg */ +#define DBGLOG_NUM_ARGS_MAX 9 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 #define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE #define DBGLOG_GET_DBGID(arg) \ - ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) #define DBGLOG_GET_MODULEID(arg) \ - ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) #define DBGLOG_GET_VDEVID(arg) \ - ((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET) + ((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET) -#define DBGLOG_GET_NUMARGS(arg) \ - ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) +#define DBGLOG_GET_NUMARGS(arg) \ + ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) #define DBGLOG_GET_TIME_STAMP(arg) \ - ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) + ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) /* Debug Log levels*/ -typedef enum { - DBGLOG_VERBOSE = 0, - DBGLOG_INFO, - DBGLOG_INFO_LVL_1, - DBGLOG_INFO_LVL_2, - DBGLOG_WARN, - DBGLOG_ERR, - DBGLOG_LVL_MAX -}DBGLOG_LOG_LVL; +enum DBGLOG_LOG_LVL { + DBGLOG_VERBOSE = 0, + DBGLOG_INFO, + DBGLOG_INFO_LVL_1, + DBGLOG_INFO_LVL_2, + DBGLOG_WARN, + DBGLOG_ERR, + DBGLOG_LVL_MAX +}; PREPACK struct dbglog_buf_s { - struct dbglog_buf_s *next; - A_UINT8 *buffer; - A_UINT32 bufsize; - A_UINT32 length; - A_UINT32 count; - A_UINT32 free; + struct dbglog_buf_s *next; + A_UINT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; } POSTPACK; PREPACK struct dbglog_hdr_s { - struct dbglog_buf_s *dbuf; - A_UINT32 dropped; + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; } POSTPACK; -#define DBGLOG_MAX_VDEVID 15 /* 0-15 */ + +#define DBGLOG_MAX_VDEVID 15 /* 0-15 */ #ifdef __cplusplus } #endif - - #endif /* _DBGLOG_H_ */ diff --git a/fw/dbglog_id.h b/fw/dbglog_id.h old mode 100755 new mode 100644 index ed6d580c0704..892f1fe96e63 --- a/fw/dbglog_id.h +++ b/fw/dbglog_id.h @@ -41,21 +41,20 @@ extern "C" { */ /* -* The target state machine framework will send dbglog messages on behalf on -* other modules. We do this do avoid each module adding identical dbglog code -* for state transitions and event processing. We also don't want to force each -* module to define the the same XXX_DBGID_SM_MSG with the same value below. -* Instead we use a special ID that the host dbglog code recognizes as a -* message sent by the SM on behalf on another module. -*/ + * The target state machine framework will send dbglog messages on behalf on + * other modules. We do this do avoid each module adding identical dbglog code + * for state transitions and event processing. We also don't want to force each + * module to define the the same XXX_DBGID_SM_MSG with the same value below. + * Instead we use a special ID that the host dbglog code recognizes as a + * message sent by the SM on behalf on another module. + */ #define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000 - /* INF debug identifier definitions */ #define INF_DBGID_DEFINITION_START 0 #define INF_ASSERTION_FAILED 1 #define INF_TARGET_ID 2 -#define INF_TARGET_MEM_REMAING 3 +#define INF_TARGET_MEM_REMAING 3 #define INF_TARGET_MEM_EXT_REMAING 4 #define INF_TARGET_MEM_ALLOC_TRACK 5 #define INF_TARGET_MEM_ALLOC_RAM 6 @@ -298,7 +297,7 @@ extern "C" { #define WHAL_ERROR_XTAL_SET 49 #define WHAL_DBGID_DEFINITION_END 50 -#define COEX_DEBUGID_START 0 +#define COEX_DEBUGID_START 0 #define BTCOEX_DBG_MCI_1 1 #define BTCOEX_DBG_MCI_2 2 #define BTCOEX_DBG_MCI_3 3 @@ -688,6 +687,7 @@ extern "C" { #define WAL_DBGID_TX_SCH_REGISTER_TIDQ 12 #define WAL_DBGID_TX_SCH_UNREGISTER_TIDQ 13 #define WAL_DBGID_TX_SCH_TICKLE_TIDQ 14 + #define WAL_DBGID_XCESS_FAILURES 15 #define WAL_DBGID_AST_ADD_WDS_ENTRY 16 #define WAL_DBGID_AST_DEL_WDS_ENTRY 17 @@ -780,6 +780,7 @@ extern "C" { #define ANI_DBGID_MRC_CCK 10 #define ANI_DBGID_SELF_CORR_LOW 11 #define ANI_DBGID_ENABLE 12 + #define ANI_DBGID_CURRENT_LEVEL 13 #define ANI_DBGID_POLL_PERIOD 14 #define ANI_DBGID_LISTEN_PERIOD 15 @@ -864,8 +865,7 @@ extern "C" { #define P2P_GO_BCN_TX_COMP 38 #define P2P_DBGID_DEFINITION_END 39 - -//CSA modules DBGIDs +/* CSA modules DBGIDs */ #define CSA_DBGID_DEFINITION_START 0 #define CSA_OFFLOAD_POOL_INIT 1 #define CSA_OFFLOAD_REGISTER_VDEV 2 @@ -925,7 +925,6 @@ extern "C" { #define WOW_IBSS_VDEV_ALLOW 23 #define WOW_DBGID_DEFINITION_END 24 - /* SWBMISS module DBGIDs */ #define SWBMISS_DBGID_DEFINITION_START 0 #define SWBMISS_ENABLED 1 @@ -1145,6 +1144,7 @@ extern "C" { #define RTT_CHANNEL_SWITCH_PREEMPT 18 #define RTT_CHANNEL_SWITCH_STOP 19 #define RTT_TIMER_START 20 + #define RTT_FTM_PARAM_INFO 21 #define RTT_RX_TM_FRAME 22 #define RTT_INITR_TSTAMP 23 @@ -1186,7 +1186,7 @@ extern "C" { #define WLAN_PHTERR_DFS_DBDID_FILTER_STATUS 5 #define WLAN_PHYERR_DFS_DBGID_DEFINITION_END 6 -/* RMC DBGIDs*/ +/* RMC DBGIDs */ #define RMC_DBGID_DEFINITION_START 0 #define RMC_CREATE_INSTANCE 1 #define RMC_DELETE_INSTANCE 2 @@ -1246,7 +1246,6 @@ extern "C" { #define WLAN_STATS_DBGID_RSSI 6 #define WLAN_STATS_DBGID_CNE_RSSI 7 #define WLAN_STATS_DBGID_DEFINITION_END 8 - /* NAN DBGIDs */ #define NAN_DBGID_START 0 @@ -1491,46 +1490,51 @@ extern "C" { #define NAN_DBGID_BEACON_RX_LAST (NAN_DBGID_OTA_PKT_LAST + 20) /* NaN Datapath Timekeeper debug IDs */ -#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST /* 116 + 20 = 136 */ -#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0) /* 136 */ -#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1) /* 137 */ -#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2) /* 138 */ -#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3) /* 139 */ -#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4) /* 140 */ -#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5) /* 141 */ -#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6) /* 142 */ -#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7) /* 143 */ -#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8) /* 144 */ -#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9) /* 145 */ -#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10) /* 146 */ -#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11) /* 147 */ -#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12) /* 148 */ -#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13) /* 149 */ -#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14) /* 150 */ -#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15) /* 151 */ -#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16) /* 152 */ -#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17) /* 153 */ -#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18) /* 154 */ -#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19) /* 155 */ -#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20) /* 156 */ -#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21) /* 157 */ -#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22) /* 158 */ -#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23) /* 159 */ -#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24) /* 160 */ -#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25) /* 161 */ -#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26) /* 162 */ -#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27) /* 163 */ -#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28) /* 164 */ -#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29) /* 165 */ -#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30) /* 166 */ -#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31) /* 167 */ -#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32) /* 168 */ -#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33) /* 169 */ -#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34) /* 170 */ -#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35) /* 171 */ -#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36) /* 172 */ -#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37) /* 173 */ -#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38) /* 174 */ +/* 116 + 20 = 136 */ +#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST +/* 136 */ +#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0) +#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1) +#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2) +#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3) +#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4) +#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5) +#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6) +#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7) +#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8) +#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9) +#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10) +#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11) +#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12) +#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13) +/* 150 */ +#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14) +#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15) +#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16) +#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17) +#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18) +#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19) +#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20) +#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21) +#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22) +#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23) +#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24) +#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25) +/* 162 */ +#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26) +#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27) +#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28) +#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29) +#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30) +#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31) +#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32) +#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33) +#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34) +#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35) +/* 172 */ +#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36) +#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37) +#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38) #define NAN_DBGID_END (NAN_DBGID_TMKR_LAST) @@ -1631,6 +1635,7 @@ extern "C" { #define ERE_DBGID_STATS_RX 12 #define ERE_DBGID_DEFINITION_END 13 /* IDs 14 - 251 reserved for ERE */ + /* Timekeeper debug IDs */ #define TIMEKEEPER_INIT 252 #define TIMEKEEPER_OPEN 253 @@ -1736,9 +1741,8 @@ extern "C" { #define WLAN_MODULE_QBOOST_DBGID_WLAN_PEER_NOT_FOUND 1 #define WLAN_MODULE_QBOOST_DEFINITION_END 2 + #ifdef __cplusplus } #endif - #endif /* _DBGLOG_ID_H_ */ - diff --git a/fw/efuse_reg.h b/fw/efuse_reg.h new file mode 100644 index 000000000000..2bff9f8a28a5 --- /dev/null +++ b/fw/efuse_reg.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef _EFUSE_REG_REG_H_ +#define _EFUSE_REG_REG_H_ + +#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 +#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 +#define EFUSE_WR_ENABLE_REG_V_MSB 0 +#define EFUSE_WR_ENABLE_REG_V_LSB 0 +#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB) +#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK) + +#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 +#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 +#define EFUSE_INT_ENABLE_REG_V_MSB 0 +#define EFUSE_INT_ENABLE_REG_V_LSB 0 +#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) +#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) + +#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 +#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 +#define EFUSE_INT_STATUS_REG_V_MSB 0 +#define EFUSE_INT_STATUS_REG_V_LSB 0 +#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 +#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB) +#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK) + +#define BITMASK_WR_REG_ADDRESS 0x0000000c +#define BITMASK_WR_REG_OFFSET 0x0000000c +#define BITMASK_WR_REG_V_MSB 31 +#define BITMASK_WR_REG_V_LSB 0 +#define BITMASK_WR_REG_V_MASK 0xffffffff +#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB) +#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK) + +#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 +#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 +#define VDDQ_SETTLE_TIME_REG_V_MSB 31 +#define VDDQ_SETTLE_TIME_REG_V_LSB 0 +#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff +#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) +#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) + +#define VDDQ_HOLD_TIME_REG_ADDRESS 0x00000014 +#define VDDQ_HOLD_TIME_REG_OFFSET 0x00000014 +#define VDDQ_HOLD_TIME_REG_V_MSB 31 +#define VDDQ_HOLD_TIME_REG_V_LSB 0 +#define VDDQ_HOLD_TIME_REG_V_MASK 0xffffffff +#define VDDQ_HOLD_TIME_REG_V_GET(x) (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB) +#define VDDQ_HOLD_TIME_REG_V_SET(x) (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK) + +#define RD_STROBE_PW_REG_ADDRESS 0x00000018 +#define RD_STROBE_PW_REG_OFFSET 0x00000018 +#define RD_STROBE_PW_REG_V_MSB 31 +#define RD_STROBE_PW_REG_V_LSB 0 +#define RD_STROBE_PW_REG_V_MASK 0xffffffff +#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB) +#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK) + +#define PG_STROBE_PW_REG_ADDRESS 0x0000001c +#define PG_STROBE_PW_REG_OFFSET 0x0000001c +#define PG_STROBE_PW_REG_V_MSB 31 +#define PG_STROBE_PW_REG_V_LSB 0 +#define PG_STROBE_PW_REG_V_MASK 0xffffffff +#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB) +#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK) + +#define PGENB_SETUP_HOLD_TIME_REG_ADDRESS 0x00000020 +#define PGENB_SETUP_HOLD_TIME_REG_OFFSET 0x00000020 +#define PGENB_SETUP_HOLD_TIME_REG_V_MSB 31 +#define PGENB_SETUP_HOLD_TIME_REG_V_LSB 0 +#define PGENB_SETUP_HOLD_TIME_REG_V_MASK 0xffffffff +#define PGENB_SETUP_HOLD_TIME_REG_V_GET(x) (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB) +#define PGENB_SETUP_HOLD_TIME_REG_V_SET(x) (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) + +#define STROBE_PULSE_INTERVAL_REG_ADDRESS 0x00000024 +#define STROBE_PULSE_INTERVAL_REG_OFFSET 0x00000024 +#define STROBE_PULSE_INTERVAL_REG_V_MSB 31 +#define STROBE_PULSE_INTERVAL_REG_V_LSB 0 +#define STROBE_PULSE_INTERVAL_REG_V_MASK 0xffffffff +#define STROBE_PULSE_INTERVAL_REG_V_GET(x) (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB) +#define STROBE_PULSE_INTERVAL_REG_V_SET(x) (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK) + +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS 0x00000028 +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET 0x00000028 +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB 31 +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB 0 +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK 0xffffffff +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x) (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) +#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x) (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) + +#define EFUSE_INTF0_ADDRESS 0x00000800 +#define EFUSE_INTF0_OFFSET 0x00000800 +#define EFUSE_INTF0_R_MSB 31 +#define EFUSE_INTF0_R_LSB 0 +#define EFUSE_INTF0_R_MASK 0xffffffff +#define EFUSE_INTF0_R_GET(x) (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB) +#define EFUSE_INTF0_R_SET(x) (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK) + +#define EFUSE_INTF1_ADDRESS 0x00001000 +#define EFUSE_INTF1_OFFSET 0x00001000 +#define EFUSE_INTF1_R_MSB 31 +#define EFUSE_INTF1_R_LSB 0 +#define EFUSE_INTF1_R_MASK 0xffffffff +#define EFUSE_INTF1_R_GET(x) (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB) +#define EFUSE_INTF1_R_SET(x) (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK) + +#ifndef __ASSEMBLER__ +typedef struct efuse_reg_reg_s { + volatile unsigned int efuse_wr_enable_reg; + volatile unsigned int efuse_int_enable_reg; + volatile unsigned int efuse_int_status_reg; + volatile unsigned int bitmask_wr_reg; + volatile unsigned int vddq_settle_time_reg; + volatile unsigned int vddq_hold_time_reg; + volatile unsigned int rd_strobe_pw_reg; + volatile unsigned int pg_strobe_pw_reg; + volatile unsigned int pgenb_setup_hold_time_reg; + volatile unsigned int strobe_pulse_interval_reg; + volatile unsigned int csb_addr_load_setup_hold_reg; + unsigned char pad0[2004]; /* pad to 0x800 */ + volatile unsigned int efuse_intf0[512]; + volatile unsigned int efuse_intf1[512]; +} efuse_reg_reg_t; +#endif /* __ASSEMBLER__ */ + +#endif /* _EFUSE_REG_H_ */ diff --git a/fw/enet.h b/fw/enet.h new file mode 100644 index 000000000000..3e66c676afa1 --- /dev/null +++ b/fw/enet.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef _ENET__H_ +#define _ENET__H_ + +#if defined(ATH_TARGET) +#include /* A_UINT8 */ +#else +#include /* A_UINT8 */ +#endif + +#define ETHERNET_ADDR_LEN 6 /* bytes */ +#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */ + +struct ethernet_hdr_t { + A_UINT8 dest_addr[ETHERNET_ADDR_LEN]; + A_UINT8 src_addr[ETHERNET_ADDR_LEN]; + A_UINT8 ethertype[ETHERNET_TYPE_LEN]; +}; + +#define ETHERNET_HDR_LEN (sizeof(struct ethernet_hdr_t)) + +#define ETHERNET_CRC_LEN 4 /* bytes - length of the Ethernet CRC */ +#define ETHERNET_MAX_LEN 1518 /* bytes */ + +#define ETHERNET_MTU (ETHERNET_MAX_LEN - (ETHERNET_HDR_LEN + ETHERNET_CRC_LEN)) + + +struct llc_snap_hdr_t { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 org_code[3]; + A_UINT8 ethertype[2]; +}; + +#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t)) +#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \ + (offsetof(struct llc_snap_hdr_t, ethertype[0])) + +#define ETHERTYPE_VLAN_LEN 4 + +struct ethernet_vlan_hdr_t { + A_UINT8 dest_addr[ETHERNET_ADDR_LEN]; + A_UINT8 src_addr[ETHERNET_ADDR_LEN]; + A_UINT8 vlan_tpid[2]; + A_UINT8 vlan_tci[2]; + A_UINT8 ethertype[2]; +}; + +#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \ + ((typeorlen) == ETHERTYPE_PAE || \ + (typeorlen) == ETHERTYPE_WAI) + +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) + +#ifndef ETHERTYPE_IPV4 +#define ETHERTYPE_IPV4 0x0800 /* Internet Protocol, Version 4 (IPv4) */ +#endif + +#ifndef ETHERTYPE_AARP +#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */ +#endif + +#ifndef ETHERTYPE_IPX +#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */ +#endif + +#ifndef ETHERTYPE_ARP +#define ETHERTYPE_ARP 0x0806 /* Address Resolution Protocol (ARP) */ +#endif + +#ifndef ETHERTYPE_RARP +#define ETHERTYPE_RARP 0x8035 /* Reverse Address Resolution Protocol (RARP) */ +#endif + +#ifndef ETHERTYPE_VLAN +#define ETHERTYPE_VLAN 0x8100 /* VLAN TAG protocol */ +#endif + +#ifndef ETHERTYPE_SNMP +#define ETHERTYPE_SNMP 0x814C /* Simple Network Management Protocol (SNMP) */ +#endif + +#ifndef ETHERTYPE_IPV6 +#define ETHERTYPE_IPV6 0x86DD /* Internet Protocol, Version 6 (IPv6) */ +#endif + +#ifndef ETHERTYPE_PAE +#define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */ +#endif + +#ifndef ETHERTYPE_WAI +#define ETHERTYPE_WAI 0x88B4 /* WAPI */ +#endif + +#ifndef ETHERTYPE_TDLS +#define ETHERTYPE_TDLS 0x890D /* TDLS */ +#endif + +#define LLC_SNAP_LSAP 0xaa +#define LLC_UI 0x3 + +#define RFC1042_SNAP_ORGCODE_0 0x00 +#define RFC1042_SNAP_ORGCODE_1 0x00 +#define RFC1042_SNAP_ORGCODE_2 0x00 + +#define BTEP_SNAP_ORGCODE_0 0x00 +#define BTEP_SNAP_ORGCODE_1 0x00 +#define BTEP_SNAP_ORGCODE_2 0xf8 + +#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \ + (_llc)->ssap == LLC_SNAP_LSAP && \ + (_llc)->cntl == LLC_UI) + +#define IS_RFC1042(_llc) ((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \ + (_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \ + (_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2) + +#define IS_BTEP(_llc) ((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \ + (_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \ + (_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2) + +#endif /* _ENET__H_ */ diff --git a/fw/epping_test.h b/fw/epping_test.h new file mode 100644 index 000000000000..b8e6d01785c6 --- /dev/null +++ b/fw/epping_test.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +/* This file contains shared definitions for the host/target endpoint ping test */ + +#ifndef EPPING_TEST_H +#define EPPING_TEST_H + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* alignment to 4-bytes */ +#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR)) + +#ifndef A_OFFSETOF +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) +#endif + +#define EPPING_RSVD_FILL 0xCC + +#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7 + +typedef PREPACK struct { + A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */ + A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */ + A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target) + When echoed: StreamEchoSent_t == StreamEcho_h */ + A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */ + A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */ + A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host */ + A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value + since this packet maps to a 14-byte ethernet frame we want + to make sure ethertype field is set to something unknown */ + + A_UINT8 _pad[2]; /* padding for alignment */ + A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */ + A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */ + A_UINT32 SeqNo; /* sequence number (set by host or target) */ + A_UINT16 Cmd_h; /* ping command (filled by host) */ + A_UINT16 CmdFlags_h; /* optional flags */ + A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */ + A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */ + A_UINT16 DataLength; /* length of data */ + A_UINT16 DataCRC; /* 16 bit CRC of data */ + A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */ +} POSTPACK EPPING_HEADER; + +#define EPPING_PING_MAGIC_0 0xAA +#define EPPING_PING_MAGIC_1 0x55 +#define EPPING_PING_MAGIC_2 0xCE +#define EPPING_PING_MAGIC_3 0xEC + +#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \ + ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \ + ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \ + ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3)) + +#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \ + (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \ + (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \ + (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3; } + +#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */ +#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */ +#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */ + +#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP) + +#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */ +#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */ +#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */ +#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */ +#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */ +#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */ + +/* test command parameters may be no more than 8 bytes */ +typedef PREPACK struct { + A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */ + A_UINT16 PacketLength; /* length of packet to generate including header */ + A_UINT16 Flags; /* flags */ + +#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */ +#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */ +#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */ +#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3) /* target will not fill buffers */ + A_UINT16 Context; /* flags */ + +} POSTPACK EPPING_CONT_RX_PARAMS; + +#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h) +#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16))) + +#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we + can use this to distinguish packets */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* EPPING_TEST_H */ diff --git a/fw/htc.h b/fw/htc.h new file mode 100644 index 000000000000..9d9f014352fb --- /dev/null +++ b/fw/htc.h @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif +#ifdef ATHR_WIN_NWF +#pragma warning(disable:4214) +#endif +#undef MS +#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB) +#undef SM +#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK) +#undef WO +#define WO(_f) ((_f ## _OFFSET) >> 2) + +#undef GET_FIELD +#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f) +#undef SET_FIELD +#define SET_FIELD(_addr, _f, _val) \ + (*((A_UINT32 *)(_addr) + WO(_f)) = \ + (*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f)) + +#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \ + GET_FIELD(_msg_buf, _msg_type ## _ ## _f) + +#define HTC_SET_FIELD(_msg_buf, _msg_type, _f, _val) \ + SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val) + +#define HTC_WRITE32(_addr, _val) \ + (*(A_UINT32 *)(_addr) = (_val)) + +#ifndef A_OFFSETOF +#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field)) +#endif + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR { + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT32 EndpointID : 8, Flags : 8, PayloadLen : 16; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT32 ControlBytes0 : 8,/*used for CRC check if CRC_CHECK flag set*/ + ControlBytes1 : 8, /*used for seq check if SEQ_CHECK flag set*/ + reserved : 16; /*used by bundle processing in SDIO systems*/ + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +#define HTC_FRAME_HDR_ENDPOINTID_LSB 0 +#define HTC_FRAME_HDR_ENDPOINTID_MASK 0x000000ff +#define HTC_FRAME_HDR_ENDPOINTID_OFFSET 0x00000000 +#define HTC_FRAME_HDR_FLAGS_LSB 8 +#define HTC_FRAME_HDR_FLAGS_MASK 0x0000ff00 +#define HTC_FRAME_HDR_FLAGS_OFFSET 0x00000000 +#define HTC_FRAME_HDR_PAYLOADLEN_LSB 16 +#define HTC_FRAME_HDR_PAYLOADLEN_MASK 0xffff0000 +#define HTC_FRAME_HDR_PAYLOADLEN_OFFSET 0x00000000 +#define HTC_FRAME_HDR_CONTROLBYTES0_LSB 0 +#define HTC_FRAME_HDR_CONTROLBYTES0_MASK 0x000000ff +#define HTC_FRAME_HDR_CONTROLBYTES0_OFFSET 0x00000004 +#define HTC_FRAME_HDR_CONTROLBYTES1_LSB 8 +#define HTC_FRAME_HDR_CONTROLBYTES1_MASK 0x0000ff00 +#define HTC_FRAME_HDR_CONTROLBYTES1_OFFSET 0x00000004 +#define HTC_FRAME_HDR_RESERVED_LSB 16 +#define HTC_FRAME_HDR_RESERVED_MASK 0xffff0000 +#define HTC_FRAME_HDR_RESERVED_OFFSET 0x00000004 + +/* frame header flags */ + +/* send direction */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */ +#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */ +#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */ +/* receive direction */ +#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */ +#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xFC) /* bits 7..2 */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 2 +/* + * To be compatible with an older definition of a smaller (4-bit) + * bundle count field, the bundle count is stored in a segmented + * format - the 4 LSbs of the bundle count value are stored in bits 5:2 + * of the BUNDLE_CNT field, which is bits 7:4 of the HTC_FLAGS word; + * the next 2 bits of the bundle count value are stored in bits 1:0 of + * the BUNDLE_CNT field, which is bits 3:2 of the HTC_FLAGS word. + */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x) \ + ((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) +#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x) \ + ((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> \ + (HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \ + ((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4)) + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_HDR_ALIGNMENT_PADDING \ + (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ + +#define HTC_MSG_READY_ID 1 +#define HTC_MSG_CONNECT_SERVICE_ID 2 +#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3 +#define HTC_MSG_SETUP_COMPLETE_ID 4 +#define HTC_MSG_SETUP_COMPLETE_EX_ID 5 +#define HTC_MSG_SEND_SUSPEND_COMPLETE 6 +#define HTC_MSG_NACK_SUSPEND 7 +#define HTC_MSG_WAKEUP_FROM_SUSPEND_ID 8 + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT32 MessageID : 16, reserved : 16; +} POSTPACK HTC_UNKNOWN_MSG; + +#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0 +#define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff +#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000 + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT32 MessageID : 16, /* ID */ + CreditCount : 16; /* number of credits the target can offer */ + A_UINT32 CreditSize : 16, /* size of each credit */ + MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */ + _Pad1 : 8; +} POSTPACK HTC_READY_MSG; + +#define HTC_READY_MSG_MESSAGEID_LSB 0 +#define HTC_READY_MSG_MESSAGEID_MASK 0x0000ffff +#define HTC_READY_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_READY_MSG_CREDITCOUNT_LSB 16 +#define HTC_READY_MSG_CREDITCOUNT_MASK 0xffff0000 +#define HTC_READY_MSG_CREDITCOUNT_OFFSET 0x00000000 +#define HTC_READY_MSG_CREDITSIZE_LSB 0 +#define HTC_READY_MSG_CREDITSIZE_MASK 0x0000ffff +#define HTC_READY_MSG_CREDITSIZE_OFFSET 0x00000004 +#define HTC_READY_MSG_MAXENDPOINTS_LSB 16 +#define HTC_READY_MSG_MAXENDPOINTS_MASK 0x00ff0000 +#define HTC_READY_MSG_MAXENDPOINTS_OFFSET 0x00000004 + +/* extended HTC ready message */ +typedef PREPACK struct { + HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */ + /* extended information */ + A_UINT32 HTCVersion : 8, MaxMsgsPerHTCBundle : 8, reserved : 16; +} POSTPACK HTC_READY_EX_MSG; + +#define HTC_READY_EX_MSG_HTCVERSION_LSB 0 +#define HTC_READY_EX_MSG_HTCVERSION_MASK 0x000000ff +#define HTC_READY_EX_MSG_HTCVERSION_OFFSET sizeof(HTC_READY_MSG) +#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_LSB 8 +#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_MASK 0x0000ff00 +#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_OFFSET sizeof(HTC_READY_MSG) + +#define HTC_VERSION_2P0 0x00 +#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */ + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + /* service ID of the service to connect to */ + A_UINT32 MessageID:16, service_id:16; + A_UINT32 ConnectionFlags : 16, /* connection flags */ +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) + /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + /* disable credit flow control on a specific service */ +#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL (1 << 3) + /* enable htc schedule on a specific service */ +#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4) + ServiceMetaLength : 8, /* length of meta data that follows */ + _Pad1 : 8; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_LSB 0 +#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_MASK 0x0000ffff +#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_LSB 16 +#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_MASK 0xffff0000 +#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_OFFSET 0x00000000 +#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_LSB 0 +#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_MASK 0x0000ffff +#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_OFFSET 0x00000004 +#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_LSB 16 +#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_MASK 0x00ff0000 +#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_OFFSET 0x00000004 + +#define HTC_SET_RECV_ALLOC_SHIFT 8 +#define HTC_SET_RECV_ALLOC_MASK 0xFF00 +#define HTC_CONNECT_FLAGS_SET_RECV_ALLOCATION(value) (((A_UINT8)value) << HTC_SET_RECV_ALLOC_SHIFT) +#define HTC_CONNECT_FLAGS_GET_RECV_ALLOCATION(value) (A_UINT8)(((value) & HTC_SET_RECV_ALLOC_MASK) >> HTC_SET_RECV_ALLOC_SHIFT) + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + /* service ID that the connection request was made */ + A_UINT32 MessageID:16, service_id:16; + A_UINT32 Status : 8, /* service connection status */ + EndpointID : 8, /* assigned endpoint ID */ + MaxMsgSize : 16; /* maximum expected message size on this endpoint */ + A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */ + _Pad1 : 8, reserved : 16; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_LSB 0 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_MASK 0x0000ffff +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_LSB 16 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_MASK 0xffff0000 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_OFFSET 0x00000000 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_LSB 0 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_MASK 0x000000ff +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_OFFSET 0x00000004 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_LSB 8 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_MASK 0x0000ff00 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_OFFSET 0x00000004 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_LSB 16 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_MASK 0xffff0000 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_OFFSET 0x00000004 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_LSB 0 +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_MASK 0x000000ff +#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008 + +typedef PREPACK struct { + A_UINT32 MessageID : 16, reserved : 16; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + +#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_LSB 0 +#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK 0x0000ffff +#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET 0x00000000 + +/* extended setup completion message */ +typedef PREPACK struct { + A_UINT32 MessageID : 16, reserved : 16; + A_UINT32 SetupFlags : 32; + A_UINT32 MaxMsgsPerBundledRecv : 8, Rsvd0 : 8, Rsvd1 : 8, Rsvd2 : 8; +} POSTPACK HTC_SETUP_COMPLETE_EX_MSG; + +#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB 0 +#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_MASK 0x0000ffff +#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_LSB 0 +#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_MASK 0xffffffff +#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_OFFSET 0x00000004 +#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_LSB 0 +#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_MASK 0x000000ff +#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_OFFSET 0x00000008 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_LSB 8 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_MASK 0x0000ff00 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_OFFSET 0x00000008 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_LSB 16 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_MASK 0x00ff0000 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_OFFSET 0x00000008 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_LSB 24 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_MASK 0xff000000 +#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_OFFSET 0x00000008 + +#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) /* enable recv bundling from target */ +#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1) /* disable credit based flow control, + only supported on some interconnects */ + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ + +#define HTC_RECORD_NULL 0 +#define HTC_RECORD_CREDITS 1 +#define HTC_RECORD_LOOKAHEAD 2 +#define HTC_RECORD_LOOKAHEAD_BUNDLE 3 + +typedef PREPACK struct { + A_UINT32 RecordID : 8, /* Record ID */ + Length : 8, /* Length of record */ + reserved : 16; +} POSTPACK HTC_RECORD_HDR; + +#define HTC_RECORD_HDR_RECORDID_LSB 0 +#define HTC_RECORD_HDR_RECORDID_MASK 0x000000ff +#define HTC_RECORD_HDR_RECORDID_OFFSET 0x00000000 +#define HTC_RECORD_HDR_LENGTH_LSB 8 +#define HTC_RECORD_HDR_LENGTH_MASK 0x0000ff00 +#define HTC_RECORD_HDR_LENGTH_OFFSET 0x00000000 + +typedef PREPACK struct { + A_UINT32 EndpointID : 8, /* Endpoint that owns these credits */ + Credits : 8, /* credits to report since last report */ + reserved : 16; +} POSTPACK HTC_CREDIT_REPORT; + +#define HTC_CREDIT_REPORT_ENDPOINTID_LSB 0 +#define HTC_CREDIT_REPORT_ENDPOINTID_MASK 0x000000ff +#define HTC_CREDIT_REPORT_ENDPOINTID_OFFSET 0x00000000 +#define HTC_CREDIT_REPORT_CREDITS_LSB 8 +#define HTC_CREDIT_REPORT_CREDITS_MASK 0x0000ff00 +#define HTC_CREDIT_REPORT_CREDITS_OFFSET 0x00000000 + +typedef PREPACK struct { + A_UINT32 PreValid : 8, /* pre valid guard */ + reserved0 : 24; + A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */ + LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8; + A_UINT32 PostValid : 8, /* post valid guard */ + reserved1 : 24; + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +#define HTC_LOOKAHEAD_REPORT_PREVALID_LSB 0 +#define HTC_LOOKAHEAD_REPORT_PREVALID_MASK 0x000000ff +#define HTC_LOOKAHEAD_REPORT_PREVALID_OFFSET 0x00000000 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000004 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000004 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000004 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000 +#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000004 +#define HTC_LOOKAHEAD_REPORT_POSTVALID_LSB 0 +#define HTC_LOOKAHEAD_REPORT_POSTVALID_MASK 0x000000ff +#define HTC_LOOKAHEAD_REPORT_POSTVALID_OFFSET 0x00000008 + +typedef PREPACK struct { + A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */ + LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8; +} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT; + +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000000 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000000 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000000 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000 +#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000000 + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __HTC_H__ */ diff --git a/fw/htc_services.h b/fw/htc_services.h new file mode 100644 index 000000000000..8021af245777 --- /dev/null +++ b/fw/htc_services.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + NMI_SERVICE_GROUP = 2, + HTT_SERVICE_GROUP = 3, + CFG_NV_SERVICE_GROUP = 4, + WDI_IPA_SERVICE_GROUP = 5, + PACKET_LOG_SERVICE_GROUP = 6, + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +} HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0) +#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1) + +#define HTT_DATA_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0) +#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1) +#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2) + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#define CFG_NV_SVC MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0) +#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0) + +#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP, 0) + +/* + * Directions for interconnect pipe configuration. + * These definitions may be used during configuration and are shared + * between Host and Target. + * + * Pipe Directions are relative to the Host, so PIPEDIR_IN means + * "coming IN over air through Target to Host" as with a WiFi Rx operation. + * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" + * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" + * Target since things that are "PIPEDIR_OUT" are coming IN to the Target + * over the interconnect. + */ +typedef A_UINT32 PIPEDIR; +#define PIPEDIR_NONE 0 +#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ +#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ +#define PIPEDIR_INOUT 3 /* bidirectional, target to target */ +#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT +#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ +#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0) + +/* Establish a mapping between a service/direction and a pipe. */ +struct service_to_pipe { + A_UINT32 service_id; + A_UINT32 pipedir; + A_UINT32 pipenum; +}; + +#endif /*HTC_SERVICES_H_ */ diff --git a/fw/htt.h b/fw/htt.h old mode 100755 new mode 100644 index 79a9a66d843e..731d1de68019 --- a/fw/htt.h +++ b/fw/htt.h @@ -34,10 +34,10 @@ #ifndef _HTT_H_ #define _HTT_H_ -#include /* A_UINT32 */ -#include /* PREPACK, POSTPACK */ +#include /* A_UINT32 */ +#include /* PREPACK, POSTPACK */ #ifdef ATHR_WIN_NWF -#pragma warning(disable:4214) /* bit field types other than int */ +#pragma warning(disable:4214) /*bit field types other than int */ #endif #include "wlan_defs.h" #include @@ -47,7 +47,7 @@ * (or more precisely, bus addresses), default to 32 bits. */ #ifndef HTT_PADDR64 - #define HTT_PADDR64 0 +#define HTT_PADDR64 0 #endif #ifndef offsetof @@ -152,25 +152,25 @@ #define HTT_NUM_TX_FRAG_DESC 1024 -#define HTT_WIFI_IP_VERSION(x,y) ((x) == (y)) +#define HTT_WIFI_IP_VERSION(x, y) ((x) == (y)) -#define HTT_CHECK_SET_VAL(field, val) \ - A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) +#define HTT_CHECK_SET_VAL(field, val) \ + A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) /* macros to assist in sign-extending fields from HTT messages */ #define HTT_SIGN_BIT_MASK(field) \ - ((field ## _M + (1 << field ## _S)) >> 1) -#define HTT_SIGN_BIT(_val, field) \ - (_val & HTT_SIGN_BIT_MASK(field)) -#define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ - (HTT_SIGN_BIT(_val, field) >> field ## _S) -#define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ - (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) -#define HTT_SIGN_BIT_EXTENSION(_val, field) \ - (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ - HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) -#define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ - (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) + ((field ## _M + (1 << field ## _S)) >> 1) + #define HTT_SIGN_BIT(_val, field) \ + (_val & HTT_SIGN_BIT_MASK(field)) + #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ + (HTT_SIGN_BIT(_val, field) >> field ## _S) + #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ + (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) + #define HTT_SIGN_BIT_EXTENSION(_val, field) \ + (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ + HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) + #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ + (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) /* @@ -193,35 +193,35 @@ /* HTT Access Category values */ enum HTT_AC_WMM { - /* WMM Access Categories */ - HTT_AC_WMM_BE = 0x0, - HTT_AC_WMM_BK = 0x1, - HTT_AC_WMM_VI = 0x2, - HTT_AC_WMM_VO = 0x3, - /* extension Access Categories */ - HTT_AC_EXT_NON_QOS = 0x4, - HTT_AC_EXT_UCAST_MGMT = 0x5, - HTT_AC_EXT_MCAST_DATA = 0x6, - HTT_AC_EXT_MCAST_MGMT = 0x7, + /* WMM Access Categories */ + HTT_AC_WMM_BE = 0x0, + HTT_AC_WMM_BK = 0x1, + HTT_AC_WMM_VI = 0x2, + HTT_AC_WMM_VO = 0x3, + /* extension Access Categories */ + HTT_AC_EXT_NON_QOS = 0x4, + HTT_AC_EXT_UCAST_MGMT = 0x5, + HTT_AC_EXT_MCAST_DATA = 0x6, + HTT_AC_EXT_MCAST_MGMT = 0x7, }; enum HTT_AC_WMM_MASK { - /* WMM Access Categories */ - HTT_AC_WMM_BE_MASK = (1 << HTT_AC_WMM_BE), - HTT_AC_WMM_BK_MASK = (1 << HTT_AC_WMM_BK), - HTT_AC_WMM_VI_MASK = (1 << HTT_AC_WMM_VI), - HTT_AC_WMM_VO_MASK = (1 << HTT_AC_WMM_VO), - /* extension Access Categories */ - HTT_AC_EXT_NON_QOS_MASK = (1 << HTT_AC_EXT_NON_QOS), - HTT_AC_EXT_UCAST_MGMT_MASK = (1 << HTT_AC_EXT_UCAST_MGMT), - HTT_AC_EXT_MCAST_DATA_MASK = (1 << HTT_AC_EXT_MCAST_DATA), - HTT_AC_EXT_MCAST_MGMT_MASK = (1 << HTT_AC_EXT_MCAST_MGMT), + /* WMM Access Categories */ + HTT_AC_WMM_BE_MASK = (1 << HTT_AC_WMM_BE), + HTT_AC_WMM_BK_MASK = (1 << HTT_AC_WMM_BK), + HTT_AC_WMM_VI_MASK = (1 << HTT_AC_WMM_VI), + HTT_AC_WMM_VO_MASK = (1 << HTT_AC_WMM_VO), + /* extension Access Categories */ + HTT_AC_EXT_NON_QOS_MASK = (1 << HTT_AC_EXT_NON_QOS), + HTT_AC_EXT_UCAST_MGMT_MASK = (1 << HTT_AC_EXT_UCAST_MGMT), + HTT_AC_EXT_MCAST_DATA_MASK = (1 << HTT_AC_EXT_MCAST_DATA), + HTT_AC_EXT_MCAST_MGMT_MASK = (1 << HTT_AC_EXT_MCAST_MGMT), }; -#define HTT_AC_MASK_WMM \ - (HTT_AC_WMM_BE_MASK | HTT_AC_WMM_BK_MASK | \ - HTT_AC_WMM_VI_MASK | HTT_AC_WMM_VO_MASK) -#define HTT_AC_MASK_EXT \ - (HTT_AC_EXT_NON_QOS_MASK | HTT_AC_EXT_UCAST_MGMT_MASK | \ - HTT_AC_EXT_MCAST_DATA_MASK | HTT_AC_EXT_MCAST_MGMT_MASK) +#define HTT_AC_MASK_WMM \ + (HTT_AC_WMM_BE_MASK | HTT_AC_WMM_BK_MASK | \ + HTT_AC_WMM_VI_MASK | HTT_AC_WMM_VO_MASK) +#define HTT_AC_MASK_EXT \ + (HTT_AC_EXT_NON_QOS_MASK | HTT_AC_EXT_UCAST_MGMT_MASK | \ + HTT_AC_EXT_MCAST_DATA_MASK | HTT_AC_EXT_MCAST_MGMT_MASK) #define HTT_AC_MASK_ALL (HTT_AC_MASK_WMM | HTT_AC_MASK_EXT) /* @@ -230,26 +230,26 @@ enum HTT_AC_WMM_MASK { * The bitmask contains 24 bits. */ enum htt_dbg_stats_type { - HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ - HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ - HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ - HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ - HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ - HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ - HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ - HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ - HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ - HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ - HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ - HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ - HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */ - HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ - HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ - HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ - /* bits 16-23 currently reserved */ + HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ + HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ + HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ + HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ + HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ + HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ + HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ + HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ + HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ + HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ + HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ + HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ + HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */ + HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ + HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ + HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ + /* bits 16-23 currently reserved */ - /* keep this last */ - HTT_DBG_NUM_STATS + /* keep this last */ + HTT_DBG_NUM_STATS }; /*=== HTT option selection TLVs === @@ -279,16 +279,16 @@ enum htt_dbg_stats_type { /*--- TLV header format - applies to all HTT option TLVs ---*/ enum HTT_OPTION_TLV_TAGS { - HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, - HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, - HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, - HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, - HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, + HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, + HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, + HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, + HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, + HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, }; PREPACK struct htt_option_tlv_header_t { - A_UINT8 tag; - A_UINT8 length; + A_UINT8 tag; + A_UINT8 length; } POSTPACK; #define HTT_OPTION_TLV_TAG_M 0x000000ff @@ -303,29 +303,29 @@ PREPACK struct htt_option_tlv_header_t { #define HTT_OPTION_TLV_VALUE0_M 0xffff0000 #define HTT_OPTION_TLV_VALUE0_S 16 -#define HTT_OPTION_TLV_TAG_SET(word, tag) \ - do { \ - HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ - (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ - } while (0) -#define HTT_OPTION_TLV_TAG_GET(word) \ - (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) +#define HTT_OPTION_TLV_TAG_SET(word, tag) \ + do { \ + HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ + (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ + } while (0) +#define HTT_OPTION_TLV_TAG_GET(word) \ + (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) -#define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ - do { \ - HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ - (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ - } while (0) -#define HTT_OPTION_TLV_LENGTH_GET(word) \ - (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) +#define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ + do { \ + HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ + (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ + } while (0) +#define HTT_OPTION_TLV_LENGTH_GET(word) \ + (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) -#define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ - do { \ - HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ - (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ - } while (0) -#define HTT_OPTION_TLV_VALUE0_GET(word) \ - (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) +#define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ + do { \ + HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ + (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ + } while (0) +#define HTT_OPTION_TLV_VALUE0_GET(word) \ + (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) /*--- format of specific HTT option TLVs ---*/ @@ -342,12 +342,12 @@ PREPACK struct htt_option_tlv_header_t { * default to providing bus addresses to the target in 32-bit format. */ enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES { - HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, - HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, + HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, + HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, }; PREPACK struct htt_option_tlv_ll_bus_addr_size_t { - struct htt_option_tlv_header_t hdr; - A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ + struct htt_option_tlv_header_t hdr; + A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ } POSTPACK; /* @@ -381,12 +381,12 @@ PREPACK struct htt_option_tlv_ll_bus_addr_size_t { * TLV. */ enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES { - HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, - HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, + HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, + HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, }; PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { - struct htt_option_tlv_header_t hdr; - A_UINT16 hl_suppress_tx_compl_ind; /* HL_SUPPRESS_TX_COMPL_IND enum */ + struct htt_option_tlv_header_t hdr; + A_UINT16 hl_suppress_tx_compl_ind;/*HL_SUPPRESS_TX_COMPL_IND enum*/ } POSTPACK; /* @@ -412,12 +412,12 @@ PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { * specify a txq_group_id larger than 3. */ enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { - HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, - /* - * values 1 through N specify the max number of tx queue groups - * the sender supports - */ - HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, + HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, + /* + * values 1 through N specify the max number of tx queue groups + * the sender supports + */ + HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, }; /* TEMPORARY backwards-compatibility alias for a typo fix - * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected @@ -425,10 +425,11 @@ enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { * to support the old name (with the typo) until all references to the * old name are replaced with the new name. */ -#define htt_option_tlv_mac_tx_queue_groups_t htt_option_tlv_max_tx_queue_groups_t +#define htt_option_tlv_mac_tx_queue_groups_t \ + htt_option_tlv_max_tx_queue_groups_t PREPACK struct htt_option_tlv_max_tx_queue_groups_t { - struct htt_option_tlv_header_t hdr; - A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ + struct htt_option_tlv_header_t hdr; + A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ } POSTPACK; /* @@ -457,37 +458,37 @@ PREPACK struct htt_option_tlv_max_tx_queue_groups_t { * extension descriptor is present. */ enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES { - HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, - HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, + HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, + HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, }; PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { - struct htt_option_tlv_header_t hdr; - A_UINT16 tx_msdu_desc_ext_support; /* SUPPORT_TX_MSDU_DESC_EXT enum */ + struct htt_option_tlv_header_t hdr; + A_UINT16 tx_msdu_desc_ext_support;/*SUPPORT_TX_MSDU_DESC_EXT enum*/ } POSTPACK; /*=== host -> target messages ===============================================*/ enum htt_h2t_msg_type { - HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, - HTT_H2T_MSG_TYPE_TX_FRM = 0x1, - HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, - HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, - HTT_H2T_MSG_TYPE_SYNC = 0x4, - HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, - HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, - DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ - HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, - HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, - HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ - HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, - HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, - HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, - HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, - HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, + HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, + HTT_H2T_MSG_TYPE_TX_FRM = 0x1, + HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, + HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, + HTT_H2T_MSG_TYPE_SYNC = 0x4, + HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, + HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, + DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ + HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, + HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, + HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /*per vdev amsdu subfrm limit*/ + HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, + HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, + HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, + HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, + HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, - /* keep this last */ - HTT_H2T_NUM_MSGS + /* keep this last */ + HTT_H2T_NUM_MSGS }; /* @@ -497,16 +498,16 @@ enum htt_h2t_msg_type { #define HTT_H2T_MSG_TYPE_M 0xff #define HTT_H2T_MSG_TYPE_S 0 -#define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ - (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ - } while (0) -#define HTT_H2T_MSG_TYPE_GET(word) \ - (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) +#define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ + (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ + } while (0) +#define HTT_H2T_MSG_TYPE_GET(word) \ + (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) /** - * @brief host -> target version number request message definition + * @brief target -> host version number request message definition * * |31 24|23 16|15 8|7 0| * |----------------+----------------+----------------+----------------| @@ -580,14 +581,20 @@ enum htt_h2t_msg_type { * Allow physical / bus addresses to be either a single 32-bit value, * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts */ -#define HTT_VAR_PADDR32(var_name) \ - A_UINT32 var_name -#define HTT_VAR_PADDR64_LE(var_name) \ - struct { \ - /* little-endian: lo precedes hi */ \ - A_UINT32 lo; \ - A_UINT32 hi; \ - } var_name + +/* + * Note that in this macro A_UINT32 has been converted to + * uint32_t only to address checkpath errors caused by declaring + * var_name as A_UINT32. + */ +#define HTT_VAR_PADDR32(var_name) uint32_t (var_name) + +#define HTT_VAR_PADDR64_LE(var_name) \ + struct { \ + /* little-endian: lo precedes hi */ \ + A_UINT32 lo; \ + A_UINT32 hi; \ + } var_name /* * TEMPLATE_HTT_TX_MSDU_DESC_T: @@ -596,195 +603,196 @@ enum htt_h2t_msg_type { * This macro is used to define both htt_tx_msdu_desc32_t and * htt_tx_msdu_desc64_t structs. */ -#define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ -PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ -{ \ - /* DWORD 0: flags and meta-data */ \ - A_UINT32 \ - msg_type: 8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ - \ - /* pkt_subtype - \ - * Detailed specification of the tx frame contents, extending the \ - * general specification provided by pkt_type. \ - * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ - * pkt_type | pkt_subtype \ - * ============================================================== \ - * 802.3 | bit 0:3 - Reserved \ - * | bit 4: 0x0 - Copy-Engine Classification Results \ - * | not appended to the HTT message \ - * | 0x1 - Copy-Engine Classification Results \ - * | appended to the HTT message in the \ - * | format: \ - * | [HTT tx desc, frame header, \ - * | CE classification results] \ - * | The CE classification results begin \ - * | at the next 4-byte boundary after \ - * | the frame header. \ - * ------------+------------------------------------------------- \ - * Eth2 | bit 0:3 - Reserved \ - * | bit 4: 0x0 - Copy-Engine Classification Results \ - * | not appended to the HTT message \ - * | 0x1 - Copy-Engine Classification Results \ - * | appended to the HTT message. \ - * | See the above specification of the \ - * | CE classification results location. \ - * ------------+------------------------------------------------- \ - * native WiFi | bit 0:3 - Reserved \ - * | bit 4: 0x0 - Copy-Engine Classification Results \ - * | not appended to the HTT message \ - * | 0x1 - Copy-Engine Classification Results \ - * | appended to the HTT message. \ - * | See the above specification of the \ - * | CE classification results location. \ - * ------------+------------------------------------------------- \ - * mgmt | 0x0 - 802.11 MAC header absent \ - * | 0x1 - 802.11 MAC header present \ - * ------------+------------------------------------------------- \ - * raw | bit 0: 0x0 - 802.11 MAC header absent \ - * | 0x1 - 802.11 MAC header present \ - * | bit 1: 0x0 - allow aggregation \ - * | 0x1 - don't allow aggregation \ - * | bit 2: 0x0 - perform encryption \ - * | 0x1 - don't perform encryption \ - * | bit 3: 0x0 - perform tx classification / queuing \ - * | 0x1 - don't perform tx classification; \ - * | insert the frame into the "misc" \ - * | tx queue \ - * | bit 4: 0x0 - Copy-Engine Classification Results \ - * | not appended to the HTT message \ - * | 0x1 - Copy-Engine Classification Results \ - * | appended to the HTT message. \ - * | See the above specification of the \ - * | CE classification results location. \ - */ \ - pkt_subtype: 5, \ - \ - /* pkt_type - \ - * General specification of the tx frame contents. \ - * The htt_pkt_type enum should be used to specify and check the \ - * value of this field. \ - */ \ - pkt_type: 3, \ - \ - /* vdev_id - \ - * ID for the vdev that is sending this tx frame. \ - * For certain non-standard packet types, e.g. pkt_type == raw \ - * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ - * This field is used primarily for determining where to queue \ - * broadcast and multicast frames. \ - */ \ - vdev_id: 6, \ - /* ext_tid - \ - * The extended traffic ID. \ - * If the TID is unknown, the extended TID is set to \ - * HTT_TX_EXT_TID_INVALID. \ - * If the tx frame is QoS data, then the extended TID has the 0-15 \ - * value of the QoS TID. \ - * If the tx frame is non-QoS data, then the extended TID is set to \ - * HTT_TX_EXT_TID_NON_QOS. \ - * If the tx frame is multicast or broadcast, then the extended TID \ - * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ - */ \ - ext_tid: 5, \ - \ - /* postponed - \ - * This flag indicates whether the tx frame has been downloaded to \ - * the target before but discarded by the target, and now is being \ - * downloaded again; or if this is a new frame that is being \ - * downloaded for the first time. \ - * This flag allows the target to determine the correct order for \ - * transmitting new vs. old frames. \ - * value: 0 -> new frame, 1 -> re-send of a previously sent frame \ - * This flag only applies to HL systems, since in LL systems, \ - * the tx flow control is handled entirely within the target. \ - */ \ - postponed: 1, \ - \ - /* extension - \ - * This flag indicates whether a HTT tx MSDU extension descriptor \ - * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor. \ - * \ - * 0x0 - no extension MSDU descriptor is present \ - * 0x1 - an extension MSDU descriptor immediately follows the \ - * regular MSDU descriptor \ - */ \ - extension: 1, \ - \ - /* cksum_offload - \ - * This flag indicates whether checksum offload is enabled or not \ - * for this frame. Target FW use this flag to turn on HW checksumming \ - * 0x0 - No checksum offload \ - * 0x1 - L3 header checksum only \ - * 0x2 - L4 checksum only \ - * 0x3 - L3 header checksum + L4 checksum \ - */ \ - cksum_offload: 2, \ - \ - /* tx_comp_req - \ - * This flag indicates whether Tx Completion \ - * from fw is required or not. \ - * This flag is only relevant if tx completion is not \ - * universally enabled. \ - * For all LL systems, tx completion is mandatory, \ - * so this flag will be irrelevant. \ - * For HL systems tx completion is optional, but HL systems in which \ - * the bus throughput exceeds the WLAN throughput will \ - * probably want to always use tx completion, and thus \ - * would not check this flag. \ - * This flag is required when tx completions are not used universally, \ - * but are still required for certain tx frames for which \ - * an OTA delivery acknowledgment is needed by the host. \ - * In practice, this would be for HL systems in which the \ - * bus throughput is less than the WLAN throughput. \ - * \ - * 0x0 - Tx Completion Indication from Fw not required \ - * 0x1 - Tx Completion Indication from Fw is required \ - */ \ - tx_compl_req: 1; \ - \ - \ - /* DWORD 1: MSDU length and ID */ \ - A_UINT32 \ - len: 16, /* MSDU length, in bytes */ \ - id: 16; /* MSDU ID used to identify the MSDU to the host, \ - * and this id is used to calculate fragmentation \ - * descriptor pointer inside the target based on \ - * the base address, configured inside the target. \ - */ \ - \ - /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ - /* frags_desc_ptr - \ - * The fragmentation descriptor pointer tells the HW's MAC DMA \ - * where the tx frame's fragments reside in memory. \ - * This field only applies to LL systems, since in HL systems the \ - * (degenerate single-fragment) fragmentation descriptor is created \ - * within the target. \ - */ \ - _paddr__frags_desc_ptr_; \ - \ - /* DWORD 3 (or 4): peerid, chanfreq */ \ - /* \ - * Peer ID : Target can use this value to know which peer-id packet \ - * destined to. \ - * It's intended to be specified by host in case of NAWDS. \ - */ \ - A_UINT16 peerid; \ - \ - /* \ - * Channel frequency: This identifies the desired channel \ - * frequency (in mhz) for tx frames. This is used by FW to help \ - * determine when it is safe to transmit or drop frames for \ - * off-channel operation. \ - * The default value of zero indicates to FW that the corresponding \ - * VDEV's home channel (if there is one) is the desired channel \ - * frequency. \ - */ \ - A_UINT16 chanfreq; \ - \ - /* Reason reserved is commented is increasing the htt structure size \ - * leads to some wierd issues. Contact Raj/Kyeyoon for more info \ - * A_UINT32 reserved_dword3_bits0_31; \ - */ \ +#define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ +PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ +{ \ + /* DWORD 0: flags and meta-data */ \ + A_UINT32 \ + msg_type:8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ + \ + /* pkt_subtype - \ + * Detailed specification of the tx frame contents, extending the \ + * general specification provided by pkt_type. \ + * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ + *pkt_type | pkt_subtype \ + *============================================================== \ + *802.3 | bit 0:3 - Reserved \ + * | bit 4: 0x0 - Copy-Engine Classification Results \ + * | not appended to the HTT message \ + * | 0x1 - Copy-Engine Classification Results \ + * | appended to the HTT message in the \ + * | format: \ + * | [HTT tx desc, frame header, \ + * | CE classification results] \ + * | The CE classification results begin \ + * | at the next 4-byte boundary after \ + * | the frame header. \ + *------------+------------------------------------------------- \ + *Eth2 | bit 0:3 - Reserved \ + * | bit 4: 0x0 - Copy-Engine Classification Results \ + * | not appended to the HTT message \ + * | 0x1 - Copy-Engine Classification Results \ + * | appended to the HTT message. \ + * | See the above specification of the \ + * | CE classification results location. \ + *------------+------------------------------------------------- \ + *native WiFi | bit 0:3 - Reserved \ + * | bit 4: 0x0 - Copy-Engine Classification Results \ + * | not appended to the HTT message \ + * | 0x1 - Copy-Engine Classification Results \ + * | appended to the HTT message. \ + * | See the above specification of the \ + * | CE classification results location. \ + *------------+------------------------------------------------- \ + *mgmt | 0x0 - 802.11 MAC header absent \ + * | 0x1 - 802.11 MAC header present \ + *------------+------------------------------------------------- \ + *raw | bit 0: 0x0 - 802.11 MAC header absent \ + * | 0x1 - 802.11 MAC header present \ + * | bit 1: 0x0 - allow aggregation \ + * | 0x1 - don't allow aggregation \ + * | bit 2: 0x0 - perform encryption \ + * | 0x1 - don't perform encryption \ + * | bit 3: 0x0 - perform tx classification / queuing \ + * | 0x1 - don't perform tx classification; \ + * | insert the frame into the "misc" \ + * | tx queue \ + * | bit 4: 0x0 - Copy-Engine Classification Results \ + * | not appended to the HTT message \ + * | 0x1 - Copy-Engine Classification Results \ + * | appended to the HTT message. \ + * | See the above specification of the \ + * | CE classification results location. \ + */ \ + pkt_subtype:5, \ + \ + /* pkt_type - \ + * General specification of the tx frame contents. \ + * The htt_pkt_type enum should be used to specify \ + * and check the value of this field. \ + */ \ + pkt_type:3, \ + \ + /* vdev_id - \ + * ID for the vdev that is sending this tx frame. \ + * For certain non-standard packet types, e.g. pkt_type == raw \ + * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ + * This field is used primarily for determining where to queue \ + * broadcast and multicast frames. \ + */ \ + vdev_id:6, \ + /* ext_tid - \ + * The extended traffic ID. \ + * If the TID is unknown, the extended TID is set to \ + * HTT_TX_EXT_TID_INVALID. \ + * If the tx frame is QoS data, then the extended TID has the 0-15 \ + * value of the QoS TID. \ + * If the tx frame is non-QoS data, then the extended TID is set to \ + * HTT_TX_EXT_TID_NON_QOS. \ + * If the tx frame is multicast or broadcast, then the extended TID \ + * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ + */ \ + ext_tid:5, \ + \ + /* postponed - \ + * This flag indicates whether the tx frame has been downloaded to \ + * the target before but discarded by the target, and now is being \ + * downloaded again; or if this is a new frame that is being \ + * downloaded for the first time. \ + * This flag allows the target to determine the correct order for \ + * transmitting new vs. old frames. \ + * value: 0 -> new frame, 1 -> re-send of a previously + * sent frame \ + * This flag only applies to HL systems, since in LL systems, \ + * the tx flow control is handled entirely within the target. \ + */ \ + postponed:1, \ + \ + /* extension - \ + * This flag indicates whether a HTT tx MSDU extension descriptor\ + * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor.\ + * \ + * 0x0 - no extension MSDU descriptor is present \ + * 0x1 - an extension MSDU descriptor immediately follows the \ + * regular MSDU descriptor \ + */ \ + extension:1, \ + \ + /* cksum_offload - \ + * This flag indicates whether checksum offload is enabled or not \ + * for this frame. Target FW use this flag to turn on HW checksumming \ + * 0x0 - No checksum offload \ + * 0x1 - L3 header checksum only \ + * 0x2 - L4 checksum only \ + * 0x3 - L3 header checksum + L4 checksum \ + */ \ + cksum_offload:2, \ + \ + /* tx_comp_req - \ + * This flag indicates whether Tx Completion \ + * from fw is required or not. \ + * This flag is only relevant if tx completion is not \ + * universally enabled. \ + * For all LL systems, tx completion is mandatory, \ + * so this flag will be irrelevant. \ + * For HL systems tx completion is optional, but HL systems in which \ + * the bus throughput exceeds the WLAN throughput will \ + * probably want to always use tx completion, and thus \ + * would not check this flag. \ + * This flag is required when tx completions are not used universally, \ + * but are still required for certain tx frames for which \ + * an OTA delivery acknowledgment is needed by the host. \ + * In practice, this would be for HL systems in which the \ + * bus throughput is less than the WLAN throughput. \ + * \ + * 0x0 - Tx Completion Indication from Fw not required \ + * 0x1 - Tx Completion Indication from Fw is required \ + */ \ + tx_compl_req:1; \ + \ + \ + /* DWORD 1: MSDU length and ID */ \ + A_UINT32 \ + len:16, /* MSDU length, in bytes */ \ + id:16; /* MSDU ID used to identify the MSDU to the host, \ + * and this id is used to calculate fragmentation \ + * descriptor pointer inside the target based on \ + * the base address, configured inside the target. \ + */ \ + \ + /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ + /* frags_desc_ptr - \ + * The fragmentation descriptor pointer tells the HW's MAC DMA \ + * where the tx frame's fragments reside in memory. \ + * This field only applies to LL systems, since in HL systems the \ + * (degenerate single-fragment) fragmentation descriptor is created \ + * within the target. \ + */ \ + _paddr__frags_desc_ptr_; \ + \ + /* DWORD 3 (or 4): peerid, chanfreq */ \ + /* \ + * Peer ID : Target can use this value to know which peer-id packet \ + * destined to. \ + * It's intended to be specified by host in case of NAWDS. \ + */ \ + A_UINT16 peerid; \ + \ + /* \ + * Channel frequency: This identifies the desired channel \ + * frequency (in mhz) for tx frames. This is used by FW to help \ + * determine when it is safe to transmit or drop frames for \ + * off-channel operation. \ + * The default value of zero indicates to FW that the \ + * corresponding VDEV's home channel (if there is one) is \ + * the desired channel frequency. \ + */ \ + A_UINT16 chanfreq; \ + \ + /* Reason reserved is commented is increasing the htt + * structure size leads to some wierd issues. + * A_UINT32 reserved_dword3_bits0_31; \ + */ \ } POSTPACK /* define a htt_tx_msdu_desc32_t type */ TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr)); @@ -795,9 +803,9 @@ TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t */ #if HTT_PADDR64 - #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t +#define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t #else - #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t +#define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t #endif /* decriptor information for Management frame*/ @@ -808,22 +816,22 @@ TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 extern A_UINT32 mgmt_hdr_len; PREPACK struct htt_mgmt_tx_desc_t { - A_UINT32 msg_type; + A_UINT32 msg_type; #if HTT_PADDR64 - A_UINT64 frag_paddr; /* DMAble address of the data */ + A_UINT64 frag_paddr; /* DMAble address of the data */ #else - A_UINT32 frag_paddr; /* DMAble address of the data */ + A_UINT32 frag_paddr; /* DMAble address of the data */ #endif - A_UINT32 desc_id; /* returned to host during completion - * to free the meory*/ - A_UINT32 len; /* Fragment length */ - A_UINT32 vdev_id; /* virtual device ID*/ - A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ + A_UINT32 desc_id; /* returned to host during completion + * to free the meory*/ + A_UINT32 len; /* Fragment length */ + A_UINT32 vdev_id; /* virtual device ID */ + A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ } POSTPACK; PREPACK struct htt_mgmt_tx_compl_ind { - A_UINT32 desc_id; - A_UINT32 status; + A_UINT32 desc_id; + A_UINT32 status; } POSTPACK; /* @@ -847,30 +855,30 @@ PREPACK struct htt_mgmt_tx_compl_ind { #define HTT_TX_HDR_SIZE_ETHERNET 14 #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW -A_COMPILE_TIME_ASSERT( - htt_encap_hdr_size_max_check_nwifi, - HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_NATIVE_WIFI); -A_COMPILE_TIME_ASSERT( - htt_encap_hdr_size_max_check_enet, - HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_ETHERNET); +A_COMPILE_TIME_ASSERT(htt_encap_hdr_size_max_check_nwifi, + HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= + HTT_TX_HDR_SIZE_NATIVE_WIFI); +A_COMPILE_TIME_ASSERT(htt_encap_hdr_size_max_check_enet, + HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= + HTT_TX_HDR_SIZE_ETHERNET); -#define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ -#define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */ +#define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ +#define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */ #define HTT_TX_HDR_SIZE_802_1Q 4 #define HTT_TX_HDR_SIZE_LLC_SNAP 8 -#define HTT_COMMON_TX_FRM_HDR_LEN \ - (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ - HTT_TX_HDR_SIZE_802_1Q + \ - HTT_TX_HDR_SIZE_LLC_SNAP) +#define HTT_COMMON_TX_FRM_HDR_LEN \ + (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ + HTT_TX_HDR_SIZE_802_1Q + \ + HTT_TX_HDR_SIZE_LLC_SNAP) -#define HTT_HL_TX_FRM_HDR_LEN \ - (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) +#define HTT_HL_TX_FRM_HDR_LEN \ + (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) -#define HTT_LL_TX_FRM_HDR_LEN \ - (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) +#define HTT_LL_TX_FRM_HDR_LEN \ + (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t) @@ -946,10 +954,10 @@ A_COMPILE_TIME_ASSERT( /* dword 3 */ #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12 -#define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ - (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) -#define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ - (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) +#define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ + (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) +#define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ + (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) #if HTT_PADDR64 #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 @@ -961,28 +969,28 @@ A_COMPILE_TIME_ASSERT( #define HTT_TX_DESC_PEER_ID_M 0x0000ffff #define HTT_TX_DESC_PEER_ID_S 0 - /* - * TEMPORARY: - * The original definitions for the PEER_ID fields contained typos - * (with _DESC_PADDR appended to this PEER_ID field name). - * Retain deprecated original names for PEER_ID fields until all code that - * refers to them has been updated. - */ - #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ - HTT_TX_DESC_PEER_ID_OFFSET_BYTES - #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ - HTT_TX_DESC_PEER_ID_OFFSET_DWORD - #define HTT_TX_DESC_PEERID_DESC_PADDR_M \ - HTT_TX_DESC_PEER_ID_M - #define HTT_TX_DESC_PEERID_DESC_PADDR_S \ - HTT_TX_DESC_PEER_ID_S +/* + * TEMPORARY: + * The original definitions for the PEER_ID fields contained typos + * (with _DESC_PADDR appended to this PEER_ID field name). + * Retain deprecated original names for PEER_ID fields until all code that + * refers to them has been updated. + */ +#define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ + HTT_TX_DESC_PEER_ID_OFFSET_BYTES +#define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ + HTT_TX_DESC_PEER_ID_OFFSET_DWORD +#define HTT_TX_DESC_PEERID_DESC_PADDR_M \ + HTT_TX_DESC_PEER_ID_M +#define HTT_TX_DESC_PEERID_DESC_PADDR_S \ + HTT_TX_DESC_PEER_ID_S #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 /* to dword with chan freq */ #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 /* to dword with chan freq */ -#define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ - (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) -#define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ - (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) +#define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ + (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) +#define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ + (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) #if HTT_PADDR64 #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 @@ -995,131 +1003,131 @@ A_COMPILE_TIME_ASSERT( #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000 #define HTT_TX_DESC_CHAN_FREQ_S 16 -#define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ - (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) -#define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ - } while (0) +#define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ + (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) +#define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ + } while (0) -#define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ - (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) -#define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ - } while (0) +#define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ + (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) +#define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ + } while (0) -#define HTT_TX_DESC_PKT_TYPE_GET(_var) \ - (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) -#define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ - } while (0) +#define HTT_TX_DESC_PKT_TYPE_GET(_var) \ + (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) +#define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ + } while (0) -#define HTT_TX_DESC_VDEV_ID_GET(_var) \ - (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) -#define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ - } while (0) +#define HTT_TX_DESC_VDEV_ID_GET(_var) \ + (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) +#define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ + } while (0) -#define HTT_TX_DESC_EXT_TID_GET(_var) \ - (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) -#define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ - } while (0) +#define HTT_TX_DESC_EXT_TID_GET(_var) \ + (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) +#define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ + } while (0) -#define HTT_TX_DESC_POSTPONED_GET(_var) \ - (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) -#define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ - } while (0) +#define HTT_TX_DESC_POSTPONED_GET(_var) \ + (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) +#define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ + } while (0) -#define HTT_TX_DESC_EXTENSION_GET(_var) \ - (((_var) & HTT_TX_DESC_EXTENSION_M) >> HTT_TX_DESC_EXTENSION_S) +#define HTT_TX_DESC_EXTENSION_GET(_var) \ + (((_var) & HTT_TX_DESC_EXTENSION_M) >> HTT_TX_DESC_EXTENSION_S) #define HTT_TX_DESC_EXTENSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_EXTENSION, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_EXTENSION_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_EXTENSION, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_EXTENSION_S)); \ + } while (0) -#define HTT_TX_DESC_FRM_LEN_GET(_var) \ - (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) -#define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ - } while (0) +#define HTT_TX_DESC_FRM_LEN_GET(_var) \ + (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) +#define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ + } while (0) -#define HTT_TX_DESC_FRM_ID_GET(_var) \ - (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) -#define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ - } while (0) +#define HTT_TX_DESC_FRM_ID_GET(_var) \ + (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) +#define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ + } while (0) -#define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ - (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) -#define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ - } while (0) +#define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ + (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) +#define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ + } while (0) -#define HTT_TX_DESC_TX_COMP_GET(_var) \ - (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) -#define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ - } while (0) +#define HTT_TX_DESC_TX_COMP_GET(_var) \ + (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) +#define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ + } while (0) -#define HTT_TX_DESC_PEER_ID_GET(_var) \ - (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) -#define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ - } while (0) +#define HTT_TX_DESC_PEER_ID_GET(_var) \ + (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) +#define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ + } while (0) -#define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ - (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) -#define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ - ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ - } while (0) +#define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ + (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) +#define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ + ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ + } while (0) /* enums used in the HTT tx MSDU extension descriptor */ enum { - htt_tx_guard_interval_regular = 0, - htt_tx_guard_interval_short = 1, + htt_tx_guard_interval_regular = 0, + htt_tx_guard_interval_short = 1, }; enum { - htt_tx_preamble_type_ofdm = 0, - htt_tx_preamble_type_cck = 1, - htt_tx_preamble_type_ht = 2, - htt_tx_preamble_type_vht = 3, + htt_tx_preamble_type_ofdm = 0, + htt_tx_preamble_type_cck = 1, + htt_tx_preamble_type_ht = 2, + htt_tx_preamble_type_vht = 3, }; enum { - htt_tx_bandwidth_5MHz = 0, - htt_tx_bandwidth_10MHz = 1, - htt_tx_bandwidth_20MHz = 2, - htt_tx_bandwidth_40MHz = 3, - htt_tx_bandwidth_80MHz = 4, - htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ + htt_tx_bandwidth_5MHz = 0, + htt_tx_bandwidth_10MHz = 1, + htt_tx_bandwidth_20MHz = 2, + htt_tx_bandwidth_40MHz = 3, + htt_tx_bandwidth_80MHz = 4, + htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ }; /** @@ -1133,146 +1141,142 @@ enum { * tx specs for each frame. */ PREPACK struct htt_tx_msdu_desc_ext_t { - /* DWORD 0: flags */ - A_UINT32 - valid_pwr: 1, /* bit 0: if set, tx pwr spec is valid */ - valid_mcs_mask: 1, /* bit 1: if set, tx MCS mask spec is valid */ - valid_nss_mask: 1, /* bit 2: if set, tx Nss mask spec is valid */ - valid_guard_interval: 1, /* bit 3: if set, tx guard intv spec is valid*/ - valid_preamble_type_mask: 1, /* 4: if set, tx preamble mask is valid */ - valid_chainmask: 1, /* bit 5: if set, tx chainmask spec is valid */ - valid_retries: 1, /* bit 6: if set, tx retries spec is valid */ - valid_bandwidth: 1, /* bit 7: if set, tx bandwidth spec is valid */ - valid_expire_tsf: 1, /* bit 8: if set, tx expire TSF spec is valid*/ - is_dsrc: 1, /* bit 9: if set, MSDU is a DSRC frame */ - reserved0_31_7: 22; /* bits 31:10 - unused, set to 0x0 */ + /* DWORD 0: flags */ + A_UINT32 valid_pwr:1,/* bit 0:if set, tx pwr spec is valid */ + valid_mcs_mask:1,/* bit 1:if set, tx MCS mask spec is valid */ + valid_nss_mask:1,/* bit 2:if set, tx Nss mask spec is valid */ + valid_guard_interval:1,/* bit 3:if set, tx guard intv spec is valid */ + valid_preamble_type_mask:1,/* 4:if set, tx preamble mask is valid */ + valid_chainmask:1,/* bit 5:if set, tx chainmask spec is valid */ + valid_retries:1,/* bit 6:if set, tx retries spec is valid */ + valid_bandwidth:1,/* bit 7:if set, tx bandwidth spec is valid */ + valid_expire_tsf:1,/* bit 8:if set, tx expire TSF spec is valid */ + is_dsrc:1, /* bit 9:if set, MSDU is a DSRC frame */ + reserved0_31_7:22; /* bits 31:10 - unused, set to 0x0 */ - /* DWORD 1: tx power, tx rate, tx BW */ - A_UINT32 - /* pwr - - * Specify what power the tx frame needs to be transmitted at. - * The power a signed (two's complement) value is in units of 0.5 dBm. - * The value needs to be appropriately sign-extended when extracting - * the value from the message and storing it in a variable that is - * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro - * automatically handles this sign-extension.) - * If the transmission uses multiple tx chains, this power spec is - * the total transmit power, assuming incoherent combination of - * per-chain power to produce the total power. - */ - pwr: 8, + /* DWORD 1:tx power, tx rate, tx BW */ + A_UINT32 + /* pwr - + * Specify what power the tx frame needs to be transmitted at. + * The power a signed (two's complement) value is in units of 0.5 dBm. + * The value needs to be appropriately sign-extended when extracting + * the value from the message and storing it in a variable that is + * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro + * automatically handles this sign-extension.) + * If the transmission uses multiple tx chains, this power spec is + * the total transmit power, assuming incoherent combination of + * per-chain power to produce the total power. + */ + pwr:8, + /* mcs_mask - + * Specify the allowable values for MCS index (modulation and coding) + * to use for transmitting the frame. + * + * For HT / VHT preamble types, this mask directly corresponds to + * the HT or VHT MCS indices that are allowed. For each bit N set + * within the mask, MCS index N is allowed for transmitting the frame. + * For legacy CCK and OFDM rates, separate bits are provided for CCK + * rates versus OFDM rates, so the host has the option of specifying + * that the target must transmit the frame with CCK or OFDM rates + * (not HT or VHT), but leaving the decision to the target whether + * to use CCK or OFDM. + * + * For CCK and OFDM, the bits within this mask are interpreted as + * follows: + * bit 0 -> CCK 1 Mbps rate is allowed + * bit 1 -> CCK 2 Mbps rate is allowed + * bit 2 -> CCK 5.5 Mbps rate is allowed + * bit 3 -> CCK 11 Mbps rate is allowed + * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed + * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed + * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed + * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed + * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed + * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed + * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed + * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed + * + * The MCS index specification needs to be compatible with the + * bandwidth mask specification. For example, a MCS index == 9 + * specification is inconsistent with a preamble type == VHT, + * Nss == 1, and channel bandwidth == 20 MHz. + * + * Furthermore, the host has only a limited ability to specify to + * the target to select from HT + legacy rates, or VHT + legacy rates, + * since this mcs_mask can specify either HT/VHT rates or legacy rates. + */ + mcs_mask:12, + /* nss_mask - + * Specify which numbers of spatial streams (MIMO factor) are permitted. + * Each bit in this mask corresponds to a Nss value: + * bit 0: if set, Nss = 1 (non-MIMO) is permitted + * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted + * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted + * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted + * The values in the Nss mask must be suitable for the recipient, e.g. + * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a + * recipient which only supports 2x2 MIMO. + */ + nss_mask:4, + /* guard_interval - + * Specify a htt_tx_guard_interval enum value to indicate whether + * the transmission should use a regular guard interval or a + * short guard interval. + */ + guard_interval:1, + /* preamble_type_mask - + * Specify which preamble types (CCK, OFDM, HT, VHT) the target + * may choose from for transmitting this frame. + * The bits in this mask correspond to the values in the + * htt_tx_preamble_type enum. For example, to allow the target + * to transmit the frame as either CCK or OFDM, this field would + * be set to + * (1 << htt_tx_preamble_type_ofdm) | + * (1 << htt_tx_preamble_type_cck) + */ + preamble_type_mask:4, - /* mcs_mask - - * Specify the allowable values for MCS index (modulation and coding) - * to use for transmitting the frame. - * - * For HT / VHT preamble types, this mask directly corresponds to - * the HT or VHT MCS indices that are allowed. For each bit N set - * within the mask, MCS index N is allowed for transmitting the frame. - * For legacy CCK and OFDM rates, separate bits are provided for CCK - * rates versus OFDM rates, so the host has the option of specifying - * that the target must transmit the frame with CCK or OFDM rates - * (not HT or VHT), but leaving the decision to the target whether - * to use CCK or OFDM. - * - * For CCK and OFDM, the bits within this mask are interpreted as - * follows: - * bit 0 -> CCK 1 Mbps rate is allowed - * bit 1 -> CCK 2 Mbps rate is allowed - * bit 2 -> CCK 5.5 Mbps rate is allowed - * bit 3 -> CCK 11 Mbps rate is allowed - * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed - * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed - * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed - * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed - * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed - * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed - * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed - * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed - * - * The MCS index specification needs to be compatible with the - * bandwidth mask specification. For example, a MCS index == 9 - * specification is inconsistent with a preamble type == VHT, - * Nss == 1, and channel bandwidth == 20 MHz. - * - * Furthermore, the host has only a limited ability to specify to - * the target to select from HT + legacy rates, or VHT + legacy rates, - * since this mcs_mask can specify either HT/VHT rates or legacy rates. - */ - mcs_mask: 12, + reserved1_31_29:3; /* unused, set to 0x0 */ - /* nss_mask - - * Specify which numbers of spatial streams (MIMO factor) are permitted. - * Each bit in this mask corresponds to a Nss value: - * bit 0: if set, Nss = 1 (non-MIMO) is permitted - * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted - * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted - * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted - * The values in the Nss mask must be suitable for the recipient, e.g. - * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a - * recipient which only supports 2x2 MIMO. - */ - nss_mask: 4, + /* DWORD 2: tx chain mask, tx retries */ + A_UINT32 + /* chain_mask - specify which chains to transmit from */ + chain_mask:4, + /* retry_limit - + * Specify the maximum number of transmissions, including the + * initial transmission, to attempt before giving up if no ack + * is received. + * If the tx rate is specified, then all retries shall use the + * same rate as the initial transmission. + * If no tx rate is specified, the target can choose whether to + * retain the original rate during the retransmissions, or to + * fall back to a more robust rate. + */ + retry_limit:4, - /* guard_interval - - * Specify a htt_tx_guard_interval enum value to indicate whether - * the transmission should use a regular guard interval or a - * short guard interval. - */ - guard_interval: 1, + /* bandwidth_mask - + * Specify what channel widths may be used for the transmission. + * A value of zero indicates "don't care" - the target may choose + * the transmission bandwidth. + * The bits within this mask correspond to the htt_tx_bandwidth + * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. + * The bandwidth_mask must be consistent with the + * preamble_type_mask * and mcs_mask specs, if they are + * provided. For example, + * 80 MHz and 160 MHz can only be enabled in the mask + * if preamble_type == VHT. + */ + bandwidth_mask:6, - /* preamble_type_mask - - * Specify which preamble types (CCK, OFDM, HT, VHT) the target - * may choose from for transmitting this frame. - * The bits in this mask correspond to the values in the - * htt_tx_preamble_type enum. For example, to allow the target - * to transmit the frame as either CCK or OFDM, this field would - * be set to - * (1 << htt_tx_preamble_type_ofdm) | - * (1 << htt_tx_preamble_type_cck) - */ - preamble_type_mask: 4, + reserved2_31_14:18; /* unused, set to 0x0 */ - reserved1_31_29: 3; /* unused, set to 0x0 */ + /* DWORD 3: tx expiry time (TSF) LSBs */ + A_UINT32 expire_tsf_lo; - /* DWORD 2: tx chain mask, tx retries */ - A_UINT32 - /* chain_mask - specify which chains to transmit from */ - chain_mask: 4, + /* DWORD 4: tx expiry time (TSF) MSBs */ + A_UINT32 expire_tsf_hi; - /* retry_limit - - * Specify the maximum number of transmissions, including the - * initial transmission, to attempt before giving up if no ack - * is received. - * If the tx rate is specified, then all retries shall use the - * same rate as the initial transmission. - * If no tx rate is specified, the target can choose whether to - * retain the original rate during the retransmissions, or to - * fall back to a more robust rate. - */ - retry_limit: 4, - - /* bandwidth_mask - - * Specify what channel widths may be used for the transmission. - * A value of zero indicates "don't care" - the target may choose - * the transmission bandwidth. - * The bits within this mask correspond to the htt_tx_bandwidth - * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. - * The bandwidth_mask must be consistent with the preamble_type_mask - * and mcs_mask specs, if they are provided. For example, 80 MHz and - * 160 MHz can only be enabled in the mask if preamble_type == VHT. - */ - bandwidth_mask: 6, - - reserved2_31_14: 18; /* unused, set to 0x0 */ - - /* DWORD 3: tx expiry time (TSF) LSBs */ - A_UINT32 expire_tsf_lo; - - /* DWORD 4: tx expiry time (TSF) MSBs */ - A_UINT32 expire_tsf_hi; - - A_UINT32 reserved_for_future_expansion_set_to_zero[3]; + A_UINT32 reserved_for_future_expansion_set_to_zero[3]; } POSTPACK; /* DWORD 0 */ @@ -1320,181 +1324,184 @@ PREPACK struct htt_tx_msdu_desc_ext_t { /* DWORD 0 */ #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL( \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ - ((_var) |= ((_val) \ - << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL( \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ + ((_var) |= ((_val) \ + << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >>\ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL( \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ - ((_var) |= ((_val) \ - << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL( \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ + ((_var) |= ((_val) \ + << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ +} while (0) #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ - HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ + HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ +} while (0) /* DWORD 1 */ #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ - HTT_TX_MSDU_EXT_DESC_PWR_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ + HTT_TX_MSDU_EXT_DESC_PWR_S) #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \ - (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ - HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) + (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ + HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \ - ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ - HTT_TX_MSDU_EXT_DESC_PWR_M) + ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ + HTT_TX_MSDU_EXT_DESC_PWR_M) #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ + } while (0) #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ + } while (0) #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ - HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ + HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ + } while (0) #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ + } while (0) /* DWORD 2 */ #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ + } while (0) #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ - HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ + HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ + } while (0) #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ - HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) + (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ + HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ + } while (0) typedef enum { - HTT_11AX_HE_LTF_SUBTYPE_1X, - HTT_11AX_HE_LTF_SUBTYPE_2X, - HTT_11AX_HE_LTF_SUBTYPE_4X, + HTT_11AX_HE_LTF_SUBTYPE_1X, + HTT_11AX_HE_LTF_SUBTYPE_2X, + HTT_11AX_HE_LTF_SUBTYPE_4X, } htt_11ax_ltf_subtype_t; typedef enum { - HTT_TX_MSDU_EXT2_DESC_PREAM_OFDM, - HTT_TX_MSDU_EXT2_DESC_PREAM_CCK, - HTT_TX_MSDU_EXT2_DESC_PREAM_HT , - HTT_TX_MSDU_EXT2_DESC_PREAM_VHT, - HTT_TX_MSDU_EXT2_DESC_PREAM_HE_SU, - HTT_TX_MSDU_EXT2_DESC_PREAM_HE_EXT_SU, + HTT_TX_MSDU_EXT2_DESC_PREAM_OFDM, + HTT_TX_MSDU_EXT2_DESC_PREAM_CCK, + HTT_TX_MSDU_EXT2_DESC_PREAM_HT, + HTT_TX_MSDU_EXT2_DESC_PREAM_VHT, + HTT_TX_MSDU_EXT2_DESC_PREAM_HE_SU, + HTT_TX_MSDU_EXT2_DESC_PREAM_HE_EXT_SU, } htt_tx_ext2_preamble_type_t; #define HTT_TX_MSDU_EXT2_DESC_BW_5MHZ_M 0x00000001 @@ -1519,99 +1526,106 @@ typedef enum { * are already part of tcl_exit_base. */ PREPACK struct htt_tx_msdu_desc_ext2_t { - /* DWORD 0: flags */ - A_UINT32 - valid_pwr : 1, /* if set, tx pwr spec is valid */ - valid_mcs_mask : 1, /* if set, tx MCS mask is valid */ - valid_nss_mask : 1, /* if set, tx Nss mask is valid */ - valid_preamble_type : 1, /* if set, tx preamble spec is valid */ - valid_retries : 1, /* if set, tx retries spec is valid */ - valid_bw_info : 1, /* if set, tx dyn_bw and bw_mask are valid */ - valid_guard_interval : 1, /* if set, tx guard intv spec is valid */ - valid_chainmask : 1, /* if set, tx chainmask is valid */ - valid_encrypt_type : 1, /* if set, encrypt type is valid */ - valid_key_flags : 1, /* if set, key flags is valid */ - valid_expire_tsf : 1, /* if set, tx expire TSF spec is valid */ - valid_chanfreq : 1, /* if set, chanfreq is valid */ - is_dsrc : 1, /* if set, MSDU is a DSRC frame */ - guard_interval : 2, /* 0.4us, 0.8us, 1.6us, 3.2us */ - encrypt_type : 2, /* 0 = NO_ENCRYPT, - 1 = ENCRYPT, - 2 ~ 3 - Reserved */ - /* retry_limit - - * Specify the maximum number of transmissions, including the - * initial transmission, to attempt before giving up if no ack - * is received. - * If the tx rate is specified, then all retries shall use the - * same rate as the initial transmission. - * If no tx rate is specified, the target can choose whether to - * retain the original rate during the retransmissions, or to - * fall back to a more robust rate. - */ - retry_limit : 4, - use_dcm_11ax : 1, /* If set, Use Dual subcarrier modulation. - * Valid only for 11ax preamble types HE_SU - * and HE_EXT_SU - */ - ltf_subtype_11ax : 2, /* Takes enum values of htt_11ax_ltf_subtype_t - * Valid only for 11ax preamble types HE_SU - * and HE_EXT_SU - */ - dyn_bw : 1, /* 0 = static bw, 1 = dynamic bw */ - bw_mask : 6, /* Valid only if dyn_bw == 0 (static bw). - * (Bit mask of 5, 10, 20, 40, 80, 160Mhz. - * Refer to HTT_TX_MSDU_EXT2_DESC_BW defs.) - */ - reserved0_31 : 1; + /* DWORD 0: flags */ + A_UINT32 + valid_pwr : 1, /* if set, tx pwr spec is valid */ + valid_mcs_mask : 1, /* if set, tx MCS mask is valid */ + valid_nss_mask : 1, /* if set, tx Nss mask is valid */ + valid_preamble_type : 1, /* if set, tx preamble spec is valid */ + valid_retries : 1, /* if set, tx retries spec is valid */ + valid_guard_interval : 1, /* if set, tx guard intv spec is valid */ + /* if set, tx dyn_bw and bw_mask are valid */ + valid_bw_info : 1, + valid_chainmask : 1, /* if set, tx chainmask is valid */ + valid_encrypt_type : 1, /* if set, encrypt type is valid */ + valid_key_flags : 1, /* if set, key flags is valid */ + valid_expire_tsf : 1, /* if set, tx expire TSF spec is valid */ + valid_chanfreq : 1, /* if set, chanfreq is valid */ + is_dsrc : 1, /* if set, MSDU is a DSRC frame */ + guard_interval : 2, /* 0.4us, 0.8us, 1.6us, 3.2us */ + encrypt_type : 2, /* 0 = NO_ENCRYPT, + * 1 = ENCRYPT, + * 2 ~ 3 - Reserved + */ + /* retry_limit - + * Specify the maximum number of transmissions, including the + * initial transmission, to attempt before giving up if no ack + * is received. + * If the tx rate is specified, then all retries shall use the + * same rate as the initial transmission. + * If no tx rate is specified, the target can choose whether to + * retain the original rate during the retransmissions, or to + * fall back to a more robust rate. + */ + retry_limit : 4, + use_dcm_11ax : 1, /* If set, Use Dual subcarrier modulation. + * Valid only for 11ax preamble types HE_SU + * and HE_EXT_SU + */ + /* Takes enum values of htt_11ax_ltf_subtype_t + * Valid only for 11ax preamble types HE_SU + * and HE_EXT_SU + */ + ltf_subtype_11ax : 2, + dyn_bw : 1, /* 0 = static bw, 1 = dynamic bw */ + bw_mask : 6, /* Valid only if dyn_bw == 0 (static bw). + * (Bit mask of 5, 10, 20, 40, 80, 160Mhz. + * Refer to HTT_TX_MSDU_EXT2_DESC_BW defs.) + */ + reserved0_31 : 1; - /* DWORD 1: tx power, tx rate */ - A_UINT32 - power : 8, /* unit of the power field is 0.5 dbm - * similar to pwr field in htt_tx_msdu_desc_ext_t - * signed value ranging from -64dbm to 63.5 dbm - */ - mcs_mask : 12, /* mcs bit mask of 0 ~ 11 - * Setting more than one MCS isn't currently - * supported by the target (but is supported - * in the interface in case in the future - * the target supports specifications of - * a limited set of MCS values. - */ - nss_mask : 8, /* Nss bit mask 0 ~ 7 - * Setting more than one Nss isn't currently - * supported by the target (but is supported - * in the interface in case in the future - * the target supports specifications of - * a limited set of Nss values. - */ - pream_type : 3, /* Takes enum values of htt_tx_ext2_preamble_type_t */ - reserved1_31 : 1; + /* DWORD 1: tx power, tx rate */ + A_UINT32 + /* unit of the power field is 0.5 dbm + * similar to pwr field in htt_tx_msdu_desc_ext_t + * signed value ranging from -64dbm to 63.5 dbm + */ + power : 8, + /* mcs bit mask of 0 ~ 11 + * Setting more than one MCS isn't currently + * supported by the target (but is supported + * in the interface in case in the future + * the target supports specifications of + * a limited set of MCS values. + */ + mcs_mask : 12, + /* Nss bit mask 0 ~ 7 + * Setting more than one Nss isn't currently + * supported by the target (but is supported + * in the interface in case in the future + * the target supports specifications of + * a limited set of Nss values. + */ + nss_mask : 8, + /* Takes enum values of htt_tx_ext2_preamble_type_t */ + pream_type : 3, + reserved1_31 : 1; - /* DWORD 2: tx chain mask, tx retries */ - A_UINT32 - /* chain_mask - specify which chains to transmit from */ - chain_mask : 8, + /* DWORD 2: tx chain mask, tx retries */ + A_UINT32 + /* chain_mask - specify which chains to transmit from */ + chain_mask : 8, - key_flags : 8, /* Key Index and related flags - used in mesh mode - * TODO: Update Enum values for key_flags - */ + /* Key Index and related flags - used in mesh mode + * TODO: Update Enum values for key_flags + */ + key_flags : 8, + /* + * Channel frequency: This identifies the desired channel + * frequency (in MHz) for tx frames. This is used by FW to help + * determine when it is safe to transmit or drop frames for + * off-channel operation. + * The default value of zero indicates to FW that the corresponding + * VDEV's home channel (if there is one) is the desired channel + * frequency. + */ + chanfreq : 16; - /* - * Channel frequency: This identifies the desired channel - * frequency (in MHz) for tx frames. This is used by FW to help - * determine when it is safe to transmit or drop frames for - * off-channel operation. - * The default value of zero indicates to FW that the corresponding - * VDEV's home channel (if there is one) is the desired channel - * frequency. - */ - chanfreq : 16; + /* DWORD 3: tx expiry time (TSF) LSBs */ + A_UINT32 expire_tsf_lo; - /* DWORD 3: tx expiry time (TSF) LSBs */ - A_UINT32 expire_tsf_lo; - - /* DWORD 4: tx expiry time (TSF) MSBs */ - A_UINT32 expire_tsf_hi; + /* DWORD 4: tx expiry time (TSF) MSBs */ + A_UINT32 expire_tsf_hi; } POSTPACK; /* DWORD 0 */ @@ -1675,261 +1689,281 @@ PREPACK struct htt_tx_msdu_desc_ext2_t { #define HTT_TX_MSDU_EXT_DESC_CHANFREQ_S 16 /* DWORD 0 */ -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK,\ + _val); \ + ((_var) |= \ + ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_MCS_MASK_S)); \ + } while (0) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S) + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK,\ + _val); \ + ((_var) |= \ + ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_NSS_MASK_S)); \ + } while (0) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S) + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL( \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE, _val); \ - ((_var) |= ((_val) \ - << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE, _val); \ + ((_var) |= ((_val) \ + << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PREAMBLE_TYPE_S)); \ + } while (0) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S) + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_RETRIES_S)); \ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO,\ + _val); \ + ((_var) |= \ + ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_BW_INFO_S)); \ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_M) >>\ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL( \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ - ((_var) |= ((_val) \ - << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ + ((_var) |= ((_val) \ + << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK,\ + _val); \ + ((_var) |= \ + ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHAIN_MASK_S)); \ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S) #define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S));\ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE, _val); \ + ((_var) |= \ + ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_ENCRYPT_TYPE_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S));\ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL( \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS, _val); \ + ((_var) |= \ + ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S));\ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_EXPIRE_TIME_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_CHANFREQ_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M) >> \ - HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S) -#define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_M) >> \ + HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S) +#define HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_IS_DSRC_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M) >> \ - HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S) -#define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_M) >> \ + HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S) +#define HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_GUARD_INTERVAL_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M) >> \ - HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S) -#define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_M) >> \ + HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S) +#define HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_ENCRYPT_TYPE_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M) >> \ - HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S) -#define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_M) >> \ + HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S) +#define HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_RETRY_LIMIT_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M) >> \ - HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S) -#define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_M) >> \ + HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S) +#define HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_USE_DCM_11AX_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M) >> \ - HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S) -#define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_M) >> \ + HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S) +#define HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT2_DESC_LTF_SUBTYPE_11AX_S)); \ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_BW_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_BW_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_BW_MASK_S) -#define HTT_TX_MSDU_EXT2_DESC_BW_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_BW_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_BW_MASK_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_BW_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_BW_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_BW_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_BW_MASK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_BW_MASK, _val); \ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_BW_MASK_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S) -#define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK, _val);\ + ((_var) |= ((_val) << \ + HTT_TX_MSDU_EXT2_DESC_PARTIAL_BW_MASK_S)); \ + } while (0) /* DWORD 1 */ -#define HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_PWR_M) >> \ - HTT_TX_MSDU_EXT2_DESC_PWR_S) -#define HTT_TX_MSDU_EXT2_DESC_PWR_GET(_var) \ - (HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) | \ - HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT2_DESC_PWR)) -#define HTT_TX_MSDU_EXT2_DESC_PWR_SET(_var, _val) \ - ((_var) |= (((_val) << HTT_TX_MSDU_EXT2_DESC_PWR_S)) & \ - HTT_TX_MSDU_EXT2_DESC_PWR_M) +#define HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_PWR_M) >> \ + HTT_TX_MSDU_EXT2_DESC_PWR_S) +#define HTT_TX_MSDU_EXT2_DESC_PWR_GET(_var) \ + (HTT_TX_MSDU_EXT2_DESC_PWR_GET_BASE(_var) | \ + HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT2_DESC_PWR)) +#define HTT_TX_MSDU_EXT2_DESC_PWR_SET(_var, _val) \ + ((_var) |= (((_val) << HTT_TX_MSDU_EXT2_DESC_PWR_S)) & \ + HTT_TX_MSDU_EXT2_DESC_PWR_M) -#define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S) -#define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_MCS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_MCS_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_MCS_MASK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_MCS_MASK, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_MCS_MASK_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S) -#define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_NSS_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_NSS_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_NSS_MASK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_NSS_MASK, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_NSS_MASK_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_M) >> \ - HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S) -#define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_M) >> \ + HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S) +#define HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_PREAMBLE_TYPE_S));\ + } while (0) /* DWORD 2 */ -#define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S) -#define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S) +#define HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHAIN_MASK_S));\ + } while (0) -#define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S) -#define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S)); \ - } while (0) - -#define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_GET(_var) \ - (((_var) & HTT_TX_MSDU_EXT2_DESC_CHANFREQ_MASK_M) >> \ - HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S) -#define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHANFREQ, _val); \ - ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S)); \ - } while (0) +#define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S) +#define HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_KEY_FLAGS_S));\ + } while (0) +#define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_GET(_var) \ + (((_var) & HTT_TX_MSDU_EXT2_DESC_CHANFREQ_MASK_M) >> \ + HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S) +#define HTT_TX_MSDU_EXT2_DESC_CHANFREQ_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_CHANFREQ, _val);\ + ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_CHANFREQ_S));\ + } while (0) typedef enum { - HTT_TCL_METADATA_TYPE_PEER_BASED = 0, - HTT_TCL_METADATA_TYPE_VDEV_BASED = 1, + HTT_TCL_METADATA_TYPE_PEER_BASED = 0, + HTT_TCL_METADATA_TYPE_VDEV_BASED = 1, } htt_tcl_metadata_type; /** @@ -1944,34 +1978,34 @@ typedef enum { */ typedef struct { - A_UINT32 - type: 1, /* vdev_id based or peer_id based */ - rsvd: 31; + A_UINT32 + type: 1, /* vdev_id based or peer_id based */ + rsvd: 31; } htt_tx_tcl_vdev_or_peer_t; typedef struct { - A_UINT32 - type: 1, /* vdev_id based or peer_id based */ - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - vdev_id: 8, - pdev_id: 2, - rsvd: 20; + A_UINT32 + type: 1, /* vdev_id based or peer_id based */ + valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ + vdev_id: 8, + pdev_id: 2, + rsvd: 20; } htt_tx_tcl_vdev_metadata; typedef struct { - A_UINT32 - type: 1, /* vdev_id based or peer_id based */ - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - peer_id: 14, - rsvd: 16; + A_UINT32 + type: 1, /* vdev_id based or peer_id based */ + valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ + peer_id: 14, + rsvd: 16; } htt_tx_tcl_peer_metadata; PREPACK struct htt_tx_tcl_metadata { - union { - htt_tx_tcl_vdev_or_peer_t vdev_or_peer; - htt_tx_tcl_vdev_metadata vdev_meta; - htt_tx_tcl_peer_metadata peer_meta; - }; + union { + htt_tx_tcl_vdev_or_peer_t vdev_or_peer; + htt_tx_tcl_vdev_metadata vdev_meta; + htt_tx_tcl_peer_metadata peer_meta; + }; } POSTPACK; /* DWORD 0 */ @@ -1986,70 +2020,70 @@ PREPACK struct htt_tx_tcl_metadata { #define HTT_TX_TCL_METADATA_PEER_ID_M 0x0000fffc #define HTT_TX_TCL_METADATA_PEER_ID_S 2 -#define HTT_TX_TCL_METADATA_TYPE_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_TYPE_M) >> \ - HTT_TX_TCL_METADATA_TYPE_S) -#define HTT_TX_TCL_METADATA_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_S)); \ - } while (0) +#define HTT_TX_TCL_METADATA_TYPE_GET(_var) \ + (((_var) & HTT_TX_TCL_METADATA_TYPE_M) >> \ + HTT_TX_TCL_METADATA_TYPE_S) +#define HTT_TX_TCL_METADATA_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE, _val);\ + ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_S));\ + } while (0) -#define HTT_TX_TCL_METADATA_VALID_HTT_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_VALID_HTT_M) >> \ - HTT_TX_TCL_METADATA_VALID_HTT_S) -#define HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VALID_HTT, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VALID_HTT_S)); \ - } while (0) +#define HTT_TX_TCL_METADATA_VALID_HTT_GET(_var) \ + (((_var) & HTT_TX_TCL_METADATA_VALID_HTT_M) >> \ + HTT_TX_TCL_METADATA_VALID_HTT_S) +#define HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VALID_HTT, _val);\ + ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VALID_HTT_S));\ + } while (0) -#define HTT_TX_TCL_METADATA_VDEV_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_VDEV_ID_M) >> \ - HTT_TX_TCL_METADATA_VDEV_ID_S) -#define HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VDEV_ID_S)); \ - } while (0) +#define HTT_TX_TCL_METADATA_VDEV_ID_GET(_var) \ + (((_var) & HTT_TX_TCL_METADATA_VDEV_ID_M) >> \ + HTT_TX_TCL_METADATA_VDEV_ID_S) +#define HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_VDEV_ID, _val);\ + ((_var) |= ((_val) << HTT_TX_TCL_METADATA_VDEV_ID_S));\ + } while (0) -#define HTT_TX_TCL_METADATA_PDEV_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_PDEV_ID_M) >> \ - HTT_TX_TCL_METADATA_PDEV_ID_S) -#define HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PDEV_ID_S)); \ - } while (0) +#define HTT_TX_TCL_METADATA_PDEV_ID_GET(_var) \ + (((_var) & HTT_TX_TCL_METADATA_PDEV_ID_M) >> \ + HTT_TX_TCL_METADATA_PDEV_ID_S) +#define HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PDEV_ID, _val);\ + ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PDEV_ID_S));\ + } while (0) -#define HTT_TX_TCL_METADATA_PEER_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_PEER_ID_M) >> \ - HTT_TX_TCL_METADATA_PEER_ID_S) -#define HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PEER_ID_S)); \ - } while (0) +#define HTT_TX_TCL_METADATA_PEER_ID_GET(_var) \ + (((_var) & HTT_TX_TCL_METADATA_PEER_ID_M) >> \ + HTT_TX_TCL_METADATA_PEER_ID_S) +#define HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_PEER_ID, _val);\ + ((_var) |= ((_val) << HTT_TX_TCL_METADATA_PEER_ID_S));\ + } while (0) typedef enum { - HTT_TX_FW2WBM_TX_STATUS_OK, - HTT_TX_FW2WBM_TX_STATUS_DROP, - HTT_TX_FW2WBM_TX_STATUS_TTL, - HTT_TX_FW2WBM_TX_STATUS_REINJECT, - HTT_TX_FW2WBM_TX_STATUS_INSPECT, + HTT_TX_FW2WBM_TX_STATUS_OK, + HTT_TX_FW2WBM_TX_STATUS_DROP, + HTT_TX_FW2WBM_TX_STATUS_TTL, + HTT_TX_FW2WBM_TX_STATUS_REINJECT, + HTT_TX_FW2WBM_TX_STATUS_INSPECT, - HTT_TX_FW2WBM_TX_STATUS_MAX + HTT_TX_FW2WBM_TX_STATUS_MAX } htt_tx_fw2wbm_tx_status_t; typedef enum { - HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, - HTT_TX_FW2WBM_REINJECT_REASON_INJECT_VIA_EXP, - HTT_TX_FW2WBM_REINJECT_REASON_MCAST, - HTT_TX_FW2WBM_REINJECT_REASON_ARP, - HTT_TX_FW2WBM_REINJECT_REASON_DHCP, + HTT_TX_FW2WBM_REINJECT_REASON_EAPOL_ENCAP_EXP, + HTT_TX_FW2WBM_REINJECT_REASON_INJECT_VIA_EXP, + HTT_TX_FW2WBM_REINJECT_REASON_MCAST, + HTT_TX_FW2WBM_REINJECT_REASON_ARP, + HTT_TX_FW2WBM_REINJECT_REASON_DHCP, - HTT_TX_FW2WBM_REINJECT_REASON_MAX, + HTT_TX_FW2WBM_REINJECT_REASON_MAX, } htt_tx_fw2wbm_reinject_reason_t; /** @@ -2062,24 +2096,27 @@ typedef enum { * be set to release_source_fw */ PREPACK struct htt_tx_wbm_completion { - A_UINT32 - sch_cmd_id: 24, - exception_frame: 1, /* If set, this packet was queued via exception path */ - rsvd0_31_25: 7; + A_UINT32 + sch_cmd_id: 24, + /* If set, this packet was queued via exception path */ + exception_frame: 1, + rsvd0_31_25: 7; - A_UINT32 - ack_frame_rssi: 8, /* If this frame is removed as the result of the - * reception of an ACK or BA, this field indicates - * the RSSI of the received ACK or BA frame. - * When the frame is removed as result of a direct - * remove command from the SW, this field is set - * to 0x0 (which is never a valid value when real - * RSSI is available). - * Units: dB w.r.t noise floor - */ - tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ - reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ - rsvd1_31_16: 16; + A_UINT32 + ack_frame_rssi: 8, /* If this frame is removed as the result of the + * reception of an ACK or BA, this field indicates + * the RSSI of the received ACK or BA frame. + * When the frame is removed as result of a direct + * remove command from the SW, this field is set + * to 0x0 (which is never a valid value when real + * RSSI is available). + * Units: dB w.r.t noise floor + */ + /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ + tx_status: 4, + /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ + reinject_reason: 4, + rsvd1_31_16: 16; } POSTPACK; /* DWORD 0 */ @@ -2097,70 +2134,70 @@ PREPACK struct htt_tx_wbm_completion { #define HTT_TX_WBM_COMPLETION_REINJECT_REASON_S 12 /* DWORD 0 */ -#define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_GET(_var) \ - (((_var) & HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M) >> \ - HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S) -#define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_SCH_CMD_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S)); \ - } while (0) +#define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_SCH_CMD_ID_M) >> \ + HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S) +#define HTT_TX_WBM_COMPLETION_SCH_CMD_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_SCH_CMD_ID, _val);\ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_SCH_CMD_ID_S));\ + } while (0) -#define HTT_TX_WBM_COMPLETION_EXP_FRAME_GET(_var) \ - (((_var) & HTT_TX_WBM_COMPLETION_EXP_FRAME_M) >> \ - HTT_TX_WBM_COMPLETION_EXP_FRAME_S) -#define HTT_TX_WBM_COMPLETION_EXP_FRAME_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_EXP_FRAME, _val); \ - ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_EXP_FRAME_S)); \ - } while (0) +#define HTT_TX_WBM_COMPLETION_EXP_FRAME_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_EXP_FRAME_M) >> \ + HTT_TX_WBM_COMPLETION_EXP_FRAME_S) +#define HTT_TX_WBM_COMPLETION_EXP_FRAME_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_EXP_FRAME, _val);\ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_EXP_FRAME_S));\ + } while (0) /* DWORD 1 */ -#define HTT_TX_WBM_COMPLETION_ACK_RSSI_GET(_var) \ - (((_var) & HTT_TX_WBM_COMPLETION_ACK_RSSI_M) >> \ - HTT_TX_WBM_COMPLETION_ACK_RSSI_S) -#define HTT_TX_WBM_COMPLETION_ACK_RSSI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_ACK_RSSI, _val); \ - ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_ACK_RSSI_S)); \ - } while (0) +#define HTT_TX_WBM_COMPLETION_ACK_RSSI_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_ACK_RSSI_M) >> \ + HTT_TX_WBM_COMPLETION_ACK_RSSI_S) +#define HTT_TX_WBM_COMPLETION_ACK_RSSI_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_ACK_RSSI, _val);\ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_ACK_RSSI_S));\ + } while (0) -#define HTT_TX_WBM_COMPLETION_TX_STATUS_GET(_var) \ - (((_var) & HTT_TX_WBM_COMPLETION_TX_STATUS_M) >> \ - HTT_TX_WBM_COMPLETION_TX_STATUS_S) -#define HTT_TX_WBM_COMPLETION_TX_STATUS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_TX_STATUS, _val); \ - ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_TX_STATUS_S)); \ - } while (0) - -#define HTT_TX_WBM_COMPLETION_REINJECT_REASON_GET(_var) \ - (((_var) & HTT_TX_WBM_COMPLETION_REINJECT_REASON_M) >> \ - HTT_TX_WBM_COMPLETION_REINJECT_REASON_S) -#define HTT_TX_WBM_COMPLETION_REINJECT_REASON_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_REINJECT_REASON, _val); \ - ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)); \ - } while (0) +#define HTT_TX_WBM_COMPLETION_TX_STATUS_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_TX_STATUS_M) >> \ + HTT_TX_WBM_COMPLETION_TX_STATUS_S) +#define HTT_TX_WBM_COMPLETION_TX_STATUS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_TX_STATUS, _val);\ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_TX_STATUS_S));\ + } while (0) +#define HTT_TX_WBM_COMPLETION_REINJECT_REASON_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_REINJECT_REASON_M) >> \ + HTT_TX_WBM_COMPLETION_REINJECT_REASON_S) +#define HTT_TX_WBM_COMPLETION_REINJECT_REASON_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_REINJECT_REASON, _val);\ + ((_var) |= ((_val) << \ + HTT_TX_WBM_COMPLETION_REINJECT_REASON_S)); \ + } while (0) typedef enum { - TX_FLOW_PRIORITY_BE, - TX_FLOW_PRIORITY_HIGH, - TX_FLOW_PRIORITY_LOW, + TX_FLOW_PRIORITY_BE, + TX_FLOW_PRIORITY_HIGH, + TX_FLOW_PRIORITY_LOW, } htt_tx_flow_priority_t; typedef enum { - TX_FLOW_LATENCY_SENSITIVE, - TX_FLOW_LATENCY_INSENSITIVE, + TX_FLOW_LATENCY_SENSITIVE, + TX_FLOW_LATENCY_INSENSITIVE, } htt_tx_flow_latency_t; typedef enum { - TX_FLOW_BEST_EFFORT_TRAFFIC, - TX_FLOW_INTERACTIVE_TRAFFIC, - TX_FLOW_PERIODIC_TRAFFIC, - TX_FLOW_BURSTY_TRAFFIC, - TX_FLOW_OVER_SUBSCRIBED_TRAFFIC, + TX_FLOW_BEST_EFFORT_TRAFFIC, + TX_FLOW_INTERACTIVE_TRAFFIC, + TX_FLOW_PERIODIC_TRAFFIC, + TX_FLOW_BURSTY_TRAFFIC, + TX_FLOW_OVER_SUBSCRIBED_TRAFFIC, } htt_tx_flow_traffic_pattern_t; /** @@ -2175,17 +2212,22 @@ typedef enum { * pointer as part of htt_tx_map_flow_info message. */ PREPACK struct htt_tx_flow_metadata { - A_UINT32 - rsvd0_1_0: 2, - tid: 4, - priority: 3, /* Takes enum values of htt_tx_flow_priority_t */ - traffic_pattern: 3, /* Takes enum values of htt_tx_flow_traffic_pattern_t */ - tid_override: 1, /* If set, tid field in this struct is the final tid. - * Else choose final tid based on latency, priority. - */ - dedicated_flowq: 1, /* Dedicated flowq per 5 tuple flow. */ - latency_sensitive: 2, /* Takes enum values of htt_tx_flow_latency_t */ - host_flow_identifier: 16; /* Used by host to map flow metadata with flow entry */ + A_UINT32 + rsvd0_1_0: 2, + tid: 4, + /* Takes enum values of htt_tx_flow_priority_t */ + priority: 3, + /* Takes enum values of htt_tx_flow_traffic_pattern_t */ + traffic_pattern: 3, + /* If set, tid field in this struct is the final tid. + * Else choose final tid based on latency, priority. + */ + tid_override: 1, + dedicated_flowq: 1, /* Dedicated flowq per 5 tuple flow. */ + /* Takes enum values of htt_tx_flow_latency_t */ + latency_sensitive: 2, + /* Used by host to map flow metadata with flow entry */ + host_flow_identifier: 16; } POSTPACK; /* DWORD 0 */ @@ -2205,72 +2247,72 @@ PREPACK struct htt_tx_flow_metadata { #define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S 16 /* DWORD 0 */ -#define HTT_TX_FLOW_METADATA_TID_GET(_var) \ - (((_var) & HTT_TX_FLOW_METADATA_TID_M) >> \ - HTT_TX_FLOW_METADATA_TID_S) -#define HTT_TX_FLOW_METADATA_TID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_S)); \ - } while (0) +#define HTT_TX_FLOW_METADATA_TID_GET(_var) \ + (((_var) & HTT_TX_FLOW_METADATA_TID_M) >> \ + HTT_TX_FLOW_METADATA_TID_S) +#define HTT_TX_FLOW_METADATA_TID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID, _val); \ + ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_S)); \ + } while (0) -#define HTT_TX_FLOW_METADATA_PRIORITY_GET(_var) \ - (((_var) & HTT_TX_FLOW_PRIORITY_M) >> \ - HTT_TX_FLOW_METADATA_PRIORITY_S) -#define HTT_TX_FLOW_METADATA_PRIORITY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_PRIORITY, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_PRIORITY_S)); \ - } while (0) +#define HTT_TX_FLOW_METADATA_PRIORITY_GET(_var) \ + (((_var) & HTT_TX_FLOW_PRIORITY_M) >> \ + HTT_TX_FLOW_METADATA_PRIORITY_S) +#define HTT_TX_FLOW_METADATA_PRIORITY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_PRIORITY, _val); \ + ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_PRIORITY_S));\ + } while (0) -#define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_GET(_var) \ - (((_var) & HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M) >> \ - HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S) -#define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S)); \ - } while (0) +#define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_GET(_var) \ + (((_var) & HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_M) >> \ + HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S) +#define HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN, _val);\ + ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TRAFFIC_PATTERN_S));\ + } while (0) -#define HTT_TX_FLOW_METADATA_TID_OVERRIDE_GET(_var) \ - (((_var) & HTT_TX_FLOW_METADATA_TID_OVERRIDE_M) >> \ - HTT_TX_FLOW_METADATA_TID_OVERRIDE_S) -#define HTT_TX_FLOW_METADATA_TID_OVERRIDE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID_OVERRIDE, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_OVERRIDE_S)); \ - } while (0) +#define HTT_TX_FLOW_METADATA_TID_OVERRIDE_GET(_var) \ + (((_var) & HTT_TX_FLOW_METADATA_TID_OVERRIDE_M) >> \ + HTT_TX_FLOW_METADATA_TID_OVERRIDE_S) +#define HTT_TX_FLOW_METADATA_TID_OVERRIDE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_TID_OVERRIDE, _val);\ + ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_TID_OVERRIDE_S));\ + } while (0) -#define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_GET(_var) \ - (((_var) & HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M) >> \ - HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S) -#define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S)); \ - } while (0) +#define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_GET(_var) \ + (((_var) & HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_M) >> \ + HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S) +#define HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ, _val);\ + ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_DEDICATED_FLOWQ_S));\ + } while (0) -#define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_GET(_var) \ - (((_var) & HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M) >> \ - HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S) -#define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_LATENCY_SENSITIVE, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_LATENCY_SENSITIVE_S)); \ - } while (0) - -#define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_GET(_var) \ - (((_var) & HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M) >> \ - HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S) -#define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_HOST_FLOW_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S)); \ - } while (0) +#define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_GET(_var) \ + (((_var) & HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_M) >> \ + HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_S) +#define HTT_TX_FLOW_METADATA_LATENCY_SENSITIVE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_LATENCY_SENSITIVE, _val); \ + ((_var) |= ((_val) << HTT_TX_FLOW_LATENCY_SENSITIVE_S));\ + } while (0) +#define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_GET(_var) \ + (((_var) & HTT_TX_FLOW_METADATA_HOST_FLOW_ID_M) >> \ + HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S) +#define HTT_TX_FLOW_METADATA_HOST_FLOW_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_FLOW_METADATA_HOST_FLOW_ID, _val);\ + ((_var) |= ((_val) << HTT_TX_FLOW_METADATA_HOST_FLOW_ID_S));\ + } while (0) /** - * @brief Used in HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY and HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY messages + * @brief for HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY and + * HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY messages * * @details * HTT wds entry from source port learning @@ -2311,16 +2353,17 @@ PREPACK struct htt_tx_flow_metadata { */ PREPACK struct htt_wds_entry { - A_UINT32 - msg_type: 8, - vdev_id: 8, - pdev_id: 2, - rsvd0: 14; - A_UINT32 sa_addr_31_0; - A_UINT32 - sa_addr_47_32: 16, - ta_peer_id: 14, - rsvd2: 2; + A_UINT32 + msg_type: 8, + vdev_id: 8, + pdev_id: 2, + rsvd0: 14; + A_UINT32 sa_addr_31_0; + + A_UINT32 + sa_addr_47_32: 16, + ta_peer_id: 14, + rsvd2: 2; } POSTPACK; /* DWORD 0 */ @@ -2336,42 +2379,42 @@ PREPACK struct htt_wds_entry { #define HTT_WDS_ENTRY_TA_PEER_ID_S 16 /* DWORD 0 */ -#define HTT_WDS_ENTRY_VDEV_ID_GET(_var) \ - (((_var) & HTT_WDS_ENTRY_VDEV_ID_M) >> \ - HTT_WDS_ENTRY_VDEV_ID_S) -#define HTT_WDS_ENTRY_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_WDS_ENTRY_VDEV_ID_S)); \ - } while (0) +#define HTT_WDS_ENTRY_VDEV_ID_GET(_var) \ + (((_var) & HTT_WDS_ENTRY_VDEV_ID_M) >> \ + HTT_WDS_ENTRY_VDEV_ID_S) +#define HTT_WDS_ENTRY_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_WDS_ENTRY_VDEV_ID_S)); \ + } while (0) -#define HTT_WDS_ENTRY_PDEV_ID_GET(_var) \ - (((_var) & HTT_WDS_ENTRY_PDEV_ID_M) >> \ - HTT_WDS_ENTRY_PDEV_ID_S) -#define HTT_WDS_ENTRY_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_WDS_ENTRY_PDEV_ID_S)); \ - } while (0) +#define HTT_WDS_ENTRY_PDEV_ID_GET(_var) \ + (((_var) & HTT_WDS_ENTRY_PDEV_ID_M) >> \ + HTT_WDS_ENTRY_PDEV_ID_S) +#define HTT_WDS_ENTRY_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_WDS_ENTRY_PDEV_ID_S)); \ + } while (0) /* DWORD 2 */ -#define HTT_WDS_ENTRY_SA_ADDR_47_32_GET(_var) \ - (((_var) & HTT_WDS_ENTRY_SA_ADDR_47_32_M) >> \ - HTT_WDS_ENTRY_SA_ADDR_47_32_S) -#define HTT_WDS_ENTRY_SA_ADDR_47_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_SA_ADDR_47_32, _val); \ - ((_var) |= ((_val) << HTT_WDS_ENTRY_SA_ADDR_47_32_S)); \ - } while (0) +#define HTT_WDS_ENTRY_SA_ADDR_47_32_GET(_var) \ + (((_var) & HTT_WDS_ENTRY_SA_ADDR_47_32_M) >> \ + HTT_WDS_ENTRY_SA_ADDR_47_32_S) +#define HTT_WDS_ENTRY_SA_ADDR_47_32_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_SA_ADDR_47_32, _val); \ + ((_var) |= ((_val) << HTT_WDS_ENTRY_SA_ADDR_47_32_S)); \ + } while (0) -#define HTT_WDS_ENTRY_TA_PEER_ID_GET(_var) \ - (((_var) & HTT_WDS_ENTRY_TA_PEER_ID_M) >> \ - HTT_WDS_ENTRY_TA_PEER_ID_S) -#define HTT_WDS_ENTRY_TA_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_TA_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_WDS_ENTRY_TA_PEER_ID_S)); \ - } while (0) +#define HTT_WDS_ENTRY_TA_PEER_ID_GET(_var) \ + (((_var) & HTT_WDS_ENTRY_TA_PEER_ID_M) >> \ + HTT_WDS_ENTRY_TA_PEER_ID_S) +#define HTT_WDS_ENTRY_TA_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDS_ENTRY_TA_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_WDS_ENTRY_TA_PEER_ID_S)); \ + } while (0) /** @@ -2389,14 +2432,14 @@ PREPACK struct htt_wds_entry { * header: | reserved | num rings | msg type | * |---------------------------------------------------------------| * payload 1: | FW_IDX shadow register physical address (bits 31:0) | -#if HTT_PADDR64 + #if HTT_PADDR64 * | FW_IDX shadow register physical address (bits 63:32) | -#endif + #endif * |---------------------------------------------------------------| * | rx ring base physical address (bits 31:0) | -#if HTT_PADDR64 + #if HTT_PADDR64 * | rx ring base physical address (bits 63:32) | -#endif + #endif * |---------------------------------------------------------------| * | rx ring buffer size | rx ring length | * |---------------------------------------------------------------| @@ -2589,298 +2632,295 @@ PREPACK struct htt_wds_entry { #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44 #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36 #if HTT_PADDR64 - #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 +#define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 #else - #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 +#define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 #endif -#define HTT_RX_RING_CFG_BYTES(num_rings) \ - (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) +#define HTT_RX_RING_CFG_BYTES(num_rings) \ + (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) -#define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) -#define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ - } while (0) +#define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) +#define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ + } while (0) /* degenerate case for 32-bit fields */ #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var) -#define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \ - ((_var) = (_val)) +#define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \ + ((_var) = (_val)) #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var) -#define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \ - ((_var) = (_val)) +#define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \ + ((_var) = (_val)) #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var) -#define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \ - ((_var) = (_val)) +#define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \ + ((_var) = (_val)) /* degenerate case for 32-bit fields */ #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var) -#define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) \ - ((_var) = (_val)) +#define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) ((_var) = (_val)) #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var) -#define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) \ - ((_var) = (_val)) +#define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) ((_var) = (_val)) #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var) -#define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) \ - ((_var) = (_val)) +#define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) ((_var) = (_val)) -#define HTT_RX_RING_CFG_LEN_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) -#define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ - } while (0) +#define HTT_RX_RING_CFG_LEN_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) +#define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ + } while (0) -#define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) -#define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ - } while (0) +#define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) +#define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ + } while (0) -#define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ - HTT_RX_RING_CFG_IDX_INIT_VAL_S) -#define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ - } while (0) +#define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ + HTT_RX_RING_CFG_IDX_INIT_VAL_S) +#define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ - HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) -#define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ + HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) +#define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ - HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) -#define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ + HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) +#define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ - HTT_RX_RING_CFG_ENABLED_PPDU_START_S) -#define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ + HTT_RX_RING_CFG_ENABLED_PPDU_START_S) +#define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ - HTT_RX_RING_CFG_ENABLED_PPDU_END_S) -#define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ + HTT_RX_RING_CFG_ENABLED_PPDU_END_S) +#define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ - HTT_RX_RING_CFG_ENABLED_MPDU_START_S) -#define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ + HTT_RX_RING_CFG_ENABLED_MPDU_START_S) +#define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ - HTT_RX_RING_CFG_ENABLED_MPDU_END_S) -#define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ + HTT_RX_RING_CFG_ENABLED_MPDU_END_S) +#define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ - HTT_RX_RING_CFG_ENABLED_MSDU_START_S) -#define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ + HTT_RX_RING_CFG_ENABLED_MSDU_START_S) +#define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ - HTT_RX_RING_CFG_ENABLED_MSDU_END_S) -#define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ + HTT_RX_RING_CFG_ENABLED_MSDU_END_S) +#define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ - HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) -#define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ + HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) +#define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ - HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) -#define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ + HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) +#define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ - HTT_RX_RING_CFG_ENABLED_UCAST_S) -#define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ + HTT_RX_RING_CFG_ENABLED_UCAST_S) +#define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ + } while (0) -#define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ - HTT_RX_RING_CFG_ENABLED_MCAST_S) -#define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ - } while (0) -#define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ - HTT_RX_RING_CFG_ENABLED_CTRL_S) -#define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ - } while (0) -#define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ - HTT_RX_RING_CFG_ENABLED_MGMT_S) -#define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ - } while (0) -#define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ - HTT_RX_RING_CFG_ENABLED_NULL_S) -#define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ - } while (0) -#define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ - HTT_RX_RING_CFG_ENABLED_PHY_S) -#define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ - } while (0) +#define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ + HTT_RX_RING_CFG_ENABLED_MCAST_S) +#define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ + } while (0) +#define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ + HTT_RX_RING_CFG_ENABLED_CTRL_S) +#define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ + } while (0) +#define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ + HTT_RX_RING_CFG_ENABLED_MGMT_S) +#define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ + } while (0) +#define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ + HTT_RX_RING_CFG_ENABLED_NULL_S) +#define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ + } while (0) +#define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ + HTT_RX_RING_CFG_ENABLED_PHY_S) +#define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ - HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) -#define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ + HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) +#define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ - HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) -#define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ + HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) +#define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ - HTT_RX_RING_CFG_OFFSET_PPDU_START_S) -#define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ + HTT_RX_RING_CFG_OFFSET_PPDU_START_S) +#define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ - HTT_RX_RING_CFG_OFFSET_PPDU_END_S) -#define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ + HTT_RX_RING_CFG_OFFSET_PPDU_END_S) +#define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ - HTT_RX_RING_CFG_OFFSET_MPDU_START_S) -#define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ + HTT_RX_RING_CFG_OFFSET_MPDU_START_S) +#define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ - HTT_RX_RING_CFG_OFFSET_MPDU_END_S) -#define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ + HTT_RX_RING_CFG_OFFSET_MPDU_END_S) +#define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ - HTT_RX_RING_CFG_OFFSET_MSDU_START_S) -#define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ + HTT_RX_RING_CFG_OFFSET_MSDU_START_S) +#define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ - HTT_RX_RING_CFG_OFFSET_MSDU_END_S) -#define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ + HTT_RX_RING_CFG_OFFSET_MSDU_END_S) +#define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ - HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) -#define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ + HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) +#define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ + } while (0) -#define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ - (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ - HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) -#define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ - } while (0) +#define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ + (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ + HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) +#define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ + } while (0) /** * @brief host -> target FW statistics retrieve @@ -2940,7 +2980,7 @@ PREPACK struct htt_wds_entry { * Value: MSBs of the opaque cookie specified by the host-side requestor */ -#define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ +#define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff @@ -2956,41 +2996,41 @@ PREPACK struct htt_wds_entry { #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000 #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24 -#define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ - (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ - HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) -#define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ - ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ - } while (0) +#define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ + (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ + HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) +#define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ + ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ + } while (0) -#define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ - (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ - HTT_H2T_STATS_REQ_RESET_TYPES_S) -#define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ - ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ - } while (0) +#define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ + (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ + HTT_H2T_STATS_REQ_RESET_TYPES_S) +#define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ + ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ + } while (0) -#define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ - (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ - HTT_H2T_STATS_REQ_CFG_VAL_S) -#define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ - ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ - } while (0) +#define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ + (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ + HTT_H2T_STATS_REQ_CFG_VAL_S) +#define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ + ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ + } while (0) -#define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ - (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ - HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) -#define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ - } while (0) +#define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ + (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ + HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) +#define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ + ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ + } while (0) /** * @brief host -> target HTT out-of-band sync request @@ -3033,14 +3073,14 @@ PREPACK struct htt_wds_entry { #define HTT_H2T_SYNC_COUNT_M 0x0000ff00 #define HTT_H2T_SYNC_COUNT_S 8 -#define HTT_H2T_SYNC_COUNT_GET(_var) \ - (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ - HTT_H2T_SYNC_COUNT_S) -#define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ - ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ - } while (0) +#define HTT_H2T_SYNC_COUNT_GET(_var) \ + (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ + HTT_H2T_SYNC_COUNT_S) +#define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ + ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ + } while (0) /** @@ -3053,23 +3093,23 @@ PREPACK struct htt_wds_entry { #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000 #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16 -#define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ - (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ - HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) -#define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ - ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ - } while (0) +#define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ + (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ + HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) +#define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ + ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ + } while (0) -#define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ - (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ - HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) -#define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ - ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ - } while (0) +#define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ + (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ + HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) +#define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ + ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ + } while (0) /** @@ -3101,23 +3141,23 @@ PREPACK struct htt_wds_entry { #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000 #define HTT_AGGR_CFG_EX_VDEV_ID_S 16 -#define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ - (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ - HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) -#define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ - ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ - } while (0) +#define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ + (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ + HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) +#define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ + ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ +} while (0) -#define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ - (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ - HTT_AGGR_CFG_EX_VDEV_ID_S) -#define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ - } while (0) +#define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ + (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ + HTT_AGGR_CFG_EX_VDEV_ID_S) +#define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ +} while (0) /** * @brief HTT WDI_IPA Config Message @@ -3207,35 +3247,35 @@ PREPACK struct htt_wds_entry { * Purpose: Total number of TX packet buffer pool allocated by Host for * WDI_IPA TX path * For systems using 32-bit format for bus addresses: - * - TX_COMP_RING_BASE_ADDR - * Bits 31:0 - * Purpose: TX Completion Ring base address in DDR - * - TX_COMP_RING_SIZE - * Bits 31:0 - * Purpose: TX Completion Ring size (must be power of 2) - * - TX_COMP_WR_IDX_ADDR - * Bits 31:0 - * Purpose: IPA doorbell register address OR DDR address where WIFI FW - * updates the Write Index for WDI_IPA TX completion ring - * - TX_CE_WR_IDX_ADDR - * Bits 31:0 - * Purpose: DDR address where IPA uC - * updates the WR Index for TX CE ring - * (needed for fusion platforms) - * - RX_IND_RING_BASE_ADDR - * Bits 31:0 - * Purpose: RX Indication Ring base address in DDR - * - RX_IND_RING_SIZE - * Bits 31:0 - * Purpose: RX Indication Ring size - * - RX_IND_RD_IDX_ADDR - * Bits 31:0 - * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA - * RX indication ring - * - RX_IND_WR_IDX_ADDR - * Bits 31:0 - * Purpose: IPA doorbell register address OR DDR address where WIFI FW - * updates the Write Index for WDI_IPA RX indication ring + * - TX_COMP_RING_BASE_ADDR + * Bits 31:0 + * Purpose: TX Completion Ring base address in DDR + * - TX_COMP_RING_SIZE + * Bits 31:0 + * Purpose: TX Completion Ring size (must be power of 2) + * - TX_COMP_WR_IDX_ADDR + * Bits 31:0 + * Purpose: IPA doorbell register address OR DDR address where WIFI FW + * updates the Write Index for WDI_IPA TX completion ring + * - TX_CE_WR_IDX_ADDR + * Bits 31:0 + * Purpose: DDR address where IPA uC + * updates the WR Index for TX CE ring + * (needed for fusion platforms) + * - RX_IND_RING_BASE_ADDR + * Bits 31:0 + * Purpose: RX Indication Ring base address in DDR + * - RX_IND_RING_SIZE + * Bits 31:0 + * Purpose: RX Indication Ring size + * - RX_IND_RD_IDX_ADDR + * Bits 31:0 + * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA + * RX indication ring + * - RX_IND_WR_IDX_ADDR + * Bits 31:0 + * Purpose: IPA doorbell register address OR DDR address where WIFI FW + * updates the Write Index for WDI_IPA RX indication ring * - RX_RING2_BASE_ADDR * Bits 31:0 * Purpose: Second RX Ring(Indication or completion)base address in DDR @@ -3256,10 +3296,12 @@ PREPACK struct htt_wds_entry { * For systems using 64-bit format for bus addresses: * - TX_COMP_RING_BASE_ADDR_LO * Bits 31:0 - * Purpose: Lower 4 bytes of TX Completion Ring base physical address in DDR + * Purpose: Lower 4 bytes of TX Completion Ring base physical + * address in DDR * - TX_COMP_RING_BASE_ADDR_HI * Bits 31:0 - * Purpose: Higher 4 bytes of TX Completion Ring base physical address in DDR + * Purpose: Higher 4 bytes of TX Completion Ring base physical + * address in DDR * - TX_COMP_RING_SIZE * Bits 31:0 * Purpose: TX Completion Ring size (must be power of 2) @@ -3294,12 +3336,12 @@ PREPACK struct htt_wds_entry { * Purpose: RX Indication Ring size * - RX_IND_RD_IDX_ADDR_LO * Bits 31:0 - * Purpose: Lower 4 bytes of DDR address where IPA uC updates the Read Index - * for WDI_IPA RX indication ring + * Purpose: Lower 4 bytes of DDR address where IPA uC updates the + * Read Index for WDI_IPA RX indication ring * - RX_IND_RD_IDX_ADDR_HI * Bits 31:0 - * Purpose: Higher 4 bytes of DDR address where IPA uC updates the Read Index - * for WDI_IPA RX indication ring + * Purpose: Higher 4 bytes of DDR address where IPA uC updates the + * Read Index for WDI_IPA RX indication ring * - RX_IND_WR_IDX_ADDR_LO * Bits 31:0 * Purpose: Lower 4 bytes of IPA doorbell register address OR @@ -3312,10 +3354,12 @@ PREPACK struct htt_wds_entry { * updates the Write Index for WDI_IPA RX indication ring * - RX_RING2_BASE_ADDR_LO * Bits 31:0 - * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion)base address in DDR + * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion) + * base address in DDR * - RX_RING2_BASE_ADDR_HI * Bits 31:0 - * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion)base address in DDR + * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion) + * base address in DDR * - RX_RING2_SIZE * Bits 31:0 * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) @@ -3346,9 +3390,9 @@ PREPACK struct htt_wds_entry { */ #if HTT_PADDR64 -#define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ +#define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ #else -#define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ +#define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ #endif #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000 @@ -3444,281 +3488,317 @@ PREPACK struct htt_wds_entry { #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0 -#define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) -#define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> \ + HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) +#define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ + } while (0) /* for systems using 32-bit format for bus addr */ -#define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) -#define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) +#define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL( \ + HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val);\ + ((_var) |= \ + ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ + } while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val);\ + ((_var) |= \ + ((_val) << \ + HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ + } while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ +} while (0) -#define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) -#define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) +#define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ + } while (0) /* for systems using 32-bit format for bus addr */ -#define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) -#define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) +#define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ + } while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ +} while (0) /* for systems using 32-bit format for bus addr */ -#define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) -#define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> \ + HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) +#define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ + } while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >>\ + HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ +} while (0) /* for systems using 32-bit format for bus addr */ -#define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) -#define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) +#define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ +} while (0) -#define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) -#define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) +#define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ +} while (0) /* for systems using 32-bit format for bus addr */ -#define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) -#define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) +#define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ +} while (0) /* for systems using 32-bit format for bus addr */ -#define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) -#define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ - } while (0) +#define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ + (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) +#define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ + } while (0) /* for systems using 32-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ +} while (0) #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ +} while (0) /* for systems using 32-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ +} while (0) /* for systems using 32-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ +} while (0) /* for systems using 64-bit format for bus addr */ #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \ - (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) + (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> \ + HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ +} while (0) /* * TEMPLATE_HTT_WDI_IPA_CONFIG_T: @@ -3728,68 +3808,84 @@ PREPACK struct htt_wds_entry { * htt_wdi_ipa_config64_t structs. */ #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \ - _paddr__tx_comp_ring_base_addr_, \ - _paddr__tx_comp_wr_idx_addr_, \ - _paddr__tx_ce_wr_idx_addr_, \ - _paddr__rx_ind_ring_base_addr_, \ - _paddr__rx_ind_rd_idx_addr_, \ - _paddr__rx_ind_wr_idx_addr_, \ - _paddr__rx_ring2_base_addr_,\ - _paddr__rx_ring2_rd_idx_addr_,\ - _paddr__rx_ring2_wr_idx_addr_) \ + _paddr__tx_comp_ring_base_addr_, \ + _paddr__tx_comp_wr_idx_addr_, \ + _paddr__tx_ce_wr_idx_addr_, \ + _paddr__rx_ind_ring_base_addr_, \ + _paddr__rx_ind_rd_idx_addr_, \ + _paddr__rx_ind_wr_idx_addr_, \ + _paddr__rx_ring2_base_addr_,\ + _paddr__rx_ring2_rd_idx_addr_,\ + _paddr__rx_ring2_wr_idx_addr_) \ PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \ { \ /* DWORD 0: flags and meta-data */ \ - A_UINT32 \ - msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ - reserved: 8, \ - tx_pkt_pool_size: 16;\ - /* DWORD 1 */\ - _paddr__tx_comp_ring_base_addr_;\ - /* DWORD 2 (or 3)*/\ - A_UINT32 tx_comp_ring_size;\ - /* DWORD 3 (or 4)*/\ - _paddr__tx_comp_wr_idx_addr_;\ - /* DWORD 4 (or 6)*/\ - _paddr__tx_ce_wr_idx_addr_;\ - /* DWORD 5 (or 8)*/\ - _paddr__rx_ind_ring_base_addr_;\ - /* DWORD 6 (or 10)*/\ - A_UINT32 rx_ind_ring_size;\ - /* DWORD 7 (or 11)*/\ - _paddr__rx_ind_rd_idx_addr_;\ - /* DWORD 8 (or 13)*/\ - _paddr__rx_ind_wr_idx_addr_;\ - /* DWORD 9 (or 15)*/\ - _paddr__rx_ring2_base_addr_;\ - /* DWORD 10 (or 17) */\ - A_UINT32 rx_ring2_size;\ - /* DWORD 11 (or 18) */\ - _paddr__rx_ring2_rd_idx_addr_;\ - /* DWORD 12 (or 20) */\ - _paddr__rx_ring2_wr_idx_addr_;\ + A_UINT32 \ + msg_type:8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ + reserved:8, \ + tx_pkt_pool_size:16;\ + /* DWORD 1 */\ + _paddr__tx_comp_ring_base_addr_;\ + /* DWORD 2 (or 3)*/\ + A_UINT32 tx_comp_ring_size;\ + /* DWORD 3 (or 4)*/\ + _paddr__tx_comp_wr_idx_addr_;\ + /* DWORD 4 (or 6)*/\ + _paddr__tx_ce_wr_idx_addr_;\ + /* DWORD 5 (or 8)*/\ + _paddr__rx_ind_ring_base_addr_;\ + /* DWORD 6 (or 10)*/\ + A_UINT32 rx_ind_ring_size;\ + /* DWORD 7 (or 11)*/\ + _paddr__rx_ind_rd_idx_addr_;\ + /* DWORD 8 (or 13)*/\ + _paddr__rx_ind_wr_idx_addr_;\ + /* DWORD 9 (or 15)*/\ + _paddr__rx_ring2_base_addr_;\ + /* DWORD 10 (or 17) */\ + A_UINT32 rx_ring2_size;\ + /* DWORD 11 (or 18) */\ + _paddr__rx_ring2_rd_idx_addr_;\ + /* DWORD 12 (or 20) */\ + _paddr__rx_ring2_wr_idx_addr_;\ } POSTPACK /* define a htt_wdi_ipa_config32_t type */ -TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), HTT_VAR_PADDR32(tx_comp_wr_idx_addr), HTT_VAR_PADDR32(tx_ce_wr_idx_addr), HTT_VAR_PADDR32(rx_ind_ring_base_addr), HTT_VAR_PADDR32(rx_ind_rd_idx_addr),HTT_VAR_PADDR32(rx_ind_wr_idx_addr), HTT_VAR_PADDR32(rx_ring2_base_addr), HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); +TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), + HTT_VAR_PADDR32(tx_comp_wr_idx_addr), + HTT_VAR_PADDR32(tx_ce_wr_idx_addr), + HTT_VAR_PADDR32(rx_ind_ring_base_addr), + HTT_VAR_PADDR32(rx_ind_rd_idx_addr), + HTT_VAR_PADDR32(rx_ind_wr_idx_addr), + HTT_VAR_PADDR32(rx_ring2_base_addr), + HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), + HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); /* define a htt_wdi_ipa_config64_t type */ -TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_base_addr), HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); +TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), + HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), + HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), + HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), + HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), + HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), + HTT_VAR_PADDR64_LE(rx_ring2_base_addr), + HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), + HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); #if HTT_PADDR64 - #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t +#define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t #else - #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t +#define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t #endif enum htt_wdi_ipa_op_code { - HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, - HTT_WDI_IPA_OPCODE_TX_RESUME = 1, - HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, - HTT_WDI_IPA_OPCODE_RX_RESUME = 3, - HTT_WDI_IPA_OPCODE_DBG_STATS = 4, - /* keep this last */ - HTT_WDI_IPA_OPCODE_MAX + HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, + HTT_WDI_IPA_OPCODE_TX_RESUME = 1, + HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, + HTT_WDI_IPA_OPCODE_RX_RESUME = 3, + HTT_WDI_IPA_OPCODE_DBG_STATS = 4, + /* keep this last */ + HTT_WDI_IPA_OPCODE_MAX }; /** @@ -3814,27 +3910,27 @@ enum htt_wdi_ipa_op_code { * value: = enum htt_wdi_ipa_op_code */ -PREPACK struct htt_wdi_ipa_op_request_t -{ - /* DWORD 0: flags and meta-data */ - A_UINT32 - msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ - reserved: 8, - op_code: 16; +PREPACK struct htt_wdi_ipa_op_request_t { + /* DWORD 0: flags and meta-data */ + A_UINT32 + msg_type:8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ + reserved:8, + op_code:16; } POSTPACK; -#define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ +#define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000 #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16 -#define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ - (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) -#define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ - } while (0) +#define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ + (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> \ + HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) +#define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ + } while (0) /* * @brief host -> target HTT_SRING_SETUP message @@ -3964,220 +4060,251 @@ PREPACK struct htt_wdi_ipa_op_request_t * b'20:31 - reserved: reserved for future use */ PREPACK struct htt_sring_setup_t { - A_UINT32 msg_type: 8, - pdev_id: 8, - ring_id: 8, - ring_type: 8; - A_UINT32 ring_base_addr_lo; - A_UINT32 ring_base_addr_hi; - A_UINT32 ring_size: 16, - ring_entry_size: 8, - ring_misc_cfg_flag: 8; - A_UINT32 ring_head_offset32_remote_addr_lo; - A_UINT32 ring_head_offset32_remote_addr_hi; - A_UINT32 ring_tail_offset32_remote_addr_lo; - A_UINT32 ring_tail_offset32_remote_addr_hi; - A_UINT32 ring_msi_addr_lo; - A_UINT32 ring_msi_addr_hi; - A_UINT32 ring_msi_data; - A_UINT32 intr_batch_counter_th: 15, - sw_intr_mode: 1, - intr_timer_th: 16; - A_UINT32 intr_low_threshold: 16, - prefetch_timer_cfg: 3, - response_required: 1, - reserved1: 12; + A_UINT32 msg_type: 8, + pdev_id: 8, + ring_id: 8, + ring_type: 8; + A_UINT32 ring_base_addr_lo; + A_UINT32 ring_base_addr_hi; + A_UINT32 ring_size: 16, + ring_entry_size: 8, + ring_misc_cfg_flag: 8; + A_UINT32 ring_head_offset32_remote_addr_lo; + A_UINT32 ring_head_offset32_remote_addr_hi; + A_UINT32 ring_tail_offset32_remote_addr_lo; + A_UINT32 ring_tail_offset32_remote_addr_hi; + A_UINT32 ring_msi_addr_lo; + A_UINT32 ring_msi_addr_hi; + A_UINT32 ring_msi_data; + A_UINT32 intr_batch_counter_th: 15, + sw_intr_mode: 1, + intr_timer_th: 16; + A_UINT32 intr_low_threshold: 16, + prefetch_timer_cfg: 3, + response_required: 1, + reserved1: 12; } POSTPACK; enum htt_srng_ring_type { - HTT_HW_TO_SW_RING = 0, - HTT_SW_TO_HW_RING, - HTT_SW_TO_SW_RING, - /* Insert new ring types above this line */ + HTT_HW_TO_SW_RING = 0, + HTT_SW_TO_HW_RING, + HTT_SW_TO_SW_RING, + /* Insert new ring types above this line */ }; enum htt_srng_ring_id { - HTT_RXDMA_HOST_BUF_RING = 0, /* Used by FW to feed remote buffers and update remote packets */ - HTT_RXDMA_MONITOR_STATUS_RING, /* For getting all PPDU/MPDU/MSDU status deescriptors on host for monitor VAP or packet log purposes */ - HTT_RXDMA_MONITOR_BUF_RING, /* For feeding free host buffers to RxDMA for monitor traffic upload */ - HTT_RXDMA_MONITOR_DESC_RING, /* For providing free LINK_DESC to RXDMA for monitor traffic upload */ - HTT_RXDMA_MONITOR_DEST_RING, /* Per MPDU indication to host for monitor traffic upload */ - HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */ - HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */ - /* Add Other SRING which can't be directly configured by host software above this line */ + /* Used by FW to feed remote buffers and update remote packets */ + HTT_RXDMA_HOST_BUF_RING = 0, + /* + * For getting all PPDU/MPDU/MSDU status deescriptors on host for + * monitor VAP or packet log purposes + */ + HTT_RXDMA_MONITOR_STATUS_RING, + /* For feeding free host buffers to RxDMA for monitor traffic upload */ + HTT_RXDMA_MONITOR_BUF_RING, + /* For providing free LINK_DESC to RXDMA for monitor traffic upload */ + HTT_RXDMA_MONITOR_DESC_RING, + /* Per MPDU indication to host for monitor traffic upload */ + HTT_RXDMA_MONITOR_DEST_RING, + /* (mobile only) used by host to provide remote RX buffers */ + HTT_HOST1_TO_FW_RXBUF_RING, + /* (mobile only) second ring used by host to provide remote RX buffers*/ + HTT_HOST2_TO_FW_RXBUF_RING, + /* + * Add Other SRING which can't be directly configured by host software + * above this line + */ }; #define HTT_SRING_SETUP_SZ (sizeof(struct htt_sring_setup_t)) #define HTT_SRING_SETUP_PDEV_ID_M 0x0000ff00 #define HTT_SRING_SETUP_PDEV_ID_S 8 -#define HTT_SRING_SETUP_PDEV_ID_GET(_var) \ - (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \ - HTT_SRING_SETUP_PDEV_ID_S) -#define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \ - } while (0) +#define HTT_SRING_SETUP_PDEV_ID_GET(_var) \ + (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \ + HTT_SRING_SETUP_PDEV_ID_S) +#define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \ + } while (0) #define HTT_SRING_SETUP_RING_ID_M 0x00ff0000 #define HTT_SRING_SETUP_RING_ID_S 16 -#define HTT_SRING_SETUP_RING_ID_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \ - HTT_SRING_SETUP_RING_ID_S) -#define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \ - } while (0) +#define HTT_SRING_SETUP_RING_ID_GET(_var) \ + (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \ + HTT_SRING_SETUP_RING_ID_S) +#define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \ + } while (0) #define HTT_SRING_SETUP_RING_TYPE_M 0xff000000 #define HTT_SRING_SETUP_RING_TYPE_S 24 -#define HTT_SRING_SETUP_RING_TYPE_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \ - HTT_SRING_SETUP_RING_TYPE_S) -#define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \ - } while (0) +#define HTT_SRING_SETUP_RING_TYPE_GET(_var) \ + (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \ + HTT_SRING_SETUP_RING_TYPE_S) +#define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \ + } while (0) #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_M 0xffffffff #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_S 0 -#define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \ - HTT_SRING_SETUP_RING_BASE_ADDR_LO_S) -#define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)); \ - } while (0) +#define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \ + (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \ + HTT_SRING_SETUP_RING_BASE_ADDR_LO_S) +#define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val);\ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S));\ + } while (0) #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_M 0xffffffff #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_S 0 -#define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \ - HTT_SRING_SETUP_RING_BASE_ADDR_HI_S) -#define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)); \ - } while (0) +#define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \ + (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \ + HTT_SRING_SETUP_RING_BASE_ADDR_HI_S) +#define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val);\ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S));\ + } while (0) #define HTT_SRING_SETUP_RING_SIZE_M 0x0000ffff #define HTT_SRING_SETUP_RING_SIZE_S 0 -#define HTT_SRING_SETUP_RING_SIZE_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \ - HTT_SRING_SETUP_RING_SIZE_S) -#define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \ - } while (0) +#define HTT_SRING_SETUP_RING_SIZE_GET(_var) \ + (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \ + HTT_SRING_SETUP_RING_SIZE_S) +#define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \ + } while (0) #define HTT_SRING_SETUP_ENTRY_SIZE_M 0x00ff00000 #define HTT_SRING_SETUP_ENTRY_SIZE_S 16 -#define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \ - (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \ - HTT_SRING_SETUP_ENTRY_SIZE_S) -#define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \ - } while (0) +#define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \ + (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \ + HTT_SRING_SETUP_ENTRY_SIZE_S) +#define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \ + } while (0) #define HTT_SRING_SETUP_MISC_CFG_FLAG_M 0xff0000000 #define HTT_SRING_SETUP_MISC_CFG_FLAG_S 24 -#define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var) \ - (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \ - HTT_SRING_SETUP_MISC_CFG_FLAG_S) +#define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var)\ + (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \ + HTT_SRING_SETUP_MISC_CFG_FLAG_S) #define HTT_SRING_SETUP_MISC_CFG_FLAG_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \ + } while (0) /* This control bit is applicable to only Producer, which updates Ring ID field -* of each descriptor before pushing into the ring. -* 0: updates ring_id(default) -* 1: ring_id updating disabled */ + * of each descriptor before pushing into the ring. + * 0: updates ring_id(default) + * 1: ring_id updating disabled + */ #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M 0x01 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S 0 -#define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M) >> \ - HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S) +#define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_GET(_var) \ + (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_M) >> \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE, _val);\ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RING_ID_DISABLE_S)); \ + } while (0) /* This control bit is applicable to only Producer, which updates Loopcnt field -* of each descriptor before pushing into the ring. -* 0: updates Loopcnt(default) -* 1: Loopcnt updating disabled */ + * of each descriptor before pushing into the ring. + * 0: updates Loopcnt(default) + * 1: Loopcnt updating disabled + */ #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M 0x02 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S 1 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M) >> \ - HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S) + (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_M) >> \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE, _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_LOOPCOUNT_DISABLE_S)); \ + } while (0) /* Secured access enable/disable bit. SRNG drives value of this register bit -* into security_id port of GXI/AXI. */ + * into security_id port of GXI/AXI. + */ #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M 0x04 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S 2 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M) >> \ - HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S) + (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_M) >> \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_SECURITY_S));\ + } while (0) /* During MSI write operation, SRNG drives value of this register bit into -* swap bit of GXI/AXI. */ + * swap bit of GXI/AXI. + */ #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M 0x08 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S 3 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ - HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) + (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ + } while (0) /* During Pointer write operation, SRNG drives value of this register bit into -* swap bit of GXI/AXI. */ + * swap bit of GXI/AXI. + */ #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M 0x10 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S 4 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M) >> \ - HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S) + (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_M) >> \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP, _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_HOST_FW_SWAP_S)); \ + } while (0) /* During any data or TLV write operation, SRNG drives value of this register -* bit into swap bit of GXI/AXI. */ + * bit into swap bit of GXI/AXI. + */ #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M 0x20 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S 5 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M) >> \ - HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S) + (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_M) >> \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_RING_MISC_CFG_FLAG_TLV_SWAP_S));\ + } while (0) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED1 0x40 #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_RESERVED2 0x80 @@ -4186,147 +4313,153 @@ enum htt_srng_ring_id { #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ - (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ - HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S) + (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ + HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S) #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ + } while (0) #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 -#define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ - (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ - HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S) -#define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ - } while (0) +#define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ + (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >>\ + HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S) +#define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val)\ + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val);\ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ + } while (0) #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ - (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ - HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S) + (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ + HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S) #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S));\ + } while (0) #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ - (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ - HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S) + (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ + HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S) #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ + ((_var) |= ((_val) << \ + HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ + } while (0) #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_M 0xffffffff #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_S 0 #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_LO_M) >> \ - HTT_SRING_SETUP_RING_MSI_ADDR_LO_S) + (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_LO_M) >> \ + HTT_SRING_SETUP_RING_MSI_ADDR_LO_S) #define HTT_SRING_SETUP_RING_MSI_ADDR_LO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_LO, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_LO, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_LO_S)); \ + } while (0) #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_M 0xffffffff #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_S 0 #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_HI_M) >> \ - HTT_SRING_SETUP_RING_MSI_ADDR_HI_S) + (((_var) & HTT_SRING_SETUP_RING_MSI_ADDR_HI_M) >> \ + HTT_SRING_SETUP_RING_MSI_ADDR_HI_S) #define HTT_SRING_SETUP_RING_MSI_ADDR_HI_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_HI, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_ADDR_HI, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_ADDR_HI_S)); \ + } while (0) #define HTT_SRING_SETUP_RING_MSI_DATA_M 0xffffffff #define HTT_SRING_SETUP_RING_MSI_DATA_S 0 #define HTT_SRING_SETUP_RING_MSI_DATA_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RING_MSI_DATA_M) >> \ - HTT_SRING_SETUP_RING_MSI_DATA_S) + (((_var) & HTT_SRING_SETUP_RING_MSI_DATA_M) >> \ + HTT_SRING_SETUP_RING_MSI_DATA_S) #define HTT_SRING_SETUP_RING_MSI_DATA_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_DATA, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_DATA_S)); \ - } while (0) - - + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MSI_DATA, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MSI_DATA_S)); \ + } while (0) #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M 0x00007fff #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S 0 #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_GET(_var) \ - (((_var) & HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M) >> \ - HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S) + (((_var) & HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_M) >> \ + HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S) #define HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)); \ - } while (0) +do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_BATCH_COUNTER_TH_S)); \ +} while (0) #define HTT_SRING_SETUP_SW_INTR_MODE_M 0x00008000 #define HTT_SRING_SETUP_SW_INTR_MODE_S 15 #define HTT_SRING_SETUP_SW_INTR_MODE_GET(_var) \ - (((_var) & HTT_SRING_SETUP_SW_INTR_MODE_M) >> \ - HTT_SRING_SETUP_SW_INTR_MODE_S) + (((_var) & HTT_SRING_SETUP_SW_INTR_MODE_M) >> \ + HTT_SRING_SETUP_SW_INTR_MODE_S) #define HTT_SRING_SETUP_SW_INTR_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_SW_INTR_MODE, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_SW_INTR_MODE_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_SW_INTR_MODE, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_SW_INTR_MODE_S)); \ + } while (0) #define HTT_SRING_SETUP_INTR_TIMER_TH_M 0xffff0000 #define HTT_SRING_SETUP_INTR_TIMER_TH_S 16 #define HTT_SRING_SETUP_INTR_TIMER_TH_GET(_var) \ - (((_var) & HTT_SRING_SETUP_INTR_TIMER_TH_M) >> \ - HTT_SRING_SETUP_INTR_TIMER_TH_S) + (((_var) & HTT_SRING_SETUP_INTR_TIMER_TH_M) >> \ + HTT_SRING_SETUP_INTR_TIMER_TH_S) #define HTT_SRING_SETUP_INTR_TIMER_TH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_TIMER_TH, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_TIMER_TH_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_TIMER_TH, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_TIMER_TH_S)); \ + } while (0) #define HTT_SRING_SETUP_INTR_LOW_TH_M 0x0000ffff #define HTT_SRING_SETUP_INTR_LOW_TH_S 0 #define HTT_SRING_SETUP_INTR_LOW_TH_GET(_var) \ - (((_var) & HTT_SRING_SETUP_INTR_LOW_TH_M) >> \ - HTT_SRING_SETUP_INTR_LOW_TH_S) + (((_var) & HTT_SRING_SETUP_INTR_LOW_TH_M) >> \ + HTT_SRING_SETUP_INTR_LOW_TH_S) #define HTT_SRING_SETUP_INTR_LOW_TH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_LOW_TH, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_LOW_TH_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_INTR_LOW_TH, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_INTR_LOW_TH_S)); \ + } while (0) #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M 0x00070000 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S 16 #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_GET(_var) \ - (((_var) & HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M) >> \ - HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S) + (((_var) & HTT_SRING_SETUP_PREFETCH_TIMER_CFG_M) >> \ + HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S) #define HTT_SRING_SETUP_PREFETCH_TIMER_CFG_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PREFETCH_TIMER_CFG, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PREFETCH_TIMER_CFG, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_PREFETCH_TIMER_CFG_S)); \ + } while (0) #define HTT_SRING_SETUP_RESPONSE_REQUIRED_M 0x00080000 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_S 19 #define HTT_SRING_SETUP_RESPONSE_REQUIRED_GET(_var) \ - (((_var) & HTT_SRING_SETUP_RESPONSE_REQUIRED_M) >> \ - HTT_SRING_SETUP_RESPONSE_REQUIRED_S) + (((_var) & HTT_SRING_SETUP_RESPONSE_REQUIRED_M) >> \ + HTT_SRING_SETUP_RESPONSE_REQUIRED_S) #define HTT_SRING_SETUP_RESPONSE_REQUIRED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RESPONSE_REQUIRED, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RESPONSE_REQUIRED, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ + } while (0) /** @@ -4400,295 +4533,361 @@ enum htt_srng_ring_id { * Refer to CFG_TLV_FILTER_IN_FLAG defs */ PREPACK struct htt_rx_ring_selection_cfg_t { - A_UINT32 msg_type: 8, - pdev_id: 8, - ring_id: 8, - status_swap: 1, - pkt_swap: 1, - rsvd1: 6; - A_UINT32 ring_buffer_size: 16, - rsvd2: 16; - A_UINT32 packet_type_enable_flags_0; - A_UINT32 packet_type_enable_flags_1; - A_UINT32 packet_type_enable_flags_2; - A_UINT32 packet_type_enable_flags_3; - A_UINT32 tlv_filter_in_flags; + A_UINT32 msg_type: 8, + pdev_id: 8, + ring_id: 8, + status_swap: 1, + pkt_swap: 1, + rsvd1: 6; + A_UINT32 ring_buffer_size: 16, + rsvd2: 16; + A_UINT32 packet_type_enable_flags_0; + A_UINT32 packet_type_enable_flags_1; + A_UINT32 packet_type_enable_flags_2; + A_UINT32 packet_type_enable_flags_3; + A_UINT32 tlv_filter_in_flags; } POSTPACK; -#define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) +#define HTT_RX_RING_SELECTION_CFG_SZ \ + (sizeof(struct htt_rx_ring_selection_cfg_t)) #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_S 8 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_PDEV_ID_M) >> \ - HTT_RX_RING_SELECTION_CFG_PDEV_ID_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_PDEV_ID_M) >> \ + HTT_RX_RING_SELECTION_CFG_PDEV_ID_S) #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PDEV_ID_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_RING_ID_M 0x00ff0000 #define HTT_RX_RING_SELECTION_CFG_RING_ID_S 16 #define HTT_RX_RING_SELECTION_CFG_RING_ID_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RING_ID_M) >> \ - HTT_RX_RING_SELECTION_CFG_RING_ID_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_RING_ID_M) >> \ + HTT_RX_RING_SELECTION_CFG_RING_ID_S) #define HTT_RX_RING_SELECTION_CFG_RING_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_ID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_ID_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M 0x01000000 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S 24 #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M) >> \ - HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_M) >> \ + HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S) #define HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SWAP_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M 0x02000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S 25 #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M) >> \ - HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_M) >> \ + HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S) #define HTT_RX_RING_SELECTION_CFG_PKT_TLV_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M) >> \ - HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M) >> \ + HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S) #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE,\ + _val); \ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S 0 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M) >> \ - HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M) >> \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0, \ + _val); \ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M 0xffffffff #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S 0 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M) >> \ - HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_M) >> \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1, _val);\ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_1_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M 0xffffffff #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S 0 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M) >> \ - HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_M) >> \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2, _val);\ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_2_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M 0xffffffff #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S 0 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M) >> \ - HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S) + (((_var) & HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_M) >> \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3, _val);\ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_3_S)); \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M 0xffffffff #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S 0 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M) >> \ - HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S) +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_M) >> \ + HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S) #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL( \ + HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG, _val); \ + ((_var) |= ((_val) << \ + HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \ + } while (0) /* * Subtype based MGMT frames enable bits. * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other */ /* association request */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0000_S 0 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_M 0x00000002 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_M \ + 0x00000002 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0000_S 1 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_M 0x00000004 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_M \ + 0x00000004 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0000_S 2 /* association response */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_M 0x00000008 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_M \ + 0x00000008 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0001_S 3 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_M 0x00000010 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_M \ + 0x00000010 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0001_S 4 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_M 0x00000020 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_M \ + 0x00000020 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0001_S 5 /* Reassociation request */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_M 0x00000040 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_M \ + 0x00000040 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0010_S 6 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_M 0x00000080 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_M \ + 0x00000080 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0010_S 7 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_M 0x00000100 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_M \ + 0x00000100 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0010_S 8 /* Reassociation response */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_M 0x00000200 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_M \ + 0x00000200 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0011_S 9 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_M 0x00000400 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_M \ + 0x00000400 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0011_S 10 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_M 0x00000800 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_M \ + 0x00000800 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0011_S 11 /* Probe request */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_M 0x00001000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_M \ + 0x00001000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0100_S 12 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_M 0x00002000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_M \ + 0x00002000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0100_S 13 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_M 0x00004000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_M \ + 0x00004000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0100_S 14 -/* Probe response */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_M 0x00008000 +/* Probe response */ +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_M \ + 0x00008000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0101_S 15 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_M 0x00010000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_M \ + 0x00010000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0101_S 16 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_M 0x00020000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_M \ + 0x00020000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0101_S 17 /* Timing Advertisement */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_M 0x00040000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_M \ + 0x00040000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0110_S 18 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_M 0x00080000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_M \ + 0x00080000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0110_S 19 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_M 0x00100000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_M \ + 0x00100000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0110_S 20 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_M 0x00200000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_M \ + 0x00200000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_0111_S 21 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_M 0x00400000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_M \ + 0x00400000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_0111_S 22 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_M 0x00800000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_M \ + 0x00800000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23 /* Beacon */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M \ + 0x01000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M \ + 0x02000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26 /* ATIM */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29 /* Disassociation */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1010_S 0 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_M 0x00000002 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_M \ + 0x00000002 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1010_S 1 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_M 0x00000004 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_M \ + 0x00000004 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1010_S 2 /* Authentication */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_M 0x00000008 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_M \ + 0x00000008 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1011_S 3 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_M 0x00000010 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_M \ + 0x00000010 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1011_S 4 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_M 0x00000020 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_M \ + 0x00000020 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1011_S 5 /* Deauthentication */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_M 0x00000040 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_M \ + 0x00000040 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1100_S 6 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_M 0x00000080 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_M \ + 0x00000080 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1100_S 7 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_M 0x00000100 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_M \ + 0x00000100 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1100_S 8 /* Action */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_M 0x00000200 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_M \ + 0x00000200 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1101_S 9 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_M 0x00000400 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_M \ + 0x00000400 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1101_S 10 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_M 0x00000800 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_M \ + 0x00000800 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1101_S 11 /* Action No Ack */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_M 0x00001000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_M \ + 0x00001000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1110_S 12 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_M 0x00002000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_M \ + 0x00002000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1110_S 13 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_M 0x00004000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_M \ + 0x00004000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1110_S 14 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_M 0x00008000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_M \ + 0x00008000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_FP_MGMT_1111_S 15 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_M 0x00010000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_M \ + 0x00010000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MD_MGMT_1111_S 16 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_M 0x00020000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_M \ + 0x00020000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG1_MO_MGMT_1111_S 17 /* @@ -4696,268 +4895,330 @@ PREPACK struct htt_rx_ring_selection_cfg_t { * FP: Filter_Pass, MD: Monitor_Direct, MO: Monitor_Other */ /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0000_S 0 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_M 0x00000002 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_M \ + 0x00000002 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0000_S 1 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_M 0x00000004 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_M \ + 0x00000004 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0000_S 2 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_M 0x00000008 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_M \ + 0x00000008 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0001_S 3 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_M 0x00000010 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_M \ + 0x00000010 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0001_S 4 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_M 0x00000020 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_M \ + 0x00000020 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0001_S 5 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_M 0x00000040 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_M \ + 0x00000040 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0010_S 6 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_M 0x00000080 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_M \ + 0x00000080 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0010_S 7 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_M 0x00000100 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_M \ + 0x00000100 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0010_S 8 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_M 0x00000200 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_M \ + 0x00000200 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0011_S 9 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_M 0x00000400 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_M \ + 0x00000400 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0011_S 10 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_M 0x00000800 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_M \ + 0x00000800 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0011_S 11 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_M 0x00001000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_M \ + 0x00001000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0100_S 12 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_M 0x00002000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_M \ + 0x00002000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0100_S 13 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_M 0x00004000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_M \ + 0x00004000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0100_S 14 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_M 0x00008000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_M \ + 0x00008000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0101_S 15 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_M 0x00010000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_M \ + 0x00010000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0101_S 16 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_M 0x00020000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_M \ + 0x00020000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0101_S 17 /* Reserved */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_M 0x00040000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_M \ + 0x00040000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0110_S 18 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_M 0x00080000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_M \ + 0x00080000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0110_S 19 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_M 0x00100000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_M \ + 0x00100000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0110_S 20 /* Control Wrapper */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_M 0x00200000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_M \ + 0x00200000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_0111_S 21 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_M 0x00400000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_M \ + 0x00400000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_0111_S 22 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_M 0x00800000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_M \ + 0x00800000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_0111_S 23 /* Block Ack Request */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_M 0x01000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_M \ + 0x01000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1000_S 24 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_M 0x02000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_M \ + 0x02000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1000_S 25 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1000_S 26 /* Block Ack*/ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_FP_CTRL_1001_S 27 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MD_CTRL_1001_S 28 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG2_MO_CTRL_1001_S 29 /* PS-POLL */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_M \ + 0x00000001 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1010_S 0 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_M 0x00000002 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_M \ + 0x00000002 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1010_S 1 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_M 0x00000004 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_M \ + 0x00000004 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1010_S 2 /* RTS */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_M 0x00000008 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_M \ + 0x00000008 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1011_S 3 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_M 0x00000010 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_M \ + 0x00000010 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1011_S 4 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_M 0x00000020 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_M \ + 0x00000020 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1011_S 5 /* CTS */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_M 0x00000040 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_M \ + 0x00000040 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1100_S 6 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_M 0x00000080 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_M \ + 0x00000080 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1100_S 7 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_M 0x00000100 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_M \ + 0x00000100 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1100_S 8 /* ACK */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_M 0x00000200 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_M \ + 0x00000200 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1101_S 9 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_M 0x00000400 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_M \ + 0x00000400 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1101_S 10 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_M 0x00000800 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_M \ + 0x00000800 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1101_S 11 /* CF-END */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_M 0x00001000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_M \ + 0x00001000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1110_S 12 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_M 0x00002000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_M \ + 0x00002000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1110_S 13 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_M 0x00004000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_M \ + 0x00004000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1110_S 14 /* CF-END + CF-ACK */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_M 0x00008000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_M \ + 0x00008000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_CTRL_1111_S 15 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_M 0x00010000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_M \ + 0x00010000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_CTRL_1111_S 16 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_M 0x00020000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_M \ + 0x00020000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_CTRL_1111_S 17 /* Multicast data */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_M 0x00040000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_M \ + 0x00040000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_MCAST_S 18 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_M 0x00080000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_M \ + 0x00080000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_MCAST_S 19 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_M 0x00100000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_M \ + 0x00100000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_MCAST_S 20 /* Unicast data */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_M 0x00200000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_M \ + 0x00200000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_UCAST_S 21 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_M 0x00400000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_M \ + 0x00400000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_UCAST_S 22 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_M 0x00800000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_M \ + 0x00800000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_UCAST_S 23 /* NULL data */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_M 0x01000000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_M \ + 0x01000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_FP_DATA_NULL_S 24 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_M 0x02000000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_M \ + 0x02000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MD_DATA_NULL_S 25 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M 0x04000000 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_M \ + 0x04000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG3_MO_DATA_NULL_S 26 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, httsym, value) \ - do { \ - HTT_CHECK_SET_VAL(httsym, value); \ - (word) |= (value) << httsym##_S; \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(httsym, value); \ + (word) |= (value) << httsym##_S; \ + } while (0) #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET(word, httsym) \ - (((word) & httsym##_M) >> httsym##_S) + (((word) & httsym##_M) >> httsym##_S) -#define htt_rx_ring_pkt_enable_subtype_set( \ - word, flag, mode, type, subtype, val) \ - HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET( \ - word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype, val) +#define htt_rx_ring_pkt_enable_subtype_set( \ + word, flag, mode, type, subtype, val) \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_SET(word, \ +HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype,\ + val) #define htt_rx_ring_pkt_enable_subtype_get( \ - word, flag, mode, type, subtype) \ - HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET( \ - word, HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype) + word, flag, mode, type, subtype) \ + HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_GET(word,\ +HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_##flag##_##mode##_##type##_##subtype) /* Definition to filter in TLVs */ -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_M 0x00000001 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_S 0 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_START_S 0 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_M 0x00000002 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_S 1 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_M 0x00000002 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_START_S 1 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_M 0x00000004 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_S 2 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_M 0x00000004 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_S 2 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_M 0x00000008 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_S 3 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_M 0x00000008 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MSDU_END_S 3 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_M 0x00000010 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_S 4 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_M 0x00000010 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_MPDU_END_S 4 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_M 0x00000020 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_S 5 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_M \ + 0x00000020 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PACKET_HEADER_S 5 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_M 0x00000040 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_S 6 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_M 0x00000040 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_RESERVED_S 6 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_M 0x00000080 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_S 7 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_M 0x00000080 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_ATTENTION_S 7 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_M 0x00000100 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_S 8 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_M 0x00000100 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_START_S 8 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_M 0x00000200 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_S 9 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_M 0x00000200 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_S 9 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_M 0x00000400 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_S 10 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_M \ + 0x00000400 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_S 10 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_M 0x00000800 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_M 0x00000800 #define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_USER_STATS_EXT_S 11 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_M 0x00001000 -#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_S 12 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_M \ + 0x00001000 +#define HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_PPDU_END_STATUS_DONE_S\ + 12 #define HTT_RX_RING_TLV_ENABLE_SET(word, httsym, enable) \ - do { \ - HTT_CHECK_SET_VAL(httsym, enable); \ - (word) |= (enable) << httsym##_S; \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(httsym, enable); \ + (word) |= (enable) << httsym##_S; \ + } while (0) #define HTT_RX_RING_TLV_ENABLE_GET(word, httsym) \ - (((word) & httsym##_M) >> httsym##_S) + (((word) & httsym##_M) >> httsym##_S) #define htt_rx_ring_tlv_filter_in_enable_set(word, tlv, enable) \ - HTT_RX_RING_TLV_ENABLE_SET( \ - word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv, enable) + HTT_RX_RING_TLV_ENABLE_SET( \ + word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv, enable) -#define htt_rx_ring_tlv_filter_in_enable_get(word, tlv) \ - HTT_RX_RING_TLV_ENABLE_GET( \ - word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv) +#define htt_rx_ring_tlv_filter_in_enable_get(word, tlv) \ + HTT_RX_RING_TLV_ENABLE_GET(word, \ + HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv) /** * @brief HTT_H2T_MSG_TYPE_RFS_CONFIG @@ -4984,55 +5245,55 @@ PREPACK struct htt_rx_ring_selection_cfg_t { * Purpose: Tells target whether to enable (1) or disable (0) * flow steering feature when sending rx indication messages to host */ +#define HTT_RFS_CFG_REQ_BYTES 4 #define HTT_H2T_RFS_CONFIG_M 0x100 #define HTT_H2T_RFS_CONFIG_S 8 -#define HTT_RX_RFS_CONFIG_GET(_var) \ - (((_var) & HTT_H2T_RFS_CONFIG_M) >> \ - HTT_H2T_RFS_CONFIG_S) -#define HTT_RX_RFS_CONFIG_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_RFS_CONFIG, _val); \ - ((_var) |= ((_val) << HTT_H2T_RFS_CONFIG_S)); \ - } while (0) - +#define HTT_RX_RFS_CONFIG_GET(_var) \ + (((_var) & HTT_H2T_RFS_CONFIG_M) >> \ + HTT_H2T_RFS_CONFIG_S) +#define HTT_RX_RFS_CONFIG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_RFS_CONFIG, _val); \ + ((_var) |= ((_val) << HTT_H2T_RFS_CONFIG_S)); \ + } while (0) /*=== target -> host messages ===============================================*/ enum htt_t2h_msg_type { - HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, - HTT_T2H_MSG_TYPE_RX_IND = 0x1, - HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, - HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, - HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, - HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, - HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, - HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, - HTT_T2H_MSG_TYPE_PKTLOG = 0x8, - HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, - HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, - HTT_T2H_MSG_TYPE_SEC_IND = 0xb, - DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* no longer used */ - HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, - HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, - /* only used for HL, add HTT MSG for HTT CREDIT update */ - HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, - HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10, - HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, - HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, - /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */ - HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, - HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, - HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, - HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17, - HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18, - HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19, - HTT_T2H_MSG_TYPE_SRING_SETUP_DONE = 0x1a, - HTT_T2H_MSG_TYPE_MAP_FLOW_INFO = 0x1b, + HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, + HTT_T2H_MSG_TYPE_RX_IND = 0x1, + HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, + HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, + HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, + HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, + HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, + HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, + HTT_T2H_MSG_TYPE_PKTLOG = 0x8, + HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, + HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, + HTT_T2H_MSG_TYPE_SEC_IND = 0xb, + DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,/* no longer used */ + HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, + HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, + /* only used for HL, add HTT MSG for HTT CREDIT update */ + HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, + HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10, + HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, + HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, + /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */ + HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, + HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, + HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, + HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17, + HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18, + HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19, + HTT_T2H_MSG_TYPE_SRING_SETUP_DONE = 0x1a, + HTT_T2H_MSG_TYPE_MAP_FLOW_INFO = 0x1b, - HTT_T2H_MSG_TYPE_TEST, - /* keep this last */ - HTT_T2H_NUM_MSGS + HTT_T2H_MSG_TYPE_TEST, + /* keep this last */ + HTT_T2H_NUM_MSGS }; /* @@ -5042,13 +5303,13 @@ enum htt_t2h_msg_type { #define HTT_T2H_MSG_TYPE_M 0xff #define HTT_T2H_MSG_TYPE_S 0 -#define HTT_T2H_MSG_TYPE_SET(word, msg_type) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \ - (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \ - } while (0) -#define HTT_T2H_MSG_TYPE_GET(word) \ - (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S) +#define HTT_T2H_MSG_TYPE_SET(word, msg_type) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \ + (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \ + } while (0) +#define HTT_T2H_MSG_TYPE_GET(word) \ + (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S) /** * @brief target -> host version number confirmation message definition @@ -5102,21 +5363,21 @@ enum htt_t2h_msg_type { #define HTT_VER_CONF_MAJOR_S 16 -#define HTT_VER_CONF_MINOR_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \ - (word) |= (value) << HTT_VER_CONF_MINOR_S; \ - } while (0) -#define HTT_VER_CONF_MINOR_GET(word) \ - (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S) +#define HTT_VER_CONF_MINOR_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \ + (word) |= (value) << HTT_VER_CONF_MINOR_S; \ + } while (0) +#define HTT_VER_CONF_MINOR_GET(word) \ + (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S) -#define HTT_VER_CONF_MAJOR_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \ - (word) |= (value) << HTT_VER_CONF_MAJOR_S; \ - } while (0) -#define HTT_VER_CONF_MAJOR_GET(word) \ - (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S) +#define HTT_VER_CONF_MAJOR_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \ + (word) |= (value) << HTT_VER_CONF_MAJOR_S; \ + } while (0) +#define HTT_VER_CONF_MAJOR_GET(word) \ + (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S) #define HTT_VER_CONF_BYTES 4 @@ -5134,16 +5395,16 @@ enum htt_t2h_msg_type { * | MSDU count | Reserved | vdev id | * |--------------------------------------------------------------------------| * | MSDU 0 bus address (bits 31:0) | -#if HTT_PADDR64 + #if HTT_PADDR64 * | MSDU 0 bus address (bits 63:32) | -#endif + #endif * |--------------------------------------------------------------------------| * | MSDU info | MSDU 0 FW Desc | MSDU 0 Length | * |--------------------------------------------------------------------------| * | MSDU 1 bus address (bits 31:0) | -#if HTT_PADDR64 + #if HTT_PADDR64 * | MSDU 1 bus address (bits 63:32) | -#endif + #endif * |--------------------------------------------------------------------------| * | MSDU info | MSDU 1 FW Desc | MSDU 1 Length | * |--------------------------------------------------------------------------| @@ -5162,56 +5423,67 @@ enum htt_t2h_msg_type { * (see fw_rx_msdu_info def in wal_rx_desc.h) */ -struct htt_rx_in_ord_paddr_ind_hdr_t -{ - A_UINT32 /* word 0 */ - msg_type: 8, - ext_tid: 5, - offload: 1, - frag: 1, - pktlog: 1, /* tell host whether to store MSDUs referenced in this message in pktlog */ - peer_id: 16; +struct htt_rx_in_ord_paddr_ind_hdr_t { + A_UINT32 /* word 0 */ + msg_type:8, + ext_tid:5, + offload:1, + frag:1, + /* + * Tell host whether to store MSDUs referenced in this message + * in pktlog + */ + pktlog:1, + peer_id:16; - A_UINT32 /* word 1 */ - vap_id: 8, - reserved_1: 8, - msdu_cnt: 16; + A_UINT32 /* word 1 */ + vap_id:8, + reserved_1:8, + msdu_cnt:16; }; -struct htt_rx_in_ord_paddr_ind_msdu32_t -{ - A_UINT32 dma_addr; - A_UINT32 - length: 16, - fw_desc: 8, - msdu_info:8; +struct htt_rx_in_ord_paddr_ind_msdu32_t { + A_UINT32 dma_addr; + A_UINT32 + length:16, + fw_desc:8, + msdu_info:8; }; -struct htt_rx_in_ord_paddr_ind_msdu64_t -{ - A_UINT32 dma_addr_lo; - A_UINT32 dma_addr_hi; - A_UINT32 - length: 16, - fw_desc: 8, - msdu_info:8; +struct htt_rx_in_ord_paddr_ind_msdu64_t { + A_UINT32 dma_addr_lo; + A_UINT32 dma_addr_hi; + A_UINT32 + length:16, + fw_desc:8, + msdu_info:8; }; #if HTT_PADDR64 - #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t +#define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t #else - #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t +#define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t #endif -#define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t)) -#define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t)) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t)) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t)) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2) +#define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES \ + (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t)) +#define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS \ + (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET \ + HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET \ + HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 \ + (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t)) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 \ + (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 \ + (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t)) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 \ + (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES \ + (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t)) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS \ + (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2) #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M 0x00001f00 #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S 8 @@ -5243,130 +5515,141 @@ struct htt_rx_in_ord_paddr_ind_msdu64_t #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S 24 -#define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S) +#define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \ + } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S) -#define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S) +#define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \ + } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S) -#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S) +#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \ + } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \ + } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S) /* for systems using 64-bit format for bus addresses */ -#define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S) -#define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S) +#define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \ +} while (0) +#define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S) +#define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \ +} while (0) +#define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S) /* for systems using 32-bit format for bus addresses */ -#define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> HTT_RX_IN_ORD_PADDR_IND_PADDR_S) +#define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \ +} while (0) +#define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_PADDR_S) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \ - } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value);\ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \ +} while (0) #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S) + (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S) -#define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S) +#define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \ +} while (0) +#define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S) -#define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S; \ - } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value);\ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S;\ +} while (0) #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S) + (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S) -#define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value); \ - (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S) - -#define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \ - (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> HTT_RX_IN_ORD_PADDR_IND_FRAG_S) +#define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value);\ + (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \ +} while (0) +#define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S) +#define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \ + (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \ +} while (0) +#define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_FRAG_S) #define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKTLOG, value); \ - (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S; \ - } while (0) -#define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_GET(word) \ - (((word) & HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M) >> HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKTLOG, value); \ + (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S; \ + } while (0) +#define HTT_RX_IN_ORD_PADDR_IND_PKTLOG_GET(word) \ + (((word) & HTT_RX_IN_ORD_PADDR_IND_PKTLOG_M) >> \ + HTT_RX_IN_ORD_PADDR_IND_PKTLOG_S) /* definitions used within target -> host rx indication message */ -PREPACK struct htt_rx_ind_hdr_prefix_t -{ - A_UINT32 /* word 0 */ - msg_type: 8, - ext_tid: 5, - release_valid: 1, - flush_valid: 1, - reserved0: 1, - peer_id: 16; +PREPACK struct htt_rx_ind_hdr_prefix_t { + A_UINT32 /* word 0 */ + msg_type:8, + ext_tid:5, + release_valid:1, + flush_valid:1, + reserved0:1, + peer_id:16; - A_UINT32 /* word 1 */ - flush_start_seq_num: 6, - flush_end_seq_num: 6, - release_start_seq_num: 6, - release_end_seq_num: 6, - num_mpdu_ranges: 8; + A_UINT32 /* word 1 */ + flush_start_seq_num:6, + flush_end_seq_num:6, + release_start_seq_num:6, + release_end_seq_num:6, + num_mpdu_ranges:8; } POSTPACK; #define HTT_RX_IND_HDR_PREFIX_BYTES (sizeof(struct htt_rx_ind_hdr_prefix_t)) @@ -5374,102 +5657,99 @@ PREPACK struct htt_rx_ind_hdr_prefix_t #define HTT_TGT_RSSI_INVALID 0x80 -PREPACK struct htt_rx_ppdu_desc_t -{ - #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0 - #define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0 - A_UINT32 /* word 0 */ - rssi_cmb: 8, - timestamp_submicrosec: 8, - phy_err_code: 8, - phy_err: 1, - legacy_rate: 4, - legacy_rate_sel: 1, - end_valid: 1, - start_valid: 1; +PREPACK struct htt_rx_ppdu_desc_t { +#define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0 +#define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0 + A_UINT32 /* word 0 */ + rssi_cmb:8, + timestamp_submicrosec:8, + phy_err_code:8, + phy_err:1, + legacy_rate:4, + legacy_rate_sel:1, + end_valid:1, + start_valid:1; - #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1 - union { - A_UINT32 /* word 1 */ - rssi0_pri20: 8, - rssi0_ext20: 8, - rssi0_ext40: 8, - rssi0_ext80: 8; - A_UINT32 rssi0; /* access all 20/40/80 per-bandwidth RSSIs together */ - } u0; +#define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1 + union { + A_UINT32 /* word 1 */ + rssi0_pri20:8, + rssi0_ext20:8, + rssi0_ext40:8, + rssi0_ext80:8; + A_UINT32 rssi0; /* access all 20/40/80 per-b/w RSSIs together */ + } u0; - #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2 - union { - A_UINT32 /* word 2 */ - rssi1_pri20: 8, - rssi1_ext20: 8, - rssi1_ext40: 8, - rssi1_ext80: 8; - A_UINT32 rssi1; /* access all 20/40/80 per-bandwidth RSSIs together */ - } u1; +#define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2 + union { + A_UINT32 /* word 2 */ + rssi1_pri20:8, + rssi1_ext20:8, + rssi1_ext40:8, + rssi1_ext80:8; + A_UINT32 rssi1; /* access all 20/40/80 per-b/w RSSIs together */ + } u1; - #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3 - union { - A_UINT32 /* word 3 */ - rssi2_pri20: 8, - rssi2_ext20: 8, - rssi2_ext40: 8, - rssi2_ext80: 8; - A_UINT32 rssi2; /* access all 20/40/80 per-bandwidth RSSIs together */ - } u2; +#define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3 + union { + A_UINT32 /* word 3 */ + rssi2_pri20:8, + rssi2_ext20:8, + rssi2_ext40:8, + rssi2_ext80:8; + A_UINT32 rssi2; /* access all 20/40/80 per-b/w RSSIs together */ + } u2; - #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4 - union { - A_UINT32 /* word 4 */ - rssi3_pri20: 8, - rssi3_ext20: 8, - rssi3_ext40: 8, - rssi3_ext80: 8; - A_UINT32 rssi3; /* access all 20/40/80 per-bandwidth RSSIs together */ - } u3; +#define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4 + union { + A_UINT32 /* word 4 */ + rssi3_pri20:8, + rssi3_ext20:8, + rssi3_ext40:8, + rssi3_ext80:8; + A_UINT32 rssi3; /* access all 20/40/80 per-b/w RSSIs together */ + } u3; - #define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5 - A_UINT32 tsf32; /* word 5 */ +#define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5 + A_UINT32 tsf32; /* word 5 */ - #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6 - A_UINT32 timestamp_microsec; /* word 6 */ +#define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6 + A_UINT32 timestamp_microsec; /* word 6 */ - #define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7 - #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7 - A_UINT32 /* word 7 */ - vht_sig_a1: 24, - preamble_type: 8; +#define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7 +#define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7 + A_UINT32 /* word 7 */ + vht_sig_a1:24, + preamble_type:8; - #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8 - A_UINT32 /* word 8 */ - vht_sig_a2: 24, - reserved0: 8; +#define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8 + A_UINT32 /* word 8 */ + vht_sig_a2:24, + reserved0:8; } POSTPACK; #define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t)) #define HTT_RX_PPDU_DESC_SIZE32 (HTT_RX_PPDU_DESC_BYTES >> 2) -PREPACK struct htt_rx_ind_hdr_suffix_t -{ - A_UINT32 /* word 0 */ - fw_rx_desc_bytes: 16, - reserved0: 16; +PREPACK struct htt_rx_ind_hdr_suffix_t { + A_UINT32 /* word 0 */ + fw_rx_desc_bytes:16, + reserved0:16; } POSTPACK; #define HTT_RX_IND_HDR_SUFFIX_BYTES (sizeof(struct htt_rx_ind_hdr_suffix_t)) #define HTT_RX_IND_HDR_SUFFIX_SIZE32 (HTT_RX_IND_HDR_SUFFIX_BYTES >> 2) -PREPACK struct htt_rx_ind_hdr_t -{ - struct htt_rx_ind_hdr_prefix_t prefix; - struct htt_rx_ppdu_desc_t rx_ppdu_desc; - struct htt_rx_ind_hdr_suffix_t suffix; +PREPACK struct htt_rx_ind_hdr_t { + struct htt_rx_ind_hdr_prefix_t prefix; + struct htt_rx_ppdu_desc_t rx_ppdu_desc; + struct htt_rx_ind_hdr_suffix_t suffix; } POSTPACK; #define HTT_RX_IND_HDR_BYTES (sizeof(struct htt_rx_ind_hdr_t)) @@ -5477,7 +5757,7 @@ PREPACK struct htt_rx_ind_hdr_t /* confirm that HTT_RX_IND_HDR_BYTES is a multiple of 4 */ A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, - (HTT_RX_IND_HDR_BYTES & 0x3) == 0); + (HTT_RX_IND_HDR_BYTES & 0x3) == 0); /* * HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET: @@ -5491,8 +5771,8 @@ A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, * the offset into the HTT rx indication message at which the * header suffix (FW rx MSDU byte count) resides */ -#define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \ - (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES) +#define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \ + (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES) /* * HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET: @@ -5953,273 +6233,278 @@ A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, #define HTT_RX_IND_MPDU_STATUS_S 8 -#define HTT_RX_IND_EXT_TID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \ - (word) |= (value) << HTT_RX_IND_EXT_TID_S; \ - } while (0) -#define HTT_RX_IND_EXT_TID_GET(word) \ - (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S) +#define HTT_RX_IND_EXT_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \ + (word) |= (value) << HTT_RX_IND_EXT_TID_S; \ + } while (0) +#define HTT_RX_IND_EXT_TID_GET(word) \ + (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S) -#define HTT_RX_IND_FLUSH_VALID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \ - (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \ - } while (0) -#define HTT_RX_IND_FLUSH_VALID_GET(word) \ - (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S) +#define HTT_RX_IND_FLUSH_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \ + (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \ + } while (0) +#define HTT_RX_IND_FLUSH_VALID_GET(word) \ + (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S) -#define HTT_RX_IND_REL_VALID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \ - (word) |= (value) << HTT_RX_IND_REL_VALID_S; \ - } while (0) -#define HTT_RX_IND_REL_VALID_GET(word) \ - (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S) +#define HTT_RX_IND_REL_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \ + (word) |= (value) << HTT_RX_IND_REL_VALID_S; \ + } while (0) +#define HTT_RX_IND_REL_VALID_GET(word) \ + (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S) -#define HTT_RX_IND_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \ - (word) |= (value) << HTT_RX_IND_PEER_ID_S; \ - } while (0) -#define HTT_RX_IND_PEER_ID_GET(word) \ - (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S) +#define HTT_RX_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \ + (word) |= (value) << HTT_RX_IND_PEER_ID_S; \ + } while (0) +#define HTT_RX_IND_PEER_ID_GET(word) \ + (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S) -#define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \ - (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \ - } while (0) -#define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \ - (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> HTT_RX_IND_FW_RX_DESC_BYTES_S) +#define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \ + (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \ + } while (0) +#define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \ + (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> \ + HTT_RX_IND_FW_RX_DESC_BYTES_S) -#define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \ - (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \ - } while (0) -#define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \ - (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \ - HTT_RX_IND_FLUSH_SEQ_NUM_START_S) +#define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \ + (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \ + } while (0) +#define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \ + (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \ + HTT_RX_IND_FLUSH_SEQ_NUM_START_S) -#define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \ - (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \ - } while (0) -#define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \ - (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \ - HTT_RX_IND_FLUSH_SEQ_NUM_END_S) +#define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \ + (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \ + } while (0) +#define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \ + (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \ + HTT_RX_IND_FLUSH_SEQ_NUM_END_S) -#define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \ - (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \ - } while (0) -#define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \ - (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \ - HTT_RX_IND_REL_SEQ_NUM_START_S) +#define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \ + (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \ + } while (0) +#define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \ + (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \ + HTT_RX_IND_REL_SEQ_NUM_START_S) -#define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \ - (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \ - } while (0) -#define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \ - (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \ - HTT_RX_IND_REL_SEQ_NUM_END_S) +#define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \ + (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \ + } while (0) +#define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \ + (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \ + HTT_RX_IND_REL_SEQ_NUM_END_S) -#define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \ - (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \ - } while (0) -#define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \ - (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \ - HTT_RX_IND_NUM_MPDU_RANGES_S) +#define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \ + (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \ + } while (0) +#define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \ + (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \ + HTT_RX_IND_NUM_MPDU_RANGES_S) /* FW rx PPDU descriptor fields */ -#define HTT_RX_IND_RSSI_CMB_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \ - (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \ - } while (0) -#define HTT_RX_IND_RSSI_CMB_GET(word) \ - (((word) & HTT_RX_IND_RSSI_CMB_M) >> \ - HTT_RX_IND_RSSI_CMB_S) +#define HTT_RX_IND_RSSI_CMB_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \ + (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \ + } while (0) +#define HTT_RX_IND_RSSI_CMB_GET(word) \ + (((word) & HTT_RX_IND_RSSI_CMB_M) >> \ + HTT_RX_IND_RSSI_CMB_S) -#define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \ - (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \ - } while (0) -#define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \ - (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \ - HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S) +#define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \ + (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \ + } while (0) +#define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \ + (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \ + HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S) -#define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \ - (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \ - } while (0) -#define HTT_RX_IND_PHY_ERR_CODE_GET(word) \ - (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \ - HTT_RX_IND_PHY_ERR_CODE_S) +#define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \ + (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \ + } while (0) +#define HTT_RX_IND_PHY_ERR_CODE_GET(word) \ + (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \ + HTT_RX_IND_PHY_ERR_CODE_S) -#define HTT_RX_IND_PHY_ERR_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \ - (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \ - } while (0) -#define HTT_RX_IND_PHY_ERR_GET(word) \ - (((word) & HTT_RX_IND_PHY_ERR_M) >> \ - HTT_RX_IND_PHY_ERR_S) +#define HTT_RX_IND_PHY_ERR_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \ + (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \ + } while (0) +#define HTT_RX_IND_PHY_ERR_GET(word) \ + (((word) & HTT_RX_IND_PHY_ERR_M) >> \ + HTT_RX_IND_PHY_ERR_S) -#define HTT_RX_IND_LEGACY_RATE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \ - (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \ - } while (0) -#define HTT_RX_IND_LEGACY_RATE_GET(word) \ - (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \ - HTT_RX_IND_LEGACY_RATE_S) +#define HTT_RX_IND_LEGACY_RATE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \ + (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \ + } while (0) +#define HTT_RX_IND_LEGACY_RATE_GET(word) \ + (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \ + HTT_RX_IND_LEGACY_RATE_S) -#define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \ - (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \ - } while (0) -#define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \ - (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \ - HTT_RX_IND_LEGACY_RATE_SEL_S) +#define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \ + (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \ + } while (0) +#define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \ + (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \ + HTT_RX_IND_LEGACY_RATE_SEL_S) -#define HTT_RX_IND_END_VALID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \ - (word) |= (value) << HTT_RX_IND_END_VALID_S; \ - } while (0) -#define HTT_RX_IND_END_VALID_GET(word) \ - (((word) & HTT_RX_IND_END_VALID_M) >> \ - HTT_RX_IND_END_VALID_S) +#define HTT_RX_IND_END_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \ + (word) |= (value) << HTT_RX_IND_END_VALID_S; \ + } while (0) +#define HTT_RX_IND_END_VALID_GET(word) \ + (((word) & HTT_RX_IND_END_VALID_M) >> \ + HTT_RX_IND_END_VALID_S) -#define HTT_RX_IND_START_VALID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \ - (word) |= (value) << HTT_RX_IND_START_VALID_S; \ - } while (0) -#define HTT_RX_IND_START_VALID_GET(word) \ - (((word) & HTT_RX_IND_START_VALID_M) >> \ - HTT_RX_IND_START_VALID_S) +#define HTT_RX_IND_START_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \ + (word) |= (value) << HTT_RX_IND_START_VALID_S; \ + } while (0) +#define HTT_RX_IND_START_VALID_GET(word) \ + (((word) & HTT_RX_IND_START_VALID_M) >> \ + HTT_RX_IND_START_VALID_S) -#define HTT_RX_IND_RSSI_PRI20_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \ - (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \ - } while (0) -#define HTT_RX_IND_RSSI_PRI20_GET(word) \ - (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \ - HTT_RX_IND_RSSI_PRI20_S) +#define HTT_RX_IND_RSSI_PRI20_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \ + (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \ + } while (0) +#define HTT_RX_IND_RSSI_PRI20_GET(word) \ + (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \ + HTT_RX_IND_RSSI_PRI20_S) -#define HTT_RX_IND_RSSI_EXT20_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \ - (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \ - } while (0) -#define HTT_RX_IND_RSSI_EXT20_GET(word) \ - (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \ - HTT_RX_IND_RSSI_EXT20_S) +#define HTT_RX_IND_RSSI_EXT20_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \ + (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \ + } while (0) +#define HTT_RX_IND_RSSI_EXT20_GET(word) \ + (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \ + HTT_RX_IND_RSSI_EXT20_S) -#define HTT_RX_IND_RSSI_EXT40_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \ - (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \ - } while (0) -#define HTT_RX_IND_RSSI_EXT40_GET(word) \ - (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \ - HTT_RX_IND_RSSI_EXT40_S) +#define HTT_RX_IND_RSSI_EXT40_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \ + (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \ + } while (0) +#define HTT_RX_IND_RSSI_EXT40_GET(word) \ + (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \ + HTT_RX_IND_RSSI_EXT40_S) -#define HTT_RX_IND_RSSI_EXT80_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \ - (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \ - } while (0) -#define HTT_RX_IND_RSSI_EXT80_GET(word) \ - (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \ - HTT_RX_IND_RSSI_EXT80_S) +#define HTT_RX_IND_RSSI_EXT80_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \ + (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \ + } while (0) +#define HTT_RX_IND_RSSI_EXT80_GET(word) \ + (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \ + HTT_RX_IND_RSSI_EXT80_S) -#define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \ - (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \ - } while (0) -#define HTT_RX_IND_VHT_SIG_A1_GET(word) \ - (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \ - HTT_RX_IND_VHT_SIG_A1_S) +#define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \ + (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \ + } while (0) +#define HTT_RX_IND_VHT_SIG_A1_GET(word) \ + (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \ + HTT_RX_IND_VHT_SIG_A1_S) -#define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \ - (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \ - } while (0) -#define HTT_RX_IND_VHT_SIG_A2_GET(word) \ - (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \ - HTT_RX_IND_VHT_SIG_A2_S) +#define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \ + (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \ + } while (0) +#define HTT_RX_IND_VHT_SIG_A2_GET(word) \ + (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \ + HTT_RX_IND_VHT_SIG_A2_S) -#define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \ - (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \ - } while (0) -#define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \ - (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \ - HTT_RX_IND_PREAMBLE_TYPE_S) +#define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \ + (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \ + } while (0) +#define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \ + (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \ + HTT_RX_IND_PREAMBLE_TYPE_S) -#define HTT_RX_IND_SERVICE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \ - (word) |= (value) << HTT_RX_IND_SERVICE_S; \ - } while (0) -#define HTT_RX_IND_SERVICE_GET(word) \ - (((word) & HTT_RX_IND_SERVICE_M) >> \ - HTT_RX_IND_SERVICE_S) +#define HTT_RX_IND_SERVICE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \ + (word) |= (value) << HTT_RX_IND_SERVICE_S; \ + } while (0) +#define HTT_RX_IND_SERVICE_GET(word) \ + (((word) & HTT_RX_IND_SERVICE_M) >> \ + HTT_RX_IND_SERVICE_S) #define HTT_RX_IND_MPDU_COUNT_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \ - (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \ - } while (0) -#define HTT_RX_IND_MPDU_COUNT_GET(word) \ - (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \ + (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \ + } while (0) +#define HTT_RX_IND_MPDU_COUNT_GET(word) \ + (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S) #define HTT_RX_IND_MPDU_STATUS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \ - (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \ - } while (0) -#define HTT_RX_IND_MPDU_STATUS_GET(word) \ - (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \ + (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \ + } while (0) +#define HTT_RX_IND_MPDU_STATUS_GET(word) \ + (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S) -#define HTT_RX_IND_HL_BYTES \ - (HTT_RX_IND_HDR_BYTES + \ - 4 /* single FW rx MSDU descriptor, plus padding */ + \ - 4 /* single MPDU range information element */) +#define HTT_RX_IND_HL_BYTES \ + (HTT_RX_IND_HDR_BYTES + \ + 4 /* single FW rx MSDU descriptor, plus padding */ + \ + 4 /* single MPDU range information element */) #define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2) /* Could we use one macro entry? */ -#define HTT_WORD_SET(word, field, value) \ - do { \ - HTT_CHECK_SET_VAL(field, value); \ - (word) |= ((value) << field ## _S); \ - } while (0) -#define HTT_WORD_GET(word, field) \ - (((word) & field ## _M) >> field ## _S) +#define HTT_WORD_SET(word, field, value) \ + do { \ + HTT_CHECK_SET_VAL(field, value); \ + (word) |= ((value) << field ## _S); \ + } while (0) +#define HTT_WORD_GET(word, field) \ + (((word) & field ## _M) >> field ## _S) PREPACK struct hl_htt_rx_ind_base { - A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; /* align with LL case rx indication message, but reduced to 5 words */ + /* + * align with LL case rx indication message,but + * reduced to 5 words + */ + A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; } POSTPACK; /* @@ -6227,74 +6512,71 @@ PREPACK struct hl_htt_rx_ind_base { * Currently, we use a resv field in hl_htt_rx_ind_base to store some * HL host needed info. The field is just after the msdu fw rx desc. */ -#define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1) +#define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ + (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1) struct htt_rx_ind_hl_rx_desc_t { - A_UINT8 ver; - A_UINT8 len; - struct { - A_UINT8 - first_msdu: 1, - last_msdu: 1, - c3_failed: 1, - c4_failed: 1, - ipv6: 1, - tcp: 1, - udp: 1, - reserved: 1; - } flags; + A_UINT8 ver; + A_UINT8 len; + struct { + A_UINT8 + first_msdu:1, + last_msdu:1, + c3_failed:1, + c4_failed:1, + ipv6:1, + tcp:1, + udp:1, + reserved:1; + } flags; }; -#define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \ - (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ - + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver)) +#define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \ + (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ + + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver)) #define HTT_RX_IND_HL_RX_DESC_VER 0 -#define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \ - (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ - + offsetof(struct htt_rx_ind_hl_rx_desc_t, len)) +#define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \ + (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ + + offsetof(struct htt_rx_ind_hl_rx_desc_t, len)) -#define HTT_RX_IND_HL_FLAG_OFFSET \ - (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ - + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags)) +#define HTT_RX_IND_HL_FLAG_OFFSET \ + (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ + + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags)) #define HTT_RX_IND_HL_FLAG_FIRST_MSDU (0x01 << 0) #define HTT_RX_IND_HL_FLAG_LAST_MSDU (0x01 << 1) -#define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */ -#define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */ -#define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or else ipv4 */ -#define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */ -#define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */ +#define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */ +#define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */ +#define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or ipv4 */ +#define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */ +#define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */ /* This structure is used in HL, the basic descriptor information * used by host. the structure is translated by FW from HW desc * or generated by FW. But in HL monitor mode, the host would use * the same structure with LL. */ PREPACK struct hl_htt_rx_desc_base { - A_UINT32 - seq_num:12, - encrypted:1, - chan_info_present:1, - resv0:2, - mcast_bcast:1, - fragment:1, - key_id_oct:8, - resv1:6; - A_UINT32 - pn_31_0; - union { - struct { - A_UINT16 pn_47_32; - A_UINT16 pn_63_48; - } pn16; - A_UINT32 pn_63_32; - } u0; - A_UINT32 - pn_95_64; - A_UINT32 - pn_127_96; + A_UINT32 + seq_num:12, + encrypted:1, + chan_info_present:1, + resv0:2, + mcast_bcast:1, + fragment:1, + key_id_oct:8, + resv1:6; + A_UINT32 pn_31_0; + union { + struct { + A_UINT16 pn_47_32; + A_UINT16 pn_63_48; + } pn16; + A_UINT32 pn_63_32; + } u0; + A_UINT32 pn_95_64; + A_UINT32 pn_127_96; } POSTPACK; - /* * Channel information can optionally be appended after hl_htt_rx_desc_base. * If so, the len field in htt_rx_ind_hl_rx_desc_t will be updated accordingly, @@ -6303,11 +6585,13 @@ PREPACK struct hl_htt_rx_desc_base { */ PREPACK struct htt_chan_info_t { - A_UINT32 primary_chan_center_freq_mhz: 16, - contig_chan1_center_freq_mhz: 16; - A_UINT32 contig_chan2_center_freq_mhz: 16, - phy_mode: 8, - reserved: 8; + A_UINT32 + primary_chan_center_freq_mhz:16, + contig_chan1_center_freq_mhz:16; + A_UINT32 + contig_chan2_center_freq_mhz:16, + phy_mode:8, + reserved:8; } POSTPACK; #define HTT_CHAN_INFO_SIZE sizeof(struct htt_chan_info_t) @@ -6328,9 +6612,10 @@ PREPACK struct htt_chan_info_t #define HTT_HL_RX_DESC_KEY_ID_OCT_M 0x3fc0000 #define HTT_HL_RX_DESC_KEY_ID_OCT_S 18 -#define HTT_HL_RX_DESC_PN_OFFSET offsetof(struct hl_htt_rx_desc_base, pn_31_0) -#define HTT_HL_RX_DESC_PN_WORD_OFFSET (HTT_HL_RX_DESC_PN_OFFSET >> 2) - +#define HTT_HL_RX_DESC_PN_OFFSET \ + offsetof(struct hl_htt_rx_desc_base, pn_31_0) +#define HTT_HL_RX_DESC_PN_WORD_OFFSET \ + (HTT_HL_RX_DESC_PN_OFFSET >> 2) /* Channel information */ #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M 0x0000ffff @@ -6343,41 +6628,44 @@ PREPACK struct htt_chan_info_t #define HTT_CHAN_INFO_PHY_MODE_S 16 -#define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \ - (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \ - } while (0) -#define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \ - (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S) +#define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \ + (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \ + } while (0) +#define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \ + (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) \ + >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S) -#define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \ - (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \ - } while (0) -#define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \ - (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S) +#define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \ + (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \ + } while (0) +#define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \ + (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) \ + >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S) -#define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \ - (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \ - } while (0) -#define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \ - (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S) +#define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \ + (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \ + } while (0) +#define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \ + (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) \ + >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S) -#define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \ - (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \ - } while (0) -#define HTT_CHAN_INFO_PHY_MODE_GET(word) \ - (((word) & HTT_CHAN_INFO_PHY_MODE_M) >> HTT_CHAN_INFO_PHY_MODE_S) - +#define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \ + (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \ + } while (0) +#define HTT_CHAN_INFO_PHY_MODE_GET(word) \ + (((word) & HTT_CHAN_INFO_PHY_MODE_M) \ + >> HTT_CHAN_INFO_PHY_MODE_S) /* * @brief target -> host rx reorder flush message definition @@ -6458,45 +6746,46 @@ PREPACK struct htt_chan_info_t #define HTT_RX_FLUSH_BYTES 8 -#define HTT_RX_FLUSH_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \ - (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \ - } while (0) -#define HTT_RX_FLUSH_PEER_ID_GET(word) \ - (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S) +#define HTT_RX_FLUSH_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \ + (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \ + } while (0) +#define HTT_RX_FLUSH_PEER_ID_GET(word) \ + (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S) -#define HTT_RX_FLUSH_TID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \ - (word) |= (value) << HTT_RX_FLUSH_TID_S; \ - } while (0) -#define HTT_RX_FLUSH_TID_GET(word) \ - (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S) +#define HTT_RX_FLUSH_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \ + (word) |= (value) << HTT_RX_FLUSH_TID_S; \ + } while (0) +#define HTT_RX_FLUSH_TID_GET(word) \ + (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S) -#define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \ - (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \ - } while (0) -#define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \ - (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S) +#define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \ + (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \ + } while (0) +#define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \ + (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S) -#define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \ - (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \ - } while (0) -#define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \ - (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> HTT_RX_FLUSH_SEQ_NUM_START_S) +#define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \ + (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \ + } while (0) +#define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \ + (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> \ + HTT_RX_FLUSH_SEQ_NUM_START_S) -#define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \ - (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \ - } while (0) -#define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \ - (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S) +#define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \ + (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \ + } while (0) +#define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \ + (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S) /* * @brief target -> host rx pn check indication message @@ -6549,25 +6838,26 @@ PREPACK struct htt_chan_info_t * The sequence number one larger then the sequence number of the last * MPDU being flushed. * This sequence number is the 6 LSBs of the 802.11 sequence number. - * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] have been checked - * for invalid PN numbers and are ready to be released for further processing. + * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] + * have been checked for invalid PN numbers and are ready + * to be released for further processing. * Not all MPDUs within this range are necessarily valid - the host * must check each sequence number within this range to see if the * corresponding MPDU is actually present. * - PN_IE_COUNT * Bits 23:16 * Purpose: - * Used to determine the variable number of PN information elements in this - * message + * Used to determine the variable number of PN information + * elements in this message * * PN information elements: * - PN_IE_x- * Purpose: - * Each PN information element contains the sequence number of the MPDU that - * has failed the target PN check. + * Each PN information element contains the sequence number + * of the MPDU that has failed the target PN check. * Value: - * Contains the 6 LSBs of the 802.11 sequence number corresponding to the MPDU - * that failed the PN check. + * Contains the 6 LSBs of the 802.11 sequence number + * corresponding to the MPDU that failed the PN check. */ /* first DWORD */ #define HTT_RX_PN_IND_PEER_ID_M 0xffff00 @@ -6584,45 +6874,46 @@ PREPACK struct htt_chan_info_t #define HTT_RX_PN_IND_BYTES 8 -#define HTT_RX_PN_IND_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \ - (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \ - } while (0) -#define HTT_RX_PN_IND_PEER_ID_GET(word) \ - (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S) +#define HTT_RX_PN_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \ + (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \ + } while (0) +#define HTT_RX_PN_IND_PEER_ID_GET(word) \ + (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S) -#define HTT_RX_PN_IND_EXT_TID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \ - (word) |= (value) << HTT_RX_PN_IND_TID_S; \ - } while (0) -#define HTT_RX_PN_IND_EXT_TID_GET(word) \ - (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S) +#define HTT_RX_PN_IND_EXT_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \ + (word) |= (value) << HTT_RX_PN_IND_TID_S; \ + } while (0) +#define HTT_RX_PN_IND_EXT_TID_GET(word) \ + (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S) -#define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \ - (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \ - } while (0) -#define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \ - (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> HTT_RX_PN_IND_SEQ_NUM_START_S) +#define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \ + (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \ + } while (0) +#define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \ + (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> \ + HTT_RX_PN_IND_SEQ_NUM_START_S) -#define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \ - (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \ - } while (0) -#define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \ - (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S) +#define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \ + (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \ + } while (0) +#define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \ + (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S) -#define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \ - (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \ - } while (0) -#define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \ - (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S) +#define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \ + (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \ + } while (0) +#define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \ + (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S) /* * @brief target -> host rx offload deliver message for LL system @@ -6691,53 +6982,59 @@ PREPACK struct htt_chan_info_t #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M 0x00ff0000 #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S 16 -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \ - (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S) -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \ - (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \ - } while (0) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \ + (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> \ + HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \ + (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \ +} while (0) \ -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \ - (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S) -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \ - (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \ - } while (0) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \ + (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> \ + HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \ + (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \ +} while (0) \ -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \ - (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S) -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \ - (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \ - } while (0) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \ + (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> \ + HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \ + (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \ +} while (0) \ -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \ - (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S) -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \ - (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \ - } while (0) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \ + (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> \ + HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \ +} while (0) \ -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \ - (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S) -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \ - (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \ - } while (0) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \ + (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> \ + HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \ + (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \ +} while (0) \ -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \ - (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S) -#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \ - (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \ - } while (0) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \ + (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> \ + HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S) +#define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \ + (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \ +} while (0) \ /** * @brief target -> host rx peer map/unmap message definition @@ -6799,25 +7096,25 @@ PREPACK struct htt_chan_info_t #define HTT_RX_PEER_MAP_MAC_ADDR_U16_M 0xffff #define HTT_RX_PEER_MAP_MAC_ADDR_U16_S 0 -#define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */ -#define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \ - (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \ - } while (0) -#define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */ -#define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \ - (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S) +#define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */ +#define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \ + } while (0) +#define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */ +#define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \ + (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S) #define HTT_RX_PEER_MAP_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ - (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \ - } while (0) -#define HTT_RX_PEER_MAP_PEER_ID_GET(word) \ - (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ + (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \ + } while (0) +#define HTT_RX_PEER_MAP_PEER_ID_GET(word) \ + (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S) -#define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ +#define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ #define HTT_RX_PEER_MAP_BYTES 12 @@ -6914,29 +7211,29 @@ PREPACK struct htt_chan_info_t #define HTT_SEC_IND_PEER_ID_M 0xffff0000 #define HTT_SEC_IND_PEER_ID_S 16 -#define HTT_SEC_IND_SEC_TYPE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \ - (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \ - } while (0) -#define HTT_SEC_IND_SEC_TYPE_GET(word) \ - (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S) +#define HTT_SEC_IND_SEC_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \ + (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \ + } while (0) +#define HTT_SEC_IND_SEC_TYPE_GET(word) \ + (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S) -#define HTT_SEC_IND_UNICAST_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \ - (word) |= (value) << HTT_SEC_IND_UNICAST_S; \ - } while (0) -#define HTT_SEC_IND_UNICAST_GET(word) \ - (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S) +#define HTT_SEC_IND_UNICAST_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \ + (word) |= (value) << HTT_SEC_IND_UNICAST_S; \ + } while (0) +#define HTT_SEC_IND_UNICAST_GET(word) \ + (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S) -#define HTT_SEC_IND_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \ - (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \ - } while (0) -#define HTT_SEC_IND_PEER_ID_GET(word) \ - (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S) +#define HTT_SEC_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \ + (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \ + } while (0) +#define HTT_SEC_IND_PEER_ID_GET(word) \ + (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S) #define HTT_SEC_IND_BYTES 28 @@ -6994,28 +7291,28 @@ PREPACK struct htt_chan_info_t #define HTT_RX_ADDBA_PEER_ID_S 20 #define HTT_RX_ADDBA_WIN_SIZE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \ - (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \ - } while (0) -#define HTT_RX_ADDBA_WIN_SIZE_GET(word) \ - (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \ + (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \ + } while (0) +#define HTT_RX_ADDBA_WIN_SIZE_GET(word) \ + (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) -#define HTT_RX_ADDBA_TID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \ - (word) |= (value) << HTT_RX_ADDBA_TID_S; \ - } while (0) -#define HTT_RX_ADDBA_TID_GET(word) \ - (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S) +#define HTT_RX_ADDBA_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \ + (word) |= (value) << HTT_RX_ADDBA_TID_S; \ + } while (0) +#define HTT_RX_ADDBA_TID_GET(word) \ + (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S) -#define HTT_RX_ADDBA_PEER_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \ - (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \ - } while (0) -#define HTT_RX_ADDBA_PEER_ID_GET(word) \ - (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S) +#define HTT_RX_ADDBA_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \ + (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \ + } while (0) +#define HTT_RX_ADDBA_PEER_ID_GET(word) \ + (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S) #define HTT_RX_ADDBA_BYTES 4 @@ -7100,16 +7397,16 @@ PREPACK struct htt_chan_info_t * vdev_id_mask would be (1 << 1) | (1 << 4) = 0x12 */ PREPACK struct htt_txq_group { - A_UINT32 - credit_count: 14, - sign: 1, - absolute: 1, - tx_queue_group_id: 8, - reserved0: 7, - extension: 1; - A_UINT32 - ac_mask: 16, - vdev_id_mask: 16; + A_UINT32 + credit_count:14, + sign:1, + absolute:1, + tx_queue_group_id:8, + reserved0:7, + extension:1; + A_UINT32 + ac_mask:16, + vdev_id_mask:16; } POSTPACK; /* first word */ @@ -7129,61 +7426,63 @@ PREPACK struct htt_txq_group { #define HTT_TXQ_GROUP_VDEV_ID_MASK_S 16 #define HTT_TXQ_GROUP_VDEV_ID_MASK_M 0xffff0000 -#define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \ - } while (0) -#define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> HTT_TXQ_GROUP_CREDIT_COUNT_S) +#define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \ + } while (0) +#define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> \ + HTT_TXQ_GROUP_CREDIT_COUNT_S) -#define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \ - } while (0) -#define HTT_TXQ_GROUP_SIGN_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S) +#define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \ + } while (0) +#define HTT_TXQ_GROUP_SIGN_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S) -#define HTT_TXQ_GROUP_ABS_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \ - } while (0) -#define HTT_TXQ_GROUP_ABS_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S) +#define HTT_TXQ_GROUP_ABS_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \ + } while (0) +#define HTT_TXQ_GROUP_ABS_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S) -#define HTT_TXQ_GROUP_ID_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \ - } while (0) -#define HTT_TXQ_GROUP_ID_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S) +#define HTT_TXQ_GROUP_ID_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \ + } while (0) +#define HTT_TXQ_GROUP_ID_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S) -#define HTT_TXQ_GROUP_EXT_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \ - } while (0) -#define HTT_TXQ_GROUP_EXT_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S) +#define HTT_TXQ_GROUP_EXT_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \ + } while (0) +#define HTT_TXQ_GROUP_EXT_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S) -#define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \ - } while (0) -#define HTT_TXQ_GROUP_AC_MASK_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S) +#define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \ + } while (0) +#define HTT_TXQ_GROUP_AC_MASK_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S) -#define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \ - ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \ - } while (0) -#define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \ - (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> HTT_TXQ_GROUP_VDEV_ID_MASK_S) +#define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \ + ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \ + } while (0) +#define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \ + (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> \ + HTT_TXQ_GROUP_VDEV_ID_MASK_S) /** * @brief target -> host TX completion indication message definition @@ -7251,41 +7550,41 @@ PREPACK struct htt_txq_group { #define HTT_TX_COMPL_IND_APPEND_M 0x01000000 #define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \ - ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \ + ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \ + } while (0) #define HTT_TX_COMPL_IND_STATUS_GET(_info) \ - (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S) + (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S) #define HTT_TX_COMPL_IND_NUM_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \ - ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \ - } while (0) -#define HTT_TX_COMPL_IND_NUM_GET(_info) \ - (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \ + ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \ + } while (0) +#define HTT_TX_COMPL_IND_NUM_GET(_info) \ + (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S) #define HTT_TX_COMPL_IND_TID_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \ - ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \ - } while (0) -#define HTT_TX_COMPL_IND_TID_GET(_info) \ - (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \ + ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \ + } while (0) +#define HTT_TX_COMPL_IND_TID_GET(_info) \ + (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S) #define HTT_TX_COMPL_IND_TID_INV_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \ - ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \ - } while (0) -#define HTT_TX_COMPL_IND_TID_INV_GET(_info) \ - (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \ - HTT_TX_COMPL_IND_TID_INV_S) -#define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \ - ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \ - } while (0) -#define HTT_TX_COMPL_IND_APPEND_GET(_info) \ - (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \ + ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \ + } while (0) +#define HTT_TX_COMPL_IND_TID_INV_GET(_info) \ + (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \ + HTT_TX_COMPL_IND_TID_INV_S) +#define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \ + ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \ + } while (0) +#define HTT_TX_COMPL_IND_APPEND_GET(_info) \ + (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S) #define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16) #define HTT_TX_COMPL_CTXT_NUM(_bytes) ((_bytes) >> 1) @@ -7309,15 +7608,15 @@ PREPACK struct htt_txq_group { #define HTT_TX_COMPL_IND_APPEND_CLR_MORE_RETRY(f) ((f) &= (~0x1)) PREPACK struct htt_tx_compl_ind_base { - A_UINT32 hdr; - A_UINT16 payload[1/*or more*/]; + A_UINT32 hdr; + A_UINT16 payload[1 /*or more */]; } POSTPACK; PREPACK struct htt_tx_compl_ind_append_retries { - A_UINT16 msdu_id; - A_UINT8 tx_retries; - A_UINT8 flag; /* Bit 0, 1: another append_retries struct is appended - 0: this is the last append_retries struct */ + A_UINT16 msdu_id; + A_UINT8 tx_retries; + A_UINT8 flag;/* Bit 0, 1: another append_retries struct is appended + 0: this is the last append_retries struct */ } POSTPACK; /** @@ -7350,29 +7649,29 @@ PREPACK struct htt_tx_compl_ind_append_retries { */ typedef struct { - A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ - A_UINT32 rate_code_flags; - A_UINT32 flags; /* Encodes information such as excessive - retransmission, aggregate, some info - from .11 frame control, - STBC, LDPC, (SGI and Tx Chain Mask - are encoded in ptx_rc->flags field), - AMPDU truncation (BT/time based etc.), - RTS/CTS attempt */ + A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ + A_UINT32 rate_code_flags; + A_UINT32 flags; /* Encodes information such as excessive + retransmission, aggregate, some info + from .11 frame control, + STBC, LDPC, (SGI and Tx Chain Mask + are encoded in ptx_rc->flags field), + AMPDU truncation (BT/time based etc.), + RTS/CTS attempt */ - A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ - A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ - A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ - A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ - A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ - A_UINT32 is_probe; /* Valid if probing. Else, 0 */ + A_UINT32 num_enqued;/* # of MPDUs (for non-AMPDU 1) for this rate */ + A_UINT32 num_retries;/* Total # of transmission attempt for this rate */ + A_UINT32 num_failed;/* # of failed MPDUs in A-MPDU, 0 otherwise */ + A_UINT32 ack_rssi;/* ACK RSSI: b'7..b'0 avg RSSI across all chain */ + A_UINT32 time_stamp; /* ACK timestamp (helps determine age) */ + A_UINT32 is_probe; /* Valid if probing. Else, 0 */ } HTT_RC_TX_DONE_PARAMS; -#define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS)) /* bytes */ -#define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */ +#define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS))/* bytes */ +#define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */ -#define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */ -#define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */ +#define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */ +#define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */ #define HTT_RC_UPDATE_VDEVID_S 8 #define HTT_RC_UPDATE_VDEVID_M 0xff00 @@ -7382,32 +7681,32 @@ typedef struct { #define HTT_RC_UPDATE_NUM_ELEMS_S 16 #define HTT_RC_UPDATE_NUM_ELEMS_M 0x00ff0000 -#define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \ - ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \ - } while (0) +#define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \ + ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \ + } while (0) -#define HTT_RC_UPDATE_VDEVID_GET(_info) \ - (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S) +#define HTT_RC_UPDATE_VDEVID_GET(_info) \ + (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S) -#define HTT_RC_UPDATE_PEERID_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \ - ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \ - } while (0) +#define HTT_RC_UPDATE_PEERID_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \ + ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \ + } while (0) -#define HTT_RC_UPDATE_PEERID_GET(_info) \ - (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S) +#define HTT_RC_UPDATE_PEERID_GET(_info) \ + (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S) -#define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \ - ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \ - } while (0) +#define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \ + ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \ + } while (0) -#define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \ - (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S) +#define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \ + (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S) /** * @brief target -> host rx fragment indication message definition @@ -7497,22 +7796,22 @@ typedef struct { #define HTT_RX_FRAG_IND_FLUSH_VALID_GET HTT_RX_IND_FLUSH_VALID_GET #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_SET \ - HTT_RX_IND_FLUSH_SEQ_NUM_START_SET + HTT_RX_IND_FLUSH_SEQ_NUM_START_SET #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_GET \ - HTT_RX_IND_FLUSH_SEQ_NUM_START_GET + HTT_RX_IND_FLUSH_SEQ_NUM_START_GET -#define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \ - HTT_RX_IND_FLUSH_SEQ_NUM_END_SET -#define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \ - HTT_RX_IND_FLUSH_SEQ_NUM_END_GET +#define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \ + HTT_RX_IND_FLUSH_SEQ_NUM_END_SET +#define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \ + HTT_RX_IND_FLUSH_SEQ_NUM_END_GET #define HTT_RX_FRAG_IND_FW_RX_DESC_BYTES_GET HTT_RX_IND_FW_RX_DESC_BYTES_GET -#define HTT_RX_FRAG_IND_BYTES \ - (4 /* msg hdr */ + \ - 4 /* flush spec */ + \ - 4 /* (unused) FW rx desc bytes spec */ + \ - 4 /* FW rx desc */) +#define HTT_RX_FRAG_IND_BYTES \ + (4 /* msg hdr */ + \ + 4 /* flush spec */ + \ + 4 /* (unused) FW rx desc bytes spec */ + \ + 4 /* FW rx desc */) /** * @brief target -> host test message definition @@ -7554,21 +7853,21 @@ typedef struct { #define HTT_RX_TEST_NUM_CHARS_M 0xffff0000 #define HTT_RX_TEST_NUM_CHARS_S 16 -#define HTT_RX_TEST_NUM_INTS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \ - (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \ - } while (0) -#define HTT_RX_TEST_NUM_INTS_GET(word) \ - (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S) +#define HTT_RX_TEST_NUM_INTS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \ + (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \ + } while (0) +#define HTT_RX_TEST_NUM_INTS_GET(word) \ + (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S) #define HTT_RX_TEST_NUM_CHARS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \ - (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \ - } while (0) -#define HTT_RX_TEST_NUM_CHARS_GET(word) \ - (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S) + do { \ + HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \ + (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \ + } while (0) +#define HTT_RX_TEST_NUM_CHARS_GET(word) \ + (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S) /** * @brief target -> host packet log message @@ -7591,8 +7890,8 @@ typedef struct { * Value: HTT_MSG_TYPE_PACKETLOG */ PREPACK struct htt_pktlog_msg { - A_UINT32 header; - A_UINT32 payload[1/* or more */]; + A_UINT32 header; + A_UINT32 payload[1 /* or more */]; } POSTPACK; @@ -7601,124 +7900,127 @@ PREPACK struct htt_pktlog_msg { * NB: all the fields must be defined in 4 octets size. */ struct rx_reorder_stats { - /* Non QoS MPDUs received */ - A_UINT32 deliver_non_qos; - /* MPDUs received in-order */ - A_UINT32 deliver_in_order; - /* Flush due to reorder timer expired */ - A_UINT32 deliver_flush_timeout; - /* Flush due to move out of window */ - A_UINT32 deliver_flush_oow; - /* Flush due to DELBA */ - A_UINT32 deliver_flush_delba; - /* MPDUs dropped due to FCS error */ - A_UINT32 fcs_error; - /* MPDUs dropped due to monitor mode non-data packet */ - A_UINT32 mgmt_ctrl; - /* Unicast-data MPDUs dropped due to invalid peer */ - A_UINT32 invalid_peer; - /* MPDUs dropped due to duplication (non aggregation) */ - A_UINT32 dup_non_aggr; - /* MPDUs dropped due to processed before */ - A_UINT32 dup_past; - /* MPDUs dropped due to duplicate in reorder queue */ - A_UINT32 dup_in_reorder; - /* Reorder timeout happened */ - A_UINT32 reorder_timeout; - /* invalid bar ssn */ - A_UINT32 invalid_bar_ssn; - /* reorder reset due to bar ssn */ - A_UINT32 ssn_reset; - /* Flush due to delete peer */ - A_UINT32 deliver_flush_delpeer; - /* Flush due to offload*/ - A_UINT32 deliver_flush_offload; - /* Flush due to out of buffer*/ - A_UINT32 deliver_flush_oob; - /* MPDUs dropped due to PN check fail */ - A_UINT32 pn_fail; - /* MPDUs dropped due to unable to allocate memory */ - A_UINT32 store_fail; - /* Number of times the tid pool alloc succeeded */ - A_UINT32 tid_pool_alloc_succ; - /* Number of times the MPDU pool alloc succeeded */ - A_UINT32 mpdu_pool_alloc_succ; - /* Number of times the MSDU pool alloc succeeded */ - A_UINT32 msdu_pool_alloc_succ; - /* Number of times the tid pool alloc failed */ - A_UINT32 tid_pool_alloc_fail; - /* Number of times the MPDU pool alloc failed */ - A_UINT32 mpdu_pool_alloc_fail; - /* Number of times the MSDU pool alloc failed */ - A_UINT32 msdu_pool_alloc_fail; - /* Number of times the tid pool freed */ - A_UINT32 tid_pool_free; - /* Number of times the MPDU pool freed */ - A_UINT32 mpdu_pool_free; - /* Number of times the MSDU pool freed */ - A_UINT32 msdu_pool_free; - /* number of MSDUs undelivered to HTT and queued to Data Rx MSDU free list*/ - A_UINT32 msdu_queued; - /* Number of MSDUs released from Data Rx MSDU list to MAC ring */ - A_UINT32 msdu_recycled; - /* Number of MPDUs with invalid peer but A2 found in AST */ - A_UINT32 invalid_peer_a2_in_ast; - /* Number of MPDUs with invalid peer but A3 found in AST */ - A_UINT32 invalid_peer_a3_in_ast; - /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */ - A_UINT32 invalid_peer_bmc_mpdus; - /* Number of MSDUs with err attention word */ - A_UINT32 rxdesc_err_att; - /* Number of MSDUs with flag of peer_idx_invalid */ - A_UINT32 rxdesc_err_peer_idx_inv; - /* Number of MSDUs with flag of peer_idx_timeout */ - A_UINT32 rxdesc_err_peer_idx_to; - /* Number of MSDUs with flag of overflow */ - A_UINT32 rxdesc_err_ov; - /* Number of MSDUs with flag of msdu_length_err */ - A_UINT32 rxdesc_err_msdu_len; - /* Number of MSDUs with flag of mpdu_length_err */ - A_UINT32 rxdesc_err_mpdu_len; - /* Number of MSDUs with flag of tkip_mic_err */ - A_UINT32 rxdesc_err_tkip_mic; - /* Number of MSDUs with flag of decrypt_err */ - A_UINT32 rxdesc_err_decrypt; - /* Number of MSDUs with flag of fcs_err */ - A_UINT32 rxdesc_err_fcs; - /* Number of Unicast (bc_mc bit is not set in attention word) - * frames with invalid peer handler - */ - A_UINT32 rxdesc_uc_msdus_inv_peer; - /* Number of unicast frame directly (direct bit is set in attention word) - * to DUT with invalid peer handler - */ - A_UINT32 rxdesc_direct_msdus_inv_peer; - /* Number of Broadcast/Multicast (bc_mc bit set in attention word) - * frames with invalid peer handler - */ - A_UINT32 rxdesc_bmc_msdus_inv_peer; - /* Number of MSDUs dropped due to no first MSDU flag */ - A_UINT32 rxdesc_no_1st_msdu; - /* Number of MSDUs droped due to ring overflow */ - A_UINT32 msdu_drop_ring_ov; - /* Number of MSDUs dropped due to FC mismatch */ - A_UINT32 msdu_drop_fc_mismatch; - /* Number of MSDUs dropped due to mgt frame in Remote ring */ - A_UINT32 msdu_drop_mgmt_remote_ring; - /* Number of MSDUs dropped due to errors not reported in attention word */ - A_UINT32 msdu_drop_misc; - /* Number of MSDUs go to offload before reorder */ - A_UINT32 offload_msdu_wal; - /* Number of data frame dropped by offload after reorder */ - A_UINT32 offload_msdu_reorder; - /* Number of MPDUs with sequence number in the past and within the BA window */ - A_UINT32 dup_past_within_window; - /* Number of MPDUs with sequence number in the past and outside the BA window */ - A_UINT32 dup_past_outside_window; - /* Number of MSDUs with decrypt/MIC error */ - A_UINT32 rxdesc_err_decrypt_mic; - /* Number of data MSDUs received on both local and remote rings */ - A_UINT32 data_msdus_on_both_rings; + /* Non QoS MPDUs received */ + A_UINT32 deliver_non_qos; + /* MPDUs received in-order */ + A_UINT32 deliver_in_order; + /* Flush due to reorder timer expired */ + A_UINT32 deliver_flush_timeout; + /* Flush due to move out of window */ + A_UINT32 deliver_flush_oow; + /* Flush due to DELBA */ + A_UINT32 deliver_flush_delba; + /* MPDUs dropped due to FCS error */ + A_UINT32 fcs_error; + /* MPDUs dropped due to monitor mode non-data packet */ + A_UINT32 mgmt_ctrl; + /* Unicast-data MPDUs dropped due to invalid peer */ + A_UINT32 invalid_peer; + /* MPDUs dropped due to duplication (non aggregation) */ + A_UINT32 dup_non_aggr; + /* MPDUs dropped due to processed before */ + A_UINT32 dup_past; + /* MPDUs dropped due to duplicate in reorder queue */ + A_UINT32 dup_in_reorder; + /* Reorder timeout happened */ + A_UINT32 reorder_timeout; + /* invalid bar ssn */ + A_UINT32 invalid_bar_ssn; + /* reorder reset due to bar ssn */ + A_UINT32 ssn_reset; + /* Flush due to delete peer */ + A_UINT32 deliver_flush_delpeer; + /* Flush due to offload */ + A_UINT32 deliver_flush_offload; + /* Flush due to out of buffer */ + A_UINT32 deliver_flush_oob; + /* MPDUs dropped due to PN check fail */ + A_UINT32 pn_fail; + /* MPDUs dropped due to unable to allocate memory */ + A_UINT32 store_fail; + /* Number of times the tid pool alloc succeeded */ + A_UINT32 tid_pool_alloc_succ; + /* Number of times the MPDU pool alloc succeeded */ + A_UINT32 mpdu_pool_alloc_succ; + /* Number of times the MSDU pool alloc succeeded */ + A_UINT32 msdu_pool_alloc_succ; + /* Number of times the tid pool alloc failed */ + A_UINT32 tid_pool_alloc_fail; + /* Number of times the MPDU pool alloc failed */ + A_UINT32 mpdu_pool_alloc_fail; + /* Number of times the MSDU pool alloc failed */ + A_UINT32 msdu_pool_alloc_fail; + /* Number of times the tid pool freed */ + A_UINT32 tid_pool_free; + /* Number of times the MPDU pool freed */ + A_UINT32 mpdu_pool_free; + /* Number of times the MSDU pool freed */ + A_UINT32 msdu_pool_free; + /* number of MSDUs undelivered to HTT and queued + * to Data Rx MSDU free list */ + A_UINT32 msdu_queued; + /* Number of MSDUs released from Data Rx MSDU list to MAC ring */ + A_UINT32 msdu_recycled; + /* Number of MPDUs with invalid peer but A2 found in AST */ + A_UINT32 invalid_peer_a2_in_ast; + /* Number of MPDUs with invalid peer but A3 found in AST */ + A_UINT32 invalid_peer_a3_in_ast; + /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */ + A_UINT32 invalid_peer_bmc_mpdus; + /* Number of MSDUs with err attention word */ + A_UINT32 rxdesc_err_att; + /* Number of MSDUs with flag of peer_idx_invalid */ + A_UINT32 rxdesc_err_peer_idx_inv; + /* Number of MSDUs with flag of peer_idx_timeout */ + A_UINT32 rxdesc_err_peer_idx_to; + /* Number of MSDUs with flag of overflow */ + A_UINT32 rxdesc_err_ov; + /* Number of MSDUs with flag of msdu_length_err */ + A_UINT32 rxdesc_err_msdu_len; + /* Number of MSDUs with flag of mpdu_length_err */ + A_UINT32 rxdesc_err_mpdu_len; + /* Number of MSDUs with flag of tkip_mic_err */ + A_UINT32 rxdesc_err_tkip_mic; + /* Number of MSDUs with flag of decrypt_err */ + A_UINT32 rxdesc_err_decrypt; + /* Number of MSDUs with flag of fcs_err */ + A_UINT32 rxdesc_err_fcs; + /* Number of Unicast (bc_mc bit is not set in attention word) + * frames with invalid peer handler + */ + A_UINT32 rxdesc_uc_msdus_inv_peer; + /* Number of unicast frame directly (direct bit is set in attention word) + * to DUT with invalid peer handler + */ + A_UINT32 rxdesc_direct_msdus_inv_peer; + /* Number of Broadcast/Multicast (bc_mc bit set in attention word) + * frames with invalid peer handler + */ + A_UINT32 rxdesc_bmc_msdus_inv_peer; + /* Number of MSDUs dropped due to no first MSDU flag */ + A_UINT32 rxdesc_no_1st_msdu; + /* Number of MSDUs droped due to ring overflow */ + A_UINT32 msdu_drop_ring_ov; + /* Number of MSDUs dropped due to FC mismatch */ + A_UINT32 msdu_drop_fc_mismatch; + /* Number of MSDUs dropped due to mgt frame in Remote ring */ + A_UINT32 msdu_drop_mgmt_remote_ring; + /* Number of MSDUs dropped due to errors not reported in attention word */ + A_UINT32 msdu_drop_misc; + /* Number of MSDUs go to offload before reorder */ + A_UINT32 offload_msdu_wal; + /* Number of data frame dropped by offload after reorder */ + A_UINT32 offload_msdu_reorder; + /* Number of MPDUs with sequence number in the past and within + the BA window */ + A_UINT32 dup_past_within_window; + /* Number of MPDUs with sequence number in the past and + * outside the BA window */ + A_UINT32 dup_past_outside_window; + /* Number of MSDUs with decrypt/MIC error */ + A_UINT32 rxdesc_err_decrypt_mic; + /* Number of data MSDUs received on both local and remote rings */ + A_UINT32 data_msdus_on_both_rings; }; @@ -7727,32 +8029,32 @@ struct rx_reorder_stats { * NB: all the fields must be defined in 4 octets size. */ struct rx_remote_buffer_mgmt_stats { - /* Total number of MSDUs reaped for Rx processing */ - A_UINT32 remote_reaped; - /* MSDUs recycled within firmware */ - A_UINT32 remote_recycled; - /* MSDUs stored by Data Rx */ - A_UINT32 data_rx_msdus_stored; - /* Number of HTT indications from WAL Rx MSDU */ - A_UINT32 wal_rx_ind; - /* Number of unconsumed HTT indications from WAL Rx MSDU */ - A_UINT32 wal_rx_ind_unconsumed; - /* Number of HTT indications from Data Rx MSDU */ - A_UINT32 data_rx_ind; - /* Number of unconsumed HTT indications from Data Rx MSDU */ - A_UINT32 data_rx_ind_unconsumed; - /* Number of HTT indications from ATHBUF */ - A_UINT32 athbuf_rx_ind; - /* Number of remote buffers requested for refill */ - A_UINT32 refill_buf_req; - /* Number of remote buffers filled by the host */ - A_UINT32 refill_buf_rsp; - /* Number of times MAC hw_index = f/w write_index */ - A_INT32 mac_no_bufs; - /* Number of times f/w write_index = f/w read_index for MAC Rx ring */ - A_INT32 fw_indices_equal; - /* Number of times f/w finds no buffers to post */ - A_INT32 host_no_bufs; + /* Total number of MSDUs reaped for Rx processing */ + A_UINT32 remote_reaped; + /* MSDUs recycled within firmware */ + A_UINT32 remote_recycled; + /* MSDUs stored by Data Rx */ + A_UINT32 data_rx_msdus_stored; + /* Number of HTT indications from WAL Rx MSDU */ + A_UINT32 wal_rx_ind; + /* Number of unconsumed HTT indications from WAL Rx MSDU */ + A_UINT32 wal_rx_ind_unconsumed; + /* Number of HTT indications from Data Rx MSDU */ + A_UINT32 data_rx_ind; + /* Number of unconsumed HTT indications from Data Rx MSDU */ + A_UINT32 data_rx_ind_unconsumed; + /* Number of HTT indications from ATHBUF */ + A_UINT32 athbuf_rx_ind; + /* Number of remote buffers requested for refill */ + A_UINT32 refill_buf_req; + /* Number of remote buffers filled by the host */ + A_UINT32 refill_buf_rsp; + /* Number of times MAC hw_index = f/w write_index */ + A_INT32 mac_no_bufs; + /* Number of times f/w write_index = f/w read_index for MAC Rx ring */ + A_INT32 fw_indices_equal; + /* Number of times f/w finds no buffers to post */ + A_INT32 host_no_bufs; }; /* @@ -7760,16 +8062,20 @@ struct rx_remote_buffer_mgmt_stats { * NB: all the fields must be defined in 4 octets size. */ struct rx_txbf_musu_ndpa_pkts_stats { - A_UINT32 number_mu_pkts; /* number of TXBF MU packets received */ - A_UINT32 number_su_pkts; /* number of TXBF SU packets received */ - A_UINT32 txbf_directed_ndpa_count; /* number of TXBF directed NDPA */ - A_UINT32 txbf_ndpa_retry_count; /* number of TXBF retried NDPA */ - A_UINT32 txbf_total_ndpa_count; /* total number of TXBF NDPA */ - - A_UINT32 reserved[3]; /* must be set to 0x0 */ + /* number of TXBF MU packets received */ + A_UINT32 number_mu_pkts; + /* number of TXBF SU packets received */ + A_UINT32 number_su_pkts; + /* number of TXBF directed NDPA */ + A_UINT32 txbf_directed_ndpa_count; + /* number of TXBF retried NDPA */ + A_UINT32 txbf_ndpa_retry_count; + /* total number of TXBF NDPA */ + A_UINT32 txbf_total_ndpa_count; + /* must be set to 0x0 */ + A_UINT32 reserved[3]; }; - /* * htt_dbg_stats_status - * present - The requested stats have been delivered in full. @@ -7792,13 +8098,13 @@ struct rx_txbf_musu_ndpa_pkts_stats { * (within a stats upload confirmation message). */ enum htt_dbg_stats_status { - HTT_DBG_STATS_STATUS_PRESENT = 0, - HTT_DBG_STATS_STATUS_PARTIAL = 1, - HTT_DBG_STATS_STATUS_ERROR = 2, - HTT_DBG_STATS_STATUS_INVALID = 3, + HTT_DBG_STATS_STATUS_PRESENT = 0, + HTT_DBG_STATS_STATUS_PARTIAL = 1, + HTT_DBG_STATS_STATUS_ERROR = 2, + HTT_DBG_STATS_STATUS_INVALID = 3, - HTT_DBG_STATS_STATUS_SERIES_DONE = 7 + HTT_DBG_STATS_STATUS_SERIES_DONE = 7 }; /** @@ -7892,32 +8198,32 @@ enum htt_dbg_stats_status { #define HTT_T2H_STATS_CONF_TLV_LENGTH_M 0xffff0000 #define HTT_T2H_STATS_CONF_TLV_LENGTH_S 16 -#define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \ - (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \ - } while (0) -#define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \ - (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \ - HTT_T2H_STATS_CONF_TLV_TYPE_S) +#define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \ + (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \ + } while (0) +#define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \ + (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \ + HTT_T2H_STATS_CONF_TLV_TYPE_S) -#define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \ - (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \ - } while (0) -#define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \ - (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \ - HTT_T2H_STATS_CONF_TLV_STATUS_S) +#define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \ + (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \ + } while (0) +#define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \ + (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \ + HTT_T2H_STATS_CONF_TLV_STATUS_S) -#define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \ - (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \ - } while (0) -#define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \ - (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \ - HTT_T2H_STATS_CONF_TLV_LENGTH_S) +#define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \ + (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \ + } while (0) +#define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \ + (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \ + HTT_T2H_STATS_CONF_TLV_LENGTH_S) #define HL_HTT_FW_RX_DESC_RSVD_SIZE 18 #define HTT_MAX_AGGR 64 @@ -7945,16 +8251,16 @@ enum htt_dbg_stats_status { * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | * |------------------------------------------------------------| * | BANK0_BASE_ADDRESS (bits 31:0) | -#if HTT_PADDR64 + #if HTT_PADDR64 * | BANK0_BASE_ADDRESS (bits 63:32) | -#endif + #endif * |------------------------------------------------------------| * | ... | * |------------------------------------------------------------| * | BANK15_BASE_ADDRESS (bits 31:0) | -#if HTT_PADDR64 + #if HTT_PADDR64 * | BANK15_BASE_ADDRESS (bits 63:32) | -#endif + #endif * |------------------------------------------------------------| * | BANK0_MAX_ID | BANK0_MIN_ID | * |------------------------------------------------------------| @@ -7994,8 +8300,8 @@ enum htt_dbg_stats_status { * */ -/** @todo Compress the fields to fit MAX HTT Message size, until then configure to a - * safe value. +/** @todo Compress the fields to fit MAX HTT Message size, until then + * configure to a safe value. * @note MAX supported banks is 16. */ #define HTT_TX_MSDU_EXT_BANK_MAX 4 @@ -8018,53 +8324,59 @@ enum htt_dbg_stats_status { #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M 0xffff0000 #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S 16 -#define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \ - (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \ - } while (0) -#define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \ - (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> HTT_H2T_FRAG_DESC_BANK_PDEVID_S) +#define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \ + (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \ + } while (0) +#define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \ + (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> \ + HTT_H2T_FRAG_DESC_BANK_PDEVID_S) -#define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value); \ - (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S); \ - } while (0) -#define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \ - (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> HTT_H2T_FRAG_DESC_BANK_SWAP_S) +#define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value);\ + (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S);\ + } while (0) +#define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \ + (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> \ + HTT_H2T_FRAG_DESC_BANK_SWAP_S) -#define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \ - (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \ - } while (0) -#define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \ - (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S) +#define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \ + (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \ + } while (0) +#define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \ + (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> \ + HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S) -#define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \ - (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \ - } while (0) -#define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \ - (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S) +#define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \ + (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \ + } while (0) +#define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \ + (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> \ + HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S) -#define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \ - (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \ - } while (0) -#define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \ - (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S) +#define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \ + (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \ + } while (0) +#define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \ + (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> \ + HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S) -#define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \ - (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \ - } while (0) -#define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \ - (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S) +#define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \ + (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \ + } while (0) +#define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \ + (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> \ + HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S) /* @@ -8074,27 +8386,28 @@ enum htt_dbg_stats_status { * This macro is used to define both htt_tx_frag_desc32_bank_cfg_t and * htt_tx_frag_desc64_bank_cfg_t structs. */ -#define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \ - _paddr_bits_, \ - _paddr__bank_base_address_) \ -PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \ - /** word 0 \ - * msg_type: 8, \ - * pdev_id: 2, \ - * swap: 1, \ - * reserved0: 5, \ - * num_banks: 8, \ - * desc_size: 8; \ - */ \ - A_UINT32 word0; \ - /* \ - * If bank_base_address is 64 bits, the upper / lower halves are stored \ - * in little-endian order (bytes 0-3 in the first A_UINT32, bytes 4-7 in \ - * the second A_UINT32). \ - */ \ - _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \ - A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \ -} POSTPACK +#define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \ + _paddr_bits_, \ + _paddr__bank_base_address_) \ + PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \ + /** word 0 \ + * msg_type: 8, \ + * pdev_id: 2, \ + * swap: 1, \ + * reserved0: 5, \ + * num_banks: 8, \ + * desc_size: 8; \ + */ \ + A_UINT32 word0; \ + /* \ + * If bank_base_address is 64 bits, the upper / lower + * halves are stored \ + * in little-endian order (bytes 0-3 in the first A_UINT32, + * bytes 4-7 in the second A_UINT32). \ + */ \ + _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \ + A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \ + } POSTPACK /* define htt_tx_frag_desc32_bank_cfg_t */ TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(32, HTT_VAR_PADDR32(bank_base_address)); /* define htt_tx_frag_desc64_bank_cfg_t */ @@ -8104,11 +8417,12 @@ TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); * htt_tx_frag_desc32_bank_cfg_t or htt_tx_frag_desc64_bank_cfg_t */ #if HTT_PADDR64 - #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t +#define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t #else - #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t +#define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t #endif + /** * @brief target -> host HTT TX Credit total count update message definition * @@ -8150,32 +8464,32 @@ TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); #define HTT_TX_CREDIT_DELTA_ABS_S 16 -#define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \ - (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \ - } while (0) +#define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \ + (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \ + } while (0) -#define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ - (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) +#define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ + (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) -#define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \ - (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \ - } while (0) +#define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \ + (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \ + } while (0) -#define HTT_TX_CREDIT_TXQ_GRP_GET(word) \ - (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S) +#define HTT_TX_CREDIT_TXQ_GRP_GET(word) \ + (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S) -#define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \ - (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \ - } while (0) +#define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \ + (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \ + } while (0) -#define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ - (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) +#define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ + (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) #define HTT_TX_CREDIT_MSG_BYTES 4 @@ -8208,7 +8522,8 @@ TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); * value: = 0x13 * - OP_CODE * Bits 31:16 - * Purpose: Identifies the operation target is responding to (e.g. TX suspend) + * Purpose: Identifies the operation target is responding to + * (e.g. TX suspend) * value: = enum htt_wdi_ipa_op_code * - RSP_LEN * Bits 16:0 @@ -8218,19 +8533,18 @@ TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); * length value will be sizeof(struct wlan_wdi_ipa_dbg_stats_t). */ -PREPACK struct htt_wdi_ipa_op_response_t -{ - /* DWORD 0: flags and meta-data */ - A_UINT32 - msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ - reserved1: 8, - op_code: 16; - A_UINT32 - rsp_len: 16, - reserved2: 16; +PREPACK struct htt_wdi_ipa_op_response_t { + /* DWORD 0: flags and meta-data */ + A_UINT32 + msg_type:8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ + reserved1:8, + op_code:16; + A_UINT32 + rsp_len:16, + reserved2:16; } POSTPACK; -#define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */ +#define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */ #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M 0xffff0000 #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S 16 @@ -8238,42 +8552,44 @@ PREPACK struct htt_wdi_ipa_op_response_t #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M 0x0000ffff #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S 0 -#define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \ - (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S) -#define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \ - } while (0) +#define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \ + (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> \ + HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S) +#define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \ + } while (0) -#define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \ - (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S) -#define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \ - ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \ - } while (0) +#define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \ + (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> \ + HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S) +#define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \ + ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \ + } while (0) enum htt_phy_mode { - htt_phy_mode_11a = 0, - htt_phy_mode_11g = 1, - htt_phy_mode_11b = 2, - htt_phy_mode_11g_only = 3, - htt_phy_mode_11na_ht20 = 4, - htt_phy_mode_11ng_ht20 = 5, - htt_phy_mode_11na_ht40 = 6, - htt_phy_mode_11ng_ht40 = 7, - htt_phy_mode_11ac_vht20 = 8, - htt_phy_mode_11ac_vht40 = 9, - htt_phy_mode_11ac_vht80 = 10, - htt_phy_mode_11ac_vht20_2g = 11, - htt_phy_mode_11ac_vht40_2g = 12, - htt_phy_mode_11ac_vht80_2g = 13, - htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */ - htt_phy_mode_11ac_vht160 = 15, + htt_phy_mode_11a = 0, + htt_phy_mode_11g = 1, + htt_phy_mode_11b = 2, + htt_phy_mode_11g_only = 3, + htt_phy_mode_11na_ht20 = 4, + htt_phy_mode_11ng_ht20 = 5, + htt_phy_mode_11na_ht40 = 6, + htt_phy_mode_11ng_ht40 = 7, + htt_phy_mode_11ac_vht20 = 8, + htt_phy_mode_11ac_vht40 = 9, + htt_phy_mode_11ac_vht80 = 10, + htt_phy_mode_11ac_vht20_2g = 11, + htt_phy_mode_11ac_vht40_2g = 12, + htt_phy_mode_11ac_vht80_2g = 13, + htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */ + htt_phy_mode_11ac_vht160 = 15, - htt_phy_mode_max, + htt_phy_mode_max, }; /** @@ -8329,16 +8645,14 @@ enum htt_phy_mode { * Value: htt_phy_mode enum value */ -PREPACK struct htt_chan_change_t -{ - /* DWORD 0: flags and meta-data */ - A_UINT32 - msg_type: 8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ - reserved1: 24; - A_UINT32 primary_chan_center_freq_mhz; - A_UINT32 contig_chan1_center_freq_mhz; - A_UINT32 contig_chan2_center_freq_mhz; - A_UINT32 phy_mode; +PREPACK struct htt_chan_change_t { + /* DWORD 0: flags and meta-data */ + A_UINT32 msg_type:8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ + reserved1:24; + A_UINT32 primary_chan_center_freq_mhz; + A_UINT32 contig_chan1_center_freq_mhz; + A_UINT32 contig_chan2_center_freq_mhz; + A_UINT32 phy_mode; } POSTPACK; #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M 0xffffffff @@ -8351,41 +8665,47 @@ PREPACK struct htt_chan_change_t #define HTT_CHAN_CHANGE_PHY_MODE_S 0 -#define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value);\ - (word) |= (value) << HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \ - } while (0) -#define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \ - (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \ - >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S) +#define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL( \ + HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value); \ + (word) |= (value) << \ + HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \ +} while (0) +#define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \ + (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \ + >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S) -#define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value);\ - (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \ - } while (0) -#define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \ - (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \ - >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S) +#define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL( \ + HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value); \ + (word) |= (value) << \ + HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \ +} while (0) +#define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \ + (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \ + >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S) -#define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value);\ - (word) |= (value) << HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \ - } while (0) -#define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \ - (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \ - >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S) +#define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL( \ + HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value); \ + (word) |= (value) << \ + HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \ +} while (0) +#define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \ + (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \ + >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S) -#define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value);\ - (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \ - } while (0) -#define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \ - (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \ - >> HTT_CHAN_CHANGE_PHY_MODE_S) +#define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \ +do { \ + HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value); \ + (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \ +} while (0) +#define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \ + (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \ + >> HTT_CHAN_CHANGE_PHY_MODE_S) #define HTT_CHAN_CHANGE_BYTES sizeof(struct htt_chan_change_t) @@ -8482,8 +8802,8 @@ PREPACK struct htt_chan_change_t */ enum htt_rx_ofld_pkt_err_type { - HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0, - HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR, + HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0, + HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR, }; /* definition for HTT_RX_OFLD_PKT_ERR msg hdr */ @@ -8498,30 +8818,31 @@ enum htt_rx_ofld_pkt_err_type { #define HTT_RX_OFLD_PKT_ERR_TID_M 0xff000000 #define HTT_RX_OFLD_PKT_ERR_TID_S 24 -#define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \ - >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S) -#define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \ + >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S) +#define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \ + } while (0) -#define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> HTT_RX_OFLD_PKT_ERR_VDEV_ID_S) -#define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> \ + HTT_RX_OFLD_PKT_ERR_VDEV_ID_S) +#define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \ + } while (0) -#define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S) -#define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S) +#define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \ + } while (0) /* definition for HTT_RX_OFLD_PKT_ERR_MIC_ERR msg sub-type payload */ #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_BYTES 28 @@ -8550,77 +8871,77 @@ enum htt_rx_ofld_pkt_err_type { #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M 0x0000ffff #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S 0 -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \ +} while (0) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \ - (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \ - HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S) -#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \ - ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \ - } while (0) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \ + (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \ + HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S) +#define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \ +do { \ + HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \ + ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \ +} while (0) /** * @brief peer rate report message @@ -8692,10 +9013,10 @@ enum htt_rx_ofld_pkt_err_type { */ enum htt_peer_rate_report_phy_type { - HTT_PEER_RATE_REPORT_11B = 0, - HTT_PEER_RATE_REPORT_11A_G, - HTT_PEER_RATE_REPORT_11N, - HTT_PEER_RATE_REPORT_11AC, + HTT_PEER_RATE_REPORT_11B = 0, + HTT_PEER_RATE_REPORT_11A_G, + HTT_PEER_RATE_REPORT_11N, + HTT_PEER_RATE_REPORT_11AC, }; #define HTT_PEER_RATE_REPORT_SIZE 8 @@ -8710,31 +9031,31 @@ enum htt_peer_rate_report_phy_type { #define HTT_PEER_RATE_REPORT_MSG_PHY_S 16 #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_GET(_var) \ - (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \ - >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S) + (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \ + >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S) #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \ - ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \ + ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \ + } while (0) #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_GET(_var) \ - (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \ - >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S) + (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \ + >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S) #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \ + } while (0) #define HTT_PEER_RATE_REPORT_MSG_PHY_GET(_var) \ - (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \ - >> HTT_PEER_RATE_REPORT_MSG_PHY_S) + (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \ + >> HTT_PEER_RATE_REPORT_MSG_PHY_S) #define HTT_PEER_RATE_REPORT_MSG_PHY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \ - ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \ + ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \ + } while (0) /** * @brief HTT_T2H_MSG_TYPE_FLOW_POOL_MAP Message @@ -8833,24 +9154,24 @@ enum htt_peer_rate_report_phy_type { */ enum htt_flow_type { - FLOW_TYPE_VDEV = 0, - /* Insert new flow types above this line */ + FLOW_TYPE_VDEV = 0, + /* Insert new flow types above this line */ }; PREPACK struct htt_flow_pool_map_payload_t { - A_UINT32 flow_type; - A_UINT32 flow_id; - A_UINT32 flow_pool_id:16, - reserved0:16; - A_UINT32 flow_pool_size:16, - reserved1:16; - A_UINT32 reserved2; + A_UINT32 flow_type; + A_UINT32 flow_id; + A_UINT32 flow_pool_id:16, + reserved0:16; + A_UINT32 flow_pool_size:16, + reserved1:16; + A_UINT32 reserved2; } POSTPACK; #define HTT_FLOW_POOL_MAP_HEADER_SZ (sizeof(A_UINT32)) #define HTT_FLOW_POOL_MAP_PAYLOAD_SZ \ - (sizeof(struct htt_flow_pool_map_payload_t)) + (sizeof(struct htt_flow_pool_map_payload_t)) #define HTT_FLOW_POOL_MAP_NUM_FLOWS_M 0x0000ff00 #define HTT_FLOW_POOL_MAP_NUM_FLOWS_S 8 @@ -8867,52 +9188,52 @@ PREPACK struct htt_flow_pool_map_payload_t { #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M 0x0000ffff #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S 0 -#define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \ - (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S) +#define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \ + (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S) -#define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \ - (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S) +#define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \ + (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S) -#define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \ - (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S) +#define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \ + (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S) -#define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \ - (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \ - HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S) +#define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \ + (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \ + HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S) -#define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \ - (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \ - HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S) +#define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \ + (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \ + HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S) -#define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \ - } while (0) +#define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \ + } while (0) -#define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \ - } while (0) +#define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \ + } while (0) -#define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \ - } while (0) +#define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \ + } while (0) -#define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \ - } while (0) +#define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \ + } while (0) -#define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \ - } while (0) +#define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \ + } while (0) /** * @brief HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP Message @@ -8960,12 +9281,12 @@ PREPACK struct htt_flow_pool_map_payload_t { */ PREPACK struct htt_flow_pool_unmap_t { - A_UINT32 msg_type:8, - reserved0:24; - A_UINT32 flow_type; - A_UINT32 flow_id; - A_UINT32 flow_pool_id:16, - reserved1:16; + A_UINT32 msg_type:8, + reserved0:24; + A_UINT32 flow_type; + A_UINT32 flow_id; + A_UINT32 flow_pool_id:16, + reserved1:16; } POSTPACK; #define HTT_FLOW_POOL_UNMAP_SZ (sizeof(struct htt_flow_pool_unmap_t)) @@ -8979,35 +9300,34 @@ PREPACK struct htt_flow_pool_unmap_t { #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M 0x0000ffff #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S 0 -#define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \ - (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \ - HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S) +#define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \ + (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \ + HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S) -#define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \ - (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S) +#define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \ + (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S) -#define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \ - (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \ - HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S) +#define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \ + (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \ + HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S) -#define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \ - } while (0) +#define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \ + } while (0) -#define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \ - } while (0) - -#define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \ - ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \ - } while (0) +#define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \ + } while (0) +#define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \ + ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \ + } while (0) /** * @brief HTT_T2H_MSG_TYPE_SRING_SETUP_DONE Message @@ -9039,15 +9359,15 @@ PREPACK struct htt_flow_pool_unmap_t { */ PREPACK struct htt_sring_setup_done_t { - A_UINT32 msg_type: 8, - pdev_id: 8, - ring_id: 8, - setup_status: 8; + A_UINT32 msg_type: 8, + pdev_id: 8, + ring_id: 8, + setup_status: 8; } POSTPACK; enum htt_ring_setup_status { - htt_ring_setup_status_ok = 0, - htt_ring_setup_status_error, + htt_ring_setup_status_ok = 0, + htt_ring_setup_status_error, }; #define HTT_SRING_SETUP_DONE_SZ (sizeof(struct htt_sring_setup_done_t)) @@ -9055,35 +9375,35 @@ enum htt_ring_setup_status { #define HTT_SRING_SETUP_DONE_PDEV_ID_M 0x0000ff00 #define HTT_SRING_SETUP_DONE_PDEV_ID_S 8 #define HTT_SRING_SETUP_DONE_PDEV_ID_GET(_var) \ - (((_var) & HTT_SRING_SETUP_DONE_PDEV_ID_M) >> \ - HTT_SRING_SETUP_DONE_PDEV_ID_S) + (((_var) & HTT_SRING_SETUP_DONE_PDEV_ID_M) >> \ + HTT_SRING_SETUP_DONE_PDEV_ID_S) #define HTT_SRING_SETUP_DONE_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_PDEV_ID_S)); \ + } while (0) #define HTT_SRING_SETUP_DONE_RING_ID_M 0x00ff0000 #define HTT_SRING_SETUP_DONE_RING_ID_S 16 #define HTT_SRING_SETUP_DONE_RING_ID_GET(_var) \ - (((_var) & HTT_SRING_SETUP_DONE_RING_ID_M) >> \ - HTT_SRING_SETUP_DONE_RING_ID_S) + (((_var) & HTT_SRING_SETUP_DONE_RING_ID_M) >> \ + HTT_SRING_SETUP_DONE_RING_ID_S) #define HTT_SRING_SETUP_DONE_RING_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_RING_ID, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_RING_ID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_RING_ID, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_RING_ID_S)); \ + } while (0) #define HTT_SRING_SETUP_DONE_STATUS_M 0xff000000 #define HTT_SRING_SETUP_DONE_STATUS_S 24 #define HTT_SRING_SETUP_DONE_STATUS_GET(_var) \ - (((_var) & HTT_SRING_SETUP_DONE_STATUS_M) >> \ - HTT_SRING_SETUP_DONE_STATUS_S) + (((_var) & HTT_SRING_SETUP_DONE_STATUS_M) >> \ + HTT_SRING_SETUP_DONE_STATUS_S) #define HTT_SRING_SETUP_DONE_STATUS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_STATUS, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_STATUS_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DONE_STATUS, _val); \ + ((_var) |= ((_val) << HTT_SRING_SETUP_DONE_STATUS_S)); \ + } while (0) /** @@ -9120,7 +9440,7 @@ enum htt_ring_setup_status { * * dword0 - b'28:31 - rsvd0: Reserved for future use * - * dword1 - b'0:13 - peer_id: Software peer id given by host during association + * dword1 - b'0:13 - peer_id: Software peer id given by host during association * * dword1 - b'14:17 - tid * @@ -9134,17 +9454,17 @@ enum htt_ring_setup_status { * given by host */ PREPACK struct htt_tx_map_flow_info { - A_UINT32 - msg_type: 8, - fse_hsh_idx: 20, - rsvd0: 4; - A_UINT32 - peer_id: 14, - tid: 4, - rsvd1: 14; - A_UINT32 tqm_flow_pntr_lo; - A_UINT32 tqm_flow_pntr_hi; - struct htt_tx_flow_metadata fse_meta_data; + A_UINT32 + msg_type: 8, + fse_hsh_idx: 20, + rsvd0: 4; + A_UINT32 + peer_id: 14, + tid: 4, + rsvd1: 14; + A_UINT32 tqm_flow_pntr_lo; + A_UINT32 tqm_flow_pntr_hi; + struct htt_tx_flow_metadata fse_meta_data; } POSTPACK; /* DWORD 0 */ @@ -9159,31 +9479,31 @@ PREPACK struct htt_tx_map_flow_info { /* DWORD 0 */ #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_GET(_var) \ - (((_var) & HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M) >> \ - HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S) + (((_var) & HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_M) >> \ + HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S) #define HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX, _val); \ - ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX, _val); \ + ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_FSE_HSH_IDX_S)); \ + } while (0) /* DWORD 1 */ #define HTT_TX_MAP_FLOW_INFO_PEER_ID_GET(_var) \ - (((_var) & HTT_TX_MAP_FLOW_INFO_PEER_ID_M) >> \ - HTT_TX_MAP_FLOW_INFO_PEER_ID_S) + (((_var) & HTT_TX_MAP_FLOW_INFO_PEER_ID_M) >> \ + HTT_TX_MAP_FLOW_INFO_PEER_ID_S) #define HTT_TX_MAP_FLOW_INFO_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_PEER_ID_IDX, _val); \ - ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_PEER_ID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_PEER_ID_IDX, _val); \ + ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_PEER_ID_S)); \ + } while (0) #define HTT_TX_MAP_FLOW_INFO_TID_GET(_var) \ - (((_var) & HTT_TX_MAP_FLOW_INFO_TID_M) >> \ - HTT_TX_MAP_FLOW_INFO_TID_S) + (((_var) & HTT_TX_MAP_FLOW_INFO_TID_M) >> \ + HTT_TX_MAP_FLOW_INFO_TID_S) #define HTT_TX_MAP_FLOW_INFO_TID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_TID_IDX, _val); \ - ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_TID_S)); \ - } while (0) + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MAP_FLOW_INFO_TID_IDX, _val); \ + ((_var) |= ((_val) << HTT_TX_MAP_FLOW_INFO_TID_S)); \ + } while (0) #endif diff --git a/fw/htt_common.h b/fw/htt_common.h old mode 100755 new mode 100644 index 93a08b221210..8f4d82fe72e3 --- a/fw/htt_common.h +++ b/fw/htt_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -35,43 +35,43 @@ #define _HTT_COMMON_H_ enum htt_sec_type { - htt_sec_type_none, - htt_sec_type_wep128, - htt_sec_type_wep104, - htt_sec_type_wep40, - htt_sec_type_tkip, - htt_sec_type_tkip_nomic, - htt_sec_type_aes_ccmp, - htt_sec_type_wapi, - htt_sec_type_aes_ccmp_256, - htt_sec_type_aes_gcmp, - htt_sec_type_aes_gcmp_256, + htt_sec_type_none, + htt_sec_type_wep128, + htt_sec_type_wep104, + htt_sec_type_wep40, + htt_sec_type_tkip, + htt_sec_type_tkip_nomic, + htt_sec_type_aes_ccmp, + htt_sec_type_wapi, + htt_sec_type_aes_ccmp_256, + htt_sec_type_aes_gcmp, + htt_sec_type_aes_gcmp_256, - /* keep this last! */ - htt_num_sec_types + /* keep this last! */ + htt_num_sec_types }; enum htt_rx_ind_mpdu_status { - HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, - HTT_RX_IND_MPDU_STATUS_OK, - HTT_RX_IND_MPDU_STATUS_ERR_FCS, - HTT_RX_IND_MPDU_STATUS_ERR_DUP, - HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, - HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, - HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */ - HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, - HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */ - HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, - HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, - HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, - HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, - HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, + HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, + HTT_RX_IND_MPDU_STATUS_OK, + HTT_RX_IND_MPDU_STATUS_ERR_FCS, + HTT_RX_IND_MPDU_STATUS_ERR_DUP, + HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, + HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, + HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */ + HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, + HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */ + HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, + HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, + HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, + HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, + HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, - /* - * MISC: discard for unspecified reasons. - * Leave this enum value last. - */ - HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF + /* + * MISC: discard for unspecified reasons. + * Leave this enum value last. + */ + HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF }; #define HTT_INVALID_PEER 0xffff @@ -103,18 +103,31 @@ enum htt_rx_ind_mpdu_status { * type rather than L2 header type. */ enum htt_pkt_type { - htt_pkt_type_raw = 0, - htt_pkt_type_native_wifi = 1, - htt_pkt_type_ethernet = 2, - htt_pkt_type_mgmt = 3, - htt_pkt_type_eth2 = 4, + htt_pkt_type_raw = 0, + htt_pkt_type_native_wifi = 1, + htt_pkt_type_ethernet = 2, + htt_pkt_type_mgmt = 3, + htt_pkt_type_eth2 = 4, - /* keep this last */ - htt_pkt_num_types + /* keep this last */ + htt_pkt_num_types }; +/* + * TX MSDU ID partition - + * FW supports bigger MSDU ID partition which is defined as + * HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN + * When both host and FW support new partition, FW uses + * HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN + * If host doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN + * Handshaking is done through WMI_READY and WMI_INIT + */ #define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0 #define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN 3000 #define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000 +/* 8192 = 0xr2000 */ +#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192 +/* 12288 = 0x3000 */ +#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288 #endif /* _HTT_COMMON_H_ */ diff --git a/fw/htt_isoc.h b/fw/htt_isoc.h new file mode 100644 index 000000000000..e0bca712e322 --- /dev/null +++ b/fw/htt_isoc.h @@ -0,0 +1,1244 @@ +/* + * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +/** + * @file htt_isoc.h + * + * @details + * This file defines the target --> host messages that configure the + * host data-path SW with the information required for data transfers + * to and from the target. + */ + +#ifndef _HTT_ISOC_H_ +#define _HTT_ISOC_H_ + +#include /* A_UINT32, A_UINT8 */ +#include /* A_COMPILE_TIME_ASSERT */ + +#ifdef ATHR_WIN_NWF +#pragma warning(disable:4214) /* bit field types other than int */ +#endif + +#include "htt_common.h" + +/*=== definitions that apply to all messages ================================*/ + +typedef enum htt_isoc_t2h_msg_type { + /* 0x0 reserved for VERSION message (probably not needed) */ + + /* PEER_INFO - specify ID and parameters of a new peer */ + HTT_ISOC_T2H_MSG_TYPE_PEER_INFO = 0x1, + + /* PEER_UNMAP - deallocate the ID that refers to a peer */ + HTT_ISOC_T2H_MSG_TYPE_PEER_UNMAP = 0x2, + + /* ADDBA - start rx aggregation for the specified peer-TID */ + HTT_ISOC_T2H_MSG_TYPE_RX_ADDBA = 0x3, + + /* DELBA - stop rx aggregation for the specified peer-TID */ + HTT_ISOC_T2H_MSG_TYPE_RX_DELBA = 0x4, + + /* TX_COMPL_IND - over-the-air tx completion notification for a tx frame */ + HTT_ISOC_T2H_MSG_TYPE_TX_COMPL_IND = 0x5, + + /* SEC_IND - notification of the type of security used for a new peer */ + HTT_ISOC_T2H_MSG_TYPE_SEC_IND = 0x6, + + /* PEER_TX_READY - the target is ready to transmit to a new peer */ + HTT_ISOC_T2H_MSG_TYPE_PEER_TX_READY = 0x7, + + /* RX_ERR - notification that an rx frame was discarded due to errors */ + HTT_ISOC_T2H_MSG_TYPE_RX_ERR = 0x8, + + /* NLO_MATCH - notification that target found NLO match */ + HTT_ISOC_T2H_MSG_TYPE_NLO_MATCH = 0x9, + + /* NLO_SCAN_END - notification that target NLO SCAN END 1:1 map with NLO_MATCH */ + HTT_ISOC_T2H_MSG_TYPE_NLO_SCAN_END = 0xA, + /* keep this last */ + HTT_ISOC_T2H_NUM_MSGS +} htt_isoc_t2h_msg_type; + +/* + * HTT ISOC target to host message type - + * stored in bits 7:0 of the first word of the message + */ +#define HTT_ISOC_T2H_MSG_TYPE_M 0xff +#define HTT_ISOC_T2H_MSG_TYPE_S 0 + +#define HTT_ISOC_T2H_MSG_TYPE_SET(msg_addr, msg_type) \ + (*((A_UINT8 *) msg_addr) = (msg_type)) +#define HTT_ISOC_T2H_MSG_TYPE_GET(msg_addr) \ + (*((A_UINT8 *) msg_addr)) + +#ifndef INLINE +#ifdef QCA_SUPPORT_INTEGRATED_SOC +/* host SW */ +#define INLINE inline +#else +/* target FW */ +#define INLINE __inline +#endif +#define HTT_ISOC_INLINE_DEF +#endif /* INLINE */ + +static INLINE void +htt_isoc_t2h_field_set( + A_UINT32 *msg_addr32, + unsigned offset32, + unsigned mask, + unsigned shift, + unsigned value) +{ + /* sanity check: make sure the value fits within the field */ + /* qdf_assert(value << shift == (value << shift) | mask); */ + + msg_addr32 += offset32; + /* clear the field */ + *msg_addr32 &= ~mask; + /* write the new value */ + *msg_addr32 |= (value << shift); +} + +#ifdef HTT_ISOC_INLINE_DEF +#undef HTT_ISOC_INLINE_DEF +#undef INLINE +#endif + +#define HTT_ISOC_T2H_FIELD_GET(msg_addr32, offset32, mask, shift) \ + (((*(msg_addr32 + offset32)) & mask) >> shift) + +typedef enum { + /* ASSOC - "real" peer from STA-AP association */ + HTT_ISOC_T2H_PEER_TYPE_ASSOC = 0x0, + + /* SELF - self-peer for unicast tx to unassociated peer */ + HTT_ISOC_T2H_PEER_TYPE_SELF = 0x1, + + /* BSSID - reserved for FW use for BT-AMP+IBSS */ + HTT_ISOC_T2H_PEER_TYPE_BSSID = 0x2, + + /* BCAST - self-peer for multicast / broadcast tx */ + HTT_ISOC_T2H_PEER_TYPE_BCAST = 0x3 +} HTT_ISOC_T2H_PEER_TYPE_ENUM; + +enum { + HTT_ISOC_NON_QOS = 0, + HTT_ISOC_QOS = 1 +}; + +enum { + HTT_ISOC_RMF_DISABLED = 0, + HTT_ISOC_RMF_ENABLED = 1 +}; + +enum { + HTT_ISOC_TID_MGMT = 7 +}; + +/*=== definitions for specific messages =====================================*/ + +/*=== PEER_INFO message ===*/ + +/** + * @brief target -> host peer info message definition + * + * @details + * The following diagram shows the format of the peer info message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * |31 25|24|23 18|17|16|15 11|10|9|8|7|6| 0| + * |-----------------------------------------------------------------------| + * | mgmt DPU idx | bcast DPU idx | DPU idx | msg type | + * |-----------------------------------------------------------------------| + * | mgmt DPU sig |bcast DPU sig | DPU sig | peer ID | + * |-----------------------------------------------------------------------| + * | MAC addr 1 | MAC addr 0 | vdev ID | |R| peer type | + * |-----------------------------------------------------------------------| + * | MAC addr 5 | MAC addr 4 | MAC addr 3 | MAC addr 2 | + * |-----------------------------------------------------------------------| + * + * + * The following field definitions describe the format of the peer info + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as peer info message + * Value: 0x1 + * - DPU_IDX + * Bits 15:8 + * Purpose: specify the DPU index (a.k.a. security key ID) to use for + * unicast data frames sent to this peer + * Value: key ID + * - BCAST_DPU_IDX + * Bits 23:16 + * Purpose: specify the DPU index (a.k.a. security key ID) to use for + * broadcast data frames sent by this (self) peer + * Value: key ID + * - MGMT_DPU_IDX + * Bits 31:24 + * Purpose: specify the DPU index (a.k.a. security key ID) to use for + * unicast management frames sent by this (self) peer + * Value: key ID + * WORD 1: + * - PEER_ID + * Bits 10:0 + * Purpose: The ID that the target has allocated to refer to the peer + * - DPU_SIG + * Bits 17:11 + * Purpose: specify the DPU signature (a.k.a. security key validity + * magic number) to specify for unicast data frames sent to this peer + * - BCAST_DPU_SIG + * Bits 24:18 + * Purpose: specify the DPU signature (a.k.a. security key validity + * magic number) to specify for broadcast data frames sent by this + * (self) peer + * - MGMT_DPU_SIG + * Bits 31:25 + * Purpose: specify the DPU signature (a.k.a. security key validity + * magic number) to specify for unicast management frames sent by this + * (self) peer + * WORD 2: + * - PEER_TYPE + * Bits 5:0 + * Purpose: specify whether the peer in question is a real peer or + * one of the types of "self-peer" created for the vdev + * Value: HTT_ISOC_T2H_PEER_TYPE enum + * - RMF_ENABLED (R) + * Bit 6 + * Purpose: specify whether the peer in question has enable robust + * management frames, to encrypt certain managment frames + * Value: HTT_ISOC_RMF enum + * Value: HTT_ISOC_NON_QOS or HTT_ISOC_QOS + * - VDEV_ID + * Bits 15:8 + * Purpose: For a real peer, the vdev ID indicates which virtual device + * the peer is associated with. For a self-peer, the vdev ID shows + * which virtual device the self-peer represents. + * - MAC_ADDR_L16 + * Bits 31:16 + * Purpose: Identifies which peer the peer ID is for. + * Value: lower 2 bytes of the peer's MAC address + * For a self-peer, the peer's MAC address is the MAC address of the + * vdev the self-peer represents. + * WORD 3: + * - MAC_ADDR_U32 + * Bits 31:0 + * Purpose: Identifies which peer the peer ID is for. + * Value: upper 4 bytes of the peer's MAC address + * For a self-peer, the peer's MAC address is the MAC address of the + * vdev the self-peer represents. + */ +typedef struct htt_isoc_t2h_peer_info_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_INFO */ + dpu_idx:8, bcast_dpu_idx:8, mgmt_dpu_idx:8; + /* word 1 */ + A_UINT32 peer_id:11, dpu_sig:7, bcast_dpu_sig:7, mgmt_dpu_sig:7; + /* word 2 */ + A_UINT32 + peer_type:6, rmf_enabled:1, reserved0:1, vdev_id:8, mac_addr_l16:16; + /* word 3 */ + A_UINT32 mac_addr_u32; +} htt_isoc_t2h_peer_info_t; + +/* word 0 */ +#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_OFFSET32 0 +#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_M 0x0000ff00 +#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_S 8 + +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_OFFSET32 0 +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M 0x00ff0000 +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_S 16 + +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_OFFSET32 0 +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M 0xff000000 +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_S 24 + +/* word 1 */ +#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_OFFSET32 1 +#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_M 0x000007ff +#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_S 0 + +#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_OFFSET32 1 +#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M 0x0003f800 +#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_S 11 + +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_OFFSET32 1 +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M 0x01fc0000 +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_S 18 + +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_OFFSET32 1 +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_M 0xfe000000 +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_S 25 + +/* word 2 */ +#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_OFFSET32 2 +#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_M 0x0000003f +#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_S 0 + +#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_OFFSET32 2 +#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_M 0x00000040 +#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_S 6 + +#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_OFFSET32 2 +#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_M 0x0000ff00 +#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_S 8 + +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_OFFSET32 2 +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_M 0xffff0000 +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_S 16 + +/* word 3 */ +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_OFFSET32 3 +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_M 0xffffffff +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_S 0 + +/* general field access macros */ + +#define HTT_ISOC_T2H_PEER_INFO_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_PEER_INFO_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_PEER_INFO_ ## field ## _M, \ + HTT_ISOC_T2H_PEER_INFO_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_PEER_INFO_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_PEER_INFO_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_PEER_INFO_ ## field ## _M, \ + HTT_ISOC_T2H_PEER_INFO_ ## field ## _S) + +/* access macros for specific fields */ + +#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(DPU_IDX, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(DPU_IDX, msg_addr) + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M_Size_Check, + (HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_S) \ + <= ((A_UINT8)~((A_UINT8)0))); +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(BCAST_DPU_IDX, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_GET(msg_addr) \ + (A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(BCAST_DPU_IDX, msg_addr)) + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M_Size_Check, + (HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_S) \ + <= ((A_UINT8)~((A_UINT8)0))); +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MGMT_DPU_IDX, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_GET(msg_addr) \ + (A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MGMT_DPU_IDX, msg_addr)) + +#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(PEER_ID, msg_addr) + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M_Size_Check, + (HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M >> HTT_ISOC_T2H_PEER_INFO_DPU_SIG_S)\ + <= ((A_UINT8)~((A_UINT8)0))); +#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(DPU_SIG, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_GET(msg_addr) \ + (A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(DPU_SIG, msg_addr)) + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M_Size_Check, + (HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_S)\ + <= ((A_UINT8)~((A_UINT8)0))); +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(BCAST_DPU_SIG, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_GET(msg_addr) \ + (A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(BCAST_DPU_SIG, msg_addr)) + +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MGMT_DPU_SIG, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MGMT_DPU_SIG, msg_addr) + +#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(PEER_TYPE, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(PEER_TYPE, msg_addr) + +#define HTT_ISOC_T2H_PEER_INFO_QOS_CAPABLE_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(QOS_CAPABLE, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_QOS_CAPABLE_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(QOS_CAPABLE, msg_addr) + +#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(RMF_ENABLED, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(RMF_ENABLED, msg_addr) + +#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(VDEV_ID, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(VDEV_ID, msg_addr) + +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MAC_ADDR_L16, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MAC_ADDR_L16, msg_addr) + +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MAC_ADDR_U32, msg_addr, value) +#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_GET(msg_addr) \ + HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MAC_ADDR_U32, msg_addr) + +/*=== PEER_UNMAP message ===*/ + +/** + * @brief target -> host peer unmap message definition + * + * @details + * The following diagram shows the format of the peer unmap message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * |31 19|18 8|7 0| + * |-----------------------------------------------------------------------| + * | reserved | peer ID | msg type | + * |-----------------------------------------------------------------------| + * + * + * The following field definitions describe the format of the peer info + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as peer unmap message + * Value: 0x2 + * - PEER_ID + * Bits 18:8 + * Purpose: The ID that the target has allocated to refer to the peer + */ +typedef struct htt_isoc_t2h_peer_unmap_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_UNMAP */ + peer_id:11, reserved0:13; +} htt_isoc_t2h_peer_unmap_t; + +/* word 0 */ +#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_OFFSET32 0 +#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M 0x0007ff00 +#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S 8 + +/* general field access macros */ + +#define HTT_ISOC_T2H_PEER_UNMAP_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _M, \ + HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_PEER_UNMAP_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _M, \ + HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _S) + +/* access macros for specific fields */ + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M_Size_Check, + (HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M >> HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S) \ + < ((A_UINT16)~((A_UINT16)0))); +#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_UNMAP_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_GET(msg_addr) \ + (A_UINT16)(HTT_ISOC_T2H_PEER_UNMAP_FIELD_GET(PEER_ID, msg_addr)) + +/*=== ADDBA message ===*/ +enum { + htt_isoc_addba_success = 0, + /* TBD: use different failure values to specify failure causes? */ + htt_isoc_addba_fail = 1, +}; + +/** + * @brief target -> host ADDBA message definition + * + * @details + * The following diagram shows the format of the rx ADDBA message sent + * from the target to the host: + * + * |31 20|19 16|15 12|11 8|7 0| + * |---------------------------------------------------------------------| + * | peer ID | TID | window size | msg type | + * |---------------------------------------------------------------------| + * | reserved |S| start seq num | + * |---------------------------------------------------------------------| + * + * The following field definitions describe the format of the ADDBA + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as an ADDBA message + * Value: 0x3 + * - WIN_SIZE + * Bits 15:8 + * Purpose: Specifies the length of the block ack window (max = 64). + * Value: + * block ack window length specified by the received ADDBA + * management message. + * - TID + * Bits 19:16 + * Purpose: Specifies which traffic identifier the ADDBA is for. + * Value: + * TID specified by the received ADDBA management message. + * - PEER_ID + * Bits 31:20 + * Purpose: Identifies which peer sent the ADDBA. + * Value: + * ID (hash value) used by the host for fast, direct lookup of + * host SW peer info, including rx reorder states. + * - START_SEQ_NUM + * Bits 11:0 + * Purpose: Specifies the initial location of the block ack window + * Value: start sequence value specified by the ADDBA-request message + * - STATUS + * Bit 12 + * Purpose: status of the WMI ADDBA request + * Value: 0 - SUCCESS, 1 - FAILURE + */ +typedef struct htt_isoc_t2h_addba_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_ADDBA */ + win_size:8, tid:4, peer_id:12; + /* word 1 */ + A_UINT32 start_seq_num:12, status:1, reserved0:19; +} htt_isoc_t2h_addba_t; + +/* word 0 */ +#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_OFFSET32 0 +#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_M 0x0000ff00 +#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_S 8 + +#define HTT_ISOC_T2H_ADDBA_TID_OFFSET32 0 +#define HTT_ISOC_T2H_ADDBA_TID_M 0x000f0000 +#define HTT_ISOC_T2H_ADDBA_TID_S 16 + +#define HTT_ISOC_T2H_ADDBA_PEER_ID_OFFSET32 0 +#define HTT_ISOC_T2H_ADDBA_PEER_ID_M 0xfff00000 +#define HTT_ISOC_T2H_ADDBA_PEER_ID_S 20 + +/* word 1 */ +#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_OFFSET32 1 +#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_M 0x00000fff +#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_S 0 + +#define HTT_ISOC_T2H_ADDBA_STATUS_OFFSET32 1 +#define HTT_ISOC_T2H_ADDBA_STATUS_M 0x00001000 +#define HTT_ISOC_T2H_ADDBA_STATUS_S 12 + +/* general field access macros */ +#define HTT_ISOC_T2H_ADDBA_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_ADDBA_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_ADDBA_ ## field ## _M, \ + HTT_ISOC_T2H_ADDBA_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_ADDBA_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_ADDBA_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_ADDBA_ ## field ## _M, \ + HTT_ISOC_T2H_ADDBA_ ## field ## _S) + +/* access macros for specific fields */ + +#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_SET(msg_addr, value) \ + HTT_ISOC_T2H_ADDBA_FIELD_SET(WIN_SIZE, msg_addr, value) +#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_GET(msg_addr) \ + HTT_ISOC_T2H_ADDBA_FIELD_GET(WIN_SIZE, msg_addr) + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_ADDBA_TID_M_Size_Check, + (HTT_ISOC_T2H_ADDBA_TID_M >> HTT_ISOC_T2H_ADDBA_TID_S) \ + < ((A_UINT8)~((A_UINT8)0))); +#define HTT_ISOC_T2H_ADDBA_TID_SET(msg_addr, value) \ + HTT_ISOC_T2H_ADDBA_FIELD_SET(TID, msg_addr, value) +#define HTT_ISOC_T2H_ADDBA_TID_GET(msg_addr) \ + (A_UINT8)(HTT_ISOC_T2H_ADDBA_FIELD_GET(TID, msg_addr)) + +#define HTT_ISOC_T2H_ADDBA_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_ADDBA_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_ADDBA_PEER_ID_GET(msg_addr) \ + HTT_ISOC_T2H_ADDBA_FIELD_GET(PEER_ID, msg_addr) + +#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_SET(msg_addr, value) \ + HTT_ISOC_T2H_ADDBA_FIELD_SET(START_SEQ_NUM, msg_addr, value) +#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_GET(msg_addr) \ + HTT_ISOC_T2H_ADDBA_FIELD_GET(START_SEQ_NUM, msg_addr) + +#define HTT_ISOC_T2H_ADDBA_STATUS_SET(msg_addr, value) \ + HTT_ISOC_T2H_ADDBA_FIELD_SET(STATUS, msg_addr, value) +#define HTT_ISOC_T2H_ADDBA_STATUS_GET(msg_addr) \ + HTT_ISOC_T2H_ADDBA_FIELD_GET(STATUS, msg_addr) + +/*=== DELBA message ===*/ + +/** + * @brief target -> host DELBA message definition + * + * @details + * The following diagram shows the format of the rx DELBA message sent + * from the target to the host: + * + * |31 20|19 16|15 12|11 8|7 0| + * |---------------------------------------------------------------------| + * | peer ID | TID | reserved |S| msg type | + * |---------------------------------------------------------------------| + * + * The following field definitions describe the format of the ADDBA + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as an DELBA message + * Value: 0x4 + * - TID + * Bits 19:16 + * Purpose: Specifies which traffic identifier the DELBA is for. + * Value: + * TID specified by the received DELBA management message. + * - PEER_ID + * Bits 31:20 + * Purpose: Identifies which peer sent the DELBA. + * Value: + * ID (hash value) used by the host for fast, direct lookup of + * host SW peer info, including rx reorder states. + * - STATUS + * Bit 8 + * Purpose: status of the WMI DELBA request + * Value: 0 - SUCCESS, 1 - FAILURE + */ +typedef struct htt_isoc_t2h_delba_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_DELBA */ + status:1, reserved0:7, tid:4, peer_id:12; +} htt_isoc_t2h_delba_t; + +/* word 0 */ +#define HTT_ISOC_T2H_DELBA_TID_OFFSET32 0 +#define HTT_ISOC_T2H_DELBA_TID_M 0x000f0000 +#define HTT_ISOC_T2H_DELBA_TID_S 16 + +#define HTT_ISOC_T2H_DELBA_PEER_ID_OFFSET32 0 +#define HTT_ISOC_T2H_DELBA_PEER_ID_M 0xfff00000 +#define HTT_ISOC_T2H_DELBA_PEER_ID_S 20 + +#define HTT_ISOC_T2H_DELBA_STATUS_OFFSET32 0 +#define HTT_ISOC_T2H_DELBA_STATUS_M 0x00000100 +#define HTT_ISOC_T2H_DELBA_STATUS_S 8 + +/* general field access macros */ + +#define HTT_ISOC_T2H_DELBA_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_DELBA_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_DELBA_ ## field ## _M, \ + HTT_ISOC_T2H_DELBA_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_DELBA_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_DELBA_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_DELBA_ ## field ## _M, \ + HTT_ISOC_T2H_DELBA_ ## field ## _S) + +/* access macros for specific fields */ + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_DELBA_TID_M_Size_Check, + (HTT_ISOC_T2H_DELBA_TID_M >> HTT_ISOC_T2H_DELBA_TID_S) \ + < ((A_UINT8)~((A_UINT8)0))); +#define HTT_ISOC_T2H_DELBA_TID_SET(msg_addr, value) \ + HTT_ISOC_T2H_DELBA_FIELD_SET(TID, msg_addr, value) +#define HTT_ISOC_T2H_DELBA_TID_GET(msg_addr) \ + (A_UINT8)HTT_ISOC_T2H_DELBA_FIELD_GET(TID, msg_addr) + +#define HTT_ISOC_T2H_DELBA_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_DELBA_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_DELBA_PEER_ID_GET(msg_addr) \ + HTT_ISOC_T2H_DELBA_FIELD_GET(PEER_ID, msg_addr) + +#define HTT_ISOC_T2H_DELBA_STATUS_SET(msg_addr, value) \ + HTT_ISOC_T2H_DELBA_FIELD_SET(STATUS, msg_addr, value) +#define HTT_ISOC_T2H_DELBA_STATUS_GET(msg_addr) \ + HTT_ISOC_T2H_DELBA_FIELD_GET(STATUS, msg_addr) + +/*=== SEC_IND message ===*/ + +/** + * @brief target -> host Security indication message definition + * + * @details + * The following diagram shows the format of the SEC_IND message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * |31 25|24|23 18|17|16|15 11|10|9|8|7|6| 0| + * |-----------------------------------------------------------------------| + * | is unicast | sec type | Peer id | msg type | + * |-----------------------------------------------------------------------| + * | mic key1 | + * |-----------------------------------------------------------------------| + * | mic key2 | + * |-----------------------------------------------------------------------| + * + * + * The following field definitions describe the format of the peer info + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as SEC_IND message + * Value: 0x6 + * - PEER_ID + * Bits 15:8 + * Purpose: The ID that the target has allocated to refer to the peer + * Value: Peer ID + * - SEC_TYPE + * Bits 23:16 + * Purpose: specify the security encryption type + * Value: htt_sec_type + * - is unicast + * Bits 31:24 + * Purpose: specify unicast/bcast + * Value: 1-unicast/0-bcast + * WORD 1: + * - MIC1 + * Bits 31:0 + * Purpose: Mickey1 + * WORD 2: + * - MIC2 + * Bits 31:0 + * Purpose: Mickey2 + */ +typedef struct htt_isoc_t2h_sec_ind_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_SEC_IND */ + peer_id:8, sec_type:8, is_unicast:8; + /* word 1 */ + A_UINT32 mic_key1; + /* word 2 */ + A_UINT32 mic_key2; + /* word 3 */ + A_UINT32 status; +} htt_isoc_t2h_sec_ind_t; + +/* word 0 */ +#define HTT_ISOC_T2H_SEC_IND_PEER_ID_OFFSET32 0 +#define HTT_ISOC_T2H_SEC_IND_PEER_ID_M 0x0000ff00 +#define HTT_ISOC_T2H_SEC_IND_PEER_ID_S 8 + +#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_OFFSET32 0 +#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_M 0x00ff0000 +#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_S 16 + +#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_OFFSET32 0 +#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_M 0xff000000 +#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_S 24 + +/* word 1 */ +#define HTT_ISOC_T2H_SEC_IND_MIC1_OFFSET32 1 +#define HTT_ISOC_T2H_SEC_IND_MIC1_M 0xffffffff +#define HTT_ISOC_T2H_SEC_IND_MIC1_S 0 + +/* word 2 */ +#define HTT_ISOC_T2H_SEC_IND_MIC2_OFFSET32 2 +#define HTT_ISOC_T2H_SEC_IND_MIC2_M 0xffffffff +#define HTT_ISOC_T2H_SEC_IND_MIC2_S 0 + +/* general field access macros */ +#define HTT_ISOC_T2H_SEC_IND_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_SEC_IND_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_SEC_IND_ ## field ## _M, \ + HTT_ISOC_T2H_SEC_IND_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_SEC_IND_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_SEC_IND_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_SEC_IND_ ## field ## _M, \ + HTT_ISOC_T2H_SEC_IND_ ## field ## _S) + +/* access macros for specific fields */ +#define HTT_ISOC_T2H_SEC_IND_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_SEC_IND_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_SEC_IND_PEER_ID_GET(msg_addr) \ + HTT_ISOC_T2H_SEC_IND_FIELD_GET(PEER_ID, msg_addr) + +#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_SET(msg_addr, value) \ + HTT_ISOC_T2H_SEC_IND_FIELD_SET(SEC_TYPE, msg_addr, value) +#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_GET(msg_addr) \ + HTT_ISOC_T2H_SEC_IND_FIELD_GET(SEC_TYPE, msg_addr) + +#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_SET(msg_addr, value) \ + HTT_ISOC_T2H_SEC_IND_FIELD_SET(IS_UNICAST, msg_addr, value) +#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_GET(msg_addr) \ + HTT_ISOC_T2H_SEC_IND_FIELD_GET(IS_UNICAST, msg_addr) + +#define HTT_ISOC_T2H_SEC_IND_MIC1_SET(msg_addr, value) \ + HTT_ISOC_T2H_SEC_IND_FIELD_SET(MIC1, msg_addr, value) +#define HTT_ISOC_T2H_SEC_IND_MIC1_GET(msg_addr) \ + HTT_ISOC_T2H_SEC_IND_FIELD_GET(MIC1, msg_addr) + +#define HTT_ISOC_T2H_SEC_IND_MIC2_SET(msg_addr, value) \ + HTT_ISOC_T2H_SEC_IND_FIELD_SET(MIC2, msg_addr, value) +#define HTT_ISOC_T2H_SEC_IND_MIC2_GET(msg_addr) \ + HTT_ISOC_T2H_SEC_IND_FIELD_GET(MIC2, msg_addr) + +/*=== PEER_TX_READY message ===*/ + +/** + * @brief target -> host peer tx ready message definition + * + * @details + * The following diagram shows the format of the peer tx ready message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * |31 19|18 8|7 0| + * |-----------------------------------------------------------------------| + * | reserved | peer ID | msg type | + * |-----------------------------------------------------------------------| + * + * + * The following field definitions describe the format of the peer info + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as peer tx ready message + * Value: 0x7 + * - PEER_ID + * Bits 18:8 + * Purpose: The ID assigned to the peer by the PEER_INFO message + */ +typedef struct htt_isoc_t2h_peer_tx_ready_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_TX_READY */ + peer_id:11, reserved0:13; +} htt_isoc_t2h_peer_tx_ready_t; + +/* word 0 */ +#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_OFFSET32 0 +#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M 0x0007ff00 +#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S 8 + +/* general field access macros */ + +#define HTT_ISOC_T2H_PEER_TX_READY_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _M, \ + HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_PEER_TX_READY_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _M, \ + HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _S) + +/* access macros for specific fields */ + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M_Size_Check, + (HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M >> \ + HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S) < ((A_UINT16)~((A_UINT16)0))); + +#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_PEER_TX_READY_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_GET(msg_addr) \ + ((A_UINT16)(HTT_ISOC_T2H_PEER_TX_READY_FIELD_GET(PEER_ID, msg_addr))) + + +/*=== RX_ERR message ===*/ + +/** + * @brief target -> host rx error notification message definition + * + * @details + * The following diagram shows the format of the rx err message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * |31 16|15 8|7|6|5|4 0| + * |---------------------------------------------------------------------| + * | peer ID | rx err type | msg type | + * |---------------------------------------------------------------------| + * | reserved | rx err count |M| r | ext TID | + * |---------------------------------------------------------------------| + * M = multicast + * r = reserved + * + * The following field definitions describe the format of the peer info + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as an rx err message + * Value: 0x8 + * - RX_ERR_TYPE + * Bits 15:8 + * Purpose: specifies which type of rx error is being reported + * Value: htt_rx_ind_mpdu_status enum + * - PEER_ID + * Bits 31:16 + * Purpose: specify which peer sent the frame that resulted in an error + * WORD 1: + * - EXT_TID + * Bits 4:0 + * Purpose: specifies which traffic type had the rx error + * Value: 0-15 for a real TID value, 16 for non-QoS data, 31 for unknown + * - MCAST + * Bit 6 + * Purpose: specify whether the rx error frame was unicast or multicast + * Value: 0 -> unicast, 1 -> multicast + * - L2_HDR_IS_80211 + * Bit 7 + * Purpose: specifies whether the included L2 header (if present) is in + * 802.3 or 802.11 format + * Value: 0 -> 802.3, 1 -> 802.11 + * - L2_HDR_BYTES + * Bits 15:8 + * Purpose: Specify the size of the L2 header in this rx error report. + * Value: + * If no L2 header is included, this field shall be 0. + * If a 802.3 + LLC/SNAP header is included, this field shall be + * 14 (ethernet header) + 8 (LLC/SNAP). + * If a 802.11 header is included, this field shall be 24 bytes for + * a basic header, or 26 bytes if a QoS control field is included, + * or 30 bytes if a 4th address is included, or 32 bytes if a 4th + * address and a QoS control field are included, etc. + * Though the L2 header included in the message needs to include + * padding up to a 4-byte boundary, this L2 header size field need + * not account for the padding following the L2 header. + * - SEC_HDR_BYTES + * Bits 23:16 + * Purpose: Specify the size of the security encapsulation header in + * this rx error report. + * Value: + * If no security header is included, this field shall be 0. + * If a security header is included, this field depends on the + * security type, which can be inferred from the rx error type. + * For TKIP MIC errors, the security header could be any of: + * 8 - if IV / KeyID and Extended IV are included + * 16 - if MIC is also included + * 20 - if ICV is also included + * - RX_ERR_CNT + * Bits 31:24 + * Purpose: specifies how many rx errors are reported in this message + * Value: + * Rx error reports that include a L2 header and/or security header + * will set this field to 1, to indicate that the error notification + * is for a single frame. + * Rx error reports that don't include a L2 header or security header + * can use this field to send a single message to report multiple + * erroneous rx frames. + */ +typedef struct htt_isoc_t2h_rx_err_s { + /* word 0 */ + A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_RX_ERR */ + rx_err_type:8, peer_id:16; + /* word 1 */ + A_UINT32 + ext_tid:5, + reserved1:1, + mcast:1, + l2_hdr_is_80211:1, l2_hdr_bytes:8, sec_hdr_bytes:8, rx_err_cnt:8; + /* words 2 - M-1: L2 header */ + /* words M - N: security header */ +} htt_isoc_t2h_rx_err_t; + +/* This needs to be exact bytes for structure htt_isoc_t2h_rx_err_t + * * Since it is shared between host and FW, sizeof may not be used. + * * */ +#define HTT_ISOC_T2H_RX_ERR_BASE_BYTES 20 + +/* word 0 */ +#define HTT_ISOC_T2H_RX_ERR_TYPE_OFFSET32 0 +#define HTT_ISOC_T2H_RX_ERR_TYPE_M 0x0000ff00 +#define HTT_ISOC_T2H_RX_ERR_TYPE_ID_S 8 + +#define HTT_ISOC_T2H_RX_ERR_PEER_ID_OFFSET32 0 +#define HTT_ISOC_T2H_RX_ERR_PEER_ID_M 0xffff0000 +#define HTT_ISOC_T2H_RX_ERR_PEER_ID_S 16 + +/* word 1 */ +#define HTT_ISOC_T2H_RX_ERR_EXT_TID_OFFSET32 1 +#define HTT_ISOC_T2H_RX_ERR_EXT_TID_M 0x0000001f +#define HTT_ISOC_T2H_RX_ERR_EXT_TID_S 0 + +#define HTT_ISOC_T2H_RX_ERR_MCAST_OFFSET32 1 +#define HTT_ISOC_T2H_RX_ERR_MCAST_M 0x00000040 +#define HTT_ISOC_T2H_RX_ERR_MCAST_S 6 + +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_OFFSET32 1 +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_M 0x00000080 +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_S 7 + +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_OFFSET32 1 +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_M 0x0000ff00 +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_S 8 + +#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_OFFSET32 1 +#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_M 0x00ff0000 +#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_S 16 + +#define HTT_ISOC_T2H_RX_ERR_CNT_OFFSET32 1 +#define HTT_ISOC_T2H_RX_ERR_CNT_M 0xff000000 +#define HTT_ISOC_T2H_RX_ERR_CNT_S 24 + + +/* general field access macros */ + +#define HTT_ISOC_T2H_RX_ERR_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_RX_ERR_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_RX_ERR_ ## field ## _M, \ + HTT_ISOC_T2H_RX_ERR_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_RX_ERR_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_RX_ERR_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_RX_ERR_ ## field ## _M, \ + HTT_ISOC_T2H_RX_ERR_ ## field ## _S) + +/* access macros for specific fields */ + +#define HTT_ISOC_T2H_RX_ERR_TYPE_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(TYPE, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_TYPE_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(TYPE, msg_addr) + +A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_RX_ERR_PEER_ID_M_Size_Check, + (HTT_ISOC_T2H_RX_ERR_PEER_ID_M >> HTT_ISOC_T2H_RX_ERR_PEER_ID_S) \ + <= ((A_UINT16)~((A_UINT16)0))); +#define HTT_ISOC_T2H_RX_ERR_PEER_ID_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(PEER_ID, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_PEER_ID_GET(msg_addr) \ + ((A_UINT16)HTT_ISOC_T2H_RX_ERR_FIELD_GET(PEER_ID, msg_addr)) + +#define HTT_ISOC_T2H_RX_ERR_EXT_TID_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(EXT_TID, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_EXT_TID_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(EXT_TID, msg_addr) + +#define HTT_ISOC_T2H_RX_ERR_MCAST_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(MCAST, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_MCAST_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(MCAST, msg_addr) + +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(L2_HDR_IS_80211, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(L2_HDR_IS_80211, msg_addr) + +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(L2_HDR_BYTES, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(L2_HDR_BYTES, msg_addr) + +#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(SEC_HDR_BYTES, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(SEC_HDR_BYTES, msg_addr) + +#define HTT_ISOC_T2H_RX_ERR_CNT_SET(msg_addr, value) \ + HTT_ISOC_T2H_RX_ERR_FIELD_SET(CNT, msg_addr, value) +#define HTT_ISOC_T2H_RX_ERR_CNT_GET(msg_addr) \ + HTT_ISOC_T2H_RX_ERR_FIELD_GET(CNT, msg_addr) + +/*=== TX OTA complete indication message ===*/ + +/** + * @brief target -> tx complete indicate message + * + * @details + * The following diagram shows the format of the tx complete indication message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * |31 19|18 8|7 0| + * |-----------------------------------------------------------------------| + * | reserved | status | msg type | + * |-----------------------------------------------------------------------| + * + * + * The following field definitions describe the format of the peer info + * message sent from the target to the host. + * + * WORD 0: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as tx complete indication message + * Value: 0x7 + * - status + * Bits 18:8 + * Purpose: TX completion status + */ +typedef struct htt_isoc_t2h_tx_compl_s { + /* word 0 */ + A_UINT32 + /* HTT_ISOC_T2H_MSG_TYPE_TX_COMPL_IND */ + qmsg_type:8, + status:11, + reserved0:13; +} htt_isoc_t2h_tx_compl_t; + +/* word 0 */ +#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_OFFSET32 0 +#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_M 0x0007ff00 +#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_S 8 + + +/* general field access macros */ + +#define HTT_ISOC_T2H_TX_COMPL_IND_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _M, \ + HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_TX_COMPL_IND_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _M, \ + HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _S) + +/* access macros for specific fields */ + +#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_SET(msg_addr, value) \ + HTT_ISOC_T2H_TX_COMPL_IND_FIELD_SET(STATUS, msg_addr, value) +#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_GET(msg_addr) \ + HTT_ISOC_T2H_TX_COMPL_IND_FIELD_GET(STATUS, msg_addr) + +#define HTT_TX_COMPL_IND_STAT_OK 0 +#define HTT_TX_COMPL_IND_STAT_DISCARD 1 +#define HTT_TX_COMPL_IND_STAT_NO_ACK 2 +#define HTT_TX_COMPL_IND_STAT_POSTPONE 3 + +/*=== NLO indication message ===*/ + +/** +* @brief target -> NLO indicate message +* +* @details +* The following diagram shows the format of the NLO indication message sent +* from the target to the host. This layout assumes the target operates +* as little-endian. +* +* |31 8|7 0| +* |-----------------------------------------------------------------------| +* | reserved | msg type | +* |-----------------------------------------------------------------------| +* +* +* The following field definitions describe the format of NLO MATCH indication +* message sent from the target to the host. +* +* WORD 0: +* - MSG_TYPE +* Bits 7:0 +* Purpose: identifies this as NLO indication message +* Value: 0x9 - HTT_ISOC_T2H_MSG_TYPE_NLO_MATCH +* Value: 0xA - HTT_ISOC_T2H_MSG_TYPE_NLO_SCAN_END +*/ +typedef struct htt_isoc_t2h_nlo_ind_s { + /* word 0 */ + A_UINT32 + msg_type:8, + vdev_id:8, + reserved0:16; +} htt_isoc_t2h_nlo_ind_t; + +/* word 0 */ +#define HTT_ISOC_T2H_NLO_IND_VDEVID_OFFSET32 0 +#define HTT_ISOC_T2H_NLO_IND_VDEVID_M 0x0000ff00 +#define HTT_ISOC_T2H_NLO_IND_VDEVID_S 8 + + +/* general field access macros */ + +#define HTT_ISOC_T2H_NLO_IND_FIELD_SET(field, msg_addr, value) \ + htt_isoc_t2h_field_set( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_NLO_IND_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_NLO_IND_ ## field ## _M, \ + HTT_ISOC_T2H_NLO_IND_ ## field ## _S, \ + value) + +#define HTT_ISOC_T2H_NLO_IND_FIELD_GET(field, msg_addr) \ + HTT_ISOC_T2H_FIELD_GET( \ + ((A_UINT32 *) msg_addr), \ + HTT_ISOC_T2H_NLO_IND_ ## field ## _OFFSET32, \ + HTT_ISOC_T2H_NLO_IND_ ## field ## _M, \ + HTT_ISOC_T2H_NLO_IND_ ## field ## _S) + +/* access macros for specific fields */ + +#define HTT_ISOC_T2H_NLO_IND_VDEVID_SET(msg_addr, value) \ + HTT_ISOC_T2H_NLO_IND_FIELD_SET(VDEVID, msg_addr, value) +#define HTT_ISOC_T2H_NLO_IND_VDEVID_GET(msg_addr) \ + HTT_ISOC_T2H_NLO_IND_FIELD_GET(VDEVID, msg_addr) + + +#endif /* _HTT_ISOC_H_ */ diff --git a/fw/ip_prot.h b/fw/ip_prot.h new file mode 100644 index 000000000000..a1722fe3eb4f --- /dev/null +++ b/fw/ip_prot.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef _IP_PROT__H_ +#define _IP_PROT__H_ + +#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */ +#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */ +#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */ +#define IP_PROTOCOL_TCP 0x06 /* Transmission Control Protocol */ +#define IP_PROTOCOL_UDP 0x11 /* User Datagram Protocol */ +#define IP_PROTOCOL_RDP 0x1B /* Reliable Datagram Protocol */ +#define IP_PROTOCOL_IPV6 0x29 /* IPv6 (encapsulation) */ +#define IP_PROTOCOL_IPV6_ROUTE 0x2B /* Routing Header for IPv6 */ +#define IP_PROTOCOL_IPV6_FRAG 0x2C /* Fragment Header for IPv6 */ +#define IP_PROTOCOL_RSVP 0x2E /* Resource Reservation Protocol */ +#define IP_PROTOCOL_GRE 0x2F /* Generic Routing Encapsulation */ +#define IP_PROTOCOL_MHRP 0x30 /* Mobile Host Routing Protocol */ +#define IP_PROTOCOL_BNA 0x31 /* BNA */ +#define IP_PROTOCOL_ESP 0x32 /* Encapsulating Security Payload */ +#define IP_PROTOCOL_MOBILE 0x37 /* IP Mobility (Min Encap) */ +#define IP_PROTOCOL_IPV6_ICMP 0x3A /* ICMP for IPv6 */ +#define IP_PROTOCOL_IPV6_NONXT 0x3B /* No Next Header for IPv6 */ +#define IP_PROTOCOL_IPV6_OPTS 0x3C /* Destination Options for IPv6 */ +#define IP_PROTOCOL_IPCOMP 0x6C /* IP Payload Compression Protocol */ +#define IP_PROTOCOL_L2TP 0x73 /* Layer Two Tunneling Protocol Version 3 */ +#define IP_PROTOCOL_SMP 0x79 /* Simple Message Protocol */ +#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */ +#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */ + +/* IPv6 ICMP types */ +#define IPV6_ICMP_TYPE_MLD 0x8F + +#endif /* _IP_PROT__H_ */ diff --git a/fw/ipv4.h b/fw/ipv4.h new file mode 100644 index 000000000000..67eb3375507d --- /dev/null +++ b/fw/ipv4.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef _IPV4__H_ +#define _IPV4__H_ + +#if defined(ATH_TARGET) +#include /* A_UINT8 */ +#else +#include /* A_UINT8 */ +#endif + +#define IPV4_ADDR_LEN 4 /* bytes */ +struct ipv4_hdr_t { + A_UINT8 ver_hdrlen; /* version and hdr length */ + A_UINT8 tos; /* type of service */ + A_UINT8 len[2]; /* total length */ + A_UINT8 id[2]; + A_UINT8 flags_fragoff[2]; /* flags and fragment offset field */ + A_UINT8 ttl; /* time to live */ + A_UINT8 protocol; + A_UINT8 hdr_checksum[2]; + A_UINT8 src_addr[IPV4_ADDR_LEN]; + A_UINT8 dst_addr[IPV4_ADDR_LEN]; +}; + +#define IPV4_HDR_LEN (sizeof(struct ipv4_hdr_t)) +#define IPV4_HDR_OFFSET_PROTOCOL (offsetof(struct ipv4_hdr_t, protocol)) +#define IPV4_HDR_OFFSET_DST_ADDR (offsetof(struct ipv4_hdr_t, dst_addr[0])) + +#endif /* _IPV4__H_ */ diff --git a/fw/ol_fw_tx_dbg.h b/fw/ol_fw_tx_dbg.h new file mode 100644 index 000000000000..254e94a6c1d5 --- /dev/null +++ b/fw/ol_fw_tx_dbg.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2012, 2014-2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +/** + * @file ol_fw_tx_dbg.h + * + * @details data structs used for uploading summary info about the FW's tx + */ + +#ifndef _OL_FW_TX_DBG__H_ +#define _OL_FW_TX_DBG__H_ + +/* + * Undef ATH_SUPPORT_FW_TX_DBG to remove the FW tx debug feature. + * Removing the FW tx debug feature saves a modest amount of program memory. + * The data memory allocation for the FW tx debug feature is controlled + * by the host --> target resource configuration parameters; even if + * ATH_SUPPORT_FW_TX_DBG is defined, no data memory will be allocated for + * the FW tx debug log unless the host --> target resource configuration + * specifies it. + */ +#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */ +/* #undef ATH_SUPPORT_FW_TX_DBG / * disabled * / */ + +#if defined(ATH_TARGET) +#include /* A_UINT32 */ +#else +#include /* A_UINT32 */ +#include /* PREPACK, POSTPACK */ +#endif + +enum ol_fw_tx_dbg_log_mode { + ol_fw_tx_dbg_log_mode_wraparound, /* overwrite old data with new */ + ol_fw_tx_dbg_log_mode_single, /* fill log once, then stop */ +}; + +/* + * tx PPDU stats upload message header + */ +struct ol_fw_tx_dbg_ppdu_msg_hdr { + /* word 0 */ +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0 +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0 +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff + A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */ + +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0 +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8 +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00 + A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */ + +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0 +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16 +#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000 + A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */ + + A_UINT8 reserved; + + /* word 1 */ +#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1 +#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0 +#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff + A_UINT32 microsec_per_tick; /* conversion for timestamp entries */ +}; + +/* + * tx PPDU log element / stats upload message element + */ +struct ol_fw_tx_dbg_ppdu_base { + /* word 0 - filled in during tx enqueue */ +#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0 +#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0 +#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff + A_UINT16 start_seq_num; +#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0 +#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16 +#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000 + A_UINT16 start_pn_lsbs; + + /* word 1 - filled in during tx enqueue */ +#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1 +#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0 +#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff + A_UINT32 num_bytes; + + /* word 2 - filled in during tx enqueue */ +#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2 +#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0 +#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff + A_UINT8 num_msdus; +#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2 +#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8 +#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00 + A_UINT8 num_mpdus; + A_UINT16 +#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2 +#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16 +#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000 + ext_tid : 5, +#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2 +#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21 +#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000 + peer_id : 11; + + /* word 3 - filled in during tx enqueue */ +#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3 +#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0 +#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff + A_UINT32 timestamp_enqueue; + + /* word 4 - filled in during tx completion */ +#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4 +#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0 +#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff + A_UINT32 timestamp_completion; + + /* word 5 - filled in during tx completion */ +#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5 +#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0 +#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff + A_UINT32 block_ack_bitmap_lsbs; + + /* word 6 - filled in during tx completion */ +#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6 +#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0 +#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff + A_UINT32 block_ack_bitmap_msbs; + + /* word 7 - filled in during tx completion (enqueue would work too) */ +#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7 +#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0 +#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff + A_UINT32 enqueued_bitmap_lsbs; + + /* word 8 - filled in during tx completion (enqueue would work too) */ +#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8 +#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0 +#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff + A_UINT32 enqueued_bitmap_msbs; + + /* word 9 - filled in during tx completion */ +#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9 +#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0 +#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff + A_UINT8 rate_code; +#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9 +#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8 +#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00 + A_UINT8 rate_flags; /* includes dynamic bandwidth info */ +#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9 +#define OL_FW_TX_DBG_PPDU_TRIES_S 16 +#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000 + A_UINT8 tries; +#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9 +#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24 +#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000 + A_UINT8 complete; +}; + +#endif /* _OL_FW_TX_DBG__H_ */ diff --git a/fw/rtc_soc_reg.h b/fw/rtc_soc_reg.h new file mode 100644 index 000000000000..11e80b1f1f92 --- /dev/null +++ b/fw/rtc_soc_reg.h @@ -0,0 +1,1966 @@ +/* + * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef _RTC_SOC_REG_REG_H_ +#define _RTC_SOC_REG_REG_H_ + +#define SOC_RESET_CONTROL_ADDRESS 0x00000000 +#define SOC_RESET_CONTROL_OFFSET 0x00000000 +#define SOC_RESET_CONTROL_SPI2_RST_MSB 30 +#define SOC_RESET_CONTROL_SPI2_RST_LSB 30 +#define SOC_RESET_CONTROL_SPI2_RST_MASK 0x40000000 +#define SOC_RESET_CONTROL_SPI2_RST_GET(x) (((x) & SOC_RESET_CONTROL_SPI2_RST_MASK) >> SOC_RESET_CONTROL_SPI2_RST_LSB) +#define SOC_RESET_CONTROL_SPI2_RST_SET(x) (((x) << SOC_RESET_CONTROL_SPI2_RST_LSB) & SOC_RESET_CONTROL_SPI2_RST_MASK) +#define SOC_RESET_CONTROL_I2S_1_RST_MSB 29 +#define SOC_RESET_CONTROL_I2S_1_RST_LSB 29 +#define SOC_RESET_CONTROL_I2S_1_RST_MASK 0x20000000 +#define SOC_RESET_CONTROL_I2S_1_RST_GET(x) (((x) & SOC_RESET_CONTROL_I2S_1_RST_MASK) >> SOC_RESET_CONTROL_I2S_1_RST_LSB) +#define SOC_RESET_CONTROL_I2S_1_RST_SET(x) (((x) << SOC_RESET_CONTROL_I2S_1_RST_LSB) & SOC_RESET_CONTROL_I2S_1_RST_MASK) +#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_MSB 28 +#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB 28 +#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK 0x10000000 +#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_GET(x) (((x) & SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK) >> SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB) +#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_SET(x) (((x) << SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB) & SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK) +#define SOC_RESET_CONTROL_I2C_SLAVE_RST_MSB 27 +#define SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB 27 +#define SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK 0x08000000 +#define SOC_RESET_CONTROL_I2C_SLAVE_RST_GET(x) (((x) & SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK) >> SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB) +#define SOC_RESET_CONTROL_I2C_SLAVE_RST_SET(x) (((x) << SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB) & SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK) +#define SOC_RESET_CONTROL_USB_PHY_ARST_MSB 26 +#define SOC_RESET_CONTROL_USB_PHY_ARST_LSB 26 +#define SOC_RESET_CONTROL_USB_PHY_ARST_MASK 0x04000000 +#define SOC_RESET_CONTROL_USB_PHY_ARST_GET(x) (((x) & SOC_RESET_CONTROL_USB_PHY_ARST_MASK) >> SOC_RESET_CONTROL_USB_PHY_ARST_LSB) +#define SOC_RESET_CONTROL_USB_PHY_ARST_SET(x) (((x) << SOC_RESET_CONTROL_USB_PHY_ARST_LSB) & SOC_RESET_CONTROL_USB_PHY_ARST_MASK) +#define SOC_RESET_CONTROL_USB_PHY_RST_MSB 25 +#define SOC_RESET_CONTROL_USB_PHY_RST_LSB 25 +#define SOC_RESET_CONTROL_USB_PHY_RST_MASK 0x02000000 +#define SOC_RESET_CONTROL_USB_PHY_RST_GET(x) (((x) & SOC_RESET_CONTROL_USB_PHY_RST_MASK) >> SOC_RESET_CONTROL_USB_PHY_RST_LSB) +#define SOC_RESET_CONTROL_USB_PHY_RST_SET(x) (((x) << SOC_RESET_CONTROL_USB_PHY_RST_LSB) & SOC_RESET_CONTROL_USB_PHY_RST_MASK) +#define SOC_RESET_CONTROL_USB_RST_MSB 24 +#define SOC_RESET_CONTROL_USB_RST_LSB 24 +#define SOC_RESET_CONTROL_USB_RST_MASK 0x01000000 +#define SOC_RESET_CONTROL_USB_RST_GET(x) (((x) & SOC_RESET_CONTROL_USB_RST_MASK) >> SOC_RESET_CONTROL_USB_RST_LSB) +#define SOC_RESET_CONTROL_USB_RST_SET(x) (((x) << SOC_RESET_CONTROL_USB_RST_LSB) & SOC_RESET_CONTROL_USB_RST_MASK) +#define SOC_RESET_CONTROL_MMAC_RST_MSB 23 +#define SOC_RESET_CONTROL_MMAC_RST_LSB 23 +#define SOC_RESET_CONTROL_MMAC_RST_MASK 0x00800000 +#define SOC_RESET_CONTROL_MMAC_RST_GET(x) (((x) & SOC_RESET_CONTROL_MMAC_RST_MASK) >> SOC_RESET_CONTROL_MMAC_RST_LSB) +#define SOC_RESET_CONTROL_MMAC_RST_SET(x) (((x) << SOC_RESET_CONTROL_MMAC_RST_LSB) & SOC_RESET_CONTROL_MMAC_RST_MASK) +#define SOC_RESET_CONTROL_MDIO_RST_MSB 22 +#define SOC_RESET_CONTROL_MDIO_RST_LSB 22 +#define SOC_RESET_CONTROL_MDIO_RST_MASK 0x00400000 +#define SOC_RESET_CONTROL_MDIO_RST_GET(x) (((x) & SOC_RESET_CONTROL_MDIO_RST_MASK) >> SOC_RESET_CONTROL_MDIO_RST_LSB) +#define SOC_RESET_CONTROL_MDIO_RST_SET(x) (((x) << SOC_RESET_CONTROL_MDIO_RST_LSB) & SOC_RESET_CONTROL_MDIO_RST_MASK) +#define SOC_RESET_CONTROL_GE0_RST_MSB 21 +#define SOC_RESET_CONTROL_GE0_RST_LSB 21 +#define SOC_RESET_CONTROL_GE0_RST_MASK 0x00200000 +#define SOC_RESET_CONTROL_GE0_RST_GET(x) (((x) & SOC_RESET_CONTROL_GE0_RST_MASK) >> SOC_RESET_CONTROL_GE0_RST_LSB) +#define SOC_RESET_CONTROL_GE0_RST_SET(x) (((x) << SOC_RESET_CONTROL_GE0_RST_LSB) & SOC_RESET_CONTROL_GE0_RST_MASK) +#define SOC_RESET_CONTROL_I2S_RST_MSB 20 +#define SOC_RESET_CONTROL_I2S_RST_LSB 20 +#define SOC_RESET_CONTROL_I2S_RST_MASK 0x00100000 +#define SOC_RESET_CONTROL_I2S_RST_GET(x) (((x) & SOC_RESET_CONTROL_I2S_RST_MASK) >> SOC_RESET_CONTROL_I2S_RST_LSB) +#define SOC_RESET_CONTROL_I2S_RST_SET(x) (((x) << SOC_RESET_CONTROL_I2S_RST_LSB) & SOC_RESET_CONTROL_I2S_RST_MASK) +#define SOC_RESET_CONTROL_I2S_MBOX_RST_MSB 19 +#define SOC_RESET_CONTROL_I2S_MBOX_RST_LSB 19 +#define SOC_RESET_CONTROL_I2S_MBOX_RST_MASK 0x00080000 +#define SOC_RESET_CONTROL_I2S_MBOX_RST_GET(x) (((x) & SOC_RESET_CONTROL_I2S_MBOX_RST_MASK) >> SOC_RESET_CONTROL_I2S_MBOX_RST_LSB) +#define SOC_RESET_CONTROL_I2S_MBOX_RST_SET(x) (((x) << SOC_RESET_CONTROL_I2S_MBOX_RST_LSB) & SOC_RESET_CONTROL_I2S_MBOX_RST_MASK) +/* TODO: */ +#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MSB 18 +#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB 18 +#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK 0x00040000 +#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_GET(x) (((x) & SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK) >> SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB) +#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_SET(x) (((x) << SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB) & SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK) +#define SOC_RESET_CONTROL_CE_RST_MSB 18 +#define SOC_RESET_CONTROL_CE_RST_LSB 18 +#define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 +#define SOC_RESET_CONTROL_CE_RST_GET(x) (((x) & SOC_RESET_CONTROL_CE_RST_MASK) >> SOC_RESET_CONTROL_CE_RST_LSB) +#define SOC_RESET_CONTROL_CE_RST_SET(x) (((x) << SOC_RESET_CONTROL_CE_RST_LSB) & SOC_RESET_CONTROL_CE_RST_MASK) +#define SOC_RESET_CONTROL_UART2_RST_MSB 17 +#define SOC_RESET_CONTROL_UART2_RST_LSB 17 +#define SOC_RESET_CONTROL_UART2_RST_MASK 0x00020000 +#define SOC_RESET_CONTROL_UART2_RST_GET(x) (((x) & SOC_RESET_CONTROL_UART2_RST_MASK) >> SOC_RESET_CONTROL_UART2_RST_LSB) +#define SOC_RESET_CONTROL_UART2_RST_SET(x) (((x) << SOC_RESET_CONTROL_UART2_RST_LSB) & SOC_RESET_CONTROL_UART2_RST_MASK) +#define SOC_RESET_CONTROL_DEBUG_UART_RST_MSB 16 +#define SOC_RESET_CONTROL_DEBUG_UART_RST_LSB 16 +#define SOC_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00010000 +#define SOC_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & SOC_RESET_CONTROL_DEBUG_UART_RST_MASK) >> SOC_RESET_CONTROL_DEBUG_UART_RST_LSB) +#define SOC_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << SOC_RESET_CONTROL_DEBUG_UART_RST_LSB) & SOC_RESET_CONTROL_DEBUG_UART_RST_MASK) +#define SOC_RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define SOC_RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define SOC_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define SOC_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & SOC_RESET_CONTROL_CPU_INIT_RESET_MASK) >> SOC_RESET_CONTROL_CPU_INIT_RESET_LSB) +#define SOC_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << SOC_RESET_CONTROL_CPU_INIT_RESET_LSB) & SOC_RESET_CONTROL_CPU_INIT_RESET_MASK) +#define SOC_RESET_CONTROL_RST_OUT_MSB 9 +#define SOC_RESET_CONTROL_RST_OUT_LSB 9 +#define SOC_RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define SOC_RESET_CONTROL_RST_OUT_GET(x) (((x) & SOC_RESET_CONTROL_RST_OUT_MASK) >> SOC_RESET_CONTROL_RST_OUT_LSB) +#define SOC_RESET_CONTROL_RST_OUT_SET(x) (((x) << SOC_RESET_CONTROL_RST_OUT_LSB) & SOC_RESET_CONTROL_RST_OUT_MASK) +#define SOC_RESET_CONTROL_COLD_RST_MSB 8 +#define SOC_RESET_CONTROL_COLD_RST_LSB 8 +#define SOC_RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define SOC_RESET_CONTROL_COLD_RST_GET(x) (((x) & SOC_RESET_CONTROL_COLD_RST_MASK) >> SOC_RESET_CONTROL_COLD_RST_LSB) +#define SOC_RESET_CONTROL_COLD_RST_SET(x) (((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & SOC_RESET_CONTROL_COLD_RST_MASK) +#define SOC_RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define SOC_RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define SOC_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK) >> SOC_RESET_CONTROL_CPU_WARM_RST_LSB) +#define SOC_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << SOC_RESET_CONTROL_CPU_WARM_RST_LSB) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK) +/* TODO: */ +#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MSB 2 +#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2 +#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004 +#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) +#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) +#define SOC_RESET_CONTROL_MBOX_RST_MSB 2 +#define SOC_RESET_CONTROL_MBOX_RST_LSB 2 +#define SOC_RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define SOC_RESET_CONTROL_MBOX_RST_GET(x) (((x) & SOC_RESET_CONTROL_MBOX_RST_MASK) >> SOC_RESET_CONTROL_MBOX_RST_LSB) +#define SOC_RESET_CONTROL_MBOX_RST_SET(x) (((x) << SOC_RESET_CONTROL_MBOX_RST_LSB) & SOC_RESET_CONTROL_MBOX_RST_MASK) +#define SOC_RESET_CONTROL_UART_RST_MSB 1 +#define SOC_RESET_CONTROL_UART_RST_LSB 1 +#define SOC_RESET_CONTROL_UART_RST_MASK 0x00000002 +#define SOC_RESET_CONTROL_UART_RST_GET(x) (((x) & SOC_RESET_CONTROL_UART_RST_MASK) >> SOC_RESET_CONTROL_UART_RST_LSB) +#define SOC_RESET_CONTROL_UART_RST_SET(x) (((x) << SOC_RESET_CONTROL_UART_RST_LSB) & SOC_RESET_CONTROL_UART_RST_MASK) +#define SOC_RESET_CONTROL_SI0_RST_MSB 0 +#define SOC_RESET_CONTROL_SI0_RST_LSB 0 +#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define SOC_RESET_CONTROL_SI0_RST_GET(x) (((x) & SOC_RESET_CONTROL_SI0_RST_MASK) >> SOC_RESET_CONTROL_SI0_RST_LSB) +#define SOC_RESET_CONTROL_SI0_RST_SET(x) (((x) << SOC_RESET_CONTROL_SI0_RST_LSB) & SOC_RESET_CONTROL_SI0_RST_MASK) + +#define SOC_TCXO_DETECT_ADDRESS 0x00000004 +#define SOC_TCXO_DETECT_OFFSET 0x00000004 +#define SOC_TCXO_DETECT_PRESENT_MSB 0 +#define SOC_TCXO_DETECT_PRESENT_LSB 0 +#define SOC_TCXO_DETECT_PRESENT_MASK 0x00000001 +#define SOC_TCXO_DETECT_PRESENT_GET(x) (((x) & SOC_TCXO_DETECT_PRESENT_MASK) >> SOC_TCXO_DETECT_PRESENT_LSB) +#define SOC_TCXO_DETECT_PRESENT_SET(x) (((x) << SOC_TCXO_DETECT_PRESENT_LSB) & SOC_TCXO_DETECT_PRESENT_MASK) + +#define SOC_XTAL_TEST_ADDRESS 0x00000008 +#define SOC_XTAL_TEST_OFFSET 0x00000008 +#define SOC_XTAL_TEST_NOTCXODET_MSB 0 +#define SOC_XTAL_TEST_NOTCXODET_LSB 0 +#define SOC_XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define SOC_XTAL_TEST_NOTCXODET_GET(x) (((x) & SOC_XTAL_TEST_NOTCXODET_MASK) >> SOC_XTAL_TEST_NOTCXODET_LSB) +#define SOC_XTAL_TEST_NOTCXODET_SET(x) (((x) << SOC_XTAL_TEST_NOTCXODET_LSB) & SOC_XTAL_TEST_NOTCXODET_MASK) + +#define SOC_CPU_CLOCK_ADDRESS 0x00000020 +#define SOC_CPU_CLOCK_OFFSET 0x00000020 +#define SOC_CPU_CLOCK_STANDARD_MSB 1 +#define SOC_CPU_CLOCK_STANDARD_LSB 0 +#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 +#define SOC_CPU_CLOCK_STANDARD_GET(x) (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) +#define SOC_CPU_CLOCK_STANDARD_SET(x) (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) + +#define SOC_CLOCK_CONTROL_ADDRESS 0x00000028 +#define SOC_CLOCK_CONTROL_OFFSET 0x00000028 +#define SOC_CLOCK_CONTROL_USB_CLOCK_MSB 3 +#define SOC_CLOCK_CONTROL_USB_CLOCK_LSB 3 +#define SOC_CLOCK_CONTROL_USB_CLOCK_MASK 0x00000008 +#define SOC_CLOCK_CONTROL_USB_CLOCK_GET(x) (((x) & SOC_CLOCK_CONTROL_USB_CLOCK_MASK) >> SOC_CLOCK_CONTROL_USB_CLOCK_LSB) +#define SOC_CLOCK_CONTROL_USB_CLOCK_SET(x) (((x) << SOC_CLOCK_CONTROL_USB_CLOCK_LSB) & SOC_CLOCK_CONTROL_USB_CLOCK_MASK) +#define SOC_CLOCK_CONTROL_LF_CLK32_MSB 2 +#define SOC_CLOCK_CONTROL_LF_CLK32_LSB 2 +#define SOC_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define SOC_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & SOC_CLOCK_CONTROL_LF_CLK32_MASK) >> SOC_CLOCK_CONTROL_LF_CLK32_LSB) +#define SOC_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << SOC_CLOCK_CONTROL_LF_CLK32_LSB) & SOC_CLOCK_CONTROL_LF_CLK32_MASK) +#define SOC_CLOCK_CONTROL_SI0_CLK_MSB 0 +#define SOC_CLOCK_CONTROL_SI0_CLK_LSB 0 +#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define SOC_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & SOC_CLOCK_CONTROL_SI0_CLK_MASK) >> SOC_CLOCK_CONTROL_SI0_CLK_LSB) +#define SOC_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << SOC_CLOCK_CONTROL_SI0_CLK_LSB) & SOC_CLOCK_CONTROL_SI0_CLK_MASK) + +#define SOC_WDT_CONTROL_ADDRESS 0x00000030 +#define SOC_WDT_CONTROL_OFFSET 0x00000030 +#define SOC_WDT_CONTROL_ACTION_MSB 2 +#define SOC_WDT_CONTROL_ACTION_LSB 0 +#define SOC_WDT_CONTROL_ACTION_MASK 0x00000007 +#define SOC_WDT_CONTROL_ACTION_GET(x) (((x) & SOC_WDT_CONTROL_ACTION_MASK) >> SOC_WDT_CONTROL_ACTION_LSB) +#define SOC_WDT_CONTROL_ACTION_SET(x) (((x) << SOC_WDT_CONTROL_ACTION_LSB) & SOC_WDT_CONTROL_ACTION_MASK) + +#define SOC_WDT_STATUS_ADDRESS 0x00000034 +#define SOC_WDT_STATUS_OFFSET 0x00000034 +#define SOC_WDT_STATUS_INTERRUPT_MSB 0 +#define SOC_WDT_STATUS_INTERRUPT_LSB 0 +#define SOC_WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define SOC_WDT_STATUS_INTERRUPT_GET(x) (((x) & SOC_WDT_STATUS_INTERRUPT_MASK) >> SOC_WDT_STATUS_INTERRUPT_LSB) +#define SOC_WDT_STATUS_INTERRUPT_SET(x) (((x) << SOC_WDT_STATUS_INTERRUPT_LSB) & SOC_WDT_STATUS_INTERRUPT_MASK) + +#define SOC_WDT_ADDRESS 0x00000038 +#define SOC_WDT_OFFSET 0x00000038 +#define SOC_WDT_TARGET_MSB 21 +#define SOC_WDT_TARGET_LSB 0 +#define SOC_WDT_TARGET_MASK 0x003fffff +#define SOC_WDT_TARGET_GET(x) (((x) & SOC_WDT_TARGET_MASK) >> SOC_WDT_TARGET_LSB) +#define SOC_WDT_TARGET_SET(x) (((x) << SOC_WDT_TARGET_LSB) & SOC_WDT_TARGET_MASK) + +#define SOC_WDT_COUNT_ADDRESS 0x0000003c +#define SOC_WDT_COUNT_OFFSET 0x0000003c +#define SOC_WDT_COUNT_VALUE_MSB 21 +#define SOC_WDT_COUNT_VALUE_LSB 0 +#define SOC_WDT_COUNT_VALUE_MASK 0x003fffff +#define SOC_WDT_COUNT_VALUE_GET(x) (((x) & SOC_WDT_COUNT_VALUE_MASK) >> SOC_WDT_COUNT_VALUE_LSB) +#define SOC_WDT_COUNT_VALUE_SET(x) (((x) << SOC_WDT_COUNT_VALUE_LSB) & SOC_WDT_COUNT_VALUE_MASK) + +#define SOC_WDT_RESET_ADDRESS 0x00000040 +#define SOC_WDT_RESET_OFFSET 0x00000040 +#define SOC_WDT_RESET_VALUE_MSB 0 +#define SOC_WDT_RESET_VALUE_LSB 0 +#define SOC_WDT_RESET_VALUE_MASK 0x00000001 +#define SOC_WDT_RESET_VALUE_GET(x) (((x) & SOC_WDT_RESET_VALUE_MASK) >> SOC_WDT_RESET_VALUE_LSB) +#define SOC_WDT_RESET_VALUE_SET(x) (((x) << SOC_WDT_RESET_VALUE_LSB) & SOC_WDT_RESET_VALUE_MASK) + +#define SOC_INT_STATUS_ADDRESS 0x00000044 +#define SOC_INT_STATUS_OFFSET 0x00000044 +#define SOC_INT_STATUS_MAC_4_MSB 23 +#define SOC_INT_STATUS_MAC_4_LSB 23 +#define SOC_INT_STATUS_MAC_4_MASK 0x00800000 +#define SOC_INT_STATUS_MAC_4_GET(x) (((x) & SOC_INT_STATUS_MAC_4_MASK) >> SOC_INT_STATUS_MAC_4_LSB) +#define SOC_INT_STATUS_MAC_4_SET(x) (((x) << SOC_INT_STATUS_MAC_4_LSB) & SOC_INT_STATUS_MAC_4_MASK) +#define SOC_INT_STATUS_MAC_3_MSB 22 +#define SOC_INT_STATUS_MAC_3_LSB 22 +#define SOC_INT_STATUS_MAC_3_MASK 0x00400000 +#define SOC_INT_STATUS_MAC_3_GET(x) (((x) & SOC_INT_STATUS_MAC_3_MASK) >> SOC_INT_STATUS_MAC_3_LSB) +#define SOC_INT_STATUS_MAC_3_SET(x) (((x) << SOC_INT_STATUS_MAC_3_LSB) & SOC_INT_STATUS_MAC_3_MASK) +#define SOC_INT_STATUS_MAC_2_MSB 21 +#define SOC_INT_STATUS_MAC_2_LSB 21 +#define SOC_INT_STATUS_MAC_2_MASK 0x00200000 +#define SOC_INT_STATUS_MAC_2_GET(x) (((x) & SOC_INT_STATUS_MAC_2_MASK) >> SOC_INT_STATUS_MAC_2_LSB) +#define SOC_INT_STATUS_MAC_2_SET(x) (((x) << SOC_INT_STATUS_MAC_2_LSB) & SOC_INT_STATUS_MAC_2_MASK) +#define SOC_INT_STATUS_MAC_1_MSB 20 +#define SOC_INT_STATUS_MAC_1_LSB 20 +#define SOC_INT_STATUS_MAC_1_MASK 0x00100000 +#define SOC_INT_STATUS_MAC_1_GET(x) (((x) & SOC_INT_STATUS_MAC_1_MASK) >> SOC_INT_STATUS_MAC_1_LSB) +#define SOC_INT_STATUS_MAC_1_SET(x) (((x) << SOC_INT_STATUS_MAC_1_LSB) & SOC_INT_STATUS_MAC_1_MASK) +#define SOC_INT_STATUS_USBDMA_MSB 19 +#define SOC_INT_STATUS_USBDMA_LSB 19 +#define SOC_INT_STATUS_USBDMA_MASK 0x00080000 +#define SOC_INT_STATUS_USBDMA_GET(x) (((x) & SOC_INT_STATUS_USBDMA_MASK) >> SOC_INT_STATUS_USBDMA_LSB) +#define SOC_INT_STATUS_USBDMA_SET(x) (((x) << SOC_INT_STATUS_USBDMA_LSB) & SOC_INT_STATUS_USBDMA_MASK) +#define SOC_INT_STATUS_USBIP_MSB 18 +#define SOC_INT_STATUS_USBIP_LSB 18 +#define SOC_INT_STATUS_USBIP_MASK 0x00040000 +#define SOC_INT_STATUS_USBIP_GET(x) (((x) & SOC_INT_STATUS_USBIP_MASK) >> SOC_INT_STATUS_USBIP_LSB) +#define SOC_INT_STATUS_USBIP_SET(x) (((x) << SOC_INT_STATUS_USBIP_LSB) & SOC_INT_STATUS_USBIP_MASK) +#define SOC_INT_STATUS_THERM_MSB 17 +#define SOC_INT_STATUS_THERM_LSB 17 +#define SOC_INT_STATUS_THERM_MASK 0x00020000 +#define SOC_INT_STATUS_THERM_GET(x) (((x) & SOC_INT_STATUS_THERM_MASK) >> SOC_INT_STATUS_THERM_LSB) +#define SOC_INT_STATUS_THERM_SET(x) (((x) << SOC_INT_STATUS_THERM_LSB) & SOC_INT_STATUS_THERM_MASK) +#define SOC_INT_STATUS_EFUSE_OVERWRITE_MSB 16 +#define SOC_INT_STATUS_EFUSE_OVERWRITE_LSB 16 +#define SOC_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00010000 +#define SOC_INT_STATUS_EFUSE_OVERWRITE_GET(x) (((x) & SOC_INT_STATUS_EFUSE_OVERWRITE_MASK) >> SOC_INT_STATUS_EFUSE_OVERWRITE_LSB) +#define SOC_INT_STATUS_EFUSE_OVERWRITE_SET(x) (((x) << SOC_INT_STATUS_EFUSE_OVERWRITE_LSB) & SOC_INT_STATUS_EFUSE_OVERWRITE_MASK) +#define SOC_INT_STATUS_RDMA_MSB 15 +#define SOC_INT_STATUS_RDMA_LSB 15 +#define SOC_INT_STATUS_RDMA_MASK 0x00008000 +#define SOC_INT_STATUS_RDMA_GET(x) (((x) & SOC_INT_STATUS_RDMA_MASK) >> SOC_INT_STATUS_RDMA_LSB) +#define SOC_INT_STATUS_RDMA_SET(x) (((x) << SOC_INT_STATUS_RDMA_LSB) & SOC_INT_STATUS_RDMA_MASK) +#define SOC_INT_STATUS_BTCOEX_MSB 14 +#define SOC_INT_STATUS_BTCOEX_LSB 14 +#define SOC_INT_STATUS_BTCOEX_MASK 0x00004000 +#define SOC_INT_STATUS_BTCOEX_GET(x) (((x) & SOC_INT_STATUS_BTCOEX_MASK) >> SOC_INT_STATUS_BTCOEX_LSB) +#define SOC_INT_STATUS_BTCOEX_SET(x) (((x) << SOC_INT_STATUS_BTCOEX_LSB) & SOC_INT_STATUS_BTCOEX_MASK) +#define SOC_INT_STATUS_RTC_POWER_MSB 13 +#define SOC_INT_STATUS_RTC_POWER_LSB 13 +#define SOC_INT_STATUS_RTC_POWER_MASK 0x00002000 +#define SOC_INT_STATUS_RTC_POWER_GET(x) (((x) & SOC_INT_STATUS_RTC_POWER_MASK) >> SOC_INT_STATUS_RTC_POWER_LSB) +#define SOC_INT_STATUS_RTC_POWER_SET(x) (((x) << SOC_INT_STATUS_RTC_POWER_LSB) & SOC_INT_STATUS_RTC_POWER_MASK) +#define SOC_INT_STATUS_MAC_MSB 12 +#define SOC_INT_STATUS_MAC_LSB 12 +#define SOC_INT_STATUS_MAC_MASK 0x00001000 +#define SOC_INT_STATUS_MAC_GET(x) (((x) & SOC_INT_STATUS_MAC_MASK) >> SOC_INT_STATUS_MAC_LSB) +#define SOC_INT_STATUS_MAC_SET(x) (((x) << SOC_INT_STATUS_MAC_LSB) & SOC_INT_STATUS_MAC_MASK) +#define SOC_INT_STATUS_MAILBOX_MSB 11 +#define SOC_INT_STATUS_MAILBOX_LSB 11 +#define SOC_INT_STATUS_MAILBOX_MASK 0x00000800 +#define SOC_INT_STATUS_MAILBOX_GET(x) (((x) & SOC_INT_STATUS_MAILBOX_MASK) >> SOC_INT_STATUS_MAILBOX_LSB) +#define SOC_INT_STATUS_MAILBOX_SET(x) (((x) << SOC_INT_STATUS_MAILBOX_LSB) & SOC_INT_STATUS_MAILBOX_MASK) +#define SOC_INT_STATUS_RTC_ALARM_MSB 10 +#define SOC_INT_STATUS_RTC_ALARM_LSB 10 +#define SOC_INT_STATUS_RTC_ALARM_MASK 0x00000400 +#define SOC_INT_STATUS_RTC_ALARM_GET(x) (((x) & SOC_INT_STATUS_RTC_ALARM_MASK) >> SOC_INT_STATUS_RTC_ALARM_LSB) +#define SOC_INT_STATUS_RTC_ALARM_SET(x) (((x) << SOC_INT_STATUS_RTC_ALARM_LSB) & SOC_INT_STATUS_RTC_ALARM_MASK) +#define SOC_INT_STATUS_HF_TIMER_MSB 9 +#define SOC_INT_STATUS_HF_TIMER_LSB 9 +#define SOC_INT_STATUS_HF_TIMER_MASK 0x00000200 +#define SOC_INT_STATUS_HF_TIMER_GET(x) (((x) & SOC_INT_STATUS_HF_TIMER_MASK) >> SOC_INT_STATUS_HF_TIMER_LSB) +#define SOC_INT_STATUS_HF_TIMER_SET(x) (((x) << SOC_INT_STATUS_HF_TIMER_LSB) & SOC_INT_STATUS_HF_TIMER_MASK) +#define SOC_INT_STATUS_LF_TIMER3_MSB 8 +#define SOC_INT_STATUS_LF_TIMER3_LSB 8 +#define SOC_INT_STATUS_LF_TIMER3_MASK 0x00000100 +#define SOC_INT_STATUS_LF_TIMER3_GET(x) (((x) & SOC_INT_STATUS_LF_TIMER3_MASK) >> SOC_INT_STATUS_LF_TIMER3_LSB) +#define SOC_INT_STATUS_LF_TIMER3_SET(x) (((x) << SOC_INT_STATUS_LF_TIMER3_LSB) & SOC_INT_STATUS_LF_TIMER3_MASK) +#define SOC_INT_STATUS_LF_TIMER2_MSB 7 +#define SOC_INT_STATUS_LF_TIMER2_LSB 7 +#define SOC_INT_STATUS_LF_TIMER2_MASK 0x00000080 +#define SOC_INT_STATUS_LF_TIMER2_GET(x) (((x) & SOC_INT_STATUS_LF_TIMER2_MASK) >> SOC_INT_STATUS_LF_TIMER2_LSB) +#define SOC_INT_STATUS_LF_TIMER2_SET(x) (((x) << SOC_INT_STATUS_LF_TIMER2_LSB) & SOC_INT_STATUS_LF_TIMER2_MASK) +#define SOC_INT_STATUS_LF_TIMER1_MSB 6 +#define SOC_INT_STATUS_LF_TIMER1_LSB 6 +#define SOC_INT_STATUS_LF_TIMER1_MASK 0x00000040 +#define SOC_INT_STATUS_LF_TIMER1_GET(x) (((x) & SOC_INT_STATUS_LF_TIMER1_MASK) >> SOC_INT_STATUS_LF_TIMER1_LSB) +#define SOC_INT_STATUS_LF_TIMER1_SET(x) (((x) << SOC_INT_STATUS_LF_TIMER1_LSB) & SOC_INT_STATUS_LF_TIMER1_MASK) +#define SOC_INT_STATUS_LF_TIMER0_MSB 5 +#define SOC_INT_STATUS_LF_TIMER0_LSB 5 +#define SOC_INT_STATUS_LF_TIMER0_MASK 0x00000020 +#define SOC_INT_STATUS_LF_TIMER0_GET(x) (((x) & SOC_INT_STATUS_LF_TIMER0_MASK) >> SOC_INT_STATUS_LF_TIMER0_LSB) +#define SOC_INT_STATUS_LF_TIMER0_SET(x) (((x) << SOC_INT_STATUS_LF_TIMER0_LSB) & SOC_INT_STATUS_LF_TIMER0_MASK) +#define SOC_INT_STATUS_SI_MSB 4 +#define SOC_INT_STATUS_SI_LSB 4 +#define SOC_INT_STATUS_SI_MASK 0x00000010 +#define SOC_INT_STATUS_SI_GET(x) (((x) & SOC_INT_STATUS_SI_MASK) >> SOC_INT_STATUS_SI_LSB) +#define SOC_INT_STATUS_SI_SET(x) (((x) << SOC_INT_STATUS_SI_LSB) & SOC_INT_STATUS_SI_MASK) +#define SOC_INT_STATUS_GPIO_MSB 3 +#define SOC_INT_STATUS_GPIO_LSB 3 +#define SOC_INT_STATUS_GPIO_MASK 0x00000008 +#define SOC_INT_STATUS_GPIO_GET(x) (((x) & SOC_INT_STATUS_GPIO_MASK) >> SOC_INT_STATUS_GPIO_LSB) +#define SOC_INT_STATUS_GPIO_SET(x) (((x) << SOC_INT_STATUS_GPIO_LSB) & SOC_INT_STATUS_GPIO_MASK) +#define SOC_INT_STATUS_DEBUG_UART_MSB 2 +#define SOC_INT_STATUS_DEBUG_UART_LSB 2 +#define SOC_INT_STATUS_DEBUG_UART_MASK 0x00000004 +#define SOC_INT_STATUS_DEBUG_UART_GET(x) (((x) & SOC_INT_STATUS_DEBUG_UART_MASK) >> SOC_INT_STATUS_DEBUG_UART_LSB) +#define SOC_INT_STATUS_DEBUG_UART_SET(x) (((x) << SOC_INT_STATUS_DEBUG_UART_LSB) & SOC_INT_STATUS_DEBUG_UART_MASK) +#define SOC_INT_STATUS_ERROR_MSB 1 +#define SOC_INT_STATUS_ERROR_LSB 1 +#define SOC_INT_STATUS_ERROR_MASK 0x00000002 +#define SOC_INT_STATUS_ERROR_GET(x) (((x) & SOC_INT_STATUS_ERROR_MASK) >> SOC_INT_STATUS_ERROR_LSB) +#define SOC_INT_STATUS_ERROR_SET(x) (((x) << SOC_INT_STATUS_ERROR_LSB) & SOC_INT_STATUS_ERROR_MASK) +#define SOC_INT_STATUS_WDT_INT_MSB 0 +#define SOC_INT_STATUS_WDT_INT_LSB 0 +#define SOC_INT_STATUS_WDT_INT_MASK 0x00000001 +#define SOC_INT_STATUS_WDT_INT_GET(x) (((x) & SOC_INT_STATUS_WDT_INT_MASK) >> SOC_INT_STATUS_WDT_INT_LSB) +#define SOC_INT_STATUS_WDT_INT_SET(x) (((x) << SOC_INT_STATUS_WDT_INT_LSB) & SOC_INT_STATUS_WDT_INT_MASK) + +#define SOC_LF_TIMER0_ADDRESS 0x00000048 +#define SOC_LF_TIMER0_OFFSET 0x00000048 +#define SOC_LF_TIMER0_TARGET_MSB 31 +#define SOC_LF_TIMER0_TARGET_LSB 0 +#define SOC_LF_TIMER0_TARGET_MASK 0xffffffff +#define SOC_LF_TIMER0_TARGET_GET(x) (((x) & SOC_LF_TIMER0_TARGET_MASK) >> SOC_LF_TIMER0_TARGET_LSB) +#define SOC_LF_TIMER0_TARGET_SET(x) (((x) << SOC_LF_TIMER0_TARGET_LSB) & SOC_LF_TIMER0_TARGET_MASK) + +#define SOC_LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define SOC_LF_TIMER_COUNT0_OFFSET 0x0000004c +#define SOC_LF_TIMER_COUNT0_VALUE_MSB 31 +#define SOC_LF_TIMER_COUNT0_VALUE_LSB 0 +#define SOC_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define SOC_LF_TIMER_COUNT0_VALUE_GET(x) (((x) & SOC_LF_TIMER_COUNT0_VALUE_MASK) >> SOC_LF_TIMER_COUNT0_VALUE_LSB) +#define SOC_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << SOC_LF_TIMER_COUNT0_VALUE_LSB) & SOC_LF_TIMER_COUNT0_VALUE_MASK) + +#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define SOC_LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define SOC_LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define SOC_LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define SOC_LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & SOC_LF_TIMER_CONTROL0_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL0_ENABLE_LSB) +#define SOC_LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << SOC_LF_TIMER_CONTROL0_ENABLE_LSB) & SOC_LF_TIMER_CONTROL0_ENABLE_MASK) +#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define SOC_LF_TIMER_CONTROL0_RESET_MSB 0 +#define SOC_LF_TIMER_CONTROL0_RESET_LSB 0 +#define SOC_LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define SOC_LF_TIMER_CONTROL0_RESET_GET(x) (((x) & SOC_LF_TIMER_CONTROL0_RESET_MASK) >> SOC_LF_TIMER_CONTROL0_RESET_LSB) +#define SOC_LF_TIMER_CONTROL0_RESET_SET(x) (((x) << SOC_LF_TIMER_CONTROL0_RESET_LSB) & SOC_LF_TIMER_CONTROL0_RESET_MASK) + +#define SOC_LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define SOC_LF_TIMER_STATUS0_OFFSET 0x00000054 +#define SOC_LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define SOC_LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define SOC_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define SOC_LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & SOC_LF_TIMER_STATUS0_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS0_INTERRUPT_LSB) +#define SOC_LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << SOC_LF_TIMER_STATUS0_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define SOC_LF_TIMER1_ADDRESS 0x00000058 +#define SOC_LF_TIMER1_OFFSET 0x00000058 +#define SOC_LF_TIMER1_TARGET_MSB 31 +#define SOC_LF_TIMER1_TARGET_LSB 0 +#define SOC_LF_TIMER1_TARGET_MASK 0xffffffff +#define SOC_LF_TIMER1_TARGET_GET(x) (((x) & SOC_LF_TIMER1_TARGET_MASK) >> SOC_LF_TIMER1_TARGET_LSB) +#define SOC_LF_TIMER1_TARGET_SET(x) (((x) << SOC_LF_TIMER1_TARGET_LSB) & SOC_LF_TIMER1_TARGET_MASK) + +#define SOC_LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define SOC_LF_TIMER_COUNT1_OFFSET 0x0000005c +#define SOC_LF_TIMER_COUNT1_VALUE_MSB 31 +#define SOC_LF_TIMER_COUNT1_VALUE_LSB 0 +#define SOC_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define SOC_LF_TIMER_COUNT1_VALUE_GET(x) (((x) & SOC_LF_TIMER_COUNT1_VALUE_MASK) >> SOC_LF_TIMER_COUNT1_VALUE_LSB) +#define SOC_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << SOC_LF_TIMER_COUNT1_VALUE_LSB) & SOC_LF_TIMER_COUNT1_VALUE_MASK) + +#define SOC_LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define SOC_LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define SOC_LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define SOC_LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define SOC_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define SOC_LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & SOC_LF_TIMER_CONTROL1_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL1_ENABLE_LSB) +#define SOC_LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << SOC_LF_TIMER_CONTROL1_ENABLE_LSB) & SOC_LF_TIMER_CONTROL1_ENABLE_MASK) +#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define SOC_LF_TIMER_CONTROL1_RESET_MSB 0 +#define SOC_LF_TIMER_CONTROL1_RESET_LSB 0 +#define SOC_LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define SOC_LF_TIMER_CONTROL1_RESET_GET(x) (((x) & SOC_LF_TIMER_CONTROL1_RESET_MASK) >> SOC_LF_TIMER_CONTROL1_RESET_LSB) +#define SOC_LF_TIMER_CONTROL1_RESET_SET(x) (((x) << SOC_LF_TIMER_CONTROL1_RESET_LSB) & SOC_LF_TIMER_CONTROL1_RESET_MASK) + +#define SOC_LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define SOC_LF_TIMER_STATUS1_OFFSET 0x00000064 +#define SOC_LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define SOC_LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define SOC_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define SOC_LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & SOC_LF_TIMER_STATUS1_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS1_INTERRUPT_LSB) +#define SOC_LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << SOC_LF_TIMER_STATUS1_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define SOC_LF_TIMER2_ADDRESS 0x00000068 +#define SOC_LF_TIMER2_OFFSET 0x00000068 +#define SOC_LF_TIMER2_TARGET_MSB 31 +#define SOC_LF_TIMER2_TARGET_LSB 0 +#define SOC_LF_TIMER2_TARGET_MASK 0xffffffff +#define SOC_LF_TIMER2_TARGET_GET(x) (((x) & SOC_LF_TIMER2_TARGET_MASK) >> SOC_LF_TIMER2_TARGET_LSB) +#define SOC_LF_TIMER2_TARGET_SET(x) (((x) << SOC_LF_TIMER2_TARGET_LSB) & SOC_LF_TIMER2_TARGET_MASK) + +#define SOC_LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define SOC_LF_TIMER_COUNT2_OFFSET 0x0000006c +#define SOC_LF_TIMER_COUNT2_VALUE_MSB 31 +#define SOC_LF_TIMER_COUNT2_VALUE_LSB 0 +#define SOC_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define SOC_LF_TIMER_COUNT2_VALUE_GET(x) (((x) & SOC_LF_TIMER_COUNT2_VALUE_MASK) >> SOC_LF_TIMER_COUNT2_VALUE_LSB) +#define SOC_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << SOC_LF_TIMER_COUNT2_VALUE_LSB) & SOC_LF_TIMER_COUNT2_VALUE_MASK) + +#define SOC_LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define SOC_LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define SOC_LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define SOC_LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define SOC_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define SOC_LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & SOC_LF_TIMER_CONTROL2_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL2_ENABLE_LSB) +#define SOC_LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << SOC_LF_TIMER_CONTROL2_ENABLE_LSB) & SOC_LF_TIMER_CONTROL2_ENABLE_MASK) +#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define SOC_LF_TIMER_CONTROL2_RESET_MSB 0 +#define SOC_LF_TIMER_CONTROL2_RESET_LSB 0 +#define SOC_LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define SOC_LF_TIMER_CONTROL2_RESET_GET(x) (((x) & SOC_LF_TIMER_CONTROL2_RESET_MASK) >> SOC_LF_TIMER_CONTROL2_RESET_LSB) +#define SOC_LF_TIMER_CONTROL2_RESET_SET(x) (((x) << SOC_LF_TIMER_CONTROL2_RESET_LSB) & SOC_LF_TIMER_CONTROL2_RESET_MASK) + +#define SOC_LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define SOC_LF_TIMER_STATUS2_OFFSET 0x00000074 +#define SOC_LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define SOC_LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define SOC_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define SOC_LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & SOC_LF_TIMER_STATUS2_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS2_INTERRUPT_LSB) +#define SOC_LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << SOC_LF_TIMER_STATUS2_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define SOC_LF_TIMER3_ADDRESS 0x00000078 +#define SOC_LF_TIMER3_OFFSET 0x00000078 +#define SOC_LF_TIMER3_TARGET_MSB 31 +#define SOC_LF_TIMER3_TARGET_LSB 0 +#define SOC_LF_TIMER3_TARGET_MASK 0xffffffff +#define SOC_LF_TIMER3_TARGET_GET(x) (((x) & SOC_LF_TIMER3_TARGET_MASK) >> SOC_LF_TIMER3_TARGET_LSB) +#define SOC_LF_TIMER3_TARGET_SET(x) (((x) << SOC_LF_TIMER3_TARGET_LSB) & SOC_LF_TIMER3_TARGET_MASK) + +#define SOC_LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define SOC_LF_TIMER_COUNT3_OFFSET 0x0000007c +#define SOC_LF_TIMER_COUNT3_VALUE_MSB 31 +#define SOC_LF_TIMER_COUNT3_VALUE_LSB 0 +#define SOC_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define SOC_LF_TIMER_COUNT3_VALUE_GET(x) (((x) & SOC_LF_TIMER_COUNT3_VALUE_MASK) >> SOC_LF_TIMER_COUNT3_VALUE_LSB) +#define SOC_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << SOC_LF_TIMER_COUNT3_VALUE_LSB) & SOC_LF_TIMER_COUNT3_VALUE_MASK) + +#define SOC_LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define SOC_LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define SOC_LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define SOC_LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define SOC_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define SOC_LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & SOC_LF_TIMER_CONTROL3_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL3_ENABLE_LSB) +#define SOC_LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << SOC_LF_TIMER_CONTROL3_ENABLE_LSB) & SOC_LF_TIMER_CONTROL3_ENABLE_MASK) +#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define SOC_LF_TIMER_CONTROL3_RESET_MSB 0 +#define SOC_LF_TIMER_CONTROL3_RESET_LSB 0 +#define SOC_LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define SOC_LF_TIMER_CONTROL3_RESET_GET(x) (((x) & SOC_LF_TIMER_CONTROL3_RESET_MASK) >> SOC_LF_TIMER_CONTROL3_RESET_LSB) +#define SOC_LF_TIMER_CONTROL3_RESET_SET(x) (((x) << SOC_LF_TIMER_CONTROL3_RESET_LSB) & SOC_LF_TIMER_CONTROL3_RESET_MASK) + +#define SOC_LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define SOC_LF_TIMER_STATUS3_OFFSET 0x00000084 +#define SOC_LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define SOC_LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define SOC_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define SOC_LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & SOC_LF_TIMER_STATUS3_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS3_INTERRUPT_LSB) +#define SOC_LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << SOC_LF_TIMER_STATUS3_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define SOC_HF_TIMER_ADDRESS 0x00000088 +#define SOC_HF_TIMER_OFFSET 0x00000088 +#define SOC_HF_TIMER_TARGET_MSB 31 +#define SOC_HF_TIMER_TARGET_LSB 12 +#define SOC_HF_TIMER_TARGET_MASK 0xfffff000 +#define SOC_HF_TIMER_TARGET_GET(x) (((x) & SOC_HF_TIMER_TARGET_MASK) >> SOC_HF_TIMER_TARGET_LSB) +#define SOC_HF_TIMER_TARGET_SET(x) (((x) << SOC_HF_TIMER_TARGET_LSB) & SOC_HF_TIMER_TARGET_MASK) + +#define SOC_HF_TIMER_COUNT_ADDRESS 0x0000008c +#define SOC_HF_TIMER_COUNT_OFFSET 0x0000008c +#define SOC_HF_TIMER_COUNT_VALUE_MSB 31 +#define SOC_HF_TIMER_COUNT_VALUE_LSB 12 +#define SOC_HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define SOC_HF_TIMER_COUNT_VALUE_GET(x) (((x) & SOC_HF_TIMER_COUNT_VALUE_MASK) >> SOC_HF_TIMER_COUNT_VALUE_LSB) +#define SOC_HF_TIMER_COUNT_VALUE_SET(x) (((x) << SOC_HF_TIMER_COUNT_VALUE_LSB) & SOC_HF_TIMER_COUNT_VALUE_MASK) + +#define SOC_HF_LF_COUNT_ADDRESS 0x00000090 +#define SOC_HF_LF_COUNT_OFFSET 0x00000090 +#define SOC_HF_LF_COUNT_VALUE_MSB 31 +#define SOC_HF_LF_COUNT_VALUE_LSB 0 +#define SOC_HF_LF_COUNT_VALUE_MASK 0xffffffff +#define SOC_HF_LF_COUNT_VALUE_GET(x) (((x) & SOC_HF_LF_COUNT_VALUE_MASK) >> SOC_HF_LF_COUNT_VALUE_LSB) +#define SOC_HF_LF_COUNT_VALUE_SET(x) (((x) << SOC_HF_LF_COUNT_VALUE_LSB) & SOC_HF_LF_COUNT_VALUE_MASK) + +#define SOC_HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define SOC_HF_TIMER_CONTROL_OFFSET 0x00000094 +#define SOC_HF_TIMER_CONTROL_ENABLE_MSB 3 +#define SOC_HF_TIMER_CONTROL_ENABLE_LSB 3 +#define SOC_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define SOC_HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & SOC_HF_TIMER_CONTROL_ENABLE_MASK) >> SOC_HF_TIMER_CONTROL_ENABLE_LSB) +#define SOC_HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << SOC_HF_TIMER_CONTROL_ENABLE_LSB) & SOC_HF_TIMER_CONTROL_ENABLE_MASK) +#define SOC_HF_TIMER_CONTROL_ON_MSB 2 +#define SOC_HF_TIMER_CONTROL_ON_LSB 2 +#define SOC_HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define SOC_HF_TIMER_CONTROL_ON_GET(x) (((x) & SOC_HF_TIMER_CONTROL_ON_MASK) >> SOC_HF_TIMER_CONTROL_ON_LSB) +#define SOC_HF_TIMER_CONTROL_ON_SET(x) (((x) << SOC_HF_TIMER_CONTROL_ON_LSB) & SOC_HF_TIMER_CONTROL_ON_MASK) +#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define SOC_HF_TIMER_CONTROL_RESET_MSB 0 +#define SOC_HF_TIMER_CONTROL_RESET_LSB 0 +#define SOC_HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define SOC_HF_TIMER_CONTROL_RESET_GET(x) (((x) & SOC_HF_TIMER_CONTROL_RESET_MASK) >> SOC_HF_TIMER_CONTROL_RESET_LSB) +#define SOC_HF_TIMER_CONTROL_RESET_SET(x) (((x) << SOC_HF_TIMER_CONTROL_RESET_LSB) & SOC_HF_TIMER_CONTROL_RESET_MASK) + +#define SOC_HF_TIMER_STATUS_ADDRESS 0x00000098 +#define SOC_HF_TIMER_STATUS_OFFSET 0x00000098 +#define SOC_HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define SOC_HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define SOC_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define SOC_HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & SOC_HF_TIMER_STATUS_INTERRUPT_MASK) >> SOC_HF_TIMER_STATUS_INTERRUPT_LSB) +#define SOC_HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << SOC_HF_TIMER_STATUS_INTERRUPT_LSB) & SOC_HF_TIMER_STATUS_INTERRUPT_MASK) + +#define SOC_RTC_CONTROL_ADDRESS 0x0000009c +#define SOC_RTC_CONTROL_OFFSET 0x0000009c +#define SOC_RTC_CONTROL_ENABLE_MSB 2 +#define SOC_RTC_CONTROL_ENABLE_LSB 2 +#define SOC_RTC_CONTROL_ENABLE_MASK 0x00000004 +#define SOC_RTC_CONTROL_ENABLE_GET(x) (((x) & SOC_RTC_CONTROL_ENABLE_MASK) >> SOC_RTC_CONTROL_ENABLE_LSB) +#define SOC_RTC_CONTROL_ENABLE_SET(x) (((x) << SOC_RTC_CONTROL_ENABLE_LSB) & SOC_RTC_CONTROL_ENABLE_MASK) +#define SOC_RTC_CONTROL_LOAD_RTC_MSB 1 +#define SOC_RTC_CONTROL_LOAD_RTC_LSB 1 +#define SOC_RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define SOC_RTC_CONTROL_LOAD_RTC_GET(x) (((x) & SOC_RTC_CONTROL_LOAD_RTC_MASK) >> SOC_RTC_CONTROL_LOAD_RTC_LSB) +#define SOC_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << SOC_RTC_CONTROL_LOAD_RTC_LSB) & SOC_RTC_CONTROL_LOAD_RTC_MASK) +#define SOC_RTC_CONTROL_LOAD_ALARM_MSB 0 +#define SOC_RTC_CONTROL_LOAD_ALARM_LSB 0 +#define SOC_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define SOC_RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & SOC_RTC_CONTROL_LOAD_ALARM_MASK) >> SOC_RTC_CONTROL_LOAD_ALARM_LSB) +#define SOC_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << SOC_RTC_CONTROL_LOAD_ALARM_LSB) & SOC_RTC_CONTROL_LOAD_ALARM_MASK) + +#define SOC_RTC_TIME_ADDRESS 0x000000a0 +#define SOC_RTC_TIME_OFFSET 0x000000a0 +#define SOC_RTC_TIME_WEEK_DAY_MSB 26 +#define SOC_RTC_TIME_WEEK_DAY_LSB 24 +#define SOC_RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define SOC_RTC_TIME_WEEK_DAY_GET(x) (((x) & SOC_RTC_TIME_WEEK_DAY_MASK) >> SOC_RTC_TIME_WEEK_DAY_LSB) +#define SOC_RTC_TIME_WEEK_DAY_SET(x) (((x) << SOC_RTC_TIME_WEEK_DAY_LSB) & SOC_RTC_TIME_WEEK_DAY_MASK) +#define SOC_RTC_TIME_HOUR_MSB 21 +#define SOC_RTC_TIME_HOUR_LSB 16 +#define SOC_RTC_TIME_HOUR_MASK 0x003f0000 +#define SOC_RTC_TIME_HOUR_GET(x) (((x) & SOC_RTC_TIME_HOUR_MASK) >> SOC_RTC_TIME_HOUR_LSB) +#define SOC_RTC_TIME_HOUR_SET(x) (((x) << SOC_RTC_TIME_HOUR_LSB) & SOC_RTC_TIME_HOUR_MASK) +#define SOC_RTC_TIME_MINUTE_MSB 14 +#define SOC_RTC_TIME_MINUTE_LSB 8 +#define SOC_RTC_TIME_MINUTE_MASK 0x00007f00 +#define SOC_RTC_TIME_MINUTE_GET(x) (((x) & SOC_RTC_TIME_MINUTE_MASK) >> SOC_RTC_TIME_MINUTE_LSB) +#define SOC_RTC_TIME_MINUTE_SET(x) (((x) << SOC_RTC_TIME_MINUTE_LSB) & SOC_RTC_TIME_MINUTE_MASK) +#define SOC_RTC_TIME_SECOND_MSB 6 +#define SOC_RTC_TIME_SECOND_LSB 0 +#define SOC_RTC_TIME_SECOND_MASK 0x0000007f +#define SOC_RTC_TIME_SECOND_GET(x) (((x) & SOC_RTC_TIME_SECOND_MASK) >> SOC_RTC_TIME_SECOND_LSB) +#define SOC_RTC_TIME_SECOND_SET(x) (((x) << SOC_RTC_TIME_SECOND_LSB) & SOC_RTC_TIME_SECOND_MASK) + +#define SOC_RTC_DATE_ADDRESS 0x000000a4 +#define SOC_RTC_DATE_OFFSET 0x000000a4 +#define SOC_RTC_DATE_YEAR_MSB 23 +#define SOC_RTC_DATE_YEAR_LSB 16 +#define SOC_RTC_DATE_YEAR_MASK 0x00ff0000 +#define SOC_RTC_DATE_YEAR_GET(x) (((x) & SOC_RTC_DATE_YEAR_MASK) >> SOC_RTC_DATE_YEAR_LSB) +#define SOC_RTC_DATE_YEAR_SET(x) (((x) << SOC_RTC_DATE_YEAR_LSB) & SOC_RTC_DATE_YEAR_MASK) +#define SOC_RTC_DATE_MONTH_MSB 12 +#define SOC_RTC_DATE_MONTH_LSB 8 +#define SOC_RTC_DATE_MONTH_MASK 0x00001f00 +#define SOC_RTC_DATE_MONTH_GET(x) (((x) & SOC_RTC_DATE_MONTH_MASK) >> SOC_RTC_DATE_MONTH_LSB) +#define SOC_RTC_DATE_MONTH_SET(x) (((x) << SOC_RTC_DATE_MONTH_LSB) & SOC_RTC_DATE_MONTH_MASK) +#define SOC_RTC_DATE_MONTH_DAY_MSB 5 +#define SOC_RTC_DATE_MONTH_DAY_LSB 0 +#define SOC_RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define SOC_RTC_DATE_MONTH_DAY_GET(x) (((x) & SOC_RTC_DATE_MONTH_DAY_MASK) >> SOC_RTC_DATE_MONTH_DAY_LSB) +#define SOC_RTC_DATE_MONTH_DAY_SET(x) (((x) << SOC_RTC_DATE_MONTH_DAY_LSB) & SOC_RTC_DATE_MONTH_DAY_MASK) + +#define SOC_RTC_SET_TIME_ADDRESS 0x000000a8 +#define SOC_RTC_SET_TIME_OFFSET 0x000000a8 +#define SOC_RTC_SET_TIME_WEEK_DAY_MSB 26 +#define SOC_RTC_SET_TIME_WEEK_DAY_LSB 24 +#define SOC_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define SOC_RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & SOC_RTC_SET_TIME_WEEK_DAY_MASK) >> SOC_RTC_SET_TIME_WEEK_DAY_LSB) +#define SOC_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << SOC_RTC_SET_TIME_WEEK_DAY_LSB) & SOC_RTC_SET_TIME_WEEK_DAY_MASK) +#define SOC_RTC_SET_TIME_HOUR_MSB 21 +#define SOC_RTC_SET_TIME_HOUR_LSB 16 +#define SOC_RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define SOC_RTC_SET_TIME_HOUR_GET(x) (((x) & SOC_RTC_SET_TIME_HOUR_MASK) >> SOC_RTC_SET_TIME_HOUR_LSB) +#define SOC_RTC_SET_TIME_HOUR_SET(x) (((x) << SOC_RTC_SET_TIME_HOUR_LSB) & SOC_RTC_SET_TIME_HOUR_MASK) +#define SOC_RTC_SET_TIME_MINUTE_MSB 14 +#define SOC_RTC_SET_TIME_MINUTE_LSB 8 +#define SOC_RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define SOC_RTC_SET_TIME_MINUTE_GET(x) (((x) & SOC_RTC_SET_TIME_MINUTE_MASK) >> SOC_RTC_SET_TIME_MINUTE_LSB) +#define SOC_RTC_SET_TIME_MINUTE_SET(x) (((x) << SOC_RTC_SET_TIME_MINUTE_LSB) & SOC_RTC_SET_TIME_MINUTE_MASK) +#define SOC_RTC_SET_TIME_SECOND_MSB 6 +#define SOC_RTC_SET_TIME_SECOND_LSB 0 +#define SOC_RTC_SET_TIME_SECOND_MASK 0x0000007f +#define SOC_RTC_SET_TIME_SECOND_GET(x) (((x) & SOC_RTC_SET_TIME_SECOND_MASK) >> SOC_RTC_SET_TIME_SECOND_LSB) +#define SOC_RTC_SET_TIME_SECOND_SET(x) (((x) << SOC_RTC_SET_TIME_SECOND_LSB) & SOC_RTC_SET_TIME_SECOND_MASK) + +#define SOC_RTC_SET_DATE_ADDRESS 0x000000ac +#define SOC_RTC_SET_DATE_OFFSET 0x000000ac +#define SOC_RTC_SET_DATE_YEAR_MSB 23 +#define SOC_RTC_SET_DATE_YEAR_LSB 16 +#define SOC_RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define SOC_RTC_SET_DATE_YEAR_GET(x) (((x) & SOC_RTC_SET_DATE_YEAR_MASK) >> SOC_RTC_SET_DATE_YEAR_LSB) +#define SOC_RTC_SET_DATE_YEAR_SET(x) (((x) << SOC_RTC_SET_DATE_YEAR_LSB) & SOC_RTC_SET_DATE_YEAR_MASK) +#define SOC_RTC_SET_DATE_MONTH_MSB 12 +#define SOC_RTC_SET_DATE_MONTH_LSB 8 +#define SOC_RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define SOC_RTC_SET_DATE_MONTH_GET(x) (((x) & SOC_RTC_SET_DATE_MONTH_MASK) >> SOC_RTC_SET_DATE_MONTH_LSB) +#define SOC_RTC_SET_DATE_MONTH_SET(x) (((x) << SOC_RTC_SET_DATE_MONTH_LSB) & SOC_RTC_SET_DATE_MONTH_MASK) +#define SOC_RTC_SET_DATE_MONTH_DAY_MSB 5 +#define SOC_RTC_SET_DATE_MONTH_DAY_LSB 0 +#define SOC_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define SOC_RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & SOC_RTC_SET_DATE_MONTH_DAY_MASK) >> SOC_RTC_SET_DATE_MONTH_DAY_LSB) +#define SOC_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << SOC_RTC_SET_DATE_MONTH_DAY_LSB) & SOC_RTC_SET_DATE_MONTH_DAY_MASK) + +#define SOC_RTC_SET_ALARM_ADDRESS 0x000000b0 +#define SOC_RTC_SET_ALARM_OFFSET 0x000000b0 +#define SOC_RTC_SET_ALARM_HOUR_MSB 21 +#define SOC_RTC_SET_ALARM_HOUR_LSB 16 +#define SOC_RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define SOC_RTC_SET_ALARM_HOUR_GET(x) (((x) & SOC_RTC_SET_ALARM_HOUR_MASK) >> SOC_RTC_SET_ALARM_HOUR_LSB) +#define SOC_RTC_SET_ALARM_HOUR_SET(x) (((x) << SOC_RTC_SET_ALARM_HOUR_LSB) & SOC_RTC_SET_ALARM_HOUR_MASK) +#define SOC_RTC_SET_ALARM_MINUTE_MSB 14 +#define SOC_RTC_SET_ALARM_MINUTE_LSB 8 +#define SOC_RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define SOC_RTC_SET_ALARM_MINUTE_GET(x) (((x) & SOC_RTC_SET_ALARM_MINUTE_MASK) >> SOC_RTC_SET_ALARM_MINUTE_LSB) +#define SOC_RTC_SET_ALARM_MINUTE_SET(x) (((x) << SOC_RTC_SET_ALARM_MINUTE_LSB) & SOC_RTC_SET_ALARM_MINUTE_MASK) +#define SOC_RTC_SET_ALARM_SECOND_MSB 6 +#define SOC_RTC_SET_ALARM_SECOND_LSB 0 +#define SOC_RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define SOC_RTC_SET_ALARM_SECOND_GET(x) (((x) & SOC_RTC_SET_ALARM_SECOND_MASK) >> SOC_RTC_SET_ALARM_SECOND_LSB) +#define SOC_RTC_SET_ALARM_SECOND_SET(x) (((x) << SOC_RTC_SET_ALARM_SECOND_LSB) & SOC_RTC_SET_ALARM_SECOND_MASK) + +#define SOC_RTC_CONFIG_ADDRESS 0x000000b4 +#define SOC_RTC_CONFIG_OFFSET 0x000000b4 +#define SOC_RTC_CONFIG_BCD_MSB 2 +#define SOC_RTC_CONFIG_BCD_LSB 2 +#define SOC_RTC_CONFIG_BCD_MASK 0x00000004 +#define SOC_RTC_CONFIG_BCD_GET(x) (((x) & SOC_RTC_CONFIG_BCD_MASK) >> SOC_RTC_CONFIG_BCD_LSB) +#define SOC_RTC_CONFIG_BCD_SET(x) (((x) << SOC_RTC_CONFIG_BCD_LSB) & SOC_RTC_CONFIG_BCD_MASK) +#define SOC_RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define SOC_RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define SOC_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define SOC_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & SOC_RTC_CONFIG_TWELVE_HOUR_MASK) >> SOC_RTC_CONFIG_TWELVE_HOUR_LSB) +#define SOC_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << SOC_RTC_CONFIG_TWELVE_HOUR_LSB) & SOC_RTC_CONFIG_TWELVE_HOUR_MASK) +#define SOC_RTC_CONFIG_DSE_MSB 0 +#define SOC_RTC_CONFIG_DSE_LSB 0 +#define SOC_RTC_CONFIG_DSE_MASK 0x00000001 +#define SOC_RTC_CONFIG_DSE_GET(x) (((x) & SOC_RTC_CONFIG_DSE_MASK) >> SOC_RTC_CONFIG_DSE_LSB) +#define SOC_RTC_CONFIG_DSE_SET(x) (((x) << SOC_RTC_CONFIG_DSE_LSB) & SOC_RTC_CONFIG_DSE_MASK) + +#define SOC_RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define SOC_RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define SOC_RTC_ALARM_STATUS_ENABLE_MSB 1 +#define SOC_RTC_ALARM_STATUS_ENABLE_LSB 1 +#define SOC_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define SOC_RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & SOC_RTC_ALARM_STATUS_ENABLE_MASK) >> SOC_RTC_ALARM_STATUS_ENABLE_LSB) +#define SOC_RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << SOC_RTC_ALARM_STATUS_ENABLE_LSB) & SOC_RTC_ALARM_STATUS_ENABLE_MASK) +#define SOC_RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define SOC_RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define SOC_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define SOC_RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & SOC_RTC_ALARM_STATUS_INTERRUPT_MASK) >> SOC_RTC_ALARM_STATUS_INTERRUPT_LSB) +#define SOC_RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << SOC_RTC_ALARM_STATUS_INTERRUPT_LSB) & SOC_RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define SOC_UART_WAKEUP_ADDRESS 0x000000bc +#define SOC_UART_WAKEUP_OFFSET 0x000000bc +#define SOC_UART_WAKEUP_ENABLE_MSB 0 +#define SOC_UART_WAKEUP_ENABLE_LSB 0 +#define SOC_UART_WAKEUP_ENABLE_MASK 0x00000001 +#define SOC_UART_WAKEUP_ENABLE_GET(x) (((x) & SOC_UART_WAKEUP_ENABLE_MASK) >> SOC_UART_WAKEUP_ENABLE_LSB) +#define SOC_UART_WAKEUP_ENABLE_SET(x) (((x) << SOC_UART_WAKEUP_ENABLE_LSB) & SOC_UART_WAKEUP_ENABLE_MASK) + +#define SOC_RESET_CAUSE_ADDRESS 0x000000c0 +#define SOC_RESET_CAUSE_OFFSET 0x000000c0 +#define SOC_RESET_CAUSE_LAST_MSB 2 +#define SOC_RESET_CAUSE_LAST_LSB 0 +#define SOC_RESET_CAUSE_LAST_MASK 0x00000007 +#define SOC_RESET_CAUSE_LAST_GET(x) (((x) & SOC_RESET_CAUSE_LAST_MASK) >> SOC_RESET_CAUSE_LAST_LSB) +#define SOC_RESET_CAUSE_LAST_SET(x) (((x) << SOC_RESET_CAUSE_LAST_LSB) & SOC_RESET_CAUSE_LAST_MASK) + +#define SOC_SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SOC_SYSTEM_SLEEP_MCI_MSB 5 +#define SOC_SYSTEM_SLEEP_MCI_LSB 5 +#define SOC_SYSTEM_SLEEP_MCI_MASK 0x00000020 +#define SOC_SYSTEM_SLEEP_MCI_GET(x) (((x) & SOC_SYSTEM_SLEEP_MCI_MASK) >> SOC_SYSTEM_SLEEP_MCI_LSB) +#define SOC_SYSTEM_SLEEP_MCI_SET(x) (((x) << SOC_SYSTEM_SLEEP_MCI_LSB) & SOC_SYSTEM_SLEEP_MCI_MASK) +#define SOC_SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SOC_SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SOC_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SOC_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SOC_SYSTEM_SLEEP_HOST_IF_MASK) >> SOC_SYSTEM_SLEEP_HOST_IF_LSB) +#define SOC_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SOC_SYSTEM_SLEEP_HOST_IF_LSB) & SOC_SYSTEM_SLEEP_HOST_IF_MASK) +#define SOC_SYSTEM_SLEEP_MBOX_MSB 3 +#define SOC_SYSTEM_SLEEP_MBOX_LSB 3 +#define SOC_SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SOC_SYSTEM_SLEEP_MBOX_GET(x) (((x) & SOC_SYSTEM_SLEEP_MBOX_MASK) >> SOC_SYSTEM_SLEEP_MBOX_LSB) +#define SOC_SYSTEM_SLEEP_MBOX_SET(x) (((x) << SOC_SYSTEM_SLEEP_MBOX_LSB) & SOC_SYSTEM_SLEEP_MBOX_MASK) +#define SOC_SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SOC_SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SOC_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SOC_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SOC_SYSTEM_SLEEP_MAC_IF_MASK) >> SOC_SYSTEM_SLEEP_MAC_IF_LSB) +#define SOC_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SOC_SYSTEM_SLEEP_MAC_IF_LSB) & SOC_SYSTEM_SLEEP_MAC_IF_MASK) +#define SOC_SYSTEM_SLEEP_LIGHT_MSB 1 +#define SOC_SYSTEM_SLEEP_LIGHT_LSB 1 +#define SOC_SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SOC_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SOC_SYSTEM_SLEEP_LIGHT_MASK) >> SOC_SYSTEM_SLEEP_LIGHT_LSB) +#define SOC_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SOC_SYSTEM_SLEEP_LIGHT_LSB) & SOC_SYSTEM_SLEEP_LIGHT_MASK) +#define SOC_SYSTEM_SLEEP_DISABLE_MSB 0 +#define SOC_SYSTEM_SLEEP_DISABLE_LSB 0 +#define SOC_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SOC_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SOC_SYSTEM_SLEEP_DISABLE_MASK) >> SOC_SYSTEM_SLEEP_DISABLE_LSB) +#define SOC_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SOC_SYSTEM_SLEEP_DISABLE_LSB) & SOC_SYSTEM_SLEEP_DISABLE_MASK) + +#define SOC_SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SOC_SDIO_WRAPPER_OFFSET 0x000000c8 +#define SOC_SDIO_WRAPPER_SLEEP_MSB 3 +#define SOC_SDIO_WRAPPER_SLEEP_LSB 3 +#define SOC_SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SOC_SDIO_WRAPPER_SLEEP_GET(x) (((x) & SOC_SDIO_WRAPPER_SLEEP_MASK) >> SOC_SDIO_WRAPPER_SLEEP_LSB) +#define SOC_SDIO_WRAPPER_SLEEP_SET(x) (((x) << SOC_SDIO_WRAPPER_SLEEP_LSB) & SOC_SDIO_WRAPPER_SLEEP_MASK) +#define SOC_SDIO_WRAPPER_WAKEUP_MSB 2 +#define SOC_SDIO_WRAPPER_WAKEUP_LSB 2 +#define SOC_SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SOC_SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SOC_SDIO_WRAPPER_WAKEUP_MASK) >> SOC_SDIO_WRAPPER_WAKEUP_LSB) +#define SOC_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SOC_SDIO_WRAPPER_WAKEUP_LSB) & SOC_SDIO_WRAPPER_WAKEUP_MASK) +#define SOC_SDIO_WRAPPER_SOC_ON_MSB 1 +#define SOC_SDIO_WRAPPER_SOC_ON_LSB 1 +#define SOC_SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SOC_SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SOC_SDIO_WRAPPER_SOC_ON_MASK) >> SOC_SDIO_WRAPPER_SOC_ON_LSB) +#define SOC_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SOC_SDIO_WRAPPER_SOC_ON_LSB) & SOC_SDIO_WRAPPER_SOC_ON_MASK) +#define SOC_SDIO_WRAPPER_ON_MSB 0 +#define SOC_SDIO_WRAPPER_ON_LSB 0 +#define SOC_SDIO_WRAPPER_ON_MASK 0x00000001 +#define SOC_SDIO_WRAPPER_ON_GET(x) (((x) & SOC_SDIO_WRAPPER_ON_MASK) >> SOC_SDIO_WRAPPER_ON_LSB) +#define SOC_SDIO_WRAPPER_ON_SET(x) (((x) << SOC_SDIO_WRAPPER_ON_LSB) & SOC_SDIO_WRAPPER_ON_MASK) + +#define SOC_INT_SLEEP_MASK_ADDRESS 0x000000cc +#define SOC_INT_SLEEP_MASK_OFFSET 0x000000cc +#define SOC_INT_SLEEP_MASK_BITMAP_MSB 31 +#define SOC_INT_SLEEP_MASK_BITMAP_LSB 0 +#define SOC_INT_SLEEP_MASK_BITMAP_MASK 0xffffffff +#define SOC_INT_SLEEP_MASK_BITMAP_GET(x) (((x) & SOC_INT_SLEEP_MASK_BITMAP_MASK) >> SOC_INT_SLEEP_MASK_BITMAP_LSB) +#define SOC_INT_SLEEP_MASK_BITMAP_SET(x) (((x) << SOC_INT_SLEEP_MASK_BITMAP_LSB) & SOC_INT_SLEEP_MASK_BITMAP_MASK) + +#define SOC_LPO_CAL_TIME_ADDRESS 0x000000d4 +#define SOC_LPO_CAL_TIME_OFFSET 0x000000d4 +#define SOC_LPO_CAL_TIME_LENGTH_MSB 13 +#define SOC_LPO_CAL_TIME_LENGTH_LSB 0 +#define SOC_LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define SOC_LPO_CAL_TIME_LENGTH_GET(x) (((x) & SOC_LPO_CAL_TIME_LENGTH_MASK) >> SOC_LPO_CAL_TIME_LENGTH_LSB) +#define SOC_LPO_CAL_TIME_LENGTH_SET(x) (((x) << SOC_LPO_CAL_TIME_LENGTH_LSB) & SOC_LPO_CAL_TIME_LENGTH_MASK) + +#define SOC_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define SOC_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define SOC_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define SOC_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define SOC_LPO_CAL_ADDRESS 0x000000e0 +#define SOC_LPO_CAL_OFFSET 0x000000e0 +#define SOC_LPO_CAL_ENABLE_MSB 20 +#define SOC_LPO_CAL_ENABLE_LSB 20 +#define SOC_LPO_CAL_ENABLE_MASK 0x00100000 +#define SOC_LPO_CAL_ENABLE_GET(x) (((x) & SOC_LPO_CAL_ENABLE_MASK) >> SOC_LPO_CAL_ENABLE_LSB) +#define SOC_LPO_CAL_ENABLE_SET(x) (((x) << SOC_LPO_CAL_ENABLE_LSB) & SOC_LPO_CAL_ENABLE_MASK) +#define SOC_LPO_CAL_COUNT_MSB 19 +#define SOC_LPO_CAL_COUNT_LSB 0 +#define SOC_LPO_CAL_COUNT_MASK 0x000fffff +#define SOC_LPO_CAL_COUNT_GET(x) (((x) & SOC_LPO_CAL_COUNT_MASK) >> SOC_LPO_CAL_COUNT_LSB) +#define SOC_LPO_CAL_COUNT_SET(x) (((x) << SOC_LPO_CAL_COUNT_LSB) & SOC_LPO_CAL_COUNT_MASK) + +#define SOC_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define SOC_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_MSB 16 +#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB 16 +#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00010000 +#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 15 +#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000ffff +#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define SOC_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define SOC_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define SOC_LPO_CAL_TEST_STATUS_READY_MSB 16 +#define SOC_LPO_CAL_TEST_STATUS_READY_LSB 16 +#define SOC_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define SOC_LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & SOC_LPO_CAL_TEST_STATUS_READY_MASK) >> SOC_LPO_CAL_TEST_STATUS_READY_LSB) +#define SOC_LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << SOC_LPO_CAL_TEST_STATUS_READY_LSB) & SOC_LPO_CAL_TEST_STATUS_READY_MASK) +#define SOC_LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define SOC_LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define SOC_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define SOC_LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & SOC_LPO_CAL_TEST_STATUS_COUNT_MASK) >> SOC_LPO_CAL_TEST_STATUS_COUNT_LSB) +#define SOC_LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << SOC_LPO_CAL_TEST_STATUS_COUNT_LSB) & SOC_LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define LEGACY_SOC_CHIP_ID_ADDRESS 0x000000ec +#define LEGACY_SOC_CHIP_ID_OFFSET 0x000000ec +#define LEGACY_SOC_CHIP_ID_DEVICE_ID_MSB 31 +#define LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB 16 +#define LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define LEGACY_SOC_CHIP_ID_DEVICE_ID_GET(x) (((x) & LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK) >> LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB) +#define LEGACY_SOC_CHIP_ID_DEVICE_ID_SET(x) (((x) << LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB) & LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK) +#define LEGACY_SOC_CHIP_ID_CONFIG_ID_MSB 15 +#define LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB 4 +#define LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define LEGACY_SOC_CHIP_ID_CONFIG_ID_GET(x) (((x) & LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK) >> LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB) +#define LEGACY_SOC_CHIP_ID_CONFIG_ID_SET(x) (((x) << LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB) & LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK) +#define LEGACY_SOC_CHIP_ID_VERSION_ID_MSB 3 +#define LEGACY_SOC_CHIP_ID_VERSION_ID_LSB 0 +#define LEGACY_SOC_CHIP_ID_VERSION_ID_MASK 0x0000000f +#define LEGACY_SOC_CHIP_ID_VERSION_ID_GET(x) (((x) & LEGACY_SOC_CHIP_ID_VERSION_ID_MASK) >> LEGACY_SOC_CHIP_ID_VERSION_ID_LSB) +#define LEGACY_SOC_CHIP_ID_VERSION_ID_SET(x) (((x) << LEGACY_SOC_CHIP_ID_VERSION_ID_LSB) & LEGACY_SOC_CHIP_ID_VERSION_ID_MASK) + +#define SOC_CHIP_ID_ADDRESS 0x000000f0 +#define SOC_CHIP_ID_OFFSET 0x000000f0 +#define SOC_CHIP_ID_DEVICE_ID_MSB 31 +#define SOC_CHIP_ID_DEVICE_ID_LSB 16 +#define SOC_CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define SOC_CHIP_ID_DEVICE_ID_GET(x) (((x) & SOC_CHIP_ID_DEVICE_ID_MASK) >> SOC_CHIP_ID_DEVICE_ID_LSB) +#define SOC_CHIP_ID_DEVICE_ID_SET(x) (((x) << SOC_CHIP_ID_DEVICE_ID_LSB) & SOC_CHIP_ID_DEVICE_ID_MASK) +#define SOC_CHIP_ID_CONFIG_ID_MSB 15 +#define SOC_CHIP_ID_CONFIG_ID_LSB 4 +#define SOC_CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define SOC_CHIP_ID_CONFIG_ID_GET(x) (((x) & SOC_CHIP_ID_CONFIG_ID_MASK) >> SOC_CHIP_ID_CONFIG_ID_LSB) +#define SOC_CHIP_ID_CONFIG_ID_SET(x) (((x) << SOC_CHIP_ID_CONFIG_ID_LSB) & SOC_CHIP_ID_CONFIG_ID_MASK) +#define SOC_CHIP_ID_VERSION_ID_MSB 3 +#define SOC_CHIP_ID_VERSION_ID_LSB 0 +#define SOC_CHIP_ID_VERSION_ID_MASK 0x0000000f +#define SOC_CHIP_ID_VERSION_ID_GET(x) (((x) & SOC_CHIP_ID_VERSION_ID_MASK) >> SOC_CHIP_ID_VERSION_ID_LSB) +#define SOC_CHIP_ID_VERSION_ID_SET(x) (((x) << SOC_CHIP_ID_VERSION_ID_LSB) & SOC_CHIP_ID_VERSION_ID_MASK) + +#define SOC_POWER_REG_ADDRESS 0x0000010c +#define SOC_POWER_REG_OFFSET 0x0000010c +#define SOC_POWER_REG_DISCON_MODE_EN_MSB 16 +#define SOC_POWER_REG_DISCON_MODE_EN_LSB 16 +#define SOC_POWER_REG_DISCON_MODE_EN_MASK 0x00010000 +#define SOC_POWER_REG_DISCON_MODE_EN_GET(x) (((x) & SOC_POWER_REG_DISCON_MODE_EN_MASK) >> SOC_POWER_REG_DISCON_MODE_EN_LSB) +#define SOC_POWER_REG_DISCON_MODE_EN_SET(x) (((x) << SOC_POWER_REG_DISCON_MODE_EN_LSB) & SOC_POWER_REG_DISCON_MODE_EN_MASK) +#define SOC_POWER_REG_DEEP_SLEEP_EN_MSB 15 +#define SOC_POWER_REG_DEEP_SLEEP_EN_LSB 15 +#define SOC_POWER_REG_DEEP_SLEEP_EN_MASK 0x00008000 +#define SOC_POWER_REG_DEEP_SLEEP_EN_GET(x) (((x) & SOC_POWER_REG_DEEP_SLEEP_EN_MASK) >> SOC_POWER_REG_DEEP_SLEEP_EN_LSB) +#define SOC_POWER_REG_DEEP_SLEEP_EN_SET(x) (((x) << SOC_POWER_REG_DEEP_SLEEP_EN_LSB) & SOC_POWER_REG_DEEP_SLEEP_EN_MASK) +#define SOC_POWER_REG_DEBUG_EN_MSB 14 +#define SOC_POWER_REG_DEBUG_EN_LSB 14 +#define SOC_POWER_REG_DEBUG_EN_MASK 0x00004000 +#define SOC_POWER_REG_DEBUG_EN_GET(x) (((x) & SOC_POWER_REG_DEBUG_EN_MASK) >> SOC_POWER_REG_DEBUG_EN_LSB) +#define SOC_POWER_REG_DEBUG_EN_SET(x) (((x) << SOC_POWER_REG_DEBUG_EN_LSB) & SOC_POWER_REG_DEBUG_EN_MASK) +#define SOC_POWER_REG_WLAN_BB_PWD_EN_MSB 13 +#define SOC_POWER_REG_WLAN_BB_PWD_EN_LSB 13 +#define SOC_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000 +#define SOC_POWER_REG_WLAN_BB_PWD_EN_GET(x) (((x) & SOC_POWER_REG_WLAN_BB_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_BB_PWD_EN_LSB) +#define SOC_POWER_REG_WLAN_BB_PWD_EN_SET(x) (((x) << SOC_POWER_REG_WLAN_BB_PWD_EN_LSB) & SOC_POWER_REG_WLAN_BB_PWD_EN_MASK) +#define SOC_POWER_REG_WLAN_MAC_PWD_EN_MSB 12 +#define SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB 12 +#define SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000 +#define SOC_POWER_REG_WLAN_MAC_PWD_EN_GET(x) (((x) & SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB) +#define SOC_POWER_REG_WLAN_MAC_PWD_EN_SET(x) (((x) << SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB) & SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK) +#define SOC_POWER_REG_CPU_INT_ENABLE_MSB 7 +#define SOC_POWER_REG_CPU_INT_ENABLE_LSB 7 +#define SOC_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define SOC_POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & SOC_POWER_REG_CPU_INT_ENABLE_MASK) >> SOC_POWER_REG_CPU_INT_ENABLE_LSB) +#define SOC_POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << SOC_POWER_REG_CPU_INT_ENABLE_LSB) & SOC_POWER_REG_CPU_INT_ENABLE_MASK) +#define SOC_POWER_REG_WLAN_ISO_DIS_MSB 6 +#define SOC_POWER_REG_WLAN_ISO_DIS_LSB 6 +#define SOC_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define SOC_POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & SOC_POWER_REG_WLAN_ISO_DIS_MASK) >> SOC_POWER_REG_WLAN_ISO_DIS_LSB) +#define SOC_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << SOC_POWER_REG_WLAN_ISO_DIS_LSB) & SOC_POWER_REG_WLAN_ISO_DIS_MASK) +#define SOC_POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define SOC_POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define SOC_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define SOC_POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & SOC_POWER_REG_WLAN_ISO_CNTL_MASK) >> SOC_POWER_REG_WLAN_ISO_CNTL_LSB) +#define SOC_POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << SOC_POWER_REG_WLAN_ISO_CNTL_LSB) & SOC_POWER_REG_WLAN_ISO_CNTL_MASK) +#define SOC_POWER_REG_RADIO_PWD_EN_MSB 4 +#define SOC_POWER_REG_RADIO_PWD_EN_LSB 4 +#define SOC_POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define SOC_POWER_REG_RADIO_PWD_EN_GET(x) (((x) & SOC_POWER_REG_RADIO_PWD_EN_MASK) >> SOC_POWER_REG_RADIO_PWD_EN_LSB) +#define SOC_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << SOC_POWER_REG_RADIO_PWD_EN_LSB) & SOC_POWER_REG_RADIO_PWD_EN_MASK) +#define SOC_POWER_REG_SOC_ISO_EN_MSB 3 +#define SOC_POWER_REG_SOC_ISO_EN_LSB 3 +#define SOC_POWER_REG_SOC_ISO_EN_MASK 0x00000008 +#define SOC_POWER_REG_SOC_ISO_EN_GET(x) (((x) & SOC_POWER_REG_SOC_ISO_EN_MASK) >> SOC_POWER_REG_SOC_ISO_EN_LSB) +#define SOC_POWER_REG_SOC_ISO_EN_SET(x) (((x) << SOC_POWER_REG_SOC_ISO_EN_LSB) & SOC_POWER_REG_SOC_ISO_EN_MASK) +#define SOC_POWER_REG_WLAN_ISO_EN_MSB 2 +#define SOC_POWER_REG_WLAN_ISO_EN_LSB 2 +#define SOC_POWER_REG_WLAN_ISO_EN_MASK 0x00000004 +#define SOC_POWER_REG_WLAN_ISO_EN_GET(x) (((x) & SOC_POWER_REG_WLAN_ISO_EN_MASK) >> SOC_POWER_REG_WLAN_ISO_EN_LSB) +#define SOC_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << SOC_POWER_REG_WLAN_ISO_EN_LSB) & SOC_POWER_REG_WLAN_ISO_EN_MASK) +#define SOC_POWER_REG_WLAN_PWD_EN_MSB 1 +#define SOC_POWER_REG_WLAN_PWD_EN_LSB 1 +#define SOC_POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define SOC_POWER_REG_WLAN_PWD_EN_GET(x) (((x) & SOC_POWER_REG_WLAN_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_PWD_EN_LSB) +#define SOC_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << SOC_POWER_REG_WLAN_PWD_EN_LSB) & SOC_POWER_REG_WLAN_PWD_EN_MASK) +#define SOC_POWER_REG_POWER_EN_MSB 0 +#define SOC_POWER_REG_POWER_EN_LSB 0 +#define SOC_POWER_REG_POWER_EN_MASK 0x00000001 +#define SOC_POWER_REG_POWER_EN_GET(x) (((x) & SOC_POWER_REG_POWER_EN_MASK) >> SOC_POWER_REG_POWER_EN_LSB) +#define SOC_POWER_REG_POWER_EN_SET(x) (((x) << SOC_POWER_REG_POWER_EN_LSB) & SOC_POWER_REG_POWER_EN_MASK) + +#define SOC_CORE_CLK_CTRL_ADDRESS 0x00000110 +#define SOC_CORE_CLK_CTRL_OFFSET 0x00000110 +#define SOC_CORE_CLK_CTRL_DIV_MSB 2 +#define SOC_CORE_CLK_CTRL_DIV_LSB 0 +#define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define SOC_CORE_CLK_CTRL_DIV_GET(x) (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) +#define SOC_CORE_CLK_CTRL_DIV_SET(x) (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) + +#define SOC_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114 +#define SOC_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114 +#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK) + +#define SLEEP_RETENTION_ADDRESS 0x00000214 +#define SLEEP_RETENTION_OFFSET 0x00000214 +#define SLEEP_RETENTION_GREEN_SAVE_MSB 10 +#define SLEEP_RETENTION_GREEN_SAVE_LSB 10 +#define SLEEP_RETENTION_GREEN_SAVE_MASK 0x00000400 +#define SLEEP_RETENTION_GREEN_SAVE_GET(x) (((x) & SLEEP_RETENTION_GREEN_SAVE_MASK) >> SLEEP_RETENTION_GREEN_SAVE_LSB) +#define SLEEP_RETENTION_GREEN_SAVE_SET(x) (((x) << SLEEP_RETENTION_GREEN_SAVE_LSB) & SLEEP_RETENTION_GREEN_SAVE_MASK) +#define SLEEP_RETENTION_TIME_MSB 9 +#define SLEEP_RETENTION_TIME_LSB 2 +#define SLEEP_RETENTION_TIME_MASK 0x000003fc +#define SLEEP_RETENTION_TIME_GET(x) (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB) +#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK) +#define SLEEP_RETENTION_MODE_MSB 1 +#define SLEEP_RETENTION_MODE_LSB 1 +#define SLEEP_RETENTION_MODE_MASK 0x00000002 +#define SLEEP_RETENTION_MODE_GET(x) (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB) +#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK) +#define SLEEP_RETENTION_ENABLE_MSB 0 +#define SLEEP_RETENTION_ENABLE_LSB 0 +#define SLEEP_RETENTION_ENABLE_MASK 0x00000001 +#define SLEEP_RETENTION_ENABLE_GET(x) (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB) +#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK) + +#define LP_PERF_COUNTER_ADDRESS 0x00000284 +#define LP_PERF_COUNTER_OFFSET 0x00000284 +#define LP_PERF_COUNTER_EN_MSB 0 +#define LP_PERF_COUNTER_EN_LSB 0 +#define LP_PERF_COUNTER_EN_MASK 0x00000001 +#define LP_PERF_COUNTER_EN_GET(x) (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB) +#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK) + +#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288 +#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288 +#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31 +#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0 +#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB) +#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK) + +#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c +#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c +#define LP_PERF_DEEP_SLEEP_CNT_MSB 31 +#define LP_PERF_DEEP_SLEEP_CNT_LSB 0 +#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB) +#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK) + +#define LP_PERF_ON_ADDRESS 0x00000290 +#define LP_PERF_ON_OFFSET 0x00000290 +#define LP_PERF_ON_CNT_MSB 31 +#define LP_PERF_ON_CNT_LSB 0 +#define LP_PERF_ON_CNT_MASK 0xffffffff +#define LP_PERF_ON_CNT_GET(x) (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB) +#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK) + +#define CHIP_MODE_ADDRESS 0x000002a8 +#define CHIP_MODE_OFFSET 0x000002a8 +#define CHIP_MODE_BIT_MSB 1 +#define CHIP_MODE_BIT_LSB 0 +#define CHIP_MODE_BIT_MASK 0x00000003 +#define CHIP_MODE_BIT_GET(x) (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB) +#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK) + +#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac +#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac +#define CLK_REQ_FALL_EDGE_EN_MSB 31 +#define CLK_REQ_FALL_EDGE_EN_LSB 31 +#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000 +#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB) +#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK) +#define CLK_REQ_FALL_EDGE_DELAY_MSB 7 +#define CLK_REQ_FALL_EDGE_DELAY_LSB 0 +#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff +#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB) +#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK) + +#define OTP_ADDRESS 0x000002b0 +#define OTP_OFFSET 0x000002b0 +#define OTP_LDO25_EN_MSB 1 +#define OTP_LDO25_EN_LSB 1 +#define OTP_LDO25_EN_MASK 0x00000002 +#define OTP_LDO25_EN_GET(x) (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB) +#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK) +#define OTP_VDD12_EN_MSB 0 +#define OTP_VDD12_EN_LSB 0 +#define OTP_VDD12_EN_MASK 0x00000001 +#define OTP_VDD12_EN_GET(x) (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB) +#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK) + +#define OTP_STATUS_ADDRESS 0x000002b4 +#define OTP_STATUS_OFFSET 0x000002b4 +#define OTP_STATUS_LDO25_EN_READY_MSB 1 +#define OTP_STATUS_LDO25_EN_READY_LSB 1 +#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002 +#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB) +#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK) +#define OTP_STATUS_VDD12_EN_READY_MSB 0 +#define OTP_STATUS_VDD12_EN_READY_LSB 0 +#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001 +#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB) +#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK) + +#define PMU_ADDRESS 0x000002b8 +#define PMU_OFFSET 0x000002b8 +#define PMU_REG_WAKEUP_TIME_SEL_MSB 1 +#define PMU_REG_WAKEUP_TIME_SEL_LSB 0 +#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003 +#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB) +#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK) + +#define PMU_CONFIG_ADDRESS 0x000002bc +#define PMU_CONFIG_OFFSET 0x000002bc +#define PMU_CONFIG_VALUE_MSB 4 +#define PMU_CONFIG_VALUE_LSB 0 +#define PMU_CONFIG_VALUE_MASK 0x0000001f +#define PMU_CONFIG_VALUE_GET(x) (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB) +#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK) + +#define PMU_PAREG_ADDRESS 0x000002c0 +#define PMU_PAREG_OFFSET 0x000002c0 +#define PMU_PAREG_LVL_CTR_MSB 2 +#define PMU_PAREG_LVL_CTR_LSB 0 +#define PMU_PAREG_LVL_CTR_MASK 0x00000007 +#define PMU_PAREG_LVL_CTR_GET(x) (((x) & PMU_PAREG_LVL_CTR_MASK) >> PMU_PAREG_LVL_CTR_LSB) +#define PMU_PAREG_LVL_CTR_SET(x) (((x) << PMU_PAREG_LVL_CTR_LSB) & PMU_PAREG_LVL_CTR_MASK) + +#define PMU_BYPASS_ADDRESS 0x000002c4 +#define PMU_BYPASS_OFFSET 0x000002c4 +#define PMU_BYPASS_SWREG_MSB 2 +#define PMU_BYPASS_SWREG_LSB 2 +#define PMU_BYPASS_SWREG_MASK 0x00000004 +#define PMU_BYPASS_SWREG_GET(x) (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB) +#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK) +#define PMU_BYPASS_DREG_MSB 1 +#define PMU_BYPASS_DREG_LSB 1 +#define PMU_BYPASS_DREG_MASK 0x00000002 +#define PMU_BYPASS_DREG_GET(x) (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB) +#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK) +#define PMU_BYPASS_PAREG_MSB 0 +#define PMU_BYPASS_PAREG_LSB 0 +#define PMU_BYPASS_PAREG_MASK 0x00000001 +#define PMU_BYPASS_PAREG_GET(x) (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB) +#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK) + +#define THERM_CTRL1_ADDRESS 0x000002dc +#define THERM_CTRL1_OFFSET 0x000002dc +#define THERM_CTRL1_BYPASS_MSB 16 +#define THERM_CTRL1_BYPASS_LSB 16 +#define THERM_CTRL1_BYPASS_MASK 0x00010000 +#define THERM_CTRL1_BYPASS_GET(x) (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB) +#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK) +#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15 +#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12 +#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000 +#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB) +#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK) +#define THERM_CTRL1_WIDTH_MSB 11 +#define THERM_CTRL1_WIDTH_LSB 5 +#define THERM_CTRL1_WIDTH_MASK 0x00000fe0 +#define THERM_CTRL1_WIDTH_GET(x) (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB) +#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK) +#define THERM_CTRL1_TYPE_MSB 4 +#define THERM_CTRL1_TYPE_LSB 3 +#define THERM_CTRL1_TYPE_MASK 0x00000018 +#define THERM_CTRL1_TYPE_GET(x) (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB) +#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK) +#define THERM_CTRL1_MEASURE_MSB 2 +#define THERM_CTRL1_MEASURE_LSB 2 +#define THERM_CTRL1_MEASURE_MASK 0x00000004 +#define THERM_CTRL1_MEASURE_GET(x) (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB) +#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK) +#define THERM_CTRL1_INT_EN_MSB 1 +#define THERM_CTRL1_INT_EN_LSB 1 +#define THERM_CTRL1_INT_EN_MASK 0x00000002 +#define THERM_CTRL1_INT_EN_GET(x) (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB) +#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK) +#define THERM_CTRL1_INT_STATUS_MSB 0 +#define THERM_CTRL1_INT_STATUS_LSB 0 +#define THERM_CTRL1_INT_STATUS_MASK 0x00000001 +#define THERM_CTRL1_INT_STATUS_GET(x) (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB) +#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK) + +#define THERM_CTRL2_ADDRESS 0x000002e0 +#define THERM_CTRL2_OFFSET 0x000002e0 +#define THERM_CTRL2_ADC_OFF_MSB 25 +#define THERM_CTRL2_ADC_OFF_LSB 25 +#define THERM_CTRL2_ADC_OFF_MASK 0x02000000 +#define THERM_CTRL2_ADC_OFF_GET(x) (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB) +#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK) +#define THERM_CTRL2_ADC_ON_MSB 24 +#define THERM_CTRL2_ADC_ON_LSB 24 +#define THERM_CTRL2_ADC_ON_MASK 0x01000000 +#define THERM_CTRL2_ADC_ON_GET(x) (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB) +#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK) +#define THERM_CTRL2_SAMPLE_MSB 23 +#define THERM_CTRL2_SAMPLE_LSB 16 +#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000 +#define THERM_CTRL2_SAMPLE_GET(x) (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB) +#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK) +#define THERM_CTRL2_HIGH_MSB 15 +#define THERM_CTRL2_HIGH_LSB 8 +#define THERM_CTRL2_HIGH_MASK 0x0000ff00 +#define THERM_CTRL2_HIGH_GET(x) (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB) +#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK) +#define THERM_CTRL2_LOW_MSB 7 +#define THERM_CTRL2_LOW_LSB 0 +#define THERM_CTRL2_LOW_MASK 0x000000ff +#define THERM_CTRL2_LOW_GET(x) (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB) +#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK) + +#define THERM_CTRL3_ADDRESS 0x000002e4 +#define THERM_CTRL3_OFFSET 0x000002e4 +#define THERM_CTRL3_ADC_GAIN_MSB 16 +#define THERM_CTRL3_ADC_GAIN_LSB 8 +#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00 +#define THERM_CTRL3_ADC_GAIN_GET(x) (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB) +#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK) +#define THERM_CTRL3_ADC_OFFSET_MSB 7 +#define THERM_CTRL3_ADC_OFFSET_LSB 0 +#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff +#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB) +#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK) + +#define LISTEN_MODE1_ADDRESS 0x000002e8 +#define LISTEN_MODE1_OFFSET 0x000002e8 +#define LISTEN_MODE1_TIMER_CLEAR_MSB 19 +#define LISTEN_MODE1_TIMER_CLEAR_LSB 19 +#define LISTEN_MODE1_TIMER_CLEAR_MASK 0x00080000 +#define LISTEN_MODE1_TIMER_CLEAR_GET(x) (((x) & LISTEN_MODE1_TIMER_CLEAR_MASK) >> LISTEN_MODE1_TIMER_CLEAR_LSB) +#define LISTEN_MODE1_TIMER_CLEAR_SET(x) (((x) << LISTEN_MODE1_TIMER_CLEAR_LSB) & LISTEN_MODE1_TIMER_CLEAR_MASK) +#define LISTEN_MODE1_TIMER_THRESH_WAKE_MSB 18 +#define LISTEN_MODE1_TIMER_THRESH_WAKE_LSB 3 +#define LISTEN_MODE1_TIMER_THRESH_WAKE_MASK 0x0007fff8 +#define LISTEN_MODE1_TIMER_THRESH_WAKE_GET(x) (((x) & LISTEN_MODE1_TIMER_THRESH_WAKE_MASK) >> LISTEN_MODE1_TIMER_THRESH_WAKE_LSB) +#define LISTEN_MODE1_TIMER_THRESH_WAKE_SET(x) (((x) << LISTEN_MODE1_TIMER_THRESH_WAKE_LSB) & LISTEN_MODE1_TIMER_THRESH_WAKE_MASK) +#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MSB 2 +#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB 2 +#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK 0x00000004 +#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_GET(x) (((x) & LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK) >> LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB) +#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_SET(x) (((x) << LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB) & LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK) +#define LISTEN_MODE1_CLOCK_GATE_MSB 1 +#define LISTEN_MODE1_CLOCK_GATE_LSB 1 +#define LISTEN_MODE1_CLOCK_GATE_MASK 0x00000002 +#define LISTEN_MODE1_CLOCK_GATE_GET(x) (((x) & LISTEN_MODE1_CLOCK_GATE_MASK) >> LISTEN_MODE1_CLOCK_GATE_LSB) +#define LISTEN_MODE1_CLOCK_GATE_SET(x) (((x) << LISTEN_MODE1_CLOCK_GATE_LSB) & LISTEN_MODE1_CLOCK_GATE_MASK) +#define LISTEN_MODE1_ENABLE_MSB 0 +#define LISTEN_MODE1_ENABLE_LSB 0 +#define LISTEN_MODE1_ENABLE_MASK 0x00000001 +#define LISTEN_MODE1_ENABLE_GET(x) (((x) & LISTEN_MODE1_ENABLE_MASK) >> LISTEN_MODE1_ENABLE_LSB) +#define LISTEN_MODE1_ENABLE_SET(x) (((x) << LISTEN_MODE1_ENABLE_LSB) & LISTEN_MODE1_ENABLE_MASK) + +#define LISTEN_MODE2_ADDRESS 0x000002ec +#define LISTEN_MODE2_OFFSET 0x000002ec +#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_MSB 15 +#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB 0 +#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK 0x0000ffff +#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_GET(x) (((x) & LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK) >> LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB) +#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_SET(x) (((x) << LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB) & LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK) + +#define AUDIO_PLL_CONFIG_ADDRESS 0x000002f0 +#define AUDIO_PLL_CONFIG_OFFSET 0x000002f0 +#define AUDIO_PLL_CONFIG_UPDATING_MSB 31 +#define AUDIO_PLL_CONFIG_UPDATING_LSB 31 +#define AUDIO_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define AUDIO_PLL_CONFIG_UPDATING_GET(x) (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB) +#define AUDIO_PLL_CONFIG_UPDATING_SET(x) (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK) +#define AUDIO_PLL_CONFIG_EXT_DIV_MSB 14 +#define AUDIO_PLL_CONFIG_EXT_DIV_LSB 12 +#define AUDIO_PLL_CONFIG_EXT_DIV_MASK 0x00007000 +#define AUDIO_PLL_CONFIG_EXT_DIV_GET(x) (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB) +#define AUDIO_PLL_CONFIG_EXT_DIV_SET(x) (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) +#define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB 9 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB 7 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK 0x00000380 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) +#define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) +#define AUDIO_PLL_CONFIG_PLLPWD_MSB 5 +#define AUDIO_PLL_CONFIG_PLLPWD_LSB 5 +#define AUDIO_PLL_CONFIG_PLLPWD_MASK 0x00000020 +#define AUDIO_PLL_CONFIG_PLLPWD_GET(x) (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB) +#define AUDIO_PLL_CONFIG_PLLPWD_SET(x) (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK) +#define AUDIO_PLL_CONFIG_BYPASS_MSB 4 +#define AUDIO_PLL_CONFIG_BYPASS_LSB 4 +#define AUDIO_PLL_CONFIG_BYPASS_MASK 0x00000010 +#define AUDIO_PLL_CONFIG_BYPASS_GET(x) (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB) +#define AUDIO_PLL_CONFIG_BYPASS_SET(x) (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK) +#define AUDIO_PLL_CONFIG_REFDIV_MSB 3 +#define AUDIO_PLL_CONFIG_REFDIV_LSB 0 +#define AUDIO_PLL_CONFIG_REFDIV_MASK 0x0000000f +#define AUDIO_PLL_CONFIG_REFDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB) +#define AUDIO_PLL_CONFIG_REFDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK) + +#define AUDIO_PLL_MODULATION_ADDRESS 0x000002f4 +#define AUDIO_PLL_MODULATION_OFFSET 0x000002f4 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB 28 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB 11 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK 0x1ffff800 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB 6 +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB 1 +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK 0x0000007e +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) +#define AUDIO_PLL_MODULATION_START_MSB 0 +#define AUDIO_PLL_MODULATION_START_LSB 0 +#define AUDIO_PLL_MODULATION_START_MASK 0x00000001 +#define AUDIO_PLL_MODULATION_START_GET(x) (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB) +#define AUDIO_PLL_MODULATION_START_SET(x) (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK) + +#define AUDIO_PLL_MOD_STEP_ADDRESS 0x000002f8 +#define AUDIO_PLL_MOD_STEP_OFFSET 0x000002f8 +#define AUDIO_PLL_MOD_STEP_FRAC_MSB 31 +#define AUDIO_PLL_MOD_STEP_FRAC_LSB 14 +#define AUDIO_PLL_MOD_STEP_FRAC_MASK 0xffffc000 +#define AUDIO_PLL_MOD_STEP_FRAC_GET(x) (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB) +#define AUDIO_PLL_MOD_STEP_FRAC_SET(x) (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK) +#define AUDIO_PLL_MOD_STEP_INT_MSB 13 +#define AUDIO_PLL_MOD_STEP_INT_LSB 4 +#define AUDIO_PLL_MOD_STEP_INT_MASK 0x00003ff0 +#define AUDIO_PLL_MOD_STEP_INT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB) +#define AUDIO_PLL_MOD_STEP_INT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK) +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB 3 +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB 0 +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK 0x0000000f +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) + +#define CURRENT_AUDIO_PLL_MODULATION_ADDRESS 0x000002fc +#define CURRENT_AUDIO_PLL_MODULATION_OFFSET 0x000002fc +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB 27 +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB 10 +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK 0x0ffffc00 +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) +#define CURRENT_AUDIO_PLL_MODULATION_INT_MSB 6 +#define CURRENT_AUDIO_PLL_MODULATION_INT_LSB 1 +#define CURRENT_AUDIO_PLL_MODULATION_INT_MASK 0x0000007e +#define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB) +#define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) + +#define ETH_PLL_CONFIG_ADDRESS 0x00000300 +#define ETH_PLL_CONFIG_OFFSET 0x00000300 +#define ETH_PLL_CONFIG_GE0_MASTER_MSB 30 +#define ETH_PLL_CONFIG_GE0_MASTER_LSB 30 +#define ETH_PLL_CONFIG_GE0_MASTER_MASK 0x40000000 +#define ETH_PLL_CONFIG_GE0_MASTER_GET(x) (((x) & ETH_PLL_CONFIG_GE0_MASTER_MASK) >> ETH_PLL_CONFIG_GE0_MASTER_LSB) +#define ETH_PLL_CONFIG_GE0_MASTER_SET(x) (((x) << ETH_PLL_CONFIG_GE0_MASTER_LSB) & ETH_PLL_CONFIG_GE0_MASTER_MASK) +#define ETH_PLL_CONFIG_GE0_MSB 29 +#define ETH_PLL_CONFIG_GE0_LSB 29 +#define ETH_PLL_CONFIG_GE0_MASK 0x20000000 +#define ETH_PLL_CONFIG_GE0_GET(x) (((x) & ETH_PLL_CONFIG_GE0_MASK) >> ETH_PLL_CONFIG_GE0_LSB) +#define ETH_PLL_CONFIG_GE0_SET(x) (((x) << ETH_PLL_CONFIG_GE0_LSB) & ETH_PLL_CONFIG_GE0_MASK) +#define ETH_PLL_CONFIG_RANGE_MSB 28 +#define ETH_PLL_CONFIG_RANGE_LSB 28 +#define ETH_PLL_CONFIG_RANGE_MASK 0x10000000 +#define ETH_PLL_CONFIG_RANGE_GET(x) (((x) & ETH_PLL_CONFIG_RANGE_MASK) >> ETH_PLL_CONFIG_RANGE_LSB) +#define ETH_PLL_CONFIG_RANGE_SET(x) (((x) << ETH_PLL_CONFIG_RANGE_LSB) & ETH_PLL_CONFIG_RANGE_MASK) +#define ETH_PLL_CONFIG_FRAC_MSB 27 +#define ETH_PLL_CONFIG_FRAC_LSB 18 +#define ETH_PLL_CONFIG_FRAC_MASK 0x0ffc0000 +#define ETH_PLL_CONFIG_FRAC_GET(x) (((x) & ETH_PLL_CONFIG_FRAC_MASK) >> ETH_PLL_CONFIG_FRAC_LSB) +#define ETH_PLL_CONFIG_FRAC_SET(x) (((x) << ETH_PLL_CONFIG_FRAC_LSB) & ETH_PLL_CONFIG_FRAC_MASK) +#define ETH_PLL_CONFIG_INT_MSB 17 +#define ETH_PLL_CONFIG_INT_LSB 12 +#define ETH_PLL_CONFIG_INT_MASK 0x0003f000 +#define ETH_PLL_CONFIG_INT_GET(x) (((x) & ETH_PLL_CONFIG_INT_MASK) >> ETH_PLL_CONFIG_INT_LSB) +#define ETH_PLL_CONFIG_INT_SET(x) (((x) << ETH_PLL_CONFIG_INT_LSB) & ETH_PLL_CONFIG_INT_MASK) +#define ETH_PLL_CONFIG_OUTDIV_MSB 9 +#define ETH_PLL_CONFIG_OUTDIV_LSB 7 +#define ETH_PLL_CONFIG_OUTDIV_MASK 0x00000380 +#define ETH_PLL_CONFIG_OUTDIV_GET(x) (((x) & ETH_PLL_CONFIG_OUTDIV_MASK) >> ETH_PLL_CONFIG_OUTDIV_LSB) +#define ETH_PLL_CONFIG_OUTDIV_SET(x) (((x) << ETH_PLL_CONFIG_OUTDIV_LSB) & ETH_PLL_CONFIG_OUTDIV_MASK) +#define ETH_PLL_CONFIG_PLLPWD_MSB 6 +#define ETH_PLL_CONFIG_PLLPWD_LSB 6 +#define ETH_PLL_CONFIG_PLLPWD_MASK 0x00000040 +#define ETH_PLL_CONFIG_PLLPWD_GET(x) (((x) & ETH_PLL_CONFIG_PLLPWD_MASK) >> ETH_PLL_CONFIG_PLLPWD_LSB) +#define ETH_PLL_CONFIG_PLLPWD_SET(x) (((x) << ETH_PLL_CONFIG_PLLPWD_LSB) & ETH_PLL_CONFIG_PLLPWD_MASK) +#define ETH_PLL_CONFIG_BYPASS_MSB 5 +#define ETH_PLL_CONFIG_BYPASS_LSB 5 +#define ETH_PLL_CONFIG_BYPASS_MASK 0x00000020 +#define ETH_PLL_CONFIG_BYPASS_GET(x) (((x) & ETH_PLL_CONFIG_BYPASS_MASK) >> ETH_PLL_CONFIG_BYPASS_LSB) +#define ETH_PLL_CONFIG_BYPASS_SET(x) (((x) << ETH_PLL_CONFIG_BYPASS_LSB) & ETH_PLL_CONFIG_BYPASS_MASK) +#define ETH_PLL_CONFIG_REFDIV_MSB 4 +#define ETH_PLL_CONFIG_REFDIV_LSB 0 +#define ETH_PLL_CONFIG_REFDIV_MASK 0x0000001f +#define ETH_PLL_CONFIG_REFDIV_GET(x) (((x) & ETH_PLL_CONFIG_REFDIV_MASK) >> ETH_PLL_CONFIG_REFDIV_LSB) +#define ETH_PLL_CONFIG_REFDIV_SET(x) (((x) << ETH_PLL_CONFIG_REFDIV_LSB) & ETH_PLL_CONFIG_REFDIV_MASK) + +#define CPU_PLL_CONFIG_ADDRESS 0x00000304 +#define CPU_PLL_CONFIG_OFFSET 0x00000304 +#define CPU_PLL_CONFIG_RANGE_MSB 28 +#define CPU_PLL_CONFIG_RANGE_LSB 28 +#define CPU_PLL_CONFIG_RANGE_MASK 0x10000000 +#define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB) +#define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK) +#define CPU_PLL_CONFIG_FRAC_MSB 25 +#define CPU_PLL_CONFIG_FRAC_LSB 20 +#define CPU_PLL_CONFIG_FRAC_MASK 0x03f00000 +#define CPU_PLL_CONFIG_FRAC_GET(x) (((x) & CPU_PLL_CONFIG_FRAC_MASK) >> CPU_PLL_CONFIG_FRAC_LSB) +#define CPU_PLL_CONFIG_FRAC_SET(x) (((x) << CPU_PLL_CONFIG_FRAC_LSB) & CPU_PLL_CONFIG_FRAC_MASK) +#define CPU_PLL_CONFIG_INT_MSB 17 +#define CPU_PLL_CONFIG_INT_LSB 12 +#define CPU_PLL_CONFIG_INT_MASK 0x0003f000 +#define CPU_PLL_CONFIG_INT_GET(x) (((x) & CPU_PLL_CONFIG_INT_MASK) >> CPU_PLL_CONFIG_INT_LSB) +#define CPU_PLL_CONFIG_INT_SET(x) (((x) << CPU_PLL_CONFIG_INT_LSB) & CPU_PLL_CONFIG_INT_MASK) +#define CPU_PLL_CONFIG_OUTDIV_MSB 9 +#define CPU_PLL_CONFIG_OUTDIV_LSB 7 +#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00000380 +#define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB) +#define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK) +#define CPU_PLL_CONFIG_PLLPWD_MSB 6 +#define CPU_PLL_CONFIG_PLLPWD_LSB 6 +#define CPU_PLL_CONFIG_PLLPWD_MASK 0x00000040 +#define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB) +#define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK) +#define CPU_PLL_CONFIG_REFDIV_MSB 4 +#define CPU_PLL_CONFIG_REFDIV_LSB 0 +#define CPU_PLL_CONFIG_REFDIV_MASK 0x0000001f +#define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB) +#define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK) + +#define BB_PLL_CONFIG_ADDRESS 0x00000308 +#define BB_PLL_CONFIG_OFFSET 0x00000308 +#define BB_PLL_CONFIG_FRAC_MSB 17 +#define BB_PLL_CONFIG_FRAC_LSB 0 +#define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff +#define BB_PLL_CONFIG_FRAC_GET(x) (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) +#define BB_PLL_CONFIG_FRAC_SET(x) (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) + +#define ETH_XMII_ADDRESS 0x0000030c +#define ETH_XMII_OFFSET 0x0000030c +#define ETH_XMII_TX_INVERT_MSB 31 +#define ETH_XMII_TX_INVERT_LSB 31 +#define ETH_XMII_TX_INVERT_MASK 0x80000000 +#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB) +#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK) +#define ETH_XMII_GIGE_QUAD_MSB 30 +#define ETH_XMII_GIGE_QUAD_LSB 30 +#define ETH_XMII_GIGE_QUAD_MASK 0x40000000 +#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB) +#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK) +#define ETH_XMII_RX_DELAY_MSB 29 +#define ETH_XMII_RX_DELAY_LSB 28 +#define ETH_XMII_RX_DELAY_MASK 0x30000000 +#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB) +#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK) +#define ETH_XMII_TX_DELAY_MSB 27 +#define ETH_XMII_TX_DELAY_LSB 26 +#define ETH_XMII_TX_DELAY_MASK 0x0c000000 +#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB) +#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK) +#define ETH_XMII_GIGE_MSB 25 +#define ETH_XMII_GIGE_LSB 25 +#define ETH_XMII_GIGE_MASK 0x02000000 +#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB) +#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK) +#define ETH_XMII_OFFSET_PHASE_MSB 24 +#define ETH_XMII_OFFSET_PHASE_LSB 24 +#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000 +#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB) +#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK) +#define ETH_XMII_OFFSET_COUNT_MSB 23 +#define ETH_XMII_OFFSET_COUNT_LSB 16 +#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000 +#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB) +#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK) +#define ETH_XMII_PHASE1_COUNT_MSB 15 +#define ETH_XMII_PHASE1_COUNT_LSB 8 +#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00 +#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB) +#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK) +#define ETH_XMII_PHASE0_COUNT_MSB 7 +#define ETH_XMII_PHASE0_COUNT_LSB 0 +#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff +#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB) +#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK) + +#define USB_PHY_CONFIG_ADDRESS 0x00000310 +#define USB_PHY_CONFIG_OFFSET 0x00000310 +#define USB_PHY_CONFIG_REFCLK_SEL_MSB 7 +#define USB_PHY_CONFIG_REFCLK_SEL_LSB 4 +#define USB_PHY_CONFIG_REFCLK_SEL_MASK 0x000000f0 +#define USB_PHY_CONFIG_REFCLK_SEL_GET(x) (((x) & USB_PHY_CONFIG_REFCLK_SEL_MASK) >> USB_PHY_CONFIG_REFCLK_SEL_LSB) +#define USB_PHY_CONFIG_REFCLK_SEL_SET(x) (((x) << USB_PHY_CONFIG_REFCLK_SEL_LSB) & USB_PHY_CONFIG_REFCLK_SEL_MASK) +#define USB_PHY_CONFIG_REFDIV_MSB 3 +#define USB_PHY_CONFIG_REFDIV_LSB 3 +#define USB_PHY_CONFIG_REFDIV_MASK 0x00000008 +#define USB_PHY_CONFIG_REFDIV_GET(x) (((x) & USB_PHY_CONFIG_REFDIV_MASK) >> USB_PHY_CONFIG_REFDIV_LSB) +#define USB_PHY_CONFIG_REFDIV_SET(x) (((x) << USB_PHY_CONFIG_REFDIV_LSB) & USB_PHY_CONFIG_REFDIV_MASK) +#define USB_PHY_CONFIG_TESTMODE_MSB 2 +#define USB_PHY_CONFIG_TESTMODE_LSB 2 +#define USB_PHY_CONFIG_TESTMODE_MASK 0x00000004 +#define USB_PHY_CONFIG_TESTMODE_GET(x) (((x) & USB_PHY_CONFIG_TESTMODE_MASK) >> USB_PHY_CONFIG_TESTMODE_LSB) +#define USB_PHY_CONFIG_TESTMODE_SET(x) (((x) << USB_PHY_CONFIG_TESTMODE_LSB) & USB_PHY_CONFIG_TESTMODE_MASK) +#define USB_PHY_CONFIG_PLL_PWD_MSB 1 +#define USB_PHY_CONFIG_PLL_PWD_LSB 1 +#define USB_PHY_CONFIG_PLL_PWD_MASK 0x00000002 +#define USB_PHY_CONFIG_PLL_PWD_GET(x) (((x) & USB_PHY_CONFIG_PLL_PWD_MASK) >> USB_PHY_CONFIG_PLL_PWD_LSB) +#define USB_PHY_CONFIG_PLL_PWD_SET(x) (((x) << USB_PHY_CONFIG_PLL_PWD_LSB) & USB_PHY_CONFIG_PLL_PWD_MASK) +#define USB_PHY_CONFIG_HOSTMODE_MSB 0 +#define USB_PHY_CONFIG_HOSTMODE_LSB 0 +#define USB_PHY_CONFIG_HOSTMODE_MASK 0x00000001 +#define USB_PHY_CONFIG_HOSTMODE_GET(x) (((x) & USB_PHY_CONFIG_HOSTMODE_MASK) >> USB_PHY_CONFIG_HOSTMODE_LSB) +#define USB_PHY_CONFIG_HOSTMODE_SET(x) (((x) << USB_PHY_CONFIG_HOSTMODE_LSB) & USB_PHY_CONFIG_HOSTMODE_MASK) + +#define USBCORE_CLK60M_ADDRESS 0x00000314 +#define USBCORE_CLK60M_OFFSET 0x00000314 +#define USBCORE_CLK60M_SEL_MSB 0 +#define USBCORE_CLK60M_SEL_LSB 0 +#define USBCORE_CLK60M_SEL_MASK 0x00000001 +#define USBCORE_CLK60M_SEL_GET(x) (((x) & USBCORE_CLK60M_SEL_MASK) >> USBCORE_CLK60M_SEL_LSB) +#define USBCORE_CLK60M_SEL_SET(x) (((x) << USBCORE_CLK60M_SEL_LSB) & USBCORE_CLK60M_SEL_MASK) + +#define USBPHY_UTMI_CLK_ADDRESS 0x00000318 +#define USBPHY_UTMI_CLK_OFFSET 0x00000318 +#define USBPHY_UTMI_CLK_EN_MSB 0 +#define USBPHY_UTMI_CLK_EN_LSB 0 +#define USBPHY_UTMI_CLK_EN_MASK 0x00000001 +#define USBPHY_UTMI_CLK_EN_GET(x) (((x) & USBPHY_UTMI_CLK_EN_MASK) >> USBPHY_UTMI_CLK_EN_LSB) +#define USBPHY_UTMI_CLK_EN_SET(x) (((x) << USBPHY_UTMI_CLK_EN_LSB) & USBPHY_UTMI_CLK_EN_MASK) + +#define USB_TXVALID_DLY_CONFIG_ADDRESS 0x0000031c +#define USB_TXVALID_DLY_CONFIG_OFFSET 0x0000031c +#define USB_TXVALID_DLY_CONFIG_UTMI16_MSB 7 +#define USB_TXVALID_DLY_CONFIG_UTMI16_LSB 4 +#define USB_TXVALID_DLY_CONFIG_UTMI16_MASK 0x000000f0 +#define USB_TXVALID_DLY_CONFIG_UTMI16_GET(x) (((x) & USB_TXVALID_DLY_CONFIG_UTMI16_MASK) >> USB_TXVALID_DLY_CONFIG_UTMI16_LSB) +#define USB_TXVALID_DLY_CONFIG_UTMI16_SET(x) (((x) << USB_TXVALID_DLY_CONFIG_UTMI16_LSB) & USB_TXVALID_DLY_CONFIG_UTMI16_MASK) +#define USB_TXVALID_DLY_CONFIG_UTMI8_MSB 3 +#define USB_TXVALID_DLY_CONFIG_UTMI8_LSB 0 +#define USB_TXVALID_DLY_CONFIG_UTMI8_MASK 0x0000000f +#define USB_TXVALID_DLY_CONFIG_UTMI8_GET(x) (((x) & USB_TXVALID_DLY_CONFIG_UTMI8_MASK) >> USB_TXVALID_DLY_CONFIG_UTMI8_LSB) +#define USB_TXVALID_DLY_CONFIG_UTMI8_SET(x) (((x) << USB_TXVALID_DLY_CONFIG_UTMI8_LSB) & USB_TXVALID_DLY_CONFIG_UTMI8_MASK) + +#define SECOND_HOST_INFT_ADDRESS 0x00000320 +#define SECOND_HOST_INFT_OFFSET 0x00000320 +#define SECOND_HOST_INFT_SDIO_MODE_MSB 0 +#define SECOND_HOST_INFT_SDIO_MODE_LSB 0 +#define SECOND_HOST_INFT_SDIO_MODE_MASK 0x00000001 +#define SECOND_HOST_INFT_SDIO_MODE_GET(x) (((x) & SECOND_HOST_INFT_SDIO_MODE_MASK) >> SECOND_HOST_INFT_SDIO_MODE_LSB) +#define SECOND_HOST_INFT_SDIO_MODE_SET(x) (((x) << SECOND_HOST_INFT_SDIO_MODE_LSB) & SECOND_HOST_INFT_SDIO_MODE_MASK) + +#define SDIO_HOST_ADDRESS 0x00000324 +#define SDIO_HOST_OFFSET 0x00000324 +#define SDIO_HOST_RESET_MSB 0 +#define SDIO_HOST_RESET_LSB 0 +#define SDIO_HOST_RESET_MASK 0x00000001 +#define SDIO_HOST_RESET_GET(x) (((x) & SDIO_HOST_RESET_MASK) >> SDIO_HOST_RESET_LSB) +#define SDIO_HOST_RESET_SET(x) (((x) << SDIO_HOST_RESET_LSB) & SDIO_HOST_RESET_MASK) + +#define ENTERPRISE_CONFIG_ADDRESS 0x00000328 +#define ENTERPRISE_CONFIG_OFFSET 0x00000328 +#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MSB 12 +#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB 12 +#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK 0x00001000 +#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_GET(x) (((x) & ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK) >> ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB) +#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_SET(x) (((x) << ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB) & ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK) +#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MSB 11 +#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB 11 +#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK 0x00000800 +#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_GET(x) (((x) & ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK) >> ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB) +#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_SET(x) (((x) << ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB) & ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK) +#define ENTERPRISE_CONFIG_STBC_DISABLE_MSB 10 +#define ENTERPRISE_CONFIG_STBC_DISABLE_LSB 10 +#define ENTERPRISE_CONFIG_STBC_DISABLE_MASK 0x00000400 +#define ENTERPRISE_CONFIG_STBC_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_STBC_DISABLE_MASK) >> ENTERPRISE_CONFIG_STBC_DISABLE_LSB) +#define ENTERPRISE_CONFIG_STBC_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_STBC_DISABLE_LSB) & ENTERPRISE_CONFIG_STBC_DISABLE_MASK) +#define ENTERPRISE_CONFIG_LDPC_DISABLE_MSB 9 +#define ENTERPRISE_CONFIG_LDPC_DISABLE_LSB 9 +#define ENTERPRISE_CONFIG_LDPC_DISABLE_MASK 0x00000200 +#define ENTERPRISE_CONFIG_LDPC_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LDPC_DISABLE_MASK) >> ENTERPRISE_CONFIG_LDPC_DISABLE_LSB) +#define ENTERPRISE_CONFIG_LDPC_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LDPC_DISABLE_LSB) & ENTERPRISE_CONFIG_LDPC_DISABLE_MASK) +#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MSB 8 +#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB 8 +#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK 0x00000100 +#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK) >> ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB) +#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB) & ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK) +#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MSB 7 +#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB 7 +#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK 0x00000080 +#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK) >> ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB) +#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB) & ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK) +#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_MSB 6 +#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB 6 +#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK 0x00000040 +#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK) >> ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB) +#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB) & ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK) +#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MSB 5 +#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB 5 +#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK 0x00000020 +#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK) >> ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB) +#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB) & ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK) +#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MSB 4 +#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB 4 +#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK 0x00000010 +#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK) >> ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB) +#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB) & ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK) +#define ENTERPRISE_CONFIG_TXBF_DISABLE_MSB 3 +#define ENTERPRISE_CONFIG_TXBF_DISABLE_LSB 3 +#define ENTERPRISE_CONFIG_TXBF_DISABLE_MASK 0x00000008 +#define ENTERPRISE_CONFIG_TXBF_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_TXBF_DISABLE_MASK) >> ENTERPRISE_CONFIG_TXBF_DISABLE_LSB) +#define ENTERPRISE_CONFIG_TXBF_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_TXBF_DISABLE_LSB) & ENTERPRISE_CONFIG_TXBF_DISABLE_MASK) +#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MSB 2 +#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB 2 +#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK 0x00000004 +#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK) >> ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB) +#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB) & ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK) +#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MSB 1 +#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB 1 +#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK 0x00000002 +#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK) >> ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB) +#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB) & ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK) +#define ENTERPRISE_CONFIG_LOCATION_DISABLE_MSB 0 +#define ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB 0 +#define ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK 0x00000001 +#define ENTERPRISE_CONFIG_LOCATION_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK) >> ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB) +#define ENTERPRISE_CONFIG_LOCATION_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB) & ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK) + +#define RTC_DEBUG_BUS_ADDRESS 0x0000032c +#define RTC_DEBUG_BUS_OFFSET 0x0000032c +#define RTC_DEBUG_BUS_SEL_MSB 0 +#define RTC_DEBUG_BUS_SEL_LSB 0 +#define RTC_DEBUG_BUS_SEL_MASK 0x00000001 +#define RTC_DEBUG_BUS_SEL_GET(x) (((x) & RTC_DEBUG_BUS_SEL_MASK) >> RTC_DEBUG_BUS_SEL_LSB) +#define RTC_DEBUG_BUS_SEL_SET(x) (((x) << RTC_DEBUG_BUS_SEL_LSB) & RTC_DEBUG_BUS_SEL_MASK) + +#define RTC_EXT_CLK_BUF_ADDRESS 0x00000330 +#define RTC_EXT_CLK_BUF_OFFSET 0x00000330 +#define RTC_EXT_CLK_BUF_EN_MSB 0 +#define RTC_EXT_CLK_BUF_EN_LSB 0 +#define RTC_EXT_CLK_BUF_EN_MASK 0x00000001 +#define RTC_EXT_CLK_BUF_EN_GET(x) (((x) & RTC_EXT_CLK_BUF_EN_MASK) >> RTC_EXT_CLK_BUF_EN_LSB) +#define RTC_EXT_CLK_BUF_EN_SET(x) (((x) << RTC_EXT_CLK_BUF_EN_LSB) & RTC_EXT_CLK_BUF_EN_MASK) + +#define WLAN_AHB_BRIDGE_TIMEOUT_ADDRESS 0x00000334 +#define WLAN_AHB_BRIDGE_TIMEOUT_OFFSET 0x00000334 +#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MSB 13 +#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB 0 +#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK 0x00003fff +#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_GET(x) (((x) & WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK) >> WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB) +#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_SET(x) (((x) << WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB) & WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK) + +#define WLAN_AHB_CONFIG_ADDRESS 0x00000338 +#define WLAN_AHB_CONFIG_OFFSET 0x00000338 +#define WLAN_AHB_CONFIG_MAX_BURST_16_MSB 2 +#define WLAN_AHB_CONFIG_MAX_BURST_16_LSB 2 +#define WLAN_AHB_CONFIG_MAX_BURST_16_MASK 0x00000004 +#define WLAN_AHB_CONFIG_MAX_BURST_16_GET(x) (((x) & WLAN_AHB_CONFIG_MAX_BURST_16_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_16_LSB) +#define WLAN_AHB_CONFIG_MAX_BURST_16_SET(x) (((x) << WLAN_AHB_CONFIG_MAX_BURST_16_LSB) & WLAN_AHB_CONFIG_MAX_BURST_16_MASK) +#define WLAN_AHB_CONFIG_MAX_BURST_8_MSB 1 +#define WLAN_AHB_CONFIG_MAX_BURST_8_LSB 1 +#define WLAN_AHB_CONFIG_MAX_BURST_8_MASK 0x00000002 +#define WLAN_AHB_CONFIG_MAX_BURST_8_GET(x) (((x) & WLAN_AHB_CONFIG_MAX_BURST_8_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_8_LSB) +#define WLAN_AHB_CONFIG_MAX_BURST_8_SET(x) (((x) << WLAN_AHB_CONFIG_MAX_BURST_8_LSB) & WLAN_AHB_CONFIG_MAX_BURST_8_MASK) +#define WLAN_AHB_CONFIG_MAX_BURST_4_MSB 0 +#define WLAN_AHB_CONFIG_MAX_BURST_4_LSB 0 +#define WLAN_AHB_CONFIG_MAX_BURST_4_MASK 0x00000001 +#define WLAN_AHB_CONFIG_MAX_BURST_4_GET(x) (((x) & WLAN_AHB_CONFIG_MAX_BURST_4_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_4_LSB) +#define WLAN_AHB_CONFIG_MAX_BURST_4_SET(x) (((x) << WLAN_AHB_CONFIG_MAX_BURST_4_LSB) & WLAN_AHB_CONFIG_MAX_BURST_4_MASK) + +#define RTC_AXI_AHB_BRIDGE_ADDRESS 0x0000033c +#define RTC_AXI_AHB_BRIDGE_OFFSET 0x0000033c +#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MSB 3 +#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB 3 +#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK 0x00000008 +#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK) >> RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB) +#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB) & RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK) +#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MSB 2 +#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB 2 +#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK 0x00000004 +#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK) >> RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB) +#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB) & RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK) +#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_MSB 1 +#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB 0 +#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK 0x00000003 +#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK) >> RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB) +#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB) & RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK) + +#define WLAN2BT_CPUCOM_INT_STS_ADDRESS 0x00000400 +#define WLAN2BT_CPUCOM_INT_STS_OFFSET 0x00000400 +#define WLAN2BT_CPUCOM_INT_STS_REG_MSB 31 +#define WLAN2BT_CPUCOM_INT_STS_REG_LSB 0 +#define WLAN2BT_CPUCOM_INT_STS_REG_MASK 0xffffffff +#define WLAN2BT_CPUCOM_INT_STS_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_STS_REG_MASK) >> WLAN2BT_CPUCOM_INT_STS_REG_LSB) +#define WLAN2BT_CPUCOM_INT_STS_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_STS_REG_LSB) & WLAN2BT_CPUCOM_INT_STS_REG_MASK) + +#define WLAN2BT_CPUCOM_INT_MASK_N_ADDRESS 0x00000404 +#define WLAN2BT_CPUCOM_INT_MASK_N_OFFSET 0x00000404 +#define WLAN2BT_CPUCOM_INT_MASK_N_REG_MSB 31 +#define WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB 0 +#define WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK 0xffffffff +#define WLAN2BT_CPUCOM_INT_MASK_N_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK) >> WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB) +#define WLAN2BT_CPUCOM_INT_MASK_N_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB) & WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK) + +#define WLAN2BT_CPUCOM_INT_EOI_ADDRESS 0x00000408 +#define WLAN2BT_CPUCOM_INT_EOI_OFFSET 0x00000408 +#define WLAN2BT_CPUCOM_INT_EOI_REG_MSB 31 +#define WLAN2BT_CPUCOM_INT_EOI_REG_LSB 0 +#define WLAN2BT_CPUCOM_INT_EOI_REG_MASK 0xffffffff +#define WLAN2BT_CPUCOM_INT_EOI_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_EOI_REG_MASK) >> WLAN2BT_CPUCOM_INT_EOI_REG_LSB) +#define WLAN2BT_CPUCOM_INT_EOI_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_EOI_REG_LSB) & WLAN2BT_CPUCOM_INT_EOI_REG_MASK) + +#define WLAN2BT_CPUCOM_INT_ACK_STS_ADDRESS 0x0000040c +#define WLAN2BT_CPUCOM_INT_ACK_STS_OFFSET 0x0000040c +#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_MSB 31 +#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB 0 +#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK 0xffffffff +#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB) +#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK) + +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_ADDRESS 0x00000410 +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_OFFSET 0x00000410 +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MSB 31 +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB 0 +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK 0xffffffff +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB) +#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK) + +#define WLAN_CPUCOM_CRD_CNT0_ADDRESS 0x00000414 +#define WLAN_CPUCOM_CRD_CNT0_OFFSET 0x00000414 +#define WLAN_CPUCOM_CRD_CNT0_REG_MSB 15 +#define WLAN_CPUCOM_CRD_CNT0_REG_LSB 0 +#define WLAN_CPUCOM_CRD_CNT0_REG_MASK 0x0000ffff +#define WLAN_CPUCOM_CRD_CNT0_REG_GET(x) (((x) & WLAN_CPUCOM_CRD_CNT0_REG_MASK) >> WLAN_CPUCOM_CRD_CNT0_REG_LSB) +#define WLAN_CPUCOM_CRD_CNT0_REG_SET(x) (((x) << WLAN_CPUCOM_CRD_CNT0_REG_LSB) & WLAN_CPUCOM_CRD_CNT0_REG_MASK) + +#define WLAN_CPUCOM_CRD_INC0_ADDRESS 0x00000418 +#define WLAN_CPUCOM_CRD_INC0_OFFSET 0x00000418 +#define WLAN_CPUCOM_CRD_INC0_REG_MSB 15 +#define WLAN_CPUCOM_CRD_INC0_REG_LSB 0 +#define WLAN_CPUCOM_CRD_INC0_REG_MASK 0x0000ffff +#define WLAN_CPUCOM_CRD_INC0_REG_GET(x) (((x) & WLAN_CPUCOM_CRD_INC0_REG_MASK) >> WLAN_CPUCOM_CRD_INC0_REG_LSB) +#define WLAN_CPUCOM_CRD_INC0_REG_SET(x) (((x) << WLAN_CPUCOM_CRD_INC0_REG_LSB) & WLAN_CPUCOM_CRD_INC0_REG_MASK) + +#define WLAN_CPUCOM_CRD_DEC0_ADDRESS 0x0000041c +#define WLAN_CPUCOM_CRD_DEC0_OFFSET 0x0000041c +#define WLAN_CPUCOM_CRD_DEC0_REG_MSB 15 +#define WLAN_CPUCOM_CRD_DEC0_REG_LSB 0 +#define WLAN_CPUCOM_CRD_DEC0_REG_MASK 0x0000ffff +#define WLAN_CPUCOM_CRD_DEC0_REG_GET(x) (((x) & WLAN_CPUCOM_CRD_DEC0_REG_MASK) >> WLAN_CPUCOM_CRD_DEC0_REG_LSB) +#define WLAN_CPUCOM_CRD_DEC0_REG_SET(x) (((x) << WLAN_CPUCOM_CRD_DEC0_REG_LSB) & WLAN_CPUCOM_CRD_DEC0_REG_MASK) + +#define WLAN_CPUCOM_CRD_CNT1_ADDRESS 0x00000420 +#define WLAN_CPUCOM_CRD_CNT1_OFFSET 0x00000420 +#define WLAN_CPUCOM_CRD_CNT1_REG_MSB 15 +#define WLAN_CPUCOM_CRD_CNT1_REG_LSB 0 +#define WLAN_CPUCOM_CRD_CNT1_REG_MASK 0x0000ffff +#define WLAN_CPUCOM_CRD_CNT1_REG_GET(x) (((x) & WLAN_CPUCOM_CRD_CNT1_REG_MASK) >> WLAN_CPUCOM_CRD_CNT1_REG_LSB) +#define WLAN_CPUCOM_CRD_CNT1_REG_SET(x) (((x) << WLAN_CPUCOM_CRD_CNT1_REG_LSB) & WLAN_CPUCOM_CRD_CNT1_REG_MASK) + +#define WLAN_CPUCOM_CRD_INC1_ADDRESS 0x00000424 +#define WLAN_CPUCOM_CRD_INC1_OFFSET 0x00000424 +#define WLAN_CPUCOM_CRD_INC1_REG_MSB 15 +#define WLAN_CPUCOM_CRD_INC1_REG_LSB 0 +#define WLAN_CPUCOM_CRD_INC1_REG_MASK 0x0000ffff +#define WLAN_CPUCOM_CRD_INC1_REG_GET(x) (((x) & WLAN_CPUCOM_CRD_INC1_REG_MASK) >> WLAN_CPUCOM_CRD_INC1_REG_LSB) +#define WLAN_CPUCOM_CRD_INC1_REG_SET(x) (((x) << WLAN_CPUCOM_CRD_INC1_REG_LSB) & WLAN_CPUCOM_CRD_INC1_REG_MASK) + +#define WLAN_CPUCOM_CRD_DEC1_ADDRESS 0x00000428 +#define WLAN_CPUCOM_CRD_DEC1_OFFSET 0x00000428 +#define WLAN_CPUCOM_CRD_DEC1_REG_MSB 15 +#define WLAN_CPUCOM_CRD_DEC1_REG_LSB 0 +#define WLAN_CPUCOM_CRD_DEC1_REG_MASK 0x0000ffff +#define WLAN_CPUCOM_CRD_DEC1_REG_GET(x) (((x) & WLAN_CPUCOM_CRD_DEC1_REG_MASK) >> WLAN_CPUCOM_CRD_DEC1_REG_LSB) +#define WLAN_CPUCOM_CRD_DEC1_REG_SET(x) (((x) << WLAN_CPUCOM_CRD_DEC1_REG_LSB) & WLAN_CPUCOM_CRD_DEC1_REG_MASK) + +#define WLAN_CPUCOM_SCRATCH0_ADDRESS 0x0000042c +#define WLAN_CPUCOM_SCRATCH0_OFFSET 0x0000042c +#define WLAN_CPUCOM_SCRATCH0_REG_MSB 31 +#define WLAN_CPUCOM_SCRATCH0_REG_LSB 0 +#define WLAN_CPUCOM_SCRATCH0_REG_MASK 0xffffffff +#define WLAN_CPUCOM_SCRATCH0_REG_GET(x) (((x) & WLAN_CPUCOM_SCRATCH0_REG_MASK) >> WLAN_CPUCOM_SCRATCH0_REG_LSB) +#define WLAN_CPUCOM_SCRATCH0_REG_SET(x) (((x) << WLAN_CPUCOM_SCRATCH0_REG_LSB) & WLAN_CPUCOM_SCRATCH0_REG_MASK) + +#define WLAN_CPUCOM_SCRATCH1_ADDRESS 0x00000430 +#define WLAN_CPUCOM_SCRATCH1_OFFSET 0x00000430 +#define WLAN_CPUCOM_SCRATCH1_REG_MSB 31 +#define WLAN_CPUCOM_SCRATCH1_REG_LSB 0 +#define WLAN_CPUCOM_SCRATCH1_REG_MASK 0xffffffff +#define WLAN_CPUCOM_SCRATCH1_REG_GET(x) (((x) & WLAN_CPUCOM_SCRATCH1_REG_MASK) >> WLAN_CPUCOM_SCRATCH1_REG_LSB) +#define WLAN_CPUCOM_SCRATCH1_REG_SET(x) (((x) << WLAN_CPUCOM_SCRATCH1_REG_LSB) & WLAN_CPUCOM_SCRATCH1_REG_MASK) + +#define WLAN_CPUCOM_SCRATCH2_ADDRESS 0x00000434 +#define WLAN_CPUCOM_SCRATCH2_OFFSET 0x00000434 +#define WLAN_CPUCOM_SCRATCH2_REG_MSB 31 +#define WLAN_CPUCOM_SCRATCH2_REG_LSB 0 +#define WLAN_CPUCOM_SCRATCH2_REG_MASK 0xffffffff +#define WLAN_CPUCOM_SCRATCH2_REG_GET(x) (((x) & WLAN_CPUCOM_SCRATCH2_REG_MASK) >> WLAN_CPUCOM_SCRATCH2_REG_LSB) +#define WLAN_CPUCOM_SCRATCH2_REG_SET(x) (((x) << WLAN_CPUCOM_SCRATCH2_REG_LSB) & WLAN_CPUCOM_SCRATCH2_REG_MASK) + +#define WLAN_CPUCOM_SCRATCH3_ADDRESS 0x00000438 +#define WLAN_CPUCOM_SCRATCH3_OFFSET 0x00000438 +#define WLAN_CPUCOM_SCRATCH3_REG_MSB 31 +#define WLAN_CPUCOM_SCRATCH3_REG_LSB 0 +#define WLAN_CPUCOM_SCRATCH3_REG_MASK 0xffffffff +#define WLAN_CPUCOM_SCRATCH3_REG_GET(x) (((x) & WLAN_CPUCOM_SCRATCH3_REG_MASK) >> WLAN_CPUCOM_SCRATCH3_REG_LSB) +#define WLAN_CPUCOM_SCRATCH3_REG_SET(x) (((x) << WLAN_CPUCOM_SCRATCH3_REG_LSB) & WLAN_CPUCOM_SCRATCH3_REG_MASK) + +#define WLAN_CPUCOM_DBG_ADDRESS 0x0000043c +#define WLAN_CPUCOM_DBG_OFFSET 0x0000043c +#define WLAN_CPUCOM_DBG_RESERVE_MSB 7 +#define WLAN_CPUCOM_DBG_RESERVE_LSB 4 +#define WLAN_CPUCOM_DBG_RESERVE_MASK 0x000000f0 +#define WLAN_CPUCOM_DBG_RESERVE_GET(x) (((x) & WLAN_CPUCOM_DBG_RESERVE_MASK) >> WLAN_CPUCOM_DBG_RESERVE_LSB) +#define WLAN_CPUCOM_DBG_RESERVE_SET(x) (((x) << WLAN_CPUCOM_DBG_RESERVE_LSB) & WLAN_CPUCOM_DBG_RESERVE_MASK) +#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MSB 3 +#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB 3 +#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK 0x00000008 +#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_GET(x) (((x) & WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB) +#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_SET(x) (((x) << WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK) +#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_MSB 2 +#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB 2 +#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK 0x00000004 +#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_GET(x) (((x) & WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB) +#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_SET(x) (((x) << WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK) +#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MSB 1 +#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB 1 +#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK 0x00000002 +#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_GET(x) (((x) & WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB) +#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_SET(x) (((x) << WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK) +#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_MSB 0 +#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB 0 +#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK 0x00000001 +#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_GET(x) (((x) & WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB) +#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_SET(x) (((x) << WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK) + +#define WLAN2BT_CPUCOM_INT_ACK_EN_ADDRESS 0x00000440 +#define WLAN2BT_CPUCOM_INT_ACK_EN_OFFSET 0x00000440 +#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_MSB 0 +#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB 0 +#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK 0x00000001 +#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB) +#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK) + +#define BT2WLAN_CPUCOM_INT_EN_ADDRESS 0x00000444 +#define BT2WLAN_CPUCOM_INT_EN_OFFSET 0x00000444 +#define BT2WLAN_CPUCOM_INT_EN_REG_MSB 0 +#define BT2WLAN_CPUCOM_INT_EN_REG_LSB 0 +#define BT2WLAN_CPUCOM_INT_EN_REG_MASK 0x00000001 +#define BT2WLAN_CPUCOM_INT_EN_REG_GET(x) (((x) & BT2WLAN_CPUCOM_INT_EN_REG_MASK) >> BT2WLAN_CPUCOM_INT_EN_REG_LSB) +#define BT2WLAN_CPUCOM_INT_EN_REG_SET(x) (((x) << BT2WLAN_CPUCOM_INT_EN_REG_LSB) & BT2WLAN_CPUCOM_INT_EN_REG_MASK) + +#ifndef __ASSEMBLER__ +typedef struct rtc_soc_reg_reg_s { + volatile unsigned int soc_reset_control; + volatile unsigned int soc_tcxo_detect; + volatile unsigned int soc_xtal_test; + unsigned char pad0[20]; /* pad to 0x20 */ + volatile unsigned int soc_cpu_clock; + unsigned char pad1[4]; /* pad to 0x28 */ + volatile unsigned int soc_clock_control; + unsigned char pad2[4]; /* pad to 0x30 */ + volatile unsigned int soc_wdt_control; + volatile unsigned int soc_wdt_status; + volatile unsigned int soc_wdt; + volatile unsigned int soc_wdt_count; + volatile unsigned int soc_wdt_reset; + volatile unsigned int soc_int_status; + volatile unsigned int soc_lf_timer0; + volatile unsigned int soc_lf_timer_count0; + volatile unsigned int soc_lf_timer_control0; + volatile unsigned int soc_lf_timer_status0; + volatile unsigned int soc_lf_timer1; + volatile unsigned int soc_lf_timer_count1; + volatile unsigned int soc_lf_timer_control1; + volatile unsigned int soc_lf_timer_status1; + volatile unsigned int soc_lf_timer2; + volatile unsigned int soc_lf_timer_count2; + volatile unsigned int soc_lf_timer_control2; + volatile unsigned int soc_lf_timer_status2; + volatile unsigned int soc_lf_timer3; + volatile unsigned int soc_lf_timer_count3; + volatile unsigned int soc_lf_timer_control3; + volatile unsigned int soc_lf_timer_status3; + volatile unsigned int soc_hf_timer; + volatile unsigned int soc_hf_timer_count; + volatile unsigned int soc_hf_lf_count; + volatile unsigned int soc_hf_timer_control; + volatile unsigned int soc_hf_timer_status; + volatile unsigned int soc_rtc_control; + volatile unsigned int soc_rtc_time; + volatile unsigned int soc_rtc_date; + volatile unsigned int soc_rtc_set_time; + volatile unsigned int soc_rtc_set_date; + volatile unsigned int soc_rtc_set_alarm; + volatile unsigned int soc_rtc_config; + volatile unsigned int soc_rtc_alarm_status; + volatile unsigned int soc_uart_wakeup; + volatile unsigned int soc_reset_cause; + volatile unsigned int soc_system_sleep; + volatile unsigned int soc_sdio_wrapper; + volatile unsigned int soc_int_sleep_mask; + unsigned char pad3[4]; /* pad to 0xd4 */ + volatile unsigned int soc_lpo_cal_time; + volatile unsigned int soc_lpo_init_dividend_int; + volatile unsigned int soc_lpo_init_dividend_fraction; + volatile unsigned int soc_lpo_cal; + volatile unsigned int soc_lpo_cal_test_control; + volatile unsigned int soc_lpo_cal_test_status; + volatile unsigned int legacy_soc_chip_id; + volatile unsigned int soc_chip_id; + unsigned char pad4[24]; /* pad to 0x10c */ + volatile unsigned int soc_power_reg; + volatile unsigned int soc_core_clk_ctrl; + volatile unsigned int soc_gpio_wakeup_control; + unsigned char pad5[252]; /* pad to 0x214 */ + volatile unsigned int sleep_retention; + unsigned char pad6[108]; /* pad to 0x284 */ + volatile unsigned int lp_perf_counter; + volatile unsigned int lp_perf_light_sleep; + volatile unsigned int lp_perf_deep_sleep; + volatile unsigned int lp_perf_on; + unsigned char pad7[20]; /* pad to 0x2a8 */ + volatile unsigned int chip_mode; + volatile unsigned int clk_req_fall_edge; + volatile unsigned int otp; + volatile unsigned int otp_status; + volatile unsigned int pmu; + volatile unsigned int pmu_config; + volatile unsigned int pmu_pareg; + volatile unsigned int pmu_bypass; + unsigned char pad8[20]; /* pad to 0x2dc */ + volatile unsigned int therm_ctrl1; + volatile unsigned int therm_ctrl2; + volatile unsigned int therm_ctrl3; + volatile unsigned int listen_mode1; + volatile unsigned int listen_mode2; + volatile unsigned int audio_pll_config; + volatile unsigned int audio_pll_modulation; + volatile unsigned int audio_pll_mod_step; + volatile unsigned int current_audio_pll_modulation; + volatile unsigned int eth_pll_config; + volatile unsigned int cpu_pll_config; + volatile unsigned int bb_pll_config; + volatile unsigned int eth_xmii; + volatile unsigned int usb_phy_config; + volatile unsigned int usbcore_clk60m; + volatile unsigned int usbphy_utmi_clk; + volatile unsigned int usb_txvalid_dly_config; + volatile unsigned int second_host_inft; + volatile unsigned int sdio_host; + volatile unsigned int enterprise_config; + volatile unsigned int rtc_debug_bus; + volatile unsigned int rtc_ext_clk_buf; + volatile unsigned int wlan_ahb_bridge_timeout; + volatile unsigned int wlan_ahb_config; + volatile unsigned int rtc_axi_ahb_bridge; + unsigned char pad9[192]; /* pad to 0x400 */ + volatile unsigned int wlan2bt_cpucom_int_sts; + volatile unsigned int wlan2bt_cpucom_int_mask_n; + volatile unsigned int wlan2bt_cpucom_int_eoi; + volatile unsigned int wlan2bt_cpucom_int_ack_sts; + volatile unsigned int wlan2bt_cpucom_int_ack_mask_n; + volatile unsigned int wlan_cpucom_crd_cnt0; + volatile unsigned int wlan_cpucom_crd_inc0[1]; + volatile unsigned int wlan_cpucom_crd_dec0[1]; + volatile unsigned int wlan_cpucom_crd_cnt1; + volatile unsigned int wlan_cpucom_crd_inc1[1]; + volatile unsigned int wlan_cpucom_crd_dec1[1]; + volatile unsigned int wlan_cpucom_scratch0; + volatile unsigned int wlan_cpucom_scratch1; + volatile unsigned int wlan_cpucom_scratch2; + volatile unsigned int wlan_cpucom_scratch3; + volatile unsigned int wlan_cpucom_dbg; + volatile unsigned int wlan2bt_cpucom_int_ack_en; + volatile unsigned int bt2wlan_cpucom_int_en; +} rtc_soc_reg_reg_t; +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_SOC_REG_H_ */ diff --git a/fw/targaddrs.h b/fw/targaddrs.h old mode 100755 new mode 100644 index 98d4b20ed02f..13e1a7136d71 --- a/fw/targaddrs.h +++ b/fw/targaddrs.h @@ -42,14 +42,14 @@ * AR6004: These bits can be set in LOCAL_SCRATCH register 0. * AR9888: These bits can be set in soc_core register SCRATCH_0. */ -#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ -#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ -#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ -#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ -#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ -#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ -#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ -#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ +#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ /* * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the @@ -80,10 +80,6 @@ #endif #define AR6006_SOC_RESET_ADDRESS 0X00004000 #define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800 -#define QCA9984_HOST_INTEREST_ADDRESS 0x00400800 -#define IPQ4019_HOST_INTEREST_ADDRESS 0x00400800 -#define QCA9888_HOST_INTEREST_ADDRESS 0x00400800 - #define HOST_INTEREST_MAX_SIZE 0x200 @@ -103,20 +99,20 @@ struct dbglog_hdr_s; * More items may be added at the end. */ PREPACK64 struct host_interest_s { - /* - * Pointer to application-defined area, if any. - * Set by Target application during startup. - */ - A_UINT32 hi_app_host_interest; /* 0x00 */ + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ - /* Pointer to register dump area, valid after Target crash. */ - A_UINT32 hi_failure_state; /* 0x04 */ + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ - /* Pointer to debug logging header */ - A_UINT32 hi_dbglog_hdr; /* 0x08 */ + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ - /* Save SW ROM version */ - A_UINT32 hi_sw_rom_version; /* 0x0c */ + /* Save SW ROM version */ + A_UINT32 hi_sw_rom_version; /* 0x0c */ /* * General-purpose flag bits, similar to SOC_OPTION_* flags. @@ -124,161 +120,161 @@ PREPACK64 struct host_interest_s { */ volatile A_UINT32 hi_option_flag; /* 0x10 */ - /* - * Boolean that determines whether or not to - * display messages on the serial port. - */ - A_UINT32 hi_serial_enable; /* 0x14 */ + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ - /* Start address of DataSet index, if any */ - A_UINT32 hi_dset_list_head; /* 0x18 */ + /* Start address of DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ - /* Override Target application start address */ - A_UINT32 hi_app_start; /* 0x1c */ + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ - /* Clock and voltage tuning */ - A_UINT32 hi_skip_clock_init; /* 0x20 */ - A_UINT32 hi_core_clock_setting; /* 0x24 */ - A_UINT32 hi_cpu_clock_setting; /* 0x28 */ - A_UINT32 hi_system_sleep_setting; /* 0x2c */ - A_UINT32 hi_xtal_control_setting; /* 0x30 */ - A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ - A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ - A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ - A_UINT32 hi_clock_info; /* 0x40 */ + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ - /* Host uses BE CPU or not */ - A_UINT32 hi_be; /* 0x44 */ + /* Host uses BE CPU or not */ + A_UINT32 hi_be; /* 0x44 */ - A_UINT32 hi_stack; /* normal stack */ /* 0x48 */ - A_UINT32 hi_err_stack; /* error stack */ /* 0x4c */ - A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */ + A_UINT32 hi_stack; /* normal stack *//* 0x48 */ + A_UINT32 hi_err_stack; /* error stack *//* 0x4c */ + A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */ - /* Pointer to Board Data */ - A_UINT32 hi_board_data; /* 0x54 */ + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ - /* - * Indication of Board Data state: - * 0: board data is not yet initialized. - * 1: board data is initialized; unknown size - * >1: number of bytes of initialized board data (varies with board type) - */ - A_UINT32 hi_board_data_initialized; /* 0x58 */ + /* + * Indication of Board Data state: + * 0: board data is not yet initialized. + * 1: board data is initialized; unknown size + * >1: number of bytes of initialized board data (varies with board type) + */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ - A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ - A_UINT32 hi_desired_baud_rate; /* 0x60 */ - A_UINT32 hi_dbglog_config; /* 0x64 */ - A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ - A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ - A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ - A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ - A_UINT32 hi_refclk_hz; /* 0x78 */ - A_UINT32 hi_ext_clk_detected; /* 0x7c */ - A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ - A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ - A_UINT32 hi_hci_uart_baud; /* 0x88 */ - A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ - /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ - A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ - A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ + A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ + A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ + A_UINT32 hi_hci_uart_baud; /* 0x88 */ + A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ + /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ + A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ + A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ - A_UINT32 hi_allocram_start; /* 0x98 */ - A_UINT32 hi_allocram_sz; /* 0x9c */ - A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ - A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ - /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ - A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ - /* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high - * [31:16]: wakeup timeout in ms - */ - /* Pointer to extended board Data */ - A_UINT32 hi_board_ext_data; /* 0xac */ - A_UINT32 hi_board_ext_data_config; /* 0xb0 */ - /* - * Bit [0] : valid - * Bit[31:16: size - */ - /* - * hi_reset_flag is used to do some stuff when target reset. - * such as restore app_start after warm reset or - * preserve host Interest area, or preserve ROM data, literals etc. - */ - A_UINT32 hi_reset_flag; /* 0xb4 */ - /* indicate hi_reset_flag is valid */ - A_UINT32 hi_reset_flag_valid; /* 0xb8 */ - A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ - /* 0xbc - [31:0]: idle timeout in ms - */ - /* ACS flags */ - A_UINT32 hi_acs_flags; /* 0xc0 */ - A_UINT32 hi_console_flags; /* 0xc4 */ - A_UINT32 hi_nvram_state; /* 0xc8 */ - volatile A_UINT32 hi_option_flag2; /* 0xcc */ + A_UINT32 hi_allocram_start; /* 0x98 */ + A_UINT32 hi_allocram_sz; /* 0x9c */ + A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ + A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ + /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ + A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ + /* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high + * [31:16]: wakeup timeout in ms + */ + /* Pointer to extended board Data */ + A_UINT32 hi_board_ext_data; /* 0xac */ + A_UINT32 hi_board_ext_data_config; /* 0xb0 */ + /* + * Bit [0] : valid + * Bit[31:16: size + */ + /* + * hi_reset_flag is used to do some stuff when target reset. + * such as restore app_start after warm reset or + * preserve host Interest area, or preserve ROM data, literals etc. + */ + A_UINT32 hi_reset_flag; /* 0xb4 */ + /* indicate hi_reset_flag is valid */ + A_UINT32 hi_reset_flag_valid; /* 0xb8 */ + A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ + /* 0xbc - [31:0]: idle timeout in ms + */ + /* ACS flags */ + A_UINT32 hi_acs_flags; /* 0xc0 */ + A_UINT32 hi_console_flags; /* 0xc4 */ + A_UINT32 hi_nvram_state; /* 0xc8 */ + volatile A_UINT32 hi_option_flag2; /* 0xcc */ - /* If non-zero, override values sent to Host in WMI_READY event. */ - A_UINT32 hi_sw_version_override; /* 0xd0 */ - A_UINT32 hi_abi_version_override; /* 0xd4 */ + /* If non-zero, override values sent to Host in WMI_READY event. */ + A_UINT32 hi_sw_version_override; /* 0xd0 */ + A_UINT32 hi_abi_version_override; /* 0xd4 */ - /* Percentage of high priority RX traffic to total expected RX traffic - - * applicable only to ar6004 */ - A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */ + /* Percentage of high priority RX traffic to total expected RX traffic - + * applicable only to ar6004 */ + A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */ - /* test applications flags */ - A_UINT32 hi_test_apps_related ; /* 0xdc */ - /* location of test script */ - A_UINT32 hi_ota_testscript; /* 0xe0 */ - /* location of CAL data */ - A_UINT32 hi_cal_data; /* 0xe4 */ + /* test applications flags */ + A_UINT32 hi_test_apps_related; /* 0xdc */ + /* location of test script */ + A_UINT32 hi_ota_testscript; /* 0xe0 */ + /* location of CAL data */ + A_UINT32 hi_cal_data; /* 0xe4 */ /* Number of packet log buffers */ volatile A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */ - /* wow extension configuration */ - A_UINT32 hi_wow_ext_config; /* 0xec */ - A_UINT32 hi_pwr_save_flags; /* 0xf0 */ + /* wow extension configuration */ + A_UINT32 hi_wow_ext_config; /* 0xec */ + A_UINT32 hi_pwr_save_flags; /* 0xf0 */ - /* Spatial Multiplexing Power Save (SMPS) options */ - A_UINT32 hi_smps_options; /* 0xf4 */ + /* Spatial Multiplexing Power Save (SMPS) options */ + A_UINT32 hi_smps_options; /* 0xf4 */ - /* Interconnect-specific state */ - A_UINT32 hi_interconnect_state; /* 0xf8 */ + /* Interconnect-specific state */ + A_UINT32 hi_interconnect_state; /* 0xf8 */ - /* Coex configuration flags */ - A_UINT32 hi_coex_config; /* 0xfc */ + /* Coex configuration flags */ + A_UINT32 hi_coex_config; /* 0xfc */ - /* Early allocation support */ - A_UINT32 hi_early_alloc; /* 0x100 */ + /* Early allocation support */ + A_UINT32 hi_early_alloc; /* 0x100 */ - /* FW swap field */ - /* Bits of this 32bit word will be used to pass specific swap - instruction to FW */ - /* Bit 0 -- AP Nart descriptor no swap. When this bit is set - FW will not swap TX descriptor. Meaning packets are formed - on the target processor.*/ - /* Bit 1 -- TBD */ + /* FW swap field */ + /* Bits of this 32bit word will be used to pass specific swap + instruction to FW */ + /* Bit 0 -- AP Nart descriptor no swap. When this bit is set + FW will not swap TX descriptor. Meaning packets are formed + on the target processor. */ + /* Bit 1 -- TBD */ - A_UINT32 hi_fw_swap; /* 0x104 */ + A_UINT32 hi_fw_swap; /* 0x104 */ - /* global arenas pointer address, used by host driver debug */ - A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */ + /* global arenas pointer address, used by host driver debug */ + A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */ - /* allocated bytes of DRAM use by allocated */ - A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */ + /* allocated bytes of DRAM use by allocated */ + A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */ - /* remaining bytes of DRAM */ - A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */ + /* remaining bytes of DRAM */ + A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */ - /* memory track count, configured by host */ - A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */ + /* memory track count, configured by host */ + A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */ - /* minidump buffer */ - A_UINT32 hi_minidump; /* 0x118 */ + /* minidump buffer */ + A_UINT32 hi_minidump; /* 0x118 */ - /* bdata's sig and key addr */ - A_UINT32 hi_bd_sig_key; /* 0x11c */ + /* bdata's sig and key addr */ + A_UINT32 hi_bd_sig_key; /* 0x11c */ } POSTPACK64; @@ -287,38 +283,38 @@ PREPACK64 struct host_interest_s { #define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002 /* Bits defined in hi_option_flag */ -#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ -#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ -#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ -#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */ -#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */ -#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ -#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ -#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ -#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ +#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */ +#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */ +#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ +#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ +#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ +#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ #define HI_OPTION_NUM_DEV_LSB 0x200 #define HI_OPTION_NUM_DEV_MSB 0x800 #define HI_OPTION_DEV_MODE_LSB 0x1000 #define HI_OPTION_DEV_MODE_MSB 0x8000000 -#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */ -#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */ -#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before - * sending WMI ready event to host */ -#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */ +#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */ +#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */ +#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before + * sending WMI ready event to host */ +#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */ #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 /* 2 bits of hi_option_flag are used to represent 3 modes */ -#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ -#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ -#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ -#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ +#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ /* 2 bits of hi_option flag are usedto represent 4 submodes */ -#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ -#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ -#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ -#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ +#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ +#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ +#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ +#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ /* Num dev Mask */ #define HI_OPTION_NUM_DEV_MASK 0x7 @@ -328,12 +324,12 @@ PREPACK64 struct host_interest_s { #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 /* Fw Mode/SubMode Mask -|-------------------------------------------------------------------------------| -| SUB | SUB | SUB | SUB | | | | | -| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] | -| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | -|-------------------------------------------------------------------------------| -*/ + |-------------------------------------------------------------------------------| + | SUB | SUB | SUB | SUB | | | | | + | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] | + | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | + |||-------------------------------------------------------------------------------| + */ #define HI_OPTION_FW_MODE_BITS 0x2 #define HI_OPTION_FW_MODE_MASK 0x3 #define HI_OPTION_FW_MODE_SHIFT 0xC @@ -345,13 +341,12 @@ PREPACK64 struct host_interest_s { #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 - /* hi_option_flag2 options */ #define HI_OPTION_OFFLOAD_AMSDU 0x01 -#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ -#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/ -#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ -#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ +#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ +#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */ +#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ +#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ #define HI_OPTION_RF_KILL_SHIFT 0x2 #define HI_OPTION_RF_KILL_MASK 0x1 @@ -359,68 +354,71 @@ PREPACK64 struct host_interest_s { #define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20 #define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE() \ - ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX)) + ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX)) /* AR9888 1.0 only. Enable/disable CDC max perf support from host */ #define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20 #define CDC_MAX_PERF_WAR_ENABLED() \ - (!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR)) + (!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR)) #define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */ #define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */ -#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/ +/* This bit is to enable BE low latency for some customers. + * The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps). + */ +#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 #define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */ - #define GPIO_WAKEUP_ENABLED() \ - (HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT) - + (HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT) /* hi_reset_flag */ -#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */ -#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */ -#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */ +#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */ +#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */ +#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */ #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 -#define HI_RESET_FLAG_WARM_RESET 0x20 +#define HI_RESET_FLAG_WARM_RESET 0x20 /* define hi_fw_swap bits */ #define HI_DESC_IN_FW_BIT 0x01 -#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */ +#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */ #define ON_RESET_FLAGS_VALID() \ - (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID) + (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID) -#define RESET_FLAGS_VALIDATE() \ - (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID) +#define RESET_FLAGS_VALIDATE() \ + (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID) #define RESET_FLAGS_INVALIDATE() \ - (HOST_INTEREST->hi_reset_flag_valid = 0) + (HOST_INTEREST->hi_reset_flag_valid = 0) #define ON_RESET_PRESERVE_APP_START() \ - (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START) + (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START) -#define ON_RESET_PRESERVE_NVRAM_STATE() \ - (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE) +#define ON_RESET_PRESERVE_NVRAM_STATE() \ + (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE) #define ON_RESET_PRESERVE_HOST_INTEREST() \ - (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST) + (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST) #define ON_RESET_PRESERVE_ROMDATA() \ - (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA) + (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA) #define ON_RESET_PRESERVE_BOOT_INFO() \ - (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO) + (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO) #define ON_RESET_WARM_RESET() \ - (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET) + (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET) /* host CPU endianness */ #define HOST_ON_BE_CPU() \ - (HOST_INTEREST->hi_be) + (HOST_INTEREST->hi_be) -/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */ +/* AP nart no swap descriptor flag. Decsriptors are created + * on the target processor. + */ #define DESC_IN_FW() \ - (HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT) + (HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT) /* redefine for hi_acs_flags since no product ever use it @@ -434,15 +432,20 @@ PREPACK64 struct host_interest_s { * 1 HOST supports HTT reduced tx completion * 2 HOST supports HTT alternate credit size for data frames * 15..3 reserved for HOST - * 16 FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done + * 16 FW set it before sending HTC_Ready to indicate MBOX swap is done * 17 same as above but to indicate HTT reduced tx completion capability * 31..18 reserved for FW */ -#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) /* HOST require to swap MBOX */ -#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */ -#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */ -#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) /* FW swapped MBOX */ -#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* FW support HTT reduced tx completion */ +/* HOST require to swap MBOX */ +#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) +/* HOST supports HTT reduced tx completion */ +#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) +/* HOST supports alternate credit size for data frames */ +#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) +/* FW swapped MBOX */ +#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) +/* FW support HTT reduced tx completion */ +#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* CONSOLE FLAGS * @@ -484,7 +487,6 @@ PREPACK64 struct host_interest_s { #define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT) #define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE) - /* WOW Extension configuration * * Bit Range Meaning @@ -508,16 +510,16 @@ PREPACK64 struct host_interest_s { #define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) #define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \ - ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \ - (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \ - (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK)) + ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \ + (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \ + (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK)) #define HI_WOW_EXT_GET_NUM_LISTS(config) \ - (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) + (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) #define HI_WOW_EXT_GET_NUM_PATTERNS(config) \ - (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT) + (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT) #define HI_WOW_EXT_GET_PATTERN_SIZE(config) \ - (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT) + (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT) /* * Early allocation configuration @@ -546,57 +548,57 @@ PREPACK64 struct host_interest_s { #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0 #define HI_EARLY_ALLOC_VALID() \ - ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \ - == (HI_EARLY_ALLOC_MAGIC)) -#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ - (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) + ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \ + == (HI_EARLY_ALLOC_MAGIC)) +#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ + (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) /* * Intended for use by Host software, this macro returns the Target RAM * address of any item in the host_interest structure. * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); */ -#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) -#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) +#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) -#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item))) +#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item))) -#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item))) +#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item))) -#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item))) +#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item))) -#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item))) +#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item))) -#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \ - (A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item))) +#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \ + (A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item))) #define HOST_INTEREST_DBGLOG_IS_ENABLED() \ - (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) + (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) #define HOST_INTEREST_PKTLOG_IS_ENABLED() \ - ((HOST_INTEREST->hi_pktlog_num_buffers)) + ((HOST_INTEREST->hi_pktlog_num_buffers)) #define HOST_INTEREST_PROFILE_IS_ENABLED() \ - (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) + (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) #define LF_TIMER_STABILIZATION_IS_ENABLED() \ - (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL)) + (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL)) #define IS_AMSDU_OFFLAOD_ENABLED() \ - ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU)) + ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU)) #define HOST_INTEREST_DFS_IS_ENABLED() \ - ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT)) + ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT)) #define HOST_INTEREST_EARLY_CFG_DONE() \ - ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE)) + ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE)) /*power save flag bit definitions*/ #define HI_PWR_SAVE_LPL_ENABLED 0x1 @@ -609,15 +611,15 @@ PREPACK64 struct host_interest_s { #define HI_PWR_SAVE_LPL_DEV_MASK 0x3 /*power save related utility macros*/ #define HI_LPL_ENABLED() \ - ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) + ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) #define HI_DEV_LPL_TYPE_GET(_devix) \ - (HOST_INTEREST->hi_pwr_save_flags & \ - ((HI_PWR_SAVE_LPL_DEV_MASK) << \ - (HI_PWR_SAVE_LPL_DEV0_LSB + \ - (_devix)*2))) + (HOST_INTEREST->hi_pwr_save_flags & \ + ((HI_PWR_SAVE_LPL_DEV_MASK) << \ + (HI_PWR_SAVE_LPL_DEV0_LSB + \ + (_devix)*2))) -#define HOST_INTEREST_SMPS_IS_ALLOWED() \ - ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) +#define HOST_INTEREST_SMPS_IS_ALLOWED() \ + ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) /* Convert a Target virtual address into a Target physical address */ #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) @@ -628,24 +630,24 @@ PREPACK64 struct host_interest_s { #define AR6320_VTOP(vaddr) (vaddr) #define AR900B_VTOP(vaddr) (vaddr) #define TARG_VTOP(TargetType, vaddr) \ - (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \ - (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ - (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \ - (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \ - (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \ - (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \ - (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \ - 0))))))) + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \ + 0))))))) #define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \ - (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ - (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \ - (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \ - (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \ - (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \ - (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \ - (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \ - 0))))))) + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \ + 0))))))) #define AR6002_BOARD_DATA_SZ 768 #define AR6002_BOARD_EXT_DATA_SZ 0 @@ -664,23 +666,8 @@ PREPACK64 struct host_interest_s { #define AR6320_BOARD_EXT_DATA_SZ 0 #define QCA9377_BOARD_DATA_SZ 8192 #define QCA9377_BOARD_EXT_DATA_SZ 0 -#define AR900B_BOARD_DATA_SZ (14 * 1024) +#define AR900B_BOARD_DATA_SZ 7168 #define AR900B_BOARD_EXT_DATA_SZ 0 -#define QCA9984_BOARD_DATA_SZ (14 * 1024) -#define QCA9984_BOARD_EXT_DATA_SZ 0 -#define QCA9888_BOARD_DATA_SZ (14 * 1024) -#define QCA9888_BOARD_EXT_DATA_SZ 0 -#define IPQ4019_BOARD_DATA_SZ (14 * 1024) -#define IPQ4019_BOARD_EXT_DATA_SZ 0 - -/* Allocate board data right at the begining of AXI SRAM, - * Current size for beeliner is 14K. - * Allocate it towards the end of DRAM, until AXI SRAM is functional. - */ -#define AR900B_BOARD_DATA_ADDR 0xc0000 -#define QCA9984_BOARD_DATA_ADDR 0xc0000 -#define QCA9888_BOARD_DATA_ADDR 0xc0000 -#define IPQ4019_BOARD_DATA_ADDR 0xc0000 #define AR6003_REV3_APP_START_OVERRIDE 0x946100 #define AR6003_REV3_APP_LOAD_ADDRESS 0x545000 diff --git a/fw/targcfg.h b/fw/targcfg.h old mode 100755 new mode 100644 index f45c71364ce4..52a8d41eaf62 --- a/fw/targcfg.h +++ b/fw/targcfg.h @@ -29,25 +29,25 @@ #define __TARGCFG_H__ #if defined(ATH_TARGET) -#include /* A_UINT32 */ +#include /* A_UINT32 */ #else -#include /* A_UINT32 */ +#include /* A_UINT32 */ #endif typedef struct _targcfg_t { - A_UINT32 num_vdev; - A_UINT32 num_peers; - A_UINT32 num_peer_ast; - A_UINT32 num_peer_keys; - A_UINT32 num_peer_tid; - A_UINT32 num_mcast_keys; - A_UINT32 num_tx; - A_UINT32 num_rx; - A_UINT32 num_mgmt_tx; - A_UINT32 num_mgmt_rx; - A_UINT32 tx_chain_mask; - A_UINT32 rx_chain_mask; - A_UINT32 override; /* Override target with the values supplied above */ + A_UINT32 num_vdev; + A_UINT32 num_peers; + A_UINT32 num_peer_ast; + A_UINT32 num_peer_keys; + A_UINT32 num_peer_tid; + A_UINT32 num_mcast_keys; + A_UINT32 num_tx; + A_UINT32 num_rx; + A_UINT32 num_mgmt_tx; + A_UINT32 num_mgmt_rx; + A_UINT32 tx_chain_mask; + A_UINT32 rx_chain_mask; + A_UINT32 override; /* Override target with the values supplied above */ } targcfg_t; #endif /* __TARGCFG_H__ */ diff --git a/fw/wal_rx_desc.h b/fw/wal_rx_desc.h old mode 100755 new mode 100644 index 6a352d5ec7ae..cb4be58b9d99 --- a/fw/wal_rx_desc.h +++ b/fw/wal_rx_desc.h @@ -28,11 +28,10 @@ #ifndef _WAL_RX_DESC__H_ #define _WAL_RX_DESC__H_ - #if defined(ATH_TARGET) -#include /* A_UINT8 */ +#include /* A_UINT8 */ #else -#include /* A_UINT8 */ +#include /* A_UINT8 */ #endif /* @@ -42,7 +41,7 @@ * */ #if !defined(ATH_PERF_PWR_OFFLOAD) -#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) //FIXME_WIFI2 beeliner enbled by default (will be removed once we have target aware HTT) +#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) #include #include #include @@ -73,33 +72,36 @@ * ring. */ struct hw_rx_desc_base { - struct rx_attention attention; - struct rx_frag_info frag_info; - struct rx_mpdu_start mpdu_start; - struct rx_msdu_start msdu_start; - struct rx_msdu_end msdu_end; - struct rx_mpdu_end mpdu_end; - struct rx_ppdu_start ppdu_start; - struct rx_ppdu_end ppdu_end; + struct rx_attention attention; + struct rx_frag_info frag_info; + struct rx_mpdu_start mpdu_start; + struct rx_msdu_start msdu_start; + struct rx_msdu_end msdu_end; + struct rx_mpdu_end mpdu_end; + struct rx_ppdu_start ppdu_start; + struct rx_ppdu_end ppdu_end; }; #endif +#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40 +#define FW_MSDU_INFO_FIRST_WAKEUP_S 6 + /* * This struct defines the basic MSDU rx descriptor created by FW. */ struct fw_rx_desc_base { - union { - struct { - A_UINT8 discard : 1, - forward : 1, - any_err : 1, - dup_err : 1, - ipa_ind : 1, - inspect : 1, - extension: 2; - }bits; - A_UINT8 val; - }u; + union { + struct { + A_UINT8 discard:1, + forward:1, + any_err:1, + dup_err:1, + ipa_ind:1, + inspect:1, + extension:2; + } bits; + A_UINT8 val; + } u; }; #define FW_RX_DESC_DISCARD_M 0x1 @@ -118,62 +120,61 @@ struct fw_rx_desc_base { #define FW_RX_DESC_CNT_2_BYTES(_fw_desc_cnt) (_fw_desc_cnt) enum { - FW_RX_DESC_EXT_NONE = 0, - FW_RX_DESC_EXT_LRO_ONLY, - FW_RX_DESC_EXT_LRO_AND_OTHER, - FW_RX_DESC_EXT_OTHER + FW_RX_DESC_EXT_NONE = 0, + FW_RX_DESC_EXT_LRO_ONLY, + FW_RX_DESC_EXT_LRO_AND_OTHER, + FW_RX_DESC_EXT_OTHER }; #define FW_RX_DESC_DISCARD_GET(_var) \ - (((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S) + (((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S) #define FW_RX_DESC_DISCARD_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_DESC_DISCARD_S)) + ((_var) |= ((_val) << FW_RX_DESC_DISCARD_S)) #define FW_RX_DESC_FORWARD_GET(_var) \ - (((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S) + (((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S) #define FW_RX_DESC_FORWARD_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_DESC_FORWARD_S)) + ((_var) |= ((_val) << FW_RX_DESC_FORWARD_S)) #define FW_RX_DESC_INSPECT_GET(_var) \ - (((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S) + (((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S) #define FW_RX_DESC_INSPECT_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_DESC_INSPECT_S)) + ((_var) |= ((_val) << FW_RX_DESC_INSPECT_S)) #define FW_RX_DESC_EXT_GET(_var) \ - (((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S) + (((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S) #define FW_RX_DESC_EXT_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_DESC_EXT_S)) - + ((_var) |= ((_val) << FW_RX_DESC_EXT_S)) /* * This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host. */ struct fw_rx_msdu_info { - union { - /* - * The "bits" struct defines the flags in fw_rx_msdu_info used - * during regular operation. - */ - struct { - A_UINT8 tcp_udp_chksum_fail : 1, /* for tcp checksum offload use */ - ip_chksum_fail : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - first_wakeup : 1, - reserved : 1; - } bits; - /* - * The "mon" struct defines the flags in fw_rx_msdu_info used - * during monitor mode. - */ - struct { - A_UINT8 last_frag : 1, - reserved : 7; - } mon; - A_UINT8 val; - } u; + union { + /* + * The "bits" struct defines the flags in fw_rx_msdu_info used + * during regular operation. + */ + struct { + A_UINT8 tcp_udp_chksum_fail:1, /* for tcp checksum offload use */ + ip_chksum_fail:1, + ipv6_proto:1, + tcp_proto:1, + udp_proto:1, + ip_frag:1, + first_wakeup:1, + reserved:1; + } bits; + /* + * The "mon" struct defines the flags in fw_rx_msdu_info used + * during monitor mode. + */ + struct { + A_UINT8 last_frag:1, + reserved:7; + } mon; + A_UINT8 val; + } u; }; /* regular operation flags */ @@ -194,39 +195,39 @@ struct fw_rx_msdu_info { #define FW_RX_MSDU_INFO_FIRST_WAKEUP_S 6 #define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S) + (((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S) #define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)) #define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S) + (((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S) #define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)) #define FW_RX_MSDU_INFO_IPV6_PROTO_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S) + (((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S) #define FW_RX_MSDU_INFO_IPV6_PROTO_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S)) #define FW_RX_MSDU_INFO_TCP_PROTO_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S) + (((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S) #define FW_RX_MSDU_INFO_TCP_PROTO_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S)) #define FW_RX_MSDU_INFO_UDP_PROTO_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S) + (((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S) #define FW_RX_MSDU_INFO_UDP_PROTO_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S)) #define FW_RX_MSDU_INFO_IP_FRAG_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S) + (((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S) #define FW_RX_MSDU_INFO_IP_FRAG_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S)) #define FW_RX_MSDU_INFO_FIRST_WAKEUP_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S) + (((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S) #define FW_RX_MSDU_INFO_FIRST_WAKEUP_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S)) + ((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S)) /* monitor mode flags */ @@ -236,9 +237,7 @@ struct fw_rx_msdu_info { #define FW_RX_MSDU_INFO_MON_LAST_FRAG_GET(_var) \ - (((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S) + (((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S) #define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \ - ((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S)) - - + ((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S)) #endif /* _WAL_RX_DESC__H_ */ diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h old mode 100755 new mode 100644 index cb95effac57c..aaf3825fc280 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -28,228 +28,235 @@ #ifndef __WLAN_DEFS_H__ #define __WLAN_DEFS_H__ -#include /* A_COMPILE_TIME_ASSERT */ +/* A_COMPILE_TIME_ASSERT */ +#include /* * This file contains WLAN definitions that may be used across both * Host and Target software. */ - - /* * MAX_SPATIAL_STREAM should be defined in a fwconfig_xxx.h file, * but for now provide a default value here in case it's not defined * in the fwconfig_xxx.h file. */ +#define NUM_SPATIAL_STREAM 2 #ifndef MAX_SPATIAL_STREAM #define MAX_SPATIAL_STREAM 3 #endif -#ifndef CONFIG_160MHZ_SUPPORT -#define CONFIG_160MHZ_SUPPORT 0 /* default: 160 MHz channels not supported */ -#endif - -#ifndef SUPPORT_11AX -#define SUPPORT_11AX 0 /* 11ax not supported by default */ -#endif - /* * MAX_SPATIAL_STREAM_ANY - * what is the largest number of spatial streams that any target supports */ -#define MAX_SPATIAL_STREAM_ANY_V2 4 /* pre-hawkeye */ -#define MAX_SPATIAL_STREAM_ANY_V3 8 /* includes hawkeye */ -/* - * (temporarily) leave the old MAX_SPATIAL_STREAM_ANY name in place as an alias, - * and in case some old code is using it - */ -#define MAX_SPATIAL_STREAM_ANY MAX_SPATIAL_STREAM_ANY_V2 /* DEPRECATED */ +#define MAX_SPATIAL_STREAM_ANY 4 + +#ifndef CONFIG_160MHZ_SUPPORT +#define CONFIG_160MHZ_SUPPORT 0 +#endif + +#ifndef SUPPORT_11AX +#define SUPPORT_11AX 0 /* 11ax not supported by default */ +#endif + +/* defines to set Packet extension values which can be 0 us, 8 us or 16 us */ +/* NOTE: Below values cannot be changed without breaking WMI Compatibility */ +#define MAX_HE_NSS 8 +#define MAX_HE_MODULATION 8 +#define MAX_HE_RU 4 +#define HE_MODULATION_NONE 7 +#define HE_PET_0_USEC 0 +#define HE_PET_8_USEC 1 +#define HE_PET_16_USEC 2 typedef enum { - MODE_11A = 0, /* 11a Mode */ - MODE_11G = 1, /* 11b/g Mode */ - MODE_11B = 2, /* 11b Mode */ - MODE_11GONLY = 3, /* 11g only Mode */ - MODE_11NA_HT20 = 4, /* 11a HT20 mode */ - MODE_11NG_HT20 = 5, /* 11g HT20 mode */ - MODE_11NA_HT40 = 6, /* 11a HT40 mode */ - MODE_11NG_HT40 = 7, /* 11g HT40 mode */ - MODE_11AC_VHT20 = 8, - MODE_11AC_VHT40 = 9, - MODE_11AC_VHT80 = 10, - MODE_11AC_VHT20_2G = 11, - MODE_11AC_VHT40_2G = 12, - MODE_11AC_VHT80_2G = 13, + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ + MODE_11NA_HT20 = 4, /* 11a HT20 mode */ + MODE_11NG_HT20 = 5, /* 11g HT20 mode */ + MODE_11NA_HT40 = 6, /* 11a HT40 mode */ + MODE_11NG_HT40 = 7, /* 11g HT40 mode */ + MODE_11AC_VHT20 = 8, + MODE_11AC_VHT40 = 9, + MODE_11AC_VHT80 = 10, + MODE_11AC_VHT20_2G = 11, + MODE_11AC_VHT40_2G = 12, + MODE_11AC_VHT80_2G = 13, #if CONFIG_160MHZ_SUPPORT - MODE_11AC_VHT80_80 = 14, - MODE_11AC_VHT160 = 15, + MODE_11AC_VHT80_80 = 14, + MODE_11AC_VHT160 = 15, #endif #if SUPPORT_11AX - MODE_11AX_HE20 = 16, - MODE_11AX_HE40 = 17, - MODE_11AX_HE80 = 18, - MODE_11AX_HE80_80 = 19, - MODE_11AX_HE160 = 20, - MODE_11AX_HE20_2G = 21, - MODE_11AX_HE40_2G = 22, - MODE_11AX_HE80_2G = 23, + MODE_11AX_HE20 = 16, + MODE_11AX_HE40 = 17, + MODE_11AX_HE80 = 18, + MODE_11AX_HE80_80 = 19, + MODE_11AX_HE160 = 20, + MODE_11AX_HE20_2G = 21, + MODE_11AX_HE40_2G = 22, + MODE_11AX_HE80_2G = 23, #endif - /* - * MODE_UNKNOWN should not be used within the host / target interface. - * Thus, it is permissible for ODE_UNKNOWN to be conditionally-defined, - * taking different values when compiling for different targets. - */ - MODE_UNKNOWN, - MODE_UNKNOWN_NO_160MHZ_SUPPORT = 14, /* not needed? */ -#if 0 - MODE_UNKNOWN_NO_11AX_SUPPORT = 16, /* not needed? */ - MODE_UNKNOWN_11AX_SUPPORT = 24, /* not needed? */ -#endif - MODE_UNKNOWN_160MHZ_SUPPORT = MODE_UNKNOWN, /* not needed? */ + /* + * MODE_UNKNOWN should not be used within the host / target interface. + * Thus, it is permissible for ODE_UNKNOWN to be conditionally-defined, + * taking different values when compiling for different targets. + */ + + MODE_UNKNOWN, + MODE_UNKNOWN_NO_160MHZ_SUPPORT = 14, /* not needed? */ + /* MODE_UNKNOWN_NO_11AX_SUPPORT = 16,*/ /* not needed? */ + /* MODE_UNKNOWN_11AX_SUPPORT = 24,*/ /* not needed? */ + MODE_UNKNOWN_160MHZ_SUPPORT = MODE_UNKNOWN, /* not needed? */ #ifdef ATHR_WIN_NWF - PHY_MODE_MAX = MODE_UNKNOWN, - PHY_MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, - PHY_MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, + PHY_MODE_MAX = MODE_UNKNOWN, + PHY_MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, + PHY_MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, #else - MODE_MAX = MODE_UNKNOWN, - MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, - MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, + MODE_MAX = MODE_UNKNOWN, + MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, + MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, #endif } WLAN_PHY_MODE; #if CONFIG_160MHZ_SUPPORT == 0 A_COMPILE_TIME_ASSERT( - mode_unknown_value_consistency_Check, - MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT); + mode_unknown_value_consistency_Check, + MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT); #else A_COMPILE_TIME_ASSERT( - mode_unknown_value_consistency_Check, - MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT); + mode_unknown_value_consistency_Check, + MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT); #endif typedef enum { - VHT_MODE_NONE = 0, /* NON VHT Mode, e.g., HT, DSSS, CCK */ - VHT_MODE_20M = 1, - VHT_MODE_40M = 2, - VHT_MODE_80M = 3, - VHT_MODE_160M = 4 + VHT_MODE_NONE = 0, /* NON VHT Mode, e.g., HT, DSSS, CCK */ + VHT_MODE_20M = 1, + VHT_MODE_40M = 2, + VHT_MODE_80M = 3, + VHT_MODE_160M = 4 } VHT_OPER_MODE; typedef enum { - WLAN_11A_CAPABILITY = 1, - WLAN_11G_CAPABILITY = 2, - WLAN_11AG_CAPABILITY = 3, + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, } WLAN_CAPABILITY; -#if (NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX - typedef struct { - A_UINT64 mask_l; - A_UINT64 mask_h; - } A_RATEMASK; -#elif (NUM_SPATIAL_STREAM > 3) - #define A_RATEMASK A_UINT64 +#if (NUM_SPATIAL_STREAM > 3) +#define A_RATEMASK A_UINT64 #else - #define A_RATEMASK A_UINT32 -#endif - -#if (NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX - typedef A_UINT16 A_RATE; - typedef A_UINT16 A_RATECODE; -#else - typedef A_UINT8 A_RATE; - typedef A_UINT8 A_RATECODE; +#define A_RATEMASK A_UINT32 #endif #define A_RATEMASK_NUM_OCTET (sizeof (A_RATEMASK)) #define A_RATEMASK_NUM_BITS ((sizeof (A_RATEMASK)) << 3) - -#if CONFIG_160MHZ_SUPPORT +#if CONFIG_160MHZ_SUPPORT != 0 #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ - ((mode) == MODE_11AC_VHT40) || \ - ((mode) == MODE_11AC_VHT80) || \ - ((mode) == MODE_11AC_VHT80_80) || \ - ((mode) == MODE_11AC_VHT160)) + ((mode) == MODE_11AC_VHT40) || \ + ((mode) == MODE_11AC_VHT80) || \ + ((mode) == MODE_11AC_VHT80_80) || \ + ((mode) == MODE_11AC_VHT160)) #else #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ - ((mode) == MODE_11AC_VHT40) || \ - ((mode) == MODE_11AC_VHT80)) + ((mode) == MODE_11AC_VHT40) || \ + ((mode) == MODE_11AC_VHT80)) #endif -#define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \ - ((mode) == MODE_11AX_HE40) || \ - ((mode) == MODE_11AX_HE80) || \ - ((mode) == MODE_11AX_HE80_80) || \ - ((mode) == MODE_11AX_HE160) || \ - ((mode) == MODE_11AX_HE20_2G) || \ - ((mode) == MODE_11AX_HE40_2G) || \ - ((mode) == MODE_11AX_HE80_2G)) +#define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \ + ((mode) == MODE_11AX_HE40) || \ + ((mode) == MODE_11AX_HE80) || \ + ((mode) == MODE_11AX_HE80_80) || \ + ((mode) == MODE_11AX_HE160) || \ + ((mode) == MODE_11AX_HE20_2G) || \ + ((mode) == MODE_11AX_HE40_2G) || \ + ((mode) == MODE_11AX_HE80_2G)) -#define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ - ((mode) == MODE_11AC_VHT40_2G) || \ - ((mode) == MODE_11AC_VHT80_2G)) +#define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ + ((mode) == MODE_11AC_VHT40_2G) || \ + ((mode) == MODE_11AC_VHT80_2G)) #define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ - ((mode) == MODE_11NA_HT20) || \ - ((mode) == MODE_11NA_HT40) || \ - (IS_MODE_VHT(mode))) + ((mode) == MODE_11NA_HT20) || \ + ((mode) == MODE_11NA_HT40) || \ + (IS_MODE_VHT(mode))) #define IS_MODE_11B(mode) ((mode) == MODE_11B) #define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ - ((mode) == MODE_11GONLY) || \ - ((mode) == MODE_11NG_HT20) || \ - ((mode) == MODE_11NG_HT40) || \ - (IS_MODE_VHT_2G(mode))) + ((mode) == MODE_11GONLY) || \ + ((mode) == MODE_11NG_HT20) || \ + ((mode) == MODE_11NG_HT40) || \ + (IS_MODE_VHT_2G(mode))) #define IS_MODE_11GN(mode) (((mode) == MODE_11NG_HT20) || \ - ((mode) == MODE_11NG_HT40)) + ((mode) == MODE_11NG_HT40)) #define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) - enum { - REGDMN_MODE_11A = 0x00000001, /* 11a channels */ - REGDMN_MODE_TURBO = 0x00000002, /* 11a turbo-only channels */ - REGDMN_MODE_11B = 0x00000004, /* 11b channels */ - REGDMN_MODE_PUREG = 0x00000008, /* 11g channels (OFDM only) */ - REGDMN_MODE_11G = 0x00000008, /* XXX historical */ - REGDMN_MODE_108G = 0x00000020, /* 11g+Turbo channels */ - REGDMN_MODE_108A = 0x00000040, /* 11a+Turbo channels */ - REGDMN_MODE_XR = 0x00000100, /* XR channels */ - REGDMN_MODE_11A_HALF_RATE = 0x00000200, /* 11A half rate channels */ - REGDMN_MODE_11A_QUARTER_RATE = 0x00000400, /* 11A quarter rate channels */ - REGDMN_MODE_11NG_HT20 = 0x00000800, /* 11N-G HT20 channels */ - REGDMN_MODE_11NA_HT20 = 0x00001000, /* 11N-A HT20 channels */ - REGDMN_MODE_11NG_HT40PLUS = 0x00002000, /* 11N-G HT40 + channels */ - REGDMN_MODE_11NG_HT40MINUS = 0x00004000, /* 11N-G HT40 - channels */ - REGDMN_MODE_11NA_HT40PLUS = 0x00008000, /* 11N-A HT40 + channels */ - REGDMN_MODE_11NA_HT40MINUS = 0x00010000, /* 11N-A HT40 - channels */ - REGDMN_MODE_11AC_VHT20 = 0x00020000, /* 5Ghz, VHT20 */ - REGDMN_MODE_11AC_VHT40PLUS = 0x00040000, /* 5Ghz, VHT40 + channels */ - REGDMN_MODE_11AC_VHT40MINUS = 0x00080000, /* 5Ghz VHT40 - channels */ - REGDMN_MODE_11AC_VHT80 = 0x000100000, /* 5Ghz, VHT80 channels */ - REGDMN_MODE_11AC_VHT20_2G = 0x000200000, /* 2Ghz, VHT20 */ - REGDMN_MODE_11AC_VHT40_2G = 0x000400000, /* 2Ghz, VHT40 */ - REGDMN_MODE_11AC_VHT80_2G = 0x000800000, /* 2Ghz, VHT80 */ - REGDMN_MODE_11AC_VHT160 = 0x001000000, /* 5Ghz, VHT160 */ - REGDMN_MODE_11AC_VHT40_2GPLUS = 0x002000000, /* 2Ghz, VHT40+ */ - REGDMN_MODE_11AC_VHT40_2GMINUS = 0x004000000, /* 2Ghz, VHT40- */ - REGDMN_MODE_11AC_VHT80_80 = 0x008000000, /* 5GHz, VHT80+80 */ + /* 11a channels */ + REGDMN_MODE_11A = 0x00000001, + /* 11a turbo-only channels */ + REGDMN_MODE_TURBO = 0x00000002, + /* 11b channels */ + REGDMN_MODE_11B = 0x00000004, + /* 11g channels (OFDM only) */ + REGDMN_MODE_PUREG = 0x00000008, + /* XXX historical */ + REGDMN_MODE_11G = 0x00000008, + /* 11g+Turbo channels */ + REGDMN_MODE_108G = 0x00000020, + /* 11a+Turbo channels */ + REGDMN_MODE_108A = 0x00000040, + /* XR channels */ + REGDMN_MODE_XR = 0x00000100, + /* 11A half rate channels */ + REGDMN_MODE_11A_HALF_RATE = 0x00000200, + /* 11A quarter rate channels */ + REGDMN_MODE_11A_QUARTER_RATE = 0x00000400, + /* 11N-G HT20 channels */ + REGDMN_MODE_11NG_HT20 = 0x00000800, + /* 11N-A HT20 channels */ + REGDMN_MODE_11NA_HT20 = 0x00001000, + /* 11N-G HT40 + channels */ + REGDMN_MODE_11NG_HT40PLUS = 0x00002000, + /* 11N-G HT40 - channels */ + REGDMN_MODE_11NG_HT40MINUS = 0x00004000, + /* 11N-A HT40 + channels */ + REGDMN_MODE_11NA_HT40PLUS = 0x00008000, + /* 11N-A HT40 - channels */ + REGDMN_MODE_11NA_HT40MINUS = 0x00010000, + /* 5Ghz, VHT20 */ + REGDMN_MODE_11AC_VHT20 = 0x00020000, + /* 5Ghz, VHT40 + channels */ + REGDMN_MODE_11AC_VHT40PLUS = 0x00040000, + /* 5Ghz VHT40 - channels */ + REGDMN_MODE_11AC_VHT40MINUS = 0x00080000, + /* 5Ghz, VHT80 channels */ + REGDMN_MODE_11AC_VHT80 = 0x000100000, + REGDMN_MODE_11AC_VHT20_2G = 0x000200000, /* 2Ghz, VHT20 */ + REGDMN_MODE_11AC_VHT40_2G = 0x000400000, /* 2Ghz, VHT40 */ + REGDMN_MODE_11AC_VHT80_2G = 0x000800000, /* 2Ghz, VHT80 */ + REGDMN_MODE_11AC_VHT160 = 0x001000000, /* 5Ghz, VHT160 */ + REGDMN_MODE_11AC_VHT40_2GPLUS = 0x002000000, /* 2Ghz, VHT40+ */ + REGDMN_MODE_11AC_VHT40_2GMINUS = 0x004000000, /* 2Ghz, VHT40- */ + REGDMN_MODE_11AC_VHT80_80 = 0x008000000, /* 5GHz, VHT80+80 */ }; -#define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum - * to prevent the ARM compile "warning #66: - * enumeration value is out of int range" - * Anyway, this is a BIT-OR of all possible values. - */ +#define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum + * to prevent the ARM compile "warning #66: + * enumeration value is out of int range" + * Anyway, this is a BIT-OR of all possible values. + */ #define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001 #define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002 #define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004 - /* regulatory capabilities */ #define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 @@ -259,16 +266,16 @@ enum { #define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_HAL_REG_CAPABILITIES */ - A_UINT32 eeprom_rd; /* regdomain value specified in EEPROM */ - A_UINT32 eeprom_rd_ext; /* regdomain */ - A_UINT32 regcap1; /* CAP1 capabilities bit map. */ - A_UINT32 regcap2; /* REGDMN EEPROM CAP. */ - A_UINT32 wireless_modes; /* REGDMN MODE */ - A_UINT32 low_2ghz_chan; - A_UINT32 high_2ghz_chan; - A_UINT32 low_5ghz_chan; - A_UINT32 high_5ghz_chan; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_HAL_REG_CAPABILITIES */ + A_UINT32 eeprom_rd; /* regdomain value specified in EEPROM */ + A_UINT32 eeprom_rd_ext; /* regdomain */ + A_UINT32 regcap1; /* CAP1 capabilities bit map. */ + A_UINT32 regcap2; /* REGDMN EEPROM CAP. */ + A_UINT32 wireless_modes; /* REGDMN MODE */ + A_UINT32 low_2ghz_chan; + A_UINT32 high_2ghz_chan; + A_UINT32 low_5ghz_chan; + A_UINT32 high_5ghz_chan; } HAL_REG_CAPABILITIES; /* @@ -278,50 +285,49 @@ typedef struct { */ typedef struct { - A_RATECODE rateCode; - A_UINT8 flags; + A_UINT8 rateCode; + A_UINT8 flags; } RATE_CODE; typedef struct { - RATE_CODE ptx_rc; /* rate code, bw, chain mask sgi */ - A_UINT8 reserved[2]; - A_UINT32 flags; /* Encodes information such as excessive - retransmission, aggregate, some info - from .11 frame control, - STBC, LDPC, (SGI and Tx Chain Mask - are encoded in ptx_rc->flags field), - AMPDU truncation (BT/time based etc.), - RTS/CTS attempt */ - A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ - A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ - A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ - A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ - A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ - A_UINT32 is_probe; /* Valid if probing. Else, 0 */ - A_UINT32 ba_win_size; /* b'7..b0, block Ack Window size, b'31..b8 Resvd */ - A_UINT32 failed_ba_bmap_0_31; /* failed BA bitmap 0..31 */ - A_UINT32 failed_ba_bmap_32_63; /* failed BA bitmap 32..63 */ - A_UINT32 bmap_tried_0_31; /* enqued bitmap 0..31 */ - A_UINT32 bmap_tried_32_63; /* enqued bitmap 32..63 */ + RATE_CODE ptx_rc; /* rate code, bw, chain mask sgi */ + A_UINT8 reserved[2]; + A_UINT32 flags; /* Encodes information such as excessive + retransmission, aggregate, some info + from .11 frame control, + STBC, LDPC, (SGI and Tx Chain Mask + are encoded in ptx_rc->flags field), + AMPDU truncation (BT/time based etc.), + RTS/CTS attempt */ + A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ + A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ + A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ + A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ + A_UINT32 time_stamp; /* ACK timestamp (helps determine age) */ + A_UINT32 is_probe; /* Valid if probing. Else, 0 */ + A_UINT32 ba_win_size; /* b'7..b0, block Ack Window size, b'31..b8 Resvd */ + A_UINT32 failed_ba_bmap_0_31; /* failed BA bitmap 0..31 */ + A_UINT32 failed_ba_bmap_32_63; /* failed BA bitmap 32..63 */ + A_UINT32 bmap_tried_0_31; /* enqued bitmap 0..31 */ + A_UINT32 bmap_tried_32_63; /* enqued bitmap 32..63 */ } RC_TX_DONE_PARAMS; - #define RC_SET_TX_DONE_INFO(_dst, _rc, _f, _nq, _nr, _nf, _rssi, _ts) \ - do { \ - (_dst).ptx_rc.rateCode = (_rc).rateCode; \ - (_dst).ptx_rc.flags = (_rc).flags; \ - (_dst).flags = (_f); \ - (_dst).num_enqued = (_nq); \ - (_dst).num_retries = (_nr); \ - (_dst).num_failed = (_nf); \ - (_dst).ack_rssi = (_rssi); \ - (_dst).time_stamp = (_ts); \ - } while (0) + do { \ + (_dst).ptx_rc.rateCode = (_rc).rateCode; \ + (_dst).ptx_rc.flags = (_rc).flags; \ + (_dst).flags = (_f); \ + (_dst).num_enqued = (_nq); \ + (_dst).num_retries = (_nr); \ + (_dst).num_failed = (_nf); \ + (_dst).ack_rssi = (_rssi); \ + (_dst).time_stamp = (_ts); \ + } while (0) -#define RC_SET_TXBF_DONE_INFO(_dst, _f) \ - do { \ - (_dst).flags |= (_f); \ - } while (0) +#define RC_SET_TXBF_DONE_INFO(_dst, _f) \ + do { \ + (_dst).flags |= (_f); \ + } while (0) /* NOTE: NUM_DYN_BW and NUM_SCHED_ENTRIES cannot be changed without breaking WMI Compatibility */ #define NUM_SCHED_ENTRIES 2 @@ -329,131 +335,121 @@ typedef struct { /* Some products only use 20/40/80; some use 20/40/80/160 */ #ifndef NUM_DYN_BW -#define NUM_DYN_BW 3 /* default: support up through 80 MHz */ +/* default: support up through 80 MHz */ +#define NUM_DYN_BW 3 #endif #define NUM_DYN_BW_MASK 0x3 #define PROD_SCHED_BW_ENTRIES (NUM_SCHED_ENTRIES * NUM_DYN_BW) +typedef A_UINT8 A_RATE; #if NUM_DYN_BW > 4 -/* Extend rate table module first */ +/* Extend rate table module first*/ #error "Extend rate table module first" #endif -#define MAX_IBSS_PEERS 32 +#define MAX_PEERS 32 + +#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) +typedef struct { + A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_UINT16 flags[NUM_SCHED_ENTRIES][NUM_DYN_BW]; + A_RATE rix[NUM_SCHED_ENTRIES][NUM_DYN_BW]; + A_UINT8 tpc[NUM_SCHED_ENTRIES][NUM_DYN_BW]; + A_UINT32 antmask[NUM_SCHED_ENTRIES]; + A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_UINT16 txbf_cv_len; + A_UINT32 txbf_cv_ptr; + A_UINT16 txbf_flags; + A_UINT16 txbf_cv_size; + A_UINT8 txbf_nc_idx; + A_UINT8 tries[NUM_SCHED_ENTRIES]; + A_UINT8 bw_mask[NUM_SCHED_ENTRIES]; + A_UINT8 max_bw[NUM_SCHED_ENTRIES]; + A_UINT8 num_sched_entries; + A_UINT8 paprd_mask; + A_UINT8 rts_rix; + A_UINT8 sh_pream; + A_UINT8 min_spacing_1_4_us; + A_UINT8 fixed_delims; + A_UINT8 bw_in_service; + A_RATE probe_rix; + A_UINT8 num_valid_rates; + A_UINT8 rtscts_tpc; + A_UINT8 dd_profile; +} RC_TX_RATE_SCHEDULE; + +#else +typedef struct { + A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_UINT32 antmask[NUM_SCHED_ENTRIES]; + A_UINT32 txbf_cv_ptr; + A_UINT16 txbf_cv_len; + A_UINT8 tries[NUM_SCHED_ENTRIES]; + A_UINT8 num_valid_rates; + A_UINT8 paprd_mask; + A_UINT8 rts_rix; + A_UINT8 sh_pream; + A_UINT8 min_spacing_1_4_us; + A_UINT8 fixed_delims; + A_UINT8 bw_in_service; + A_RATE probe_rix; +} RC_TX_RATE_SCHEDULE; +#endif + +typedef struct { + A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; + A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; +#ifdef DYN_TPC_ENABLE + A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; +#endif +#ifdef SECTORED_ANTENNA + A_UINT32 antmask[NUM_SCHED_ENTRIES]; +#endif + A_UINT8 tries[NUM_SCHED_ENTRIES]; + A_UINT8 num_valid_rates; + A_UINT8 rts_rix; + A_UINT8 sh_pream; + A_UINT8 bw_in_service; + A_RATE probe_rix; + A_UINT8 dd_profile; +} RC_TX_RATE_INFO; /* - * RC_TX_RATE_SCHEDULE and RC_TX_RATE_INFO defs are used only in the target. - * (Host-based rate control is no longer applicable.) - * Maintain the defs in wlanfw_cmn for the sake of existing Rome / Helium - * targets, but for Lithium targets remove them from wlanfw_cmn and define - * them in a target-only location instead. - * SUPPORT_11AX is essentially used as a condition to identify Lithium targets. - * Some host drivers would also have SUPPORT_11AX defined, and thus would lose - * the definition of RC_TX_RATE_SCHEDULE and RC_TX_RATE_INFO, but that's okay - * because the host should have no references to these target-only data - * structures. - */ -#if !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) - #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) - typedef struct{ - A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_UINT16 flags[NUM_SCHED_ENTRIES][NUM_DYN_BW]; - A_RATE rix[NUM_SCHED_ENTRIES][NUM_DYN_BW]; - A_UINT8 tpc[NUM_SCHED_ENTRIES][NUM_DYN_BW]; - A_UINT32 antmask[NUM_SCHED_ENTRIES]; - A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_UINT16 txbf_cv_len; - A_UINT32 txbf_cv_ptr; - A_UINT16 txbf_flags; - A_UINT16 txbf_cv_size; - A_UINT8 txbf_nc_idx; - A_UINT8 tries[NUM_SCHED_ENTRIES]; - A_UINT8 bw_mask[NUM_SCHED_ENTRIES]; - A_UINT8 max_bw[NUM_SCHED_ENTRIES]; - A_UINT8 num_sched_entries; - A_UINT8 paprd_mask; - A_UINT8 rts_rix; - A_UINT8 sh_pream; - A_UINT8 min_spacing_1_4_us; - A_UINT8 fixed_delims; - A_UINT8 bw_in_service; - A_RATE probe_rix; - A_UINT8 num_valid_rates; - A_UINT8 rtscts_tpc; - A_UINT8 dd_profile; - } RC_TX_RATE_SCHEDULE; - #else - typedef struct{ - A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_UINT32 antmask[NUM_SCHED_ENTRIES]; - A_UINT32 txbf_cv_ptr; - A_UINT16 txbf_cv_len; - A_UINT8 tries[NUM_SCHED_ENTRIES]; - A_UINT8 num_valid_rates; - A_UINT8 paprd_mask; - A_UINT8 rts_rix; - A_UINT8 sh_pream; - A_UINT8 min_spacing_1_4_us; - A_UINT8 fixed_delims; - A_UINT8 bw_in_service; - A_RATE probe_rix; - } RC_TX_RATE_SCHEDULE; - #endif - - typedef struct{ - A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - #ifdef DYN_TPC_ENABLE - A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; - #endif - #ifdef SECTORED_ANTENNA - A_UINT32 antmask[NUM_SCHED_ENTRIES]; - #endif - A_UINT8 tries[NUM_SCHED_ENTRIES]; - A_UINT8 num_valid_rates; - A_UINT8 rts_rix; - A_UINT8 sh_pream; - A_UINT8 bw_in_service; - A_RATE probe_rix; - A_UINT8 dd_profile; - } RC_TX_RATE_INFO; -#endif /* !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) */ - -/* - * Temporarily continue to provide the WHAL_RC_INIT_RC_MASKS def in wlan_defs.h + * Temporarily continue to provide the WHAL_RC_INIT_RC_MASKS def in wlan_defsh * for older targets. * The WHAL_RX_INIT_RC_MASKS macro def needs to be moved into ratectrl_11ac.h * for all targets, but until this is complete, the WHAL_RC_INIT_RC_MASKS def * will be maintained here in its old location. */ #if CONFIG_160MHZ_SUPPORT == 0 -#define WHAL_RC_INIT_RC_MASKS(_rm) do { \ - _rm[WHAL_RC_MASK_IDX_NON_HT] = A_RATEMASK_OFDM_CCK; \ - _rm[WHAL_RC_MASK_IDX_HT_20] = A_RATEMASK_HT_20; \ - _rm[WHAL_RC_MASK_IDX_HT_40] = A_RATEMASK_HT_40; \ - _rm[WHAL_RC_MASK_IDX_VHT_20] = A_RATEMASK_VHT_20; \ - _rm[WHAL_RC_MASK_IDX_VHT_40] = A_RATEMASK_VHT_40; \ - _rm[WHAL_RC_MASK_IDX_VHT_80] = A_RATEMASK_VHT_80; \ - } while (0) + +#define WHAL_RC_INIT_RC_MASKS(_rm) do { \ + _rm[WHAL_RC_MASK_IDX_NON_HT] = A_RATEMASK_OFDM_CCK; \ + _rm[WHAL_RC_MASK_IDX_HT_20] = A_RATEMASK_HT_20; \ + _rm[WHAL_RC_MASK_IDX_HT_40] = A_RATEMASK_HT_40; \ + _rm[WHAL_RC_MASK_IDX_VHT_20] = A_RATEMASK_VHT_20; \ + _rm[WHAL_RC_MASK_IDX_VHT_40] = A_RATEMASK_VHT_40; \ + _rm[WHAL_RC_MASK_IDX_VHT_80] = A_RATEMASK_VHT_80; \ +} while (0) #endif /** * strucutre describing host memory chunk. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */ - /** id of the request that is passed up in service ready */ - A_UINT32 req_id; - /** the physical address the memory chunk */ - A_UINT32 ptr; - /** size of the chunk */ - A_UINT32 size; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */ + /** id of the request that is passed up in service ready */ + A_UINT32 req_id; + /** the physical address the memory chunk */ + A_UINT32 ptr; + /** size of the chunk */ + A_UINT32 size; } wlan_host_memory_chunk; #define NUM_UNITS_IS_NUM_VDEVS 0x1 @@ -466,33 +462,33 @@ typedef struct { * structure used by FW for requesting host memory */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_wlan_host_mem_req */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_wlan_host_mem_req */ - /** ID of the request */ - A_UINT32 req_id; - /** size of the of each unit */ - A_UINT32 unit_size; - /** - * flags to indicate that - * the number units is dependent - * on number of resources(num vdevs num peers .. etc) - */ - A_UINT32 num_unit_info; - /* - * actual number of units to allocate . if flags in the num_unit_info - * indicate that number of units is tied to number of a particular - * resource to allocate then num_units filed is set to 0 and host - * will derive the number units from number of the resources it is - * requesting. - */ - A_UINT32 num_units; + /** ID of the request */ + A_UINT32 req_id; + /** size of the of each unit */ + A_UINT32 unit_size; + /** + * flags to indicate that + * the number units is dependent + * on number of resources(num vdevs num peers .. etc) + */ + A_UINT32 num_unit_info; + /* + * actual number of units to allocate . if flags in the num_unit_info + * indicate that number of units is tied to number of a particular + * resource to allocate then num_units filed is set to 0 and host + * will derive the number units from number of the resources it is + * requesting. + */ + A_UINT32 num_units; } wlan_host_mem_req; typedef enum { - IGNORE_DTIM = 0x01, - NORMAL_DTIM = 0x02, - STICK_DTIM = 0x03, - AUTO_DTIM = 0x04, + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, + AUTO_DTIM = 0x04, } BEACON_DTIM_POLICY; /* During test it is observed that 6 * 400 = 2400 can @@ -521,174 +517,166 @@ typedef enum { * smart antenna = 50 */ #define MEMORY_REQ_FOR_PEER 800 + /* * NB: it is important to keep all the fields in the structure dword long * so that it is easy to handle the statistics in BE host. */ struct wlan_dbg_tx_stats { - /* Num HTT cookies queued to dispatch list */ - A_INT32 comp_queued; - /* Num HTT cookies dispatched */ - A_INT32 comp_delivered; - /* Num MSDU queued to WAL */ - A_INT32 msdu_enqued; - /* Num MPDU queue to WAL */ - A_INT32 mpdu_enqued; - /* Num MSDUs dropped by WMM limit */ - A_INT32 wmm_drop; - /* Num Local frames queued */ - A_INT32 local_enqued; - /* Num Local frames done */ - A_INT32 local_freed; - /* Num queued to HW */ - A_INT32 hw_queued; - /* Num PPDU reaped from HW */ - A_INT32 hw_reaped; - /* Num underruns */ - A_INT32 underrun; + /* Num HTT cookies queued to dispatch list */ + A_INT32 comp_queued; + /* Num HTT cookies dispatched */ + A_INT32 comp_delivered; + /* Num MSDU queued to WAL */ + A_INT32 msdu_enqued; + /* Num MPDU queue to WAL */ + A_INT32 mpdu_enqued; + /* Num MSDUs dropped by WMM limit */ + A_INT32 wmm_drop; + /* Num Local frames queued */ + A_INT32 local_enqued; + /* Num Local frames done */ + A_INT32 local_freed; + /* Num queued to HW */ + A_INT32 hw_queued; + /* Num PPDU reaped from HW */ + A_INT32 hw_reaped; + /* Num underruns */ + A_INT32 underrun; #if defined(AR900B) - /* HW Paused. */ - A_UINT32 hw_paused; + /* HW Paused. */ + A_UINT32 hw_paused; #endif - /* Num PPDUs cleaned up in TX abort */ - A_INT32 tx_abort; - /* Num MPDUs requed by SW */ - A_INT32 mpdus_requed; - /* excessive retries */ - A_UINT32 tx_ko; + /* Num PPDUs cleaned up in TX abort */ + A_INT32 tx_abort; + /* Num MPDUs requed by SW */ + A_INT32 mpdus_requed; + /* excessive retries */ + A_UINT32 tx_ko; #if defined(AR900B) - A_UINT32 tx_xretry; + A_UINT32 tx_xretry; #endif - /* data hw rate code */ - A_UINT32 data_rc; - /* Scheduler self triggers */ - A_UINT32 self_triggers; - /* frames dropped due to excessive sw retries */ - A_UINT32 sw_retry_failure; - /* illegal rate phy errors */ - A_UINT32 illgl_rate_phy_err; - /* wal pdev continous xretry */ - A_UINT32 pdev_cont_xretry; - /* wal pdev continous xretry */ - A_UINT32 pdev_tx_timeout; - /* wal pdev resets */ - A_UINT32 pdev_resets; - /* frames dropped due to non-availability of stateless TIDs */ - A_UINT32 stateless_tid_alloc_failure; - /* PhY/BB underrun */ - A_UINT32 phy_underrun; - /* MPDU is more than txop limit */ - A_UINT32 txop_ovf; + /* data hw rate code */ + A_UINT32 data_rc; + /* Scheduler self triggers */ + A_UINT32 self_triggers; + /* frames dropped due to excessive sw retries */ + A_UINT32 sw_retry_failure; + /* illegal rate phy errors */ + A_UINT32 illgl_rate_phy_err; + /* wal pdev continous xretry */ + A_UINT32 pdev_cont_xretry; + /* wal pdev continous xretry */ + A_UINT32 pdev_tx_timeout; + /* wal pdev resets */ + A_UINT32 pdev_resets; + /* frames dropped due to non-availability of stateless TIDs */ + A_UINT32 stateless_tid_alloc_failure; + /* PhY/BB underrun */ + A_UINT32 phy_underrun; + /* MPDU is more than txop limit */ + A_UINT32 txop_ovf; #if defined(AR900B) - /* Number of Sequences posted */ - A_UINT32 seq_posted; - /* Number of Sequences failed queueing */ - A_UINT32 seq_failed_queueing; - /* Number of Sequences completed */ - A_UINT32 seq_completed; - /* Number of Sequences restarted */ - A_UINT32 seq_restarted; - /* Number of MU Sequences posted */ - A_UINT32 mu_seq_posted; - /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ - A_INT32 mpdus_sw_flush; - /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ - A_INT32 mpdus_hw_filter; - /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ - A_INT32 mpdus_truncated; - /* Num MPDUs that was tried but didn't receive ACK or BA */ - A_INT32 mpdus_ack_failed; - /* Num MPDUs that was dropped du to expiry. */ - A_INT32 mpdus_expired; + /* Number of Sequences posted */ + A_UINT32 seq_posted; + /* Number of Sequences failed queueing */ + A_UINT32 seq_failed_queueing; + /* Number of Sequences completed */ + A_UINT32 seq_completed; + /* Number of Sequences restarted */ + A_UINT32 seq_restarted; + /* Number of MU Sequences posted */ + A_UINT32 mu_seq_posted; + /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ + A_INT32 mpdus_sw_flush; + /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ + A_INT32 mpdus_hw_filter; + /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ + A_INT32 mpdus_truncated; + /* Num MPDUs that was tried but didn't receive ACK or BA */ + A_INT32 mpdus_ack_failed; + /* Num MPDUs that was dropped du to expiry. */ + A_INT32 mpdus_expired; + /* Num mc drops */ + /* A_UINT32 mc_drop; */ #endif }; struct wlan_dbg_rx_stats { - /* Cnts any change in ring routing mid-ppdu */ - A_INT32 mid_ppdu_route_change; - /* Total number of statuses processed */ - A_INT32 status_rcvd; - /* Extra frags on rings 0-3 */ - A_INT32 r0_frags; - A_INT32 r1_frags; - A_INT32 r2_frags; - A_INT32 r3_frags; - /* MSDUs / MPDUs delivered to HTT */ - A_INT32 htt_msdus; - A_INT32 htt_mpdus; - /* MSDUs / MPDUs delivered to local stack */ - A_INT32 loc_msdus; - A_INT32 loc_mpdus; - /* AMSDUs that have more MSDUs than the status ring size */ - A_INT32 oversize_amsdu; - /* Number of PHY errors */ - A_INT32 phy_errs; - /* Number of PHY errors drops */ - A_INT32 phy_err_drop; - /* Number of mpdu errors - FCS, MIC, ENC etc. */ - A_INT32 mpdu_errs; + /* Cnts any change in ring routing mid-ppdu */ + A_INT32 mid_ppdu_route_change; + /* Total number of statuses processed */ + A_INT32 status_rcvd; + /* Extra frags on rings 0-3 */ + A_INT32 r0_frags; + A_INT32 r1_frags; + A_INT32 r2_frags; + A_INT32 r3_frags; + /* MSDUs / MPDUs delivered to HTT */ + A_INT32 htt_msdus; + A_INT32 htt_mpdus; + /* MSDUs / MPDUs delivered to local stack */ + A_INT32 loc_msdus; + A_INT32 loc_mpdus; + /* AMSDUs that have more MSDUs than the status ring size */ + A_INT32 oversize_amsdu; + /* Number of PHY errors */ + A_INT32 phy_errs; + /* Number of PHY errors drops */ + A_INT32 phy_err_drop; + /* Number of mpdu errors - FCS, MIC, ENC etc. */ + A_INT32 mpdu_errs; #if defined(AR900B) - /* Number of rx overflow errors. */ - A_INT32 rx_ovfl_errs; + /* Number of rx overflow errors. */ + A_INT32 rx_ovfl_errs; #endif }; - struct wlan_dbg_mem_stats { - A_UINT32 iram_free_size; - A_UINT32 dram_free_size; + A_UINT32 iram_free_size; + A_UINT32 dram_free_size; }; struct wlan_dbg_peer_stats { - A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ + A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ }; typedef struct { - A_UINT32 mcs[10]; - A_UINT32 sgi[10]; - A_UINT32 nss[4]; - A_UINT32 nsts; - A_UINT32 stbc[10]; - A_UINT32 bw[3]; - A_UINT32 pream[6]; - A_UINT32 ldpc; - A_UINT32 txbf; - A_UINT32 mgmt_rssi; - A_UINT32 data_rssi; - A_UINT32 rssi_chain0; - A_UINT32 rssi_chain1; - A_UINT32 rssi_chain2; -/* - * TEMPORARY: leave rssi_chain3 in place for AR900B builds until code using - * rssi_chain3 has been converted to use wlan_dbg_rx_rate_info_v2_t. - * At that time, this rssi_chain3 field will be deleted. - */ + A_UINT32 mcs[10]; + A_UINT32 sgi[10]; + A_UINT32 nss[4]; + A_UINT32 nsts; + A_UINT32 stbc[10]; + A_UINT32 bw[3]; + A_UINT32 pream[6]; + A_UINT32 ldpc; + A_UINT32 txbf; + A_UINT32 mgmt_rssi; + A_UINT32 data_rssi; + A_UINT32 rssi_chain0; + A_UINT32 rssi_chain1; + A_UINT32 rssi_chain2; #if defined(AR900B) A_UINT32 rssi_chain3; #endif -} wlan_dbg_rx_rate_info_t ; +} wlan_dbg_rx_rate_info_t; typedef struct { - A_UINT32 mcs[10]; - A_UINT32 sgi[10]; -/* - * TEMPORARY: leave nss conditionally defined, until all code that - * requires nss[4] is converted to use wlan_dbg_tx_rate_info_v2_t. - * At that time, this nss array will be made length = 3 unconditionally. - */ + A_UINT32 mcs[10]; + A_UINT32 sgi[10]; #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) - A_UINT32 nss[4]; + A_UINT32 nss[4]; #else - A_UINT32 nss[3]; + A_UINT32 nss[3]; #endif - A_UINT32 stbc[10]; - A_UINT32 bw[3]; - A_UINT32 pream[4]; - A_UINT32 ldpc; - A_UINT32 rts_cnt; - A_UINT32 ack_rssi; + A_UINT32 stbc[10]; + A_UINT32 bw[3]; + A_UINT32 pream[4]; + A_UINT32 ldpc; + A_UINT32 rts_cnt; + A_UINT32 ack_rssi; } wlan_dbg_tx_rate_info_t ; #define WLAN_MAX_MCS 10 @@ -696,7 +684,7 @@ typedef struct { typedef struct { A_UINT32 mcs[WLAN_MAX_MCS]; A_UINT32 sgi[WLAN_MAX_MCS]; - A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V2]; + A_UINT32 nss[MAX_SPATIAL_STREAM_ANY]; A_UINT32 nsts; A_UINT32 stbc[WLAN_MAX_MCS]; A_UINT32 bw[NUM_DYN_BW_MAX]; @@ -710,12 +698,12 @@ typedef struct { A_UINT32 rssi_chain2; A_UINT32 rssi_chain3; A_UINT32 reserved[8]; -} wlan_dbg_rx_rate_info_v2_t; +} wlan_dbg_rx_rate_info_v2_t ; typedef struct { A_UINT32 mcs[WLAN_MAX_MCS]; A_UINT32 sgi[WLAN_MAX_MCS]; - A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V2]; + A_UINT32 nss[MAX_SPATIAL_STREAM_ANY]; A_UINT32 stbc[WLAN_MAX_MCS]; A_UINT32 bw[NUM_DYN_BW_MAX]; A_UINT32 pream[4]; @@ -723,39 +711,7 @@ typedef struct { A_UINT32 rts_cnt; A_UINT32 ack_rssi; A_UINT32 reserved[8]; -} wlan_dbg_tx_rate_info_v2_t; - -typedef struct { - A_UINT32 mcs[WLAN_MAX_MCS]; - A_UINT32 sgi[WLAN_MAX_MCS]; - A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V3]; - A_UINT32 nsts; - A_UINT32 stbc[WLAN_MAX_MCS]; - A_UINT32 bw[NUM_DYN_BW_MAX]; - A_UINT32 pream[6]; - A_UINT32 ldpc; - A_UINT32 txbf; - A_UINT32 mgmt_rssi; - A_UINT32 data_rssi; - A_UINT32 rssi_chain0; - A_UINT32 rssi_chain1; - A_UINT32 rssi_chain2; - A_UINT32 rssi_chain3; - A_UINT32 reserved[8]; -} wlan_dbg_rx_rate_info_v3_t; - -typedef struct { - A_UINT32 mcs[WLAN_MAX_MCS]; - A_UINT32 sgi[WLAN_MAX_MCS]; - A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V3]; - A_UINT32 stbc[WLAN_MAX_MCS]; - A_UINT32 bw[NUM_DYN_BW_MAX]; - A_UINT32 pream[4]; - A_UINT32 ldpc; - A_UINT32 rts_cnt; - A_UINT32 ack_rssi; - A_UINT32 reserved[8]; -} wlan_dbg_tx_rate_info_v3_t; +} wlan_dbg_tx_rate_info_v2_t ; #define WHAL_DBG_PHY_ERR_MAXCNT 18 #define WHAL_DBG_SIFS_STATUS_MAXCNT 8 @@ -765,33 +721,33 @@ typedef struct { #define WHAL_DBG_FLUSH_REASON_MAXCNT 40 typedef enum { - WIFI_URRN_STATS_FIRST_PKT, - WIFI_URRN_STATS_BETWEEN_MPDU, - WIFI_URRN_STATS_WITHIN_MPDU, - WHAL_MAX_URRN_STATS + WIFI_URRN_STATS_FIRST_PKT, + WIFI_URRN_STATS_BETWEEN_MPDU, + WIFI_URRN_STATS_WITHIN_MPDU, + WHAL_MAX_URRN_STATS } wifi_urrn_type_t; typedef struct wlan_dbg_txbf_snd_stats { - A_UINT32 cbf_20[4]; - A_UINT32 cbf_40[4]; - A_UINT32 cbf_80[4]; - A_UINT32 sounding[9]; - A_UINT32 cbf_160[4]; + A_UINT32 cbf_20[4]; + A_UINT32 cbf_40[4]; + A_UINT32 cbf_80[4]; + A_UINT32 sounding[9]; + A_UINT32 cbf_160[4]; } wlan_dbg_txbf_snd_stats_t; typedef struct wlan_dbg_wifi2_error_stats { - A_UINT32 urrn_stats[WHAL_MAX_URRN_STATS]; - A_UINT32 flush_errs[WHAL_DBG_FLUSH_REASON_MAXCNT]; - A_UINT32 schd_stall_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; - A_UINT32 schd_cmd_result[WHAL_DBG_CMD_RESULT_MAXCNT]; - A_UINT32 sifs_status[WHAL_DBG_SIFS_STATUS_MAXCNT]; - A_UINT8 phy_errs[WHAL_DBG_PHY_ERR_MAXCNT]; - A_UINT32 rx_rate_inval; + A_UINT32 urrn_stats[WHAL_MAX_URRN_STATS]; + A_UINT32 flush_errs[WHAL_DBG_FLUSH_REASON_MAXCNT]; + A_UINT32 schd_stall_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; + A_UINT32 schd_cmd_result[WHAL_DBG_CMD_RESULT_MAXCNT]; + A_UINT32 sifs_status[WHAL_DBG_SIFS_STATUS_MAXCNT]; + A_UINT8 phy_errs[WHAL_DBG_PHY_ERR_MAXCNT]; + A_UINT32 rx_rate_inval; } wlan_dbg_wifi2_error_stats_t; typedef struct wlan_dbg_wifi2_error2_stats { - A_UINT32 schd_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; - A_UINT32 sifs_errs[WHAL_DBG_SIFS_ERR_MAXCNT]; + A_UINT32 schd_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; + A_UINT32 sifs_errs[WHAL_DBG_SIFS_ERR_MAXCNT]; } wlan_dbg_wifi2_error2_stats_t; #define WLAN_DBG_STATS_SIZE_TXBF_VHT 10 @@ -800,68 +756,66 @@ typedef struct wlan_dbg_wifi2_error2_stats { #define WLAN_DBG_STATS_SIZE_TXBF_CCK 7 typedef struct wlan_dbg_txbf_data_stats { - A_UINT32 tx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; - A_UINT32 rx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; - A_UINT32 tx_txbf_ht[WLAN_DBG_STATS_SIZE_TXBF_HT]; - A_UINT32 tx_txbf_ofdm[WLAN_DBG_STATS_SIZE_TXBF_OFDM]; - A_UINT32 tx_txbf_cck[WLAN_DBG_STATS_SIZE_TXBF_CCK]; + A_UINT32 tx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; + A_UINT32 rx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; + A_UINT32 tx_txbf_ht[WLAN_DBG_STATS_SIZE_TXBF_HT]; + A_UINT32 tx_txbf_ofdm[WLAN_DBG_STATS_SIZE_TXBF_OFDM]; + A_UINT32 tx_txbf_cck[WLAN_DBG_STATS_SIZE_TXBF_CCK]; } wlan_dbg_txbf_data_stats_t; struct wlan_dbg_tx_mu_stats { - A_UINT32 mu_sch_nusers_2; - A_UINT32 mu_sch_nusers_3; - A_UINT32 mu_mpdus_queued_usr[4]; - A_UINT32 mu_mpdus_tried_usr[4]; - A_UINT32 mu_mpdus_failed_usr[4]; - A_UINT32 mu_mpdus_requeued_usr[4]; - A_UINT32 mu_err_no_ba_usr[4]; - A_UINT32 mu_mpdu_underrun_usr[4]; - A_UINT32 mu_ampdu_underrun_usr[4]; + A_UINT32 mu_sch_nusers_2; + A_UINT32 mu_sch_nusers_3; + A_UINT32 mu_mpdus_queued_usr[4]; + A_UINT32 mu_mpdus_tried_usr[4]; + A_UINT32 mu_mpdus_failed_usr[4]; + A_UINT32 mu_mpdus_requeued_usr[4]; + A_UINT32 mu_err_no_ba_usr[4]; + A_UINT32 mu_mpdu_underrun_usr[4]; + A_UINT32 mu_ampdu_underrun_usr[4]; }; struct wlan_dbg_tx_selfgen_stats { - A_UINT32 su_ndpa; - A_UINT32 su_ndp; - A_UINT32 mu_ndpa; - A_UINT32 mu_ndp; - A_UINT32 mu_brpoll_1; - A_UINT32 mu_brpoll_2; - A_UINT32 mu_bar_1; - A_UINT32 mu_bar_2; - A_UINT32 cts_burst; - A_UINT32 su_ndp_err; - A_UINT32 su_ndpa_err; - A_UINT32 mu_ndp_err; - A_UINT32 mu_brp1_err; - A_UINT32 mu_brp2_err; + A_UINT32 su_ndpa; + A_UINT32 su_ndp; + A_UINT32 mu_ndpa; + A_UINT32 mu_ndp; + A_UINT32 mu_brpoll_1; + A_UINT32 mu_brpoll_2; + A_UINT32 mu_bar_1; + A_UINT32 mu_bar_2; + A_UINT32 cts_burst; + A_UINT32 su_ndp_err; + A_UINT32 su_ndpa_err; + A_UINT32 mu_ndp_err; + A_UINT32 mu_brp1_err; + A_UINT32 mu_brp2_err; }; typedef struct wlan_dbg_sifs_resp_stats { - A_UINT32 ps_poll_trigger; /* num ps-poll trigger frames */ - A_UINT32 uapsd_trigger; /* num uapsd trigger frames */ - A_UINT32 qb_data_trigger[2]; /* num data trigger frames; idx 0: explicit and idx 1: implicit */ - A_UINT32 qb_bar_trigger[2]; /* num bar trigger frames; idx 0: explicit and idx 1: implicit */ - A_UINT32 sifs_resp_data; /* num ppdus transmitted at SIFS interval */ - A_UINT32 sifs_resp_err; /* num ppdus failed to meet SIFS resp timing */ + A_UINT32 ps_poll_trigger; /* num ps-poll trigger frames */ + A_UINT32 uapsd_trigger; /* num uapsd trigger frames */ + A_UINT32 qb_data_trigger[2]; /* num data trigger frames; idx 0: explicit and idx 1: implicit */ + A_UINT32 qb_bar_trigger[2]; /* num bar trigger frames; idx 0: explicit and idx 1: implicit */ + A_UINT32 sifs_resp_data; /* num ppdus transmitted at SIFS interval */ + A_UINT32 sifs_resp_err; /* num ppdus failed to meet SIFS resp timing */ } wlan_dgb_sifs_resp_stats_t; - - /** wlan_dbg_wifi2_error_stats_t is not grouped with the * following structure as it is allocated differently and only * belongs to whal */ typedef struct wlan_dbg_stats_wifi2 { - wlan_dbg_txbf_snd_stats_t txbf_snd_info; - wlan_dbg_txbf_data_stats_t txbf_data_info; - struct wlan_dbg_tx_selfgen_stats tx_selfgen; - struct wlan_dbg_tx_mu_stats tx_mu; - wlan_dgb_sifs_resp_stats_t sifs_resp_info; + wlan_dbg_txbf_snd_stats_t txbf_snd_info; + wlan_dbg_txbf_data_stats_t txbf_data_info; + struct wlan_dbg_tx_selfgen_stats tx_selfgen; + struct wlan_dbg_tx_mu_stats tx_mu; + wlan_dgb_sifs_resp_stats_t sifs_resp_info; } wlan_dbg_wifi2_stats_t; typedef struct { - wlan_dbg_rx_rate_info_t rx_phy_info; - wlan_dbg_tx_rate_info_t tx_rate_info; + wlan_dbg_rx_rate_info_t rx_phy_info; + wlan_dbg_tx_rate_info_t tx_rate_info; } wlan_dbg_rate_info_t; typedef struct { @@ -870,26 +824,35 @@ typedef struct { } wlan_dbg_rate_info_v2_t; struct wlan_dbg_stats { - struct wlan_dbg_tx_stats tx; - struct wlan_dbg_rx_stats rx; + struct wlan_dbg_tx_stats tx; + struct wlan_dbg_rx_stats rx; #if defined(AR900B) - struct wlan_dbg_mem_stats mem; + struct wlan_dbg_mem_stats mem; #endif - struct wlan_dbg_peer_stats peer; + struct wlan_dbg_peer_stats peer; }; #define DBG_STATS_MAX_HWQ_NUM 10 #define DBG_STATS_MAX_TID_NUM 20 #define DBG_STATS_MAX_CONG_NUM 16 struct wlan_dbg_txq_stats { - A_UINT16 num_pkts_queued[DBG_STATS_MAX_HWQ_NUM]; - A_UINT16 tid_hw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ - A_UINT16 tid_sw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ + A_UINT16 num_pkts_queued[DBG_STATS_MAX_HWQ_NUM]; + A_UINT16 tid_hw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ + A_UINT16 tid_sw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ }; -struct wlan_dbg_tidq_stats{ - A_UINT32 wlan_dbg_tid_txq_status; - struct wlan_dbg_txq_stats txq_st; +struct wlan_dbg_tidq_stats { + A_UINT32 wlan_dbg_tid_txq_status; + struct wlan_dbg_txq_stats txq_st; }; +typedef enum { + WHAL_REG_EXT_FCC_MIDBAND = 0, + WHAL_REG_EXT_JAPAN_MIDBAND = 1, + WHAL_REG_EXT_FCC_DFS_HT40 = 2, + WHAL_REG_EXT_JAPAN_NONDFS_HT40 = 3, + WHAL_REG_EXT_JAPAN_DFS_HT40 = 4, + WHAL_REG_EXT_FCC_CH_144 = 5, +} WHAL_REG_EXT_BITMAP; + #endif /* __WLANDEFS_H__ */ diff --git a/fw/wlan_module_ids.h b/fw/wlan_module_ids.h old mode 100755 new mode 100644 index 771e1bb14d87..39b9d4db517f --- a/fw/wlan_module_ids.h +++ b/fw/wlan_module_ids.h @@ -1,3 +1,23 @@ +/* + * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ /* * This file was originally distributed by Qualcomm Atheros, Inc. @@ -10,79 +30,79 @@ /* Wlan module ids , global across all the modules */ typedef enum { - WLAN_MODULE_ID_MIN = 0, - WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */ - WLAN_MODULE_WMI, /* 0x1 */ - WLAN_MODULE_STA_PWRSAVE, /* 0x2 */ - WLAN_MODULE_WHAL, /* 0x3 */ - WLAN_MODULE_COEX, /* 0x4 */ - WLAN_MODULE_ROAM, /* 0x5 */ - WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */ - WLAN_MODULE_RESMGR, /* 0x7 */ - WLAN_MODULE_VDEV_MGR, /* 0x8 */ - WLAN_MODULE_SCAN, /* 0x9 */ - WLAN_MODULE_RATECTRL, /* 0xa */ - WLAN_MODULE_AP_PWRSAVE, /* 0xb */ - WLAN_MODULE_BLOCKACK, /* 0xc */ - WLAN_MODULE_MGMT_TXRX, /* 0xd */ - WLAN_MODULE_DATA_TXRX, /* 0xe */ - WLAN_MODULE_HTT, /* 0xf */ - WLAN_MODULE_HOST, /* 0x10 */ - WLAN_MODULE_BEACON, /* 0x11 */ - WLAN_MODULE_OFFLOAD, /* 0x12 */ - WLAN_MODULE_WAL, /* 0x13 */ - WAL_MODULE_DE, /* 0x14 */ - WLAN_MODULE_PCIELP, /* 0x15 */ - WLAN_MODULE_RTT, /* 0x16 */ - WLAN_MODULE_RESOURCE, /* 0x17 */ - WLAN_MODULE_DCS, /* 0x18 */ - WLAN_MODULE_CACHEMGR, /* 0x19 */ - WLAN_MODULE_ANI, /* 0x1a */ - WLAN_MODULE_P2P, /* 0x1b */ - WLAN_MODULE_CSA, /* 0x1c */ - WLAN_MODULE_NLO, /* 0x1d */ - WLAN_MODULE_CHATTER, /* 0x1e */ - WLAN_MODULE_WOW, /* 0x1f */ - WLAN_MODULE_WAL_VDEV, /* 0x20 */ - WLAN_MODULE_WAL_PDEV, /* 0x21 */ - WLAN_MODULE_TEST, /* 0x22 */ - WLAN_MODULE_STA_SMPS, /* 0x23 */ - WLAN_MODULE_SWBMISS, /* 0x24 */ - WLAN_MODULE_WMMAC, /* 0x25 */ - WLAN_MODULE_TDLS, /* 0x26 */ - WLAN_MODULE_HB, /* 0x27 */ - WLAN_MODULE_TXBF, /* 0x28 */ - WLAN_MODULE_BATCH_SCAN, /* 0x29 */ - WLAN_MODULE_THERMAL_MGR, /* 0x2a */ - WLAN_MODULE_PHYERR_DFS, /* 0x2b */ - WLAN_MODULE_RMC, /* 0x2c */ - WLAN_MODULE_STATS, /* 0x2d */ - WLAN_MODULE_NAN, /* 0x2e */ - WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */ - WLAN_MODULE_HIF_UART, /* 0x30 */ - WLAN_MODULE_LPI, /* 0x31 */ - WLAN_MODULE_EXTSCAN, /* 0x32 */ - WLAN_MODULE_UNIT_TEST, /* 0x33 */ - WLAN_MODULE_MLME, /* 0x34 */ - WLAN_MODULE_SUPPL, /* 0x35 */ - WLAN_MODULE_ERE, /* 0x36 */ - WLAN_MODULE_OCB, /* 0x37 */ - WLAN_MODULE_RSSI_MONITOR, /* 0x38 */ - WLAN_MODULE_WPM, /* 0x39 */ - WLAN_MODULE_CSS, /* 0x3a */ - WLAN_MODULE_PPS, /* 0x3b */ - WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */ - WLAN_MODULE_MAWC, /* 0x3d */ - WLAN_MODULE_CMC_QMIC, /* 0x3e */ - WLAN_MODULE_EGAP, /* 0x3f */ - WLAN_MODULE_NAN20, /* 0x40 */ - WLAN_MODULE_QBOOST, /* 0x41 */ - WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */ - WLAN_MODULE_HALPHY, /* 0x43 */ - WAL_MODULE_ENQ, /* 0x44 */ + WLAN_MODULE_ID_MIN = 0, + WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */ + WLAN_MODULE_WMI, /* 0x1 */ + WLAN_MODULE_STA_PWRSAVE, /* 0x2 */ + WLAN_MODULE_WHAL, /* 0x3 */ + WLAN_MODULE_COEX, /* 0x4 */ + WLAN_MODULE_ROAM, /* 0x5 */ + WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */ + WLAN_MODULE_RESMGR, /* 0x7 */ + WLAN_MODULE_VDEV_MGR, /* 0x8 */ + WLAN_MODULE_SCAN, /* 0x9 */ + WLAN_MODULE_RATECTRL, /* 0xa */ + WLAN_MODULE_AP_PWRSAVE, /* 0xb */ + WLAN_MODULE_BLOCKACK, /* 0xc */ + WLAN_MODULE_MGMT_TXRX, /* 0xd */ + WLAN_MODULE_DATA_TXRX, /* 0xe */ + WLAN_MODULE_HTT, /* 0xf */ + WLAN_MODULE_HOST, /* 0x10 */ + WLAN_MODULE_BEACON, /* 0x11 */ + WLAN_MODULE_OFFLOAD, /* 0x12 */ + WLAN_MODULE_WAL, /* 0x13 */ + WAL_MODULE_DE, /* 0x14 */ + WLAN_MODULE_PCIELP, /* 0x15 */ + WLAN_MODULE_RTT, /* 0x16 */ + WLAN_MODULE_RESOURCE, /* 0x17 */ + WLAN_MODULE_DCS, /* 0x18 */ + WLAN_MODULE_CACHEMGR, /* 0x19 */ + WLAN_MODULE_ANI, /* 0x1a */ + WLAN_MODULE_P2P, /* 0x1b */ + WLAN_MODULE_CSA, /* 0x1c */ + WLAN_MODULE_NLO, /* 0x1d */ + WLAN_MODULE_CHATTER, /* 0x1e */ + WLAN_MODULE_WOW, /* 0x1f */ + WLAN_MODULE_WAL_VDEV, /* 0x20 */ + WLAN_MODULE_WAL_PDEV, /* 0x21 */ + WLAN_MODULE_TEST, /* 0x22 */ + WLAN_MODULE_STA_SMPS, /* 0x23 */ + WLAN_MODULE_SWBMISS, /* 0x24 */ + WLAN_MODULE_WMMAC, /* 0x25 */ + WLAN_MODULE_TDLS, /* 0x26 */ + WLAN_MODULE_HB, /* 0x27 */ + WLAN_MODULE_TXBF, /* 0x28 */ + WLAN_MODULE_BATCH_SCAN, /* 0x29 */ + WLAN_MODULE_THERMAL_MGR, /* 0x2a */ + WLAN_MODULE_PHYERR_DFS, /* 0x2b */ + WLAN_MODULE_RMC, /* 0x2c */ + WLAN_MODULE_STATS, /* 0x2d */ + WLAN_MODULE_NAN, /* 0x2e */ + WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */ + WLAN_MODULE_HIF_UART, /* 0x30 */ + WLAN_MODULE_LPI, /* 0x31 */ + WLAN_MODULE_EXTSCAN, /* 0x32 */ + WLAN_MODULE_UNIT_TEST, /* 0x33 */ + WLAN_MODULE_MLME, /* 0x34 */ + WLAN_MODULE_SUPPL, /* 0x35 */ + WLAN_MODULE_ERE, /* 0x36 */ + WLAN_MODULE_OCB, /* 0x37 */ + WLAN_MODULE_RSSI_MONITOR, /* 0x38 */ + WLAN_MODULE_WPM, /* 0x39 */ + WLAN_MODULE_CSS, /* 0x3a */ + WLAN_MODULE_PPS, /* 0x3b */ + WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */ + WLAN_MODULE_MAWC, /* 0x3d */ + WLAN_MODULE_CMC_QMIC, /* 0x3e */ + WLAN_MODULE_EGAP, /* 0x3f */ + WLAN_MODULE_NAN20, /* 0x40 */ + WLAN_MODULE_QBOOST, /* 0x41 */ + WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */ + WLAN_MODULE_HALPHY, /* 0x43 */ + WAL_MODULE_ENQ, /* 0x44 */ - WLAN_MODULE_ID_MAX, - WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, + WLAN_MODULE_ID_MAX, + WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, } WLAN_MODULE_ID; diff --git a/fw/wlan_tgt_def_config.h b/fw/wlan_tgt_def_config.h new file mode 100644 index 000000000000..40e0e9d843d3 --- /dev/null +++ b/fw/wlan_tgt_def_config.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved. + * + * Previously licensed under the ISC license by Qualcomm Atheros, Inc. + * + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * This file was originally distributed by Qualcomm Atheros, Inc. + * under proprietary terms before Copyright ownership was assigned + * to the Linux Foundation. + */ + +#ifndef __WLAN_TGT_DEF_CONFIG_H__ +#define __WLAN_TGT_DEF_CONFIG_H__ + +/* + * set of default target config , that can be over written by platform + */ + +/* + * default limit of 8 VAPs per device. + */ +/* Rome PRD support 4 vdevs */ +#define CFG_TGT_NUM_VDEV 4 + +/* + * We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize hash collisions. + * TODO: This scaling factor would be taken care inside the WAL in the future. + */ +#define CFG_TGT_NUM_PEER_AST 2 + +/* # of WDS entries to support. + */ +#define CFG_TGT_WDS_ENTRIES 0 + +/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B + */ +#define CFG_TGT_DEFAULT_DMA_BURST_SIZE 0 + +/* Fixed delimiters to be inserted after every MPDU + */ +#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM 0 + +/* + * This value may need to be fine tuned, but a constant value will + * probably always be appropriate; it is probably not necessary to + * determine this value dynamically. + */ +#define CFG_TGT_AST_SKID_LIMIT 16 + +/* + * total number of peers per device. + */ +#define CFG_TGT_NUM_PEERS 14 + +/* + * In offload mode target supports features like WOW, chatter and other + * protocol offloads. In order to support them some functionalities like + * reorder buffering, PN checking need to be done in target. This determines + * maximum number of peers suported by target in offload mode + */ + +/* + * The current firmware implementation requires the number of offload peers + * should be (number of vdevs + 1). + + * The reason for this is the firmware clubbed the self peer and offload peer + * in the same pool. So if the firmware wanted to support n vdevs then the + * number of offload peer must be n+1 of which n buffers will be used for + * self peer and the remaining 1 is used for offload peer to support chatter + * mode for single STA. + + * Technically the macro should be 1 however the current firmware requires n+1. + + * TODO: This MACRO need to be modified in the future, if the firmware modified + * to allocate buffers for self peer and offload peer independently. + */ + +#define CFG_TGT_NUM_OFFLOAD_PEERS (CFG_TGT_NUM_VDEV+1) + +/* + * Number of reorder buffers used in offload mode + */ +#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS 4 + +/* + * keys per peer node + */ +#define CFG_TGT_NUM_PEER_KEYS 2 +/* + * total number of data TX and RX TIDs + */ +#define CFG_TGT_NUM_TIDS (2 * (CFG_TGT_NUM_PEERS + CFG_TGT_NUM_VDEV + 2)) +/* + * set this to 0x7 (Peregrine = 3 chains). + * need to be set dynamically based on the HW capability. + */ +#define CFG_TGT_DEFAULT_TX_CHAIN_MASK 0x7 +/* + * set this to 0x7 (Peregrine = 3 chains). + * need to be set dynamically based on the HW capability. + */ +#define CFG_TGT_DEFAULT_RX_CHAIN_MASK 0x7 +/* 100 ms for video, best-effort, and background */ +#define CFG_TGT_RX_TIMEOUT_LO_PRI 100 +/* 40 ms for voice*/ +#define CFG_TGT_RX_TIMEOUT_HI_PRI 40 + +/* AR9888 unified is default in ethernet mode */ +#define CFG_TGT_RX_DECAP_MODE (0x2) +/* Decap to native Wifi header */ +#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1) +/* Decap to raw mode header */ +#define CFG_TGT_RX_DECAP_MODE_RAW (0x0) + +/* maximum number of pending scan requests */ +#define CFG_TGT_DEFAULT_SCAN_MAX_REQS 0x4 + +/* maximum number of VDEV that could use BMISS offload */ +#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV 0x3 + +/* maximum number of VDEV offload Roaming to support */ +#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV 0x3 + +/* maximum number of AP profiles pushed to offload Roaming */ +#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES 0x8 + +/* maximum number of VDEV offload GTK to support */ +#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV 0x3 + +/* default: mcast->ucast disabled if ATH_SUPPORT_MCAST2UCAST not defined */ +#ifndef ATH_SUPPORT_MCAST2UCAST +#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0 +#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0 +#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */ +#else +/* (for testing) small multicast group membership table enabled */ +#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 4 +#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 16 +#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 2 +#endif + +#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 32 +/* + * Specify how much memory the target should allocate for a debug log of + * tx PPDU meta-information (how large the PPDU was, when it was sent, + * whether it was successful, etc.) + * The size of the log records is configurable, from a minimum of 28 bytes + * to a maximum of about 300 bytes. A typical configuration would result + * in each log record being about 124 bytes. + * Thus, 1KB of log space can hold about 30 small records, 3 large records, + * or about 8 typical-sized records. + */ +#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */ + +/* target based fragment timeout and MPDU duplicate detection */ +#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 + +/* Default VoW configuration + */ +#define CFG_TGT_DEFAULT_VOW_CONFIG 0 + +/* + * total number of descriptors to use in the target + */ +#define CFG_TGT_NUM_MSDU_DESC (1024 + 32) + +/* + * Maximum number of frag table entries + */ +#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 10 + +/* + * Maximum number of VDEV that beacon tx offload will support + */ +#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 3 + +/* + * number of vdevs that can support tdls + */ +#define CFG_TGT_NUM_TDLS_VDEVS 1 + +/* + * number of peers that each Tdls vdev can track + */ +#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES 32 + +/* + * number of TDLS concurrent sleep STAs + */ +#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS 1 + +/* + * number of TDLS concurrent buffer STAs + */ +#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS 1 + +/* + * ht enable highest MCS by default + */ +#define CFG_TGT_DEFAULT_GTX_HT_MASK 0x8080 +/* + * vht enable highest MCS by default + */ +#define CFG_TGT_DEFAULT_GTX_VHT_MASK 0x80200 +/* + * threshold to enable GTX + */ +#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD 3 +/* + * margin to move back when per > margin + threshold + */ +#define CFG_TGT_DEFAULT_GTX_PER_MARGIN 2 +/* + * step for every move + */ +#define CFG_TGT_DEFAULT_GTX_TPC_STEP 1 +/* + * lowest TPC + */ +#define CFG_TGT_DEFAULT_GTX_TPC_MIN 0 +/* + * enable all BW 20/40/80/160 + */ +#define CFG_TGT_DEFAULT_GTX_BW_MASK 0xf + +/* + * number of vdevs that can support OCB + */ +#define CFG_TGT_NUM_OCB_VDEVS 1 + +/* + * maximum number of channels that can do OCB + */ +#define CFG_TGT_NUM_OCB_CHANNELS 2 + +/* + * maximum number of channels in an OCB schedule + */ +#define CFG_TGT_NUM_OCB_SCHEDULES 2 + +#endif /*__WLAN_TGT_DEF_CONFIG_H__ */ diff --git a/fw/wlan_tgt_def_config_hl.h b/fw/wlan_tgt_def_config_hl.h new file mode 100644 index 000000000000..cf28f06c82be --- /dev/null +++ b/fw/wlan_tgt_def_config_hl.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef __WLAN_TGT_DEF_CONFIG_H__ +#define __WLAN_TGT_DEF_CONFIG_H__ + +/* + * TODO: please help to consider if we need a seperate config file from LL case. + */ + +/* + * set of default target config , that can be over written by platform + */ + +#ifdef QCA_SUPPORT_INTEGRATED_SOC +#define CFG_TGT_NUM_VDEV 3 /*STA, P2P device, P2P GO/Cli*/ +#else +/* + * default limit of VAPs per device. + */ +#define CFG_TGT_NUM_VDEV 3 +#endif +/* + * We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize + * hash collisions. + * TODO: This scaling factor would be taken care inside the WAL in the future. + */ +#define CFG_TGT_NUM_PEER_AST 2 + +/* # of WDS entries to support. + */ +#define CFG_TGT_WDS_ENTRIES 2 + +/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B + */ +#define CFG_TGT_DEFAULT_DMA_BURST_SIZE 0 + +/* Fixed delimiters to be inserted after every MPDU + */ +#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM 0 + +/* + * This value may need to be fine tuned, but a constant value will + * probably always be appropriate; it is probably not necessary to + * determine this value dynamically. + */ +#define CFG_TGT_AST_SKID_LIMIT 6 +/* + * total number of peers per device. + * currently set to 8 to bring up IP3.9 for memory size problem + */ +#define CFG_TGT_NUM_PEERS 8 +/* + * max number of peers per device. + */ +#define CFG_TGT_NUM_PEERS_MAX 8 +/* + * In offload mode target supports features like WOW, chatter and other + * protocol offloads. In order to support them some functionalities like + * reorder buffering, PN checking need to be done in target. This determines + * maximum number of peers suported by target in offload mode + */ +#define CFG_TGT_NUM_OFFLOAD_PEERS 0 +/* + * Number of reorder buffers used in offload mode + */ +#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS 0 +/* + * keys per peer node + */ +#define CFG_TGT_NUM_PEER_KEYS 2 +/* + * total number of TX/RX data TIDs + */ +#define CFG_TGT_NUM_TIDS (2 * (CFG_TGT_NUM_PEERS + \ + CFG_TGT_NUM_VDEV)) +/* + * max number of Tx TIDS + */ +#define CFG_TGT_NUM_TIDS_MAX (2 * (CFG_TGT_NUM_PEERS_MAX + \ + CFG_TGT_NUM_VDEV)) +/* + * number of multicast keys. + */ +#define CFG_TGT_NUM_MCAST_KEYS 8 +/* + * A value of 3 would probably suffice - one for the control stack, one for + * the data stack, and one for debugging. + * This value may need to be fine tuned, but a constant value will + * probably always be appropriate; it is probably not necessary to + * determine this value dynamically. + */ +#define CFG_TGT_NUM_PDEV_HANDLERS 8 +/* + * A value of 3 would probably suffice - one for the control stack, one for + * the data stack, and one for debugging. + * This value may need to be fine tuned, but a constant value will + * probably always be appropriate; it is probably not necessary to + * determine this value dynamically. + */ +#define CFG_TGT_NUM_VDEV_HANDLERS 4 +/* + * set this to 8: + * one for WAL interals (connection pause) + * one for the control stack, + * one for the data stack + * and one for debugging + * This value may need to be fine tuned, but a constant value will + * probably always be appropriate; it is probably not necessary to + * determine this value dynamically. + */ +#define CFG_TGT_NUM_HANDLERS 14 +/* + * set this to 3: one for the control stack, one for + * the data stack, and one for debugging. + * This value may need to be fine tuned, but a constant value will + * probably always be appropriate; it is probably not necessary to + * determine this value dynamically. + */ +#define CFG_TGT_NUM_PEER_HANDLERS 32 +/* + * set this to 0x7 (Peregrine = 3 chains). + * need to be set dynamically based on the HW capability. + * this is rome + */ +#define CFG_TGT_DEFAULT_TX_CHAIN_MASK 0x3 +/* + * set this to 0x7 (Peregrine = 3 chains). + * need to be set dynamically based on the HW capability. + * this is rome + */ +#define CFG_TGT_DEFAULT_RX_CHAIN_MASK 0x3 +/* 100 ms for video, best-effort, and background */ +#define CFG_TGT_RX_TIMEOUT_LO_PRI 100 +/* 40 ms for voice*/ +#define CFG_TGT_RX_TIMEOUT_HI_PRI 40 + +/* AR9888 unified is default in ethernet mode */ +#define CFG_TGT_RX_DECAP_MODE (0x2) +/* Decap to native Wifi header */ +#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1) + +/* Decap to raw mode header */ +#define CFG_TGT_RX_DECAP_MODE_RAW (0x0) + +/* maximum number of pending scan requests */ +#define CFG_TGT_DEFAULT_SCAN_MAX_REQS 0x4 + +/* maximum number of scan event handlers */ +#define CFG_TGT_DEFAULT_SCAN_MAX_HANDLERS 0x4 + +/* maximum number of VDEV that could use BMISS offload */ +#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV 0x2 + +/* maximum number of VDEV offload Roaming to support */ +#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV 0x2 + +/* maximum number of AP profiles pushed to offload Roaming */ +#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES 0x8 + +/* maximum number of VDEV offload GTK to support */ +#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV 0x2 +/* default: mcast->ucast disabled */ + +#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0 +#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0 +#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */ + +/* + * Specify how much memory the target should allocate for a debug log of + * tx PPDU meta-information (how large the PPDU was, when it was sent, + * whether it was successful, etc.) + * The size of the log records is configurable, from a minimum of 28 bytes + * to a maximum of about 300 bytes. A typical configuration would result + * in each log record being about 124 bytes. + * Thus, 1KB of log space can hold about 30 small records, 3 large records, + * or about 8 typical-sized records. + */ +#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */ + +/* target based fragment timeout and MPDU duplicate detection */ +#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 +/* Default VoW configuration + */ +#define CFG_TGT_DEFAULT_VOW_CONFIG 0 + +/* + * total number of descriptors to use in the target + */ +#ifndef HIF_SDIO +#define CFG_TGT_NUM_MSDU_DESC (32) +#else +#define CFG_TGT_NUM_MSDU_DESC (0) +#endif +/* + * Maximum number of frag table entries + */ +#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 2 + +/* + * number of vdevs that can support tdls + */ +#define CFG_TGT_NUM_TDLS_VDEVS 1 + +/* + * number of peers that each Tdls vdev can track + */ +#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES 32 +/* + * number of TDLS concurrent sleep STAs + */ +#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS 1 + +/* + * number of TDLS concurrent buffer STAs + */ +#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS 1 + +#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 16 +/* + * Maximum number of VDEV that beacon tx offload will support + */ +#ifdef HIF_SDIO +#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 2 +#else +#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 1 +#endif + +/* + * ht enable highest MCS by default + */ +#define CFG_TGT_DEFAULT_GTX_HT_MASK 0x8080 +/* + * vht enable highest MCS by default + */ +#define CFG_TGT_DEFAULT_GTX_VHT_MASK 0x80200 +/* + * threshold to enable GTX + */ +#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD 3 +/* + * margin to move back when per > margin + threshold + */ +#define CFG_TGT_DEFAULT_GTX_PER_MARGIN 2 +/* + * step for every move + */ +#define CFG_TGT_DEFAULT_GTX_TPC_STEP 1 +/* + * lowest TPC + */ +#define CFG_TGT_DEFAULT_GTX_TPC_MIN 0 +/* + * enable all BW 20/40/80/160 + */ +#define CFG_TGT_DEFAULT_GTX_BW_MASK 0xf + +/* + * number of vdevs that can support OCB + */ +#define CFG_TGT_NUM_OCB_VDEVS 1 + +/* + * maximum number of channels that can do OCB + */ +#define CFG_TGT_NUM_OCB_CHANNELS 2 + +/* + * maximum number of channels in an OCB schedule + */ +#define CFG_TGT_NUM_OCB_SCHEDULES 2 + +#endif /*__WLAN_TGT_DEF_CONFIG_H__ */ diff --git a/fw/wmi.h b/fw/wmi.h old mode 100755 new mode 100644 index 06ff44e1d7f7..6d760c150ff5 --- a/fw/wmi.h +++ b/fw/wmi.h @@ -50,7 +50,6 @@ extern "C" { #endif - #define HTC_PROTOCOL_VERSION 0x0002 #define WMI_PROTOCOL_VERSION 0x0002 @@ -58,37 +57,38 @@ extern "C" { #define WMI_MODE_MAX 8 #define WMI_MAX_RATE_MASK 6 - PREPACK struct host_app_area_s { - A_UINT32 wmi_protocol_ver; + A_UINT32 wmi_protocol_ver; } POSTPACK; - #undef MS -#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB) +#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB) #undef SM -#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) +#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK) #undef WO -#define WO(_f) ((_f##_OFFSET) >> 2) +#define WO(_f) ((_f ## _OFFSET) >> 2) #undef GET_FIELD #define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f) #undef SET_FIELD #define SET_FIELD(_addr, _f, _val) \ - (*((A_UINT32 *)(_addr) + WO(_f)) = \ - (*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f)) + (*((A_UINT32 *)(_addr) + WO(_f)) = \ + (*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f)) #define WMI_GET_FIELD(_msg_buf, _msg_type, _f) \ - GET_FIELD(_msg_buf, _msg_type ## _ ## _f) + GET_FIELD(_msg_buf, _msg_type ## _ ## _f) #define WMI_SET_FIELD(_msg_buf, _msg_type, _f, _val) \ - SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val) + SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val) -#define WMI_EP_APASS WMI_EP_APSS /* TYPO: leave incorrect name as an alias for the correct name */ -#define WMI_EP_APSS 0x0 /* WLAN driver running on apps processor sub-system */ +/* TYPO: leave incorrect name as an alias for the correct name */ +#define WMI_EP_APASS WMI_EP_APSS +/* WLAN driver running on apps processor sub-system */ +#define WMI_EP_APSS 0x0 #define WMI_EP_LPASS 0x1 #define WMI_EP_SENSOR 0x2 -#define WMI_EP_NANOHUB 0x3 /* WLAN driver running on NANO Hub */ +/* WLAN driver running on NANO Hub */ +#define WMI_EP_NANOHUB 0x3 #define WMI_EP_MODEM 0x4 #define WMI_EP_LOCATION 0x5 @@ -96,37 +96,35 @@ PREPACK struct host_app_area_s { * Control Path */ typedef PREPACK struct { - A_UINT32 commandId : 24, - reserved : 2, /* used for WMI endpoint ID */ - plt_priv : 6; /* platform private */ -} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + A_UINT32 commandId : 24, reserved : 2, /* used for WMI endpoint ID */ + plt_priv : 6; /* platform private */ +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ #define WMI_CMD_HDR_COMMANDID_LSB 0 #define WMI_CMD_HDR_COMMANDID_MASK 0x00ffffff #define WMI_CMD_HDR_COMMANDID_OFFSET 0x00000000 -#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK 0x03000000 -#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET 24 -#define WMI_CMD_HDR_PLT_PRIV_LSB 24 -#define WMI_CMD_HDR_PLT_PRIV_MASK 0xff000000 -#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000 +#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK 0x03000000 +#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET 24 +#define WMI_CMD_HDR_PLT_PRIV_LSB 24 +#define WMI_CMD_HDR_PLT_PRIV_MASK 0xff000000 +#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000 /* * List of Commnands */ typedef enum { - WMI_EXTENSION_CMDID, //used in wmi_svc.c /* Non-wireless extensions */ - WMI_IGNORE_CMDID, //used in wlan_wmi.c + WMI_EXTENSION_CMDID, /* used in wmi_svc.c / * Non-wireless extensions * / */ + WMI_IGNORE_CMDID, /* used in wlan_wmi.c */ } WMI_COMMAND_ID; - typedef enum { - NONE_CRYPT = 0x01, - WEP_CRYPT = 0x02, - TKIP_CRYPT = 0x04, - AES_CRYPT = 0x08, + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x04, + AES_CRYPT = 0x08, #ifdef WAPI_ENABLE - WAPI_CRYPT = 0x10, -#endif /*WAPI_ENABLE*/ + WAPI_CRYPT = 0x10, +#endif /*WAPI_ENABLE */ } CRYPTO_TYPE; #define WMI_MAX_SSID_LEN 32 @@ -136,63 +134,63 @@ typedef enum { */ #define WMI_PMK_LEN 32 - /* * WMI_ADD_CIPHER_KEY_CMDID */ typedef enum { - PAIRWISE_USAGE = 0x00, - GROUP_USAGE = 0x01, - TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ } KEY_USAGE; + /* * List of Events (target to host) */ typedef enum { - WMI_EXTENSION_EVENTID //wmi_profhook.c and umac_wmi_events.c + WMI_EXTENSION_EVENTID, /* wmi_profhook.c and umac_wmi_events.c */ } WMI_EVENT_ID; typedef enum { - WMI_11A_CAPABILITY = 1, - WMI_11G_CAPABILITY = 2, - WMI_11AG_CAPABILITY = 3, - WMI_11NA_CAPABILITY = 4, - WMI_11NG_CAPABILITY = 5, - WMI_11NAG_CAPABILITY = 6, - WMI_11AC_CAPABILITY = 7, - WMI_11AX_CAPABILITY = 8, - // END CAPABILITY - WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY), + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, + WMI_11NA_CAPABILITY = 4, + WMI_11NG_CAPABILITY = 5, + WMI_11NAG_CAPABILITY = 6, + WMI_11AC_CAPABILITY = 7, + WMI_11AX_CAPABILITY = 8, + /* END CAPABILITY */ + WMI_11N_CAPABILITY_OFFSET = + (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY), } WMI_PHY_CAPABILITY; - /* Deprectated, need clean up */ #define WMI_MAX_RX_META_SZ (12) typedef PREPACK struct { - A_INT8 rssi; - A_UINT8 info; /* usage of 'info' field(8-bit): - * b1:b0 - WMI_MSG_TYPE - * b4:b3:b2 - UP(tid) - * b5 - Used in AP mode. More-data in tx dir, PS in rx. - * b7:b6 - Dot3 header(0), - * Dot11 Header(1), - * ACL data(2) - */ + A_INT8 rssi; + A_UINT8 info; /* usage of 'info' field(8-bit): + * b1:b0 - WMI_MSG_TYPE + * b4:b3:b2 - UP(tid) + * b5 - Used in AP mode. More-data in tx dir, PS in rx. + * b7:b6 - Dot3 header(0), + * Dot11 Header(1), + * ACL data(2) + */ - A_UINT16 info2; /* usage of 'info2' field(16-bit): - * b11:b0 - seq_no - * b12 - A-MSDU? - * b15:b13 - META_DATA_VERSION 0 - 7 - */ - A_UINT16 info3; /* b3:b2:b1:b0 - device id - * b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx - * b7:b5 - unused? - * b15:b8 - pad before data start(irrespective of meta version) - */ + A_UINT16 info2; /* usage of 'info2' field(16-bit): + * b11:b0 - seq_no + * b12 - A-MSDU? + * b15:b13 - META_DATA_VERSION 0 - 7 + */ + A_UINT16 info3; /* b3:b2:b1:b0 - device id + * b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx + * b7:b5 - unused? + * b15:b8 - pad before data start(irrespective of meta version) + */ } POSTPACK WMI_DATA_HDR; + #ifdef __cplusplus } #endif - #endif /* _WMI_H_ */ diff --git a/fw/wmi_services.h b/fw/wmi_services.h old mode 100755 new mode 100644 index cf128bb43a29..64cda28e1ab5 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -35,170 +35,262 @@ #ifndef _WMI_SERVICES_H_ #define _WMI_SERVICES_H_ - #ifdef __cplusplus extern "C" { #endif -typedef enum { - WMI_SERVICE_BEACON_OFFLOAD=0, /* beacon offload */ - WMI_SERVICE_SCAN_OFFLOAD=1, /* scan offload */ - WMI_SERVICE_ROAM_SCAN_OFFLOAD=2, /* roam scan offload */ - WMI_SERVICE_BCN_MISS_OFFLOAD=3, /* beacon miss offload */ - WMI_SERVICE_STA_PWRSAVE=4, /* fake sleep + basic power save */ - WMI_SERVICE_STA_ADVANCED_PWRSAVE=5, /* uapsd, pspoll, force sleep */ - WMI_SERVICE_AP_UAPSD=6, /* uapsd on AP */ - WMI_SERVICE_AP_DFS=7, /* DFS on AP */ - WMI_SERVICE_11AC=8, /* supports 11ac */ - WMI_SERVICE_BLOCKACK=9, /* Supports triggering ADDBA/DELBA from host*/ - WMI_SERVICE_PHYERR=10, /* PHY error */ - WMI_SERVICE_BCN_FILTER=11, /* Beacon filter support */ - WMI_SERVICE_RTT=12, /* RTT (round trip time) support */ - WMI_SERVICE_WOW=13, /* WOW Support */ - WMI_SERVICE_RATECTRL_CACHE=14, /* Rate-control caching */ - WMI_SERVICE_IRAM_TIDS=15, /* TIDs in IRAM */ - WMI_SERVICE_ARPNS_OFFLOAD=16, /* ARP NS Offload support for STA vdev */ - WMI_SERVICE_NLO=17, /* Network list offload service */ - WMI_SERVICE_GTK_OFFLOAD=18, /* GTK offload */ - WMI_SERVICE_SCAN_SCH=19, /* Scan Scheduler Service */ - WMI_SERVICE_CSA_OFFLOAD=20, /* CSA offload service */ - WMI_SERVICE_CHATTER=21, /* Chatter service */ - WMI_SERVICE_COEX_FREQAVOID=22, /* FW report freq range to avoid */ - WMI_SERVICE_PACKET_POWER_SAVE=23, /* packet power save service */ - WMI_SERVICE_FORCE_FW_HANG=24, /* Service to test the firmware recovery mechanism */ - WMI_SERVICE_GPIO=25, /* GPIO service */ - WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM=26, /* Modulated DTIM support */ - WMI_STA_UAPSD_BASIC_AUTO_TRIG=27, /* Basic version of station UAPSD AC Trigger Generation Method with - * variable tigger periods (service, delay, and suspend intervals) */ - WMI_STA_UAPSD_VAR_AUTO_TRIG=28, /* Station UAPSD AC Trigger Generation Method with variable - * trigger periods (service, delay, and suspend intervals) */ - WMI_SERVICE_STA_KEEP_ALIVE=29, /* Serivce to support the STA KEEP ALIVE mechanism */ - WMI_SERVICE_TX_ENCAP=30, /* Packet type for TX encapsulation */ - WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC=31, /* detect out-of-sync sleeping stations */ - WMI_SERVICE_EARLY_RX=32, /* adaptive early-rx feature */ - WMI_SERVICE_STA_SMPS=33, /* STA MIMO-PS */ - WMI_SERVICE_FWTEST=34, /* Firmware test service */ - WMI_SERVICE_STA_WMMAC=35, /* STA WMMAC */ - WMI_SERVICE_TDLS=36, /* TDLS support */ - WMI_SERVICE_BURST=37, /* SIFS spaced burst support */ - WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE=38, /* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */ - WMI_SERVICE_ADAPTIVE_OCS=39, /* Service to support adaptive off-channel scheduler */ - WMI_SERVICE_BA_SSN_SUPPORT=40, /* target will provide Sequence number for the peer/tid combo */ - WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE=41, - WMI_SERVICE_WLAN_HB=42, /* wlan HB service */ - WMI_SERVICE_LTE_ANT_SHARE_SUPPORT=43, /* support LTE/WLAN antenna sharing */ - WMI_SERVICE_BATCH_SCAN=44, /* Service to support batch scan */ - WMI_SERVICE_QPOWER=45, /* QPower service */ - WMI_SERVICE_PLMREQ=46, - WMI_SERVICE_THERMAL_MGMT=47, /* thermal throttling support */ - WMI_SERVICE_RMC=48, /* RMC support */ - WMI_SERVICE_MHF_OFFLOAD=49, /* multi-hop forwarding offload */ - WMI_SERVICE_COEX_SAR=50, /* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */ - WMI_SERVICE_BCN_TXRATE_OVERRIDE=51, /* Will support the bcn/prb rsp rate override */ - WMI_SERVICE_NAN=52, /* Neighbor Awareness Network */ - WMI_SERVICE_L1SS_STAT=53, /* L1SS statistics counter report */ - WMI_SERVICE_ESTIMATE_LINKSPEED=54, /* Linkspeed Estimation per peer */ - WMI_SERVICE_OBSS_SCAN=55, /* Service to support OBSS scan */ - WMI_SERVICE_TDLS_OFFCHAN=56, /* TDLS off channel support */ - WMI_SERVICE_TDLS_UAPSD_BUFFER_STA=57, /* TDLS UAPSD Buffer STA support */ - WMI_SERVICE_TDLS_UAPSD_SLEEP_STA=58, /* TDLS UAPSD Sleep STA support */ - WMI_SERVICE_IBSS_PWRSAVE=59, /* IBSS power save support */ - WMI_SERVICE_LPASS=60, /* Service to support LPASS */ - WMI_SERVICE_EXTSCAN=61, /* Extended Scans */ - WMI_SERVICE_D0WOW=62, /* D0-WOW Support */ - WMI_SERVICE_HSOFFLOAD=63, /* Hotspot offload feature Support */ - WMI_SERVICE_ROAM_HO_OFFLOAD=64, /* roam handover offload */ - WMI_SERVICE_RX_FULL_REORDER=65, /* target-based Rx full reorder */ - WMI_SERVICE_DHCP_OFFLOAD=66, /* DHCP offload support */ - WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT=67, /* STA RX DATA offload to IPA support */ - WMI_SERVICE_MDNS_OFFLOAD=68, /* mDNS responder offload support */ - WMI_SERVICE_SAP_AUTH_OFFLOAD=69, /* softap auth offload */ - WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT=70, /* Dual Band Simultaneous support */ - WMI_SERVICE_OCB=71, /* OCB mode support */ - WMI_SERVICE_AP_ARPNS_OFFLOAD=72, /* arp offload support for ap mode vdev */ - WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT=73, /* Per band chainmask support */ - WMI_SERVICE_PACKET_FILTER_OFFLOAD=74, /* Per vdev packet filters */ - WMI_SERVICE_MGMT_TX_HTT=75, /* Mgmt Tx via HTT interface */ - WMI_SERVICE_MGMT_TX_WMI=76, /* Mgmt Tx via WMI interface */ - WMI_SERVICE_EXT_MSG=77, /* WMI_SERVICE_READY_EXT msg follows */ - WMI_SERVICE_MAWC=78, /* Motion Aided WiFi Connectivity (MAWC)*/ - WMI_SERVICE_PEER_ASSOC_CONF=79, /* target will send ASSOC_CONF after ASSOC_CMD is processed */ - WMI_SERVICE_EGAP=80, /* enhanced green ap support */ - WMI_SERVICE_STA_PMF_OFFLOAD=81, /* FW supports 11W PMF Offload for STA */ - WMI_SERVICE_UNIFIED_WOW_CAPABILITY=82, /* FW supports unified D0 and D3 wow */ - WMI_SERVICE_ENHANCED_PROXY_STA=83, /* Enhanced ProxySTA mode support */ - WMI_SERVICE_ATF=84, /* Air Time Fairness support */ - WMI_SERVICE_COEX_GPIO=85, /* BTCOEX GPIO support */ - WMI_SERVICE_AUX_SPECTRAL_INTF=86, /* Aux Radio enhancement support for ignoring spectral scan intf from main radios */ - WMI_SERVICE_AUX_CHAN_LOAD_INTF=87, /* Aux Radio enhancement support for ignoring chan load intf from main radios*/ - WMI_SERVICE_BSS_CHANNEL_INFO_64=88, /* BSS channel info (freq, noise floor, 64-bit counters) event support */ - WMI_SERVICE_ENTERPRISE_MESH=89, /* Enterprise MESH Service Support */ - WMI_SERVICE_RESTRT_CHNL_SUPPORT=90, /* Restricted Channel Support */ - WMI_SERVICE_BPF_OFFLOAD=91, /* FW supports bpf offload */ - WMI_SERVICE_SYNC_DELETE_CMDS=92, /* FW sends response event for Peer, Vdev delete commands */ - WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT=93, - WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT=94, - WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES=95, /* allow per-peer tx MCS min/max limits by host */ - WMI_SERVICE_NAN_DATA=96, /* FW supports NAN data */ - WMI_SERVICE_NAN_RTT=97, /* FW supports NAN RTT */ - WMI_SERVICE_11AX=98, /* FW supports 802.11ax */ - /* WMI_SERVICE_DEPRECATED_REPLACE - * FW supports these new WMI commands, to be used rather than - * deprecated matching commands: - * - WMI_PDEV_SET_PCL_CMDID (vs. WMI_SOC_SET_PCL_CMDID) - * - WMI_PDEV_SET_HW_MODE_CMDID (vs. WMI_SOC_SET_HW_MODE_CMDID) - * - WMI_PDEV_SET_MAC_CONFIG_CMDID (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID) - * - WMI_PDEV_SET_ANTENNA_MODE_CMDID (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID) - * - WMI_VDEV_SET_DSCP_TID_MAP_CMDID (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID) - */ - WMI_SERVICE_DEPRECATED_REPLACE=99, - WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE=100, /* FW supports a new mode that allows to run connection tracker in host */ - WMI_SERVICE_ENHANCED_MCAST_FILTER=101, /* FW supports enhanced multicast filtering (of mcast IP inside ucast WLAN) */ - WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT=102, /* periodic channel stats service */ - WMI_SERVICE_MESH_11S=103, /* 11s mesh service support */ - WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT=104, /* FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate) channel bandwidth */ - WMI_SERVICE_VDEV_RX_FILTER=105, /* Support per-vdev specs of which rx frames to filter out */ - WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT=106, - WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET=107, /* FW supports marking the first data packet which wakes the host from suspend */ - WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET=108, /* FW supports command that can add/delete multiple mcast filters */ - /* WMI_SERVICE_HOST_MANAGED_RX_REORDER - - * FW supports host-managed RX reorder. - * Host managed RX reorder involves RX BA state machine handling - * on peer/TID basis, REO configuration for HW based reordering/PN - * check and processing reorder exceptions generated by HW. - */ - WMI_SERVICE_HOST_MANAGED_RX_REORDER=109, - /* Specify whether the target supports the following WMI messages for - * reading / writing its flash memory: - * WMI_READ_DATA_FROM_FLASH_CMDID, - * WMI_READ_DATA_FROM_FLASH_EVENTID, - * WMI_TRANSFER_DATA_TO_FLASH_CMDID, - * WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, - */ - WMI_SERVICE_FLASH_RDWR_SUPPORT=110, - WMI_SERVICE_WLAN_STATS_REPORT=111, /* support WLAN stats report */ +typedef enum { + WMI_SERVICE_BEACON_OFFLOAD = 0, /* beacon offload */ + WMI_SERVICE_SCAN_OFFLOAD = 1, /* scan offload */ + WMI_SERVICE_ROAM_SCAN_OFFLOAD = 2, /* roam scan offload */ + WMI_SERVICE_BCN_MISS_OFFLOAD = 3, /* beacon miss offload */ + /* fake sleep + basic power save */ + WMI_SERVICE_STA_PWRSAVE = 4, + WMI_SERVICE_STA_ADVANCED_PWRSAVE = 5, /* uapsd, pspoll, force sleep */ + WMI_SERVICE_AP_UAPSD = 6, /* uapsd on AP */ + WMI_SERVICE_AP_DFS = 7, /* DFS on AP */ + WMI_SERVICE_11AC = 8, /* supports 11ac */ + /* Supports triggering ADDBA/DELBA from host*/ + WMI_SERVICE_BLOCKACK = 9, + WMI_SERVICE_PHYERR = 10, /* PHY error */ + WMI_SERVICE_BCN_FILTER = 11, /* Beacon filter support */ + /* RTT (round trip time) support */ + WMI_SERVICE_RTT = 12, + WMI_SERVICE_WOW = 13, /* WOW Support */ + WMI_SERVICE_RATECTRL_CACHE = 14, /* Rate-control caching */ + WMI_SERVICE_IRAM_TIDS = 15, /* TIDs in IRAM */ + /* ARP NS Offload support for STA vdev */ + WMI_SERVICE_ARPNS_OFFLOAD = 16, + /* Network list offload service */ + WMI_SERVICE_NLO = 17, + WMI_SERVICE_GTK_OFFLOAD = 18, /* GTK offload */ + WMI_SERVICE_SCAN_SCH = 19, /* Scan Scheduler Service */ + WMI_SERVICE_CSA_OFFLOAD = 20, /* CSA offload service */ + WMI_SERVICE_CHATTER = 21, /* Chatter service */ + /* FW report freq range to avoid */ + WMI_SERVICE_COEX_FREQAVOID = 22, + WMI_SERVICE_PACKET_POWER_SAVE = 23, /* packet power save service */ + /* Service to test the firmware recovery mechanism */ + WMI_SERVICE_FORCE_FW_HANG = 24, + WMI_SERVICE_GPIO = 25, /* GPIO service */ + /* Modulated DTIM support */ + WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, + /** + * Basic version of station UAPSD AC Trigger Generation Method with + * variable tigger periods (service, delay, and suspend intervals) + */ + WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, + /** + * Station UAPSD AC Trigger Generation Method with variable + * trigger periods (service, delay, and suspend intervals) + */ + WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, + /* Serivce to support the STA KEEP ALIVE mechanism */ + WMI_SERVICE_STA_KEEP_ALIVE = 29, + /* Packet type for TX encapsulation */ + WMI_SERVICE_TX_ENCAP = 30, + /* detect out-of-sync sleeping stations */ + WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, + WMI_SERVICE_EARLY_RX = 32, /* adaptive early-rx feature */ + WMI_SERVICE_STA_SMPS = 33, /* STA MIMO-PS */ + WMI_SERVICE_FWTEST = 34, /* Firmware test service */ + WMI_SERVICE_STA_WMMAC = 35, /* STA WMMAC */ + WMI_SERVICE_TDLS = 36, /* TDLS support */ + WMI_SERVICE_BURST = 37, /* SIFS spaced burst support */ + /* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */ + WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, + /* Service to support adaptive off-channel scheduler */ + WMI_SERVICE_ADAPTIVE_OCS = 39, + /* target will provide Sequence number for the peer/tid combo */ + WMI_SERVICE_BA_SSN_SUPPORT = 40, + WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, + WMI_SERVICE_WLAN_HB = 42, /* wlan HB service */ + /* support LTE/WLAN antenna sharing */ + WMI_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, + WMI_SERVICE_BATCH_SCAN = 44, /*Service to support batch scan*/ + WMI_SERVICE_QPOWER = 45, /* QPower service */ + WMI_SERVICE_PLMREQ = 46, + WMI_SERVICE_THERMAL_MGMT = 47, /* thermal throttling support */ + WMI_SERVICE_RMC = 48, /* RMC support */ + /* multi-hop forwarding offload */ + WMI_SERVICE_MHF_OFFLOAD = 49, + /* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */ + WMI_SERVICE_COEX_SAR = 50, + /* Will support the bcn/prb rsp rate override */ + WMI_SERVICE_BCN_TXRATE_OVERRIDE = 51, + WMI_SERVICE_NAN = 52, /* Neighbor Awareness Network */ + /* L1SS statistics counter report */ + WMI_SERVICE_L1SS_STAT = 53, + /* Linkspeed Estimation per peer */ + WMI_SERVICE_ESTIMATE_LINKSPEED = 54, + /* Service to support OBSS scan */ + WMI_SERVICE_OBSS_SCAN = 55, + WMI_SERVICE_TDLS_OFFCHAN = 56, /* TDLS off channel support */ + /* TDLS UAPSD Buffer STA support */ + WMI_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, + /* TDLS UAPSD Sleep STA support */ + WMI_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, + WMI_SERVICE_IBSS_PWRSAVE = 59, /* IBSS power save support */ + WMI_SERVICE_LPASS = 60, /*Service to support LPASS*/ + WMI_SERVICE_EXTSCAN = 61, /* Extended Scans */ + WMI_SERVICE_D0WOW = 62, /* D0-WOW Support */ + /* Hotspot offload feature Support */ + WMI_SERVICE_HSOFFLOAD = 63, + WMI_SERVICE_ROAM_HO_OFFLOAD = 64, /* roam handover offload */ + /* target-based Rx full reorder */ + WMI_SERVICE_RX_FULL_REORDER = 65, + WMI_SERVICE_DHCP_OFFLOAD = 66, /* DHCP offload support */ + /* STA RX DATA offload to IPA support */ + WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, + /* mDNS responder offload support */ + WMI_SERVICE_MDNS_OFFLOAD = 68, + WMI_SERVICE_SAP_AUTH_OFFLOAD = 69, /* softap auth offload */ + /* Dual Band Simultaneous support */ + WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, + WMI_SERVICE_OCB = 71, /* OCB mode support */ + /* arp offload support for ap mode vdev */ + WMI_SERVICE_AP_ARPNS_OFFLOAD = 72, + /* Per band chainmask support */ + WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, + WMI_SERVICE_PACKET_FILTER_OFFLOAD = 74, /* Per vdev packet filters */ + WMI_SERVICE_MGMT_TX_HTT = 75, /* Mgmt Tx via HTT interface */ + WMI_SERVICE_MGMT_TX_WMI = 76, /* Mgmt Tx via WMI interface */ + /* WMI_SERVICE_READY_EXT msg follows */ + WMI_SERVICE_EXT_MSG = 77, + /* Motion Aided WiFi Connectivity (MAWC)*/ + WMI_SERVICE_MAWC = 78, + /* target will send ASSOC_CONF after ASSOC_CMD is processed */ + WMI_SERVICE_PEER_ASSOC_CONF = 79, + WMI_SERVICE_EGAP = 80, /* enhanced green ap support */ + /* FW supports 11W PMF Offload for STA */ + WMI_SERVICE_STA_PMF_OFFLOAD = 81, + /* FW supports unified D0 and D3 wow */ + WMI_SERVICE_UNIFIED_WOW_CAPABILITY = 82, + /* Enhanced ProxySTA mode support */ + WMI_SERVICE_ENHANCED_PROXY_STA = 83, + WMI_SERVICE_ATF = 84, /* Air Time Fairness support */ + WMI_SERVICE_COEX_GPIO = 85, /* BTCOEX GPIO support */ + /** + * Aux Radio enhancement support for ignoring spectral scan intf + * from main radios + */ + WMI_SERVICE_AUX_SPECTRAL_INTF = 86, + /** + * Aux Radio enhancement support for ignoring chan load intf + * from main radios + */ + WMI_SERVICE_AUX_CHAN_LOAD_INTF = 87, + /** + * BSS channel info (freq, noise floor, 64-bit counters) + * event support + */ + WMI_SERVICE_BSS_CHANNEL_INFO_64 = 88, + /* Enterprise MESH Service Support */ + WMI_SERVICE_ENTERPRISE_MESH = 89, + WMI_SERVICE_RESTRT_CHNL_SUPPORT = 90, /* Restricted Channel Support */ + WMI_SERVICE_BPF_OFFLOAD = 91, /* FW supports bpf offload */ + /* FW sends response event for Peer, Vdev delete commands */ + WMI_SERVICE_SYNC_DELETE_CMDS = 92, + WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, + WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, + /* allow per-peer tx MCS min/max limits by host */ + WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, + WMI_SERVICE_NAN_DATA = 96, /* FW supports NAN data */ + WMI_SERVICE_NAN_RTT = 97, /* FW supports NAN RTT */ + WMI_SERVICE_11AX = 98, /* FW supports 802.11ax */ + /* WMI_SERVICE_DEPRECATED_REPLACE + * FW supports these new WMI commands, to be used rather than + * deprecated matching commands: + * - WMI_PDEV_SET_PCL_CMDID (vs. WMI_SOC_SET_PCL_CMDID) + * - WMI_PDEV_SET_HW_MODE_CMDID + * (vs. WMI_SOC_SET_HW_MODE_CMDID) + * - WMI_PDEV_SET_MAC_CONFIG_CMDID + * (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID) + * - WMI_PDEV_SET_ANTENNA_MODE_CMDID + * (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID) + * - WMI_VDEV_SET_DSCP_TID_MAP_CMDID + * (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID) + */ + WMI_SERVICE_DEPRECATED_REPLACE = 99, + /** + * FW supports a new mode that allows to run connection tracker + * in host + */ + WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, + /** + * FW supports enhanced multicast filtering (of mcast IP inside + * ucast WLAN) + */ + WMI_SERVICE_ENHANCED_MCAST_FILTER = 101, + /* periodic channel stats service */ + WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, + WMI_SERVICE_MESH_11S = 103, + /** + * FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate) + * channel bandwidth + */ + WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, + /* Support per-vdev specs of which rx frames to filter out */ + WMI_SERVICE_VDEV_RX_FILTER = 105, + WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, + /** + * FW supports marking the first data packet which wakes + * the host from suspend + */ + WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, + /* FW supports command that can add/delete multiple mcast filters */ + WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, + /* WMI_SERVICE_HOST_MANAGED_RX_REORDER - + * FW supports host-managed RX reorder. + * Host managed RX reorder involves RX BA state machine handling + * on peer/TID basis, REO configuration for HW based reordering/PN + * check and processing reorder exceptions generated by HW. + */ + WMI_SERVICE_HOST_MANAGED_RX_REORDER = 109, + /* Specify whether the target supports the following WMI messages + * for reading / writing its flash memory: + * WMI_READ_DATA_FROM_FLASH_CMDID, + * WMI_READ_DATA_FROM_FLASH_EVENTID, + * WMI_TRANSFER_DATA_TO_FLASH_CMDID, + * WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, + */ + WMI_SERVICE_FLASH_RDWR_SUPPORT = 110, + WMI_SERVICE_WLAN_STATS_REPORT = 111, /* support WLAN stats report */ - /******* ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED *******/ + /* WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT - + * FW supports bigger MSDU ID partition which is defined as + * HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. When both host and FW support + * new partition, FW uses HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. If host + * doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN + * Handshaking is done through WMI_INIT and WMI service ready + * + * support bigger MSDU ID partition + */ + WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, + WMI_SERVICE_DFS_PHYERR_OFFLOAD = 113, - WMI_MAX_SERVICE=128, /* max service */ + /*** ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED ***/ - /* NOTE: - * The above service flags are delivered in the wmi_service_bitmap field - * of the WMI_SERVICE_READY_EVENT message. - * The below service flags are delivered in a WMI_SERVICE_AVAILABLE_EVENT - * message rather than in the WMI_SERVICE_READY_EVENT message's - * wmi_service_bitmap field. - * The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the - * WMI_SERVICE_READY_EVENT message. - */ + WMI_MAX_SERVICE = 128, /* max service */ - /*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/ - /*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/ + /** + * NOTE: + * The above service flags are delivered in the wmi_service_bitmap + * field of the WMI_SERVICE_READY_EVENT message. + * The below service flags are delivered in a + * WMI_SERVICE_AVAILABLE_EVENT message rather than in the + * WMI_SERVICE_READY_EVENT message's wmi_service_bitmap field. + * The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the + * WMI_SERVICE_READY_EVENT message. + */ - WMI_MAX_EXT_SERVICE + /*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/ + /*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/ + + WMI_MAX_EXT_SERVICE } WMI_SERVICE; @@ -207,59 +299,61 @@ typedef enum { #define WMI_NUM_EXT_SERVICES (WMI_MAX_EXT_SERVICE - WMI_MAX_SERVICE) #define WMI_SERVICE_EXT_BM_SIZE32 ((WMI_NUM_EXT_SERVICES + 31) / 32) -#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD /* depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help compiling with old host driver */ +/** + * depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help + * compiling with old host driver + */ +#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD /* * turn on the WMI service bit corresponding to the WMI service. */ #define WMI_SERVICE_ENABLE(pwmi_svc_bmap,svc_id) \ - ( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \ - (1 << ((svc_id)%(sizeof(A_UINT32)))) ) + ( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \ + (1 << ((svc_id)%(sizeof(A_UINT32)))) ) #define WMI_SERVICE_DISABLE(pwmi_svc_bmap,svc_id) \ - ( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \ - ( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) ) + ( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \ + ( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) ) #define WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap,svc_id) \ - ( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \ - (1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0) - + ( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \ + (1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0) #define WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \ - do { \ - if (svc_id < WMI_MAX_SERVICE) { \ - WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \ - } else { \ - int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \ - int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \ - (pwmi_svc_ext_bmap)[word] |= (1 << bit); \ - } \ - } while (0) + do { \ + if (svc_id < WMI_MAX_SERVICE) { \ + WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \ + } else { \ + int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \ + int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \ + (pwmi_svc_ext_bmap)[word] |= (1 << bit); \ + } \ + } while (0) #define WMI_SERVICE_EXT_DISABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \ - do { \ - if (svc_id < WMI_MAX_SERVICE) { \ - WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \ - } else { \ - int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \ - int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \ - (pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \ - } \ - } while (0) + do { \ + if (svc_id < WMI_MAX_SERVICE) { \ + WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \ + } else { \ + int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \ + int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \ + (pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \ + } \ + } while (0) #define WMI_SERVICE_EXT_IS_ENABLED(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \ - /* If the service ID is beyond the known limit, treat it as disabled */ \ - ((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \ - /* If service ID is in the non-extension range, use the old check */ \ - (svc_id) < WMI_MAX_SERVICE ? \ - WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \ - /* If service ID is in the extended range, check ext_bmap */ \ - (pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \ - ((svc_id) & 0x1f)) + /* If the service ID is beyond the known limit, treat it as disabled */ \ + ((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \ + /* If service ID is in the non-extension range, use the old check */ \ + (svc_id) < WMI_MAX_SERVICE ? \ + WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \ + /* If service ID is in the extended range, check ext_bmap */ \ + (pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \ + ((svc_id) & 0x1f)) #ifdef __cplusplus } #endif - #endif /*_WMI_SERVICES_H_*/ diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h old mode 100755 new mode 100644 index e9d0feba7c96..563ccfadf3e7 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -24,6 +24,7 @@ * under proprietary terms before Copyright ownership was assigned * to the Linux Foundation. */ + #ifndef _WMI_TLV_DEFS_H_ #define _WMI_TLV_DEFS_H_ @@ -32,37 +33,37 @@ extern "C" { #endif #define WMITLV_FIELD_BUF_IS_ALLOCATED(elem_name) \ - is_allocated_##elem_name + is_allocated_ ## elem_name #define WMITLV_FIELD_NUM_OF(elem_name) \ - num_##elem_name + num_ ## elem_name /* Define the structure typedef for the TLV parameters of each cmd/event */ #define WMITLV_TYPEDEF_STRUCT_PARAMS_TLVS(wmi_cmd_event_id) \ - wmi_cmd_event_id##_param_tlvs + wmi_cmd_event_id ## _param_tlvs /* * The following macro WMITLV_OP_* are created by the macro WMITLV_ELEM(). */ /* macro to define the TLV name in the correct order. When (op==TAG_ORDER) */ -#define WMITLV_OP_TAG_ORDER_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - wmi_cmd_event_id##_tlv_order_##elem_name, +#define WMITLV_OP_TAG_ORDER_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ + wmi_cmd_event_id ## _tlv_order_ ## elem_name, /* macro to define the TLV name with the TLV Tag value. When (op==TAG_ID) */ #define WMITLV_OP_TAG_ID_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - wmi_cmd_event_id##_tlv_tag_##elem_name = elem_tlv_tag, + wmi_cmd_event_id ## _tlv_tag_ ## elem_name = elem_tlv_tag, /* macro to define the TLV name with the TLV structure size. May not be accurate when variable length. When (op==TAG_SIZEOF) */ -#define WMITLV_OP_TAG_SIZEOF_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - wmi_cmd_event_id##_sizeof_##elem_name = sizeof(elem_struc_type), +#define WMITLV_OP_TAG_SIZEOF_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ + wmi_cmd_event_id ## _sizeof_ ## elem_name = sizeof(elem_struc_type), /* macro to define the TLV name with value indicating whether the TLV is variable length. When (op==TAG_VAR_SIZED) */ #define WMITLV_OP_TAG_VAR_SIZED_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - wmi_cmd_event_id##_var_sized_##elem_name = var_len, + wmi_cmd_event_id ## _var_sized_ ## elem_name = var_len, /* macro to define the TLV name with value indicating the fixed array size. When (op==TAG_ARR_SIZE) */ #define WMITLV_OP_TAG_ARR_SIZE_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - wmi_cmd_event_id##_arr_size_##elem_name = arr_size, + wmi_cmd_event_id ## _arr_size_ ## elem_name = arr_size, /* * macro to define afew fields associated to a TLV. For example, a structure pointer with the TLV name. @@ -71,9 +72,9 @@ extern "C" { * should be updated too. */ #define WMITLV_OP_STRUCT_FIELD_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - elem_struc_type *elem_name; \ - A_UINT32 WMITLV_FIELD_NUM_OF(elem_name); \ - A_UINT32 WMITLV_FIELD_BUF_IS_ALLOCATED(elem_name); + elem_struc_type *elem_name; \ + A_UINT32 WMITLV_FIELD_NUM_OF(elem_name); \ + A_UINT32 WMITLV_FIELD_BUF_IS_ALLOCATED(elem_name); /* * A "mirror" structure that contains the fields that is created by the @@ -82,9 +83,9 @@ extern "C" { * so that they both has the same kind of fields. */ typedef struct { - void *tlv_ptr; /* Pointer to the TLV Buffer. But the "real" one will have the right type instead of void. */ - A_UINT32 num_elements; /* Number of elements. For non-array, this is one. For array, this is the number of elements. */ - A_UINT32 buf_is_allocated;/* Boolean flag to indicate that a new buffer is allocated for this TLV. */ + void *tlv_ptr; /* Pointer to the TLV Buffer. But the "real" one will have the right type instead of void. */ + A_UINT32 num_elements; /* Number of elements. For non-array, this is one. For array, this is the number of elements. */ + A_UINT32 buf_is_allocated; /* Boolean flag to indicate that a new buffer is allocated for this TLV. */ } wmitlv_cmd_param_info; /* @@ -92,17 +93,17 @@ typedef struct { * WMITLV_ELEM is re-defined to a "op" specific macro. * Eg. WMITLV_OP_TAG_ORDER_macro is created for the op_type=TAG_ORDER. */ -#define WMITLV_ELEM(wmi_cmd_event_id, op_type, param_ptr, param_len, elem_tlv_tag, elem_struc_type, elem_name, var_len) \ - WMITLV_OP_##op_type##_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, WMITLV_ARR_SIZE_INVALID) +#define WMITLV_ELEM(wmi_cmd_event_id, op_type, param_ptr, param_len, elem_tlv_tag, elem_struc_type, elem_name, var_len) \ + WMITLV_OP_ ## op_type ## _macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, WMITLV_ARR_SIZE_INVALID) /* * WMITLV_FXAR (FiX ARray) is similar to WMITLV_ELEM except it has an extra parameter for the fixed number of elements. * It is re-defined to a "op" specific macro. * Eg. WMITLV_OP_TAG_ORDER_macro is created for the op_type=TAG_ORDER. */ #define WMITLV_FXAR(wmi_cmd_event_id, op_type, param_ptr, param_len, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) \ - WMITLV_OP_##op_type##_macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) + WMITLV_OP_ ## op_type ## _macro(param_ptr, param_len, wmi_cmd_event_id, elem_tlv_tag, elem_struc_type, elem_name, var_len, arr_size) -#define WMITLV_TABLE(id,op,buf,len) WMITLV_TABLE_##id(id,op,buf,len) +#define WMITLV_TABLE(id,op,buf,len) WMITLV_TABLE_ ## id(id,op,buf,len) /* * This macro will create various enumerations and structures to describe the TLVs for @@ -172,2318 +173,2358 @@ typedef struct { * */ -#define WMITLV_CREATE_PARAM_STRUC(wmi_cmd_event_id) \ - typedef enum { \ - WMITLV_TABLE(wmi_cmd_event_id, TAG_ORDER, NULL, 0) \ - WMI_TLV_HLPR_NUM_TLVS_FOR_##wmi_cmd_event_id \ - } wmi_cmd_event_id##_TAG_ORDER_enum_type; \ - \ - typedef struct { \ - WMITLV_TABLE(wmi_cmd_event_id, STRUCT_FIELD, NULL, 0) \ - } WMITLV_TYPEDEF_STRUCT_PARAMS_TLVS(wmi_cmd_event_id); \ +#define WMITLV_CREATE_PARAM_STRUC(wmi_cmd_event_id) \ + typedef enum { \ + WMITLV_TABLE(wmi_cmd_event_id, TAG_ORDER, NULL, 0) \ + WMI_TLV_HLPR_NUM_TLVS_FOR_ ## wmi_cmd_event_id \ + } wmi_cmd_event_id ## _TAG_ORDER_enum_type; \ + \ + typedef struct { \ + WMITLV_TABLE(wmi_cmd_event_id, STRUCT_FIELD, NULL, 0) \ + } WMITLV_TYPEDEF_STRUCT_PARAMS_TLVS (wmi_cmd_event_id); \ /** Enum list of TLV Tags for each parameter structure type. */ typedef enum { - /* 0 to 15 is reserved */ - WMITLV_TAG_LAST_RESERVED = 15, - WMITLV_TAG_FIRST_ARRAY_ENUM, /* First entry of ARRAY type tags */ - WMITLV_TAG_ARRAY_UINT32 = WMITLV_TAG_FIRST_ARRAY_ENUM, - WMITLV_TAG_ARRAY_BYTE, - WMITLV_TAG_ARRAY_STRUC, - WMITLV_TAG_ARRAY_FIXED_STRUC, - WMITLV_TAG_LAST_ARRAY_ENUM = 31, /* Last entry of ARRAY type tags */ - WMITLV_TAG_STRUC_wmi_service_ready_event_fixed_param, - WMITLV_TAG_STRUC_HAL_REG_CAPABILITIES, - WMITLV_TAG_STRUC_wlan_host_mem_req, - WMITLV_TAG_STRUC_wmi_ready_event_fixed_param, - WMITLV_TAG_STRUC_wmi_scan_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param, - WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, - WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr, - WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_sta_kickout_event_fixed_param, - WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr, - WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tx_delba_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tx_addba_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, - WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param, - WMITLV_TAG_STRUC_WOW_EVENT_INFO_SECTION_BITMAP, - WMITLV_TAG_STRUC_wmi_rtt_event_header, - WMITLV_TAG_STRUC_wmi_rtt_error_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_rtt_meas_event_fixed_param, - WMITLV_TAG_STRUC_wmi_echo_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ftm_intg_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param, - WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, - WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, - WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, - WMITLV_TAG_STRUC_wmi_igtk_info, - WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, - WMITLV_TAG_STRUC_ath_dcs_cw_int, /* DEPRECATED */ - WMITLV_TAG_STRUC_wlan_dcs_cw_int = /* alias */ - WMITLV_TAG_STRUC_ath_dcs_cw_int, - WMITLV_TAG_STRUC_ath_dcs_wlan_int_stat, /* DEPRECATED */ - WMITLV_TAG_STRUC_wlan_dcs_im_tgt_stats_t = /* alias */ - WMITLV_TAG_STRUC_ath_dcs_wlan_int_stat, - WMITLV_TAG_STRUC_wmi_wlan_profile_ctx_t, - WMITLV_TAG_STRUC_wmi_wlan_profile_t, - WMITLV_TAG_STRUC_wmi_pdev_qvit_event_fixed_param, - WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tim_info, - WMITLV_TAG_STRUC_wmi_p2p_noa_info, - WMITLV_TAG_STRUC_wmi_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_avoid_freq_ranges_event_fixed_param, - WMITLV_TAG_STRUC_wmi_avoid_freq_range_desc, - WMITLV_TAG_STRUC_wmi_gtk_rekey_fail_event_fixed_param, - WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_resource_config, - WMITLV_TAG_STRUC_wlan_host_memory_chunk, - WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_channel, - WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_wmm_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wmm_params, - WMITLV_TAG_STRUC_wmi_pdev_set_quiet_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_delete_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_p2p_noa_descriptor, - WMITLV_TAG_STRUC_wmi_p2p_go_set_beacon_ie_fixed_param, - WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vht_rate_set, - WMITLV_TAG_STRUC_wmi_bcn_tmpl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_bcn_prb_info, - WMITLV_TAG_STRUC_wmi_peer_tid_addba_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_tid_delba_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sta_powersave_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sta_powersave_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_scan_mode_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_scan_rssi_threshold_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_scan_period_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_scan_rssi_change_threshold_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_resume_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_add_bcn_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rmv_bcn_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wow_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_param, - WMITLV_TAG_STRUC_WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_ARP_OFFLOAD_TUPLE, - WMITLV_TAG_STRUC_WMI_NS_OFFLOAD_TUPLE, - WMITLV_TAG_STRUC_wmi_ftm_intg_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_STA_KEEPALIVE_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_STA_KEEPALVE_ARP_RESPONSE, - WMITLV_TAG_STRUC_wmi_p2p_set_vendor_ie_data_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ap_ps_peer_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_rate_retry_sched_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_profile_trigger_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_profile_set_hist_intvl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_profile_get_prof_data_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_profile_enable_profile_id_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_DEL_PATTERN_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_ADD_DEL_EVT_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_rtt_measreq_head, - WMITLV_TAG_STRUC_wmi_rtt_measreq_body, - WMITLV_TAG_STRUC_wmi_rtt_tsf_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_spectral_configure_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_spectral_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, - WMITLV_TAG_STRUC_nlo_configured_parameters, - WMITLV_TAG_STRUC_wmi_csa_offload_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_csa_offload_chanswitch_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_chatter_set_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_echo_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_keepalive_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_FORCE_FW_HANG_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_gpio_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_add_wds_entry_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_bcn_tx_hdr, - WMITLV_TAG_STRUC_wmi_bcn_send_from_host_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mgmt_tx_hdr, - WMITLV_TAG_STRUC_wmi_addba_clear_resp_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_addba_send_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_delba_send_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_addba_setresponse_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_send_singleamsdu_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_pktlog_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_ht_ie_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_vht_ie_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_green_ap_ps_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_get_tpc_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_mcast_group_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param, - WMITLV_TAG_STRUC_wmi_ap_profile, - WMITLV_TAG_STRUC_wmi_scan_sch_priority_table_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_dfs_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_dfs_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_ADD_PATTERN_CMD_fixed_param, - WMITLV_TAG_STRUC_WOW_BITMAP_PATTERN_T, - WMITLV_TAG_STRUC_WOW_IPV4_SYNC_PATTERN_T, - WMITLV_TAG_STRUC_WOW_IPV6_SYNC_PATTERN_T, - WMITLV_TAG_STRUC_WOW_MAGIC_PATTERN_CMD, - WMITLV_TAG_STRUC_WMI_scan_update_request_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_chatter_pkt_coalescing_filter, - WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_chatter_coalescing_delete_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_chatter_coalescing_query_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_txbf_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_debug_log_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nlo_event, - WMITLV_TAG_STRUC_wmi_chatter_query_reply_event_fixed_param, - WMITLV_TAG_STRUC_wmi_upload_h_hdr, - WMITLV_TAG_STRUC_wmi_capture_h_event_hdr, - WMITLV_TAG_STRUC_WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_wmm_addts_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_wmm_delts_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_wmm_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_set_state_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_peer_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_peer_capabilities, - WMITLV_TAG_STRUC_wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_chan_list_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_mcc_bcn_intvl_change_event_fixed_param, - WMITLV_TAG_STRUC_wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_resmgr_set_chan_time_quota_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_resmgr_set_chan_latency_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ba_rsp_ssn_event_fixed_param, - WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_p2p_set_oppps_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_p2p_set_noa_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_sub_struct_param, - WMITLV_TAG_STRUC_wmi_ba_req_ssn_event_sub_struct_param, - WMITLV_TAG_STRUC_wmi_sta_smps_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_gtx_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mcc_sched_traffic_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mcc_sched_sta_traffic_stats, - WMITLV_TAG_STRUC_wmi_offload_bcn_tx_status_event_fixed_param, - WMITLV_TAG_STRUC_wmi_p2p_noa_event_fixed_param, - WMITLV_TAG_STRUC_wmi_hb_set_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hb_set_tcp_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hb_set_tcp_pkt_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hb_set_udp_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hb_set_udp_pkt_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hb_ind_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tx_pause_event_fixed_param, - WMITLV_TAG_STRUC_wmi_rfkill_event_fixed_param, - WMITLV_TAG_STRUC_wmi_dfs_radar_event_fixed_param, - WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_ena_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_dis_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_batch_scan_result_scan_list, - WMITLV_TAG_STRUC_wmi_batch_scan_result_network_info, - WMITLV_TAG_STRUC_wmi_batch_scan_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_batch_scan_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_batch_scan_trigger_result_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_batch_scan_enabled_event_fixed_param, - WMITLV_TAG_STRUC_wmi_batch_scan_result_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_plmreq_start_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_plmreq_stop_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_thermal_mgmt_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_info_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_info_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_info, - WMITLV_TAG_STRUC_wmi_peer_tx_fail_cnt_thr_event_fixed_param, - WMITLV_TAG_STRUC_wmi_rmc_set_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rmc_set_action_period_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rmc_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mhf_offload_set_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mhf_offload_plumb_routing_table_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_cmd_param, - WMITLV_TAG_STRUC_wmi_nan_event_hdr, - WMITLV_TAG_STRUC_wmi_pdev_l1ss_track_event_fixed_param, - WMITLV_TAG_STRUC_wmi_diag_data_container_event_fixed_param, + /* 0 to 15 is reserved */ + WMITLV_TAG_LAST_RESERVED = 15, + WMITLV_TAG_FIRST_ARRAY_ENUM, /* First entry of ARRAY type tags */ + WMITLV_TAG_ARRAY_UINT32 = WMITLV_TAG_FIRST_ARRAY_ENUM, + WMITLV_TAG_ARRAY_BYTE, + WMITLV_TAG_ARRAY_STRUC, + WMITLV_TAG_ARRAY_FIXED_STRUC, + WMITLV_TAG_LAST_ARRAY_ENUM = 31, /* Last entry of ARRAY type tags */ + WMITLV_TAG_STRUC_wmi_service_ready_event_fixed_param, + WMITLV_TAG_STRUC_HAL_REG_CAPABILITIES, + WMITLV_TAG_STRUC_wlan_host_mem_req, + WMITLV_TAG_STRUC_wmi_ready_event_fixed_param, + WMITLV_TAG_STRUC_wmi_scan_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param, + WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr, + WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_sta_kickout_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr, + WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param, + WMITLV_TAG_STRUC_wmi_tx_delba_complete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_tx_addba_complete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, + WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param, + WMITLV_TAG_STRUC_WOW_EVENT_INFO_SECTION_BITMAP, + WMITLV_TAG_STRUC_wmi_rtt_event_header, + WMITLV_TAG_STRUC_wmi_rtt_error_report_event_fixed_param, + WMITLV_TAG_STRUC_wmi_rtt_meas_event_fixed_param, + WMITLV_TAG_STRUC_wmi_echo_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ftm_intg_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, + WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, + WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, + WMITLV_TAG_STRUC_wmi_igtk_info, + WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, + WMITLV_TAG_STRUC_ath_dcs_cw_int, /* DEPRECATED */ + WMITLV_TAG_STRUC_wlan_dcs_cw_int = /* alias */ + WMITLV_TAG_STRUC_ath_dcs_cw_int, + WMITLV_TAG_STRUC_ath_dcs_wlan_int_stat, /* DEPRECATED */ + WMITLV_TAG_STRUC_wlan_dcs_im_tgt_stats_t = /* alias */ + WMITLV_TAG_STRUC_ath_dcs_wlan_int_stat, + WMITLV_TAG_STRUC_wmi_wlan_profile_ctx_t, + WMITLV_TAG_STRUC_wmi_wlan_profile_t, + WMITLV_TAG_STRUC_wmi_pdev_qvit_event_fixed_param, + WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, + WMITLV_TAG_STRUC_wmi_tim_info, + WMITLV_TAG_STRUC_wmi_p2p_noa_info, + WMITLV_TAG_STRUC_wmi_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_avoid_freq_ranges_event_fixed_param, + WMITLV_TAG_STRUC_wmi_avoid_freq_range_desc, + WMITLV_TAG_STRUC_wmi_gtk_rekey_fail_event_fixed_param, + WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_resource_config, + WMITLV_TAG_STRUC_wlan_host_memory_chunk, + WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_channel, + WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_wmm_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wmm_params, + WMITLV_TAG_STRUC_wmi_pdev_set_quiet_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_delete_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_p2p_noa_descriptor, + WMITLV_TAG_STRUC_wmi_p2p_go_set_beacon_ie_fixed_param, + WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vht_rate_set, + WMITLV_TAG_STRUC_wmi_bcn_tmpl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_bcn_prb_info, + WMITLV_TAG_STRUC_wmi_peer_tid_addba_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_tid_delba_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sta_powersave_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sta_powersave_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_scan_mode_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_scan_rssi_threshold_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_scan_period_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_scan_rssi_change_threshold_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_resume_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_add_bcn_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rmv_bcn_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wow_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_param, + WMITLV_TAG_STRUC_WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_ARP_OFFLOAD_TUPLE, + WMITLV_TAG_STRUC_WMI_NS_OFFLOAD_TUPLE, + WMITLV_TAG_STRUC_wmi_ftm_intg_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_STA_KEEPALIVE_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_STA_KEEPALVE_ARP_RESPONSE, + WMITLV_TAG_STRUC_wmi_p2p_set_vendor_ie_data_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ap_ps_peer_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_rate_retry_sched_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wlan_profile_trigger_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wlan_profile_set_hist_intvl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wlan_profile_get_prof_data_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_wlan_profile_enable_profile_id_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_DEL_PATTERN_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_ADD_DEL_EVT_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_rtt_measreq_head, + WMITLV_TAG_STRUC_wmi_rtt_measreq_body, + WMITLV_TAG_STRUC_wmi_rtt_tsf_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_spectral_configure_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_spectral_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, + WMITLV_TAG_STRUC_nlo_configured_parameters, + WMITLV_TAG_STRUC_wmi_csa_offload_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_csa_offload_chanswitch_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_chatter_set_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_echo_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_keepalive_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_FORCE_FW_HANG_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_add_wds_entry_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_bcn_tx_hdr, + WMITLV_TAG_STRUC_wmi_bcn_send_from_host_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mgmt_tx_hdr, + WMITLV_TAG_STRUC_wmi_addba_clear_resp_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_addba_send_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_delba_send_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_addba_setresponse_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_send_singleamsdu_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_pktlog_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_ht_ie_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_vht_ie_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_green_ap_ps_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_get_tpc_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_mcast_group_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param, + WMITLV_TAG_STRUC_wmi_ap_profile, + WMITLV_TAG_STRUC_wmi_scan_sch_priority_table_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_dfs_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_dfs_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_ADD_PATTERN_CMD_fixed_param, + WMITLV_TAG_STRUC_WOW_BITMAP_PATTERN_T, + WMITLV_TAG_STRUC_WOW_IPV4_SYNC_PATTERN_T, + WMITLV_TAG_STRUC_WOW_IPV6_SYNC_PATTERN_T, + WMITLV_TAG_STRUC_WOW_MAGIC_PATTERN_CMD, + WMITLV_TAG_STRUC_WMI_scan_update_request_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_chatter_pkt_coalescing_filter, + WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_chatter_coalescing_delete_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_chatter_coalescing_query_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_txbf_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_debug_log_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_nlo_event, + WMITLV_TAG_STRUC_wmi_chatter_query_reply_event_fixed_param, + WMITLV_TAG_STRUC_wmi_upload_h_hdr, + WMITLV_TAG_STRUC_wmi_capture_h_event_hdr, + WMITLV_TAG_STRUC_WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_wmm_addts_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_wmm_delts_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_wmm_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tdls_set_state_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tdls_peer_event_fixed_param, + WMITLV_TAG_STRUC_wmi_tdls_peer_capabilities, + WMITLV_TAG_STRUC_wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_chan_list_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_mcc_bcn_intvl_change_event_fixed_param, + WMITLV_TAG_STRUC_wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_resmgr_set_chan_time_quota_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_resmgr_set_chan_latency_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ba_rsp_ssn_event_fixed_param, + WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_p2p_set_oppps_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_p2p_set_noa_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_sub_struct_param, + WMITLV_TAG_STRUC_wmi_ba_req_ssn_event_sub_struct_param, + WMITLV_TAG_STRUC_wmi_sta_smps_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_gtx_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mcc_sched_traffic_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mcc_sched_sta_traffic_stats, + WMITLV_TAG_STRUC_wmi_offload_bcn_tx_status_event_fixed_param, + WMITLV_TAG_STRUC_wmi_p2p_noa_event_fixed_param, + WMITLV_TAG_STRUC_wmi_hb_set_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hb_set_tcp_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hb_set_tcp_pkt_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hb_set_udp_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hb_set_udp_pkt_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hb_ind_event_fixed_param, + WMITLV_TAG_STRUC_wmi_tx_pause_event_fixed_param, + WMITLV_TAG_STRUC_wmi_rfkill_event_fixed_param, + WMITLV_TAG_STRUC_wmi_dfs_radar_event_fixed_param, + WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_ena_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_dis_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_batch_scan_result_scan_list, + WMITLV_TAG_STRUC_wmi_batch_scan_result_network_info, + WMITLV_TAG_STRUC_wmi_batch_scan_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_batch_scan_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_batch_scan_trigger_result_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_batch_scan_enabled_event_fixed_param, + WMITLV_TAG_STRUC_wmi_batch_scan_result_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_plmreq_start_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_plmreq_stop_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_thermal_mgmt_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_info_req_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_info, + WMITLV_TAG_STRUC_wmi_peer_tx_fail_cnt_thr_event_fixed_param, + WMITLV_TAG_STRUC_wmi_rmc_set_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rmc_set_action_period_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rmc_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mhf_offload_set_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mhf_offload_plumb_routing_table_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_cmd_param, + WMITLV_TAG_STRUC_wmi_nan_event_hdr, + WMITLV_TAG_STRUC_wmi_pdev_l1ss_track_event_fixed_param, + WMITLV_TAG_STRUC_wmi_diag_data_container_event_fixed_param, WMITLV_TAG_STRUC_wmi_modem_power_state_cmd_param, - WMITLV_TAG_STRUC_wmi_peer_get_estimated_linkspeed_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_estimated_linkspeed_event_fixed_param, - WMITLV_TAG_STRUC_wmi_aggr_state_trig_event_fixed_param, - WMITLV_TAG_STRUC_wmi_mhf_offload_routing_table_entry, - WMITLV_TAG_STRUC_wmi_roam_scan_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_req_stats_ext_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, - WMITLV_TAG_STRUC_wmi_obss_scan_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_obss_scan_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_offload_prb_rsp_tx_status_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_led_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_host_auto_shutdown_cfg_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_host_auto_shutdown_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_get_estimated_linkspeed_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_estimated_linkspeed_event_fixed_param, + WMITLV_TAG_STRUC_wmi_aggr_state_trig_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mhf_offload_routing_table_entry, + WMITLV_TAG_STRUC_wmi_roam_scan_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_req_stats_ext_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, + WMITLV_TAG_STRUC_wmi_obss_scan_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_obss_scan_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_offload_prb_rsp_tx_status_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_led_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_host_auto_shutdown_cfg_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_host_auto_shutdown_event_fixed_param, WMITLV_TAG_STRUC_wmi_update_whal_mib_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_chan_avoid_update_cmd_param, - WMITLV_TAG_STRUC_WOW_IOAC_PKT_PATTERN_T, - WMITLV_TAG_STRUC_WOW_IOAC_TMR_PATTERN_T, - WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_IOAC_KEEPALIVE_T, - WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_start_link_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_request_link_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_radio_link_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_channel_stats, - WMITLV_TAG_STRUC_wmi_radio_link_stats, - WMITLV_TAG_STRUC_wmi_rate_stats, - WMITLV_TAG_STRUC_wmi_peer_link_stats, - WMITLV_TAG_STRUC_wmi_wmm_ac_stats, - WMITLV_TAG_STRUC_wmi_iface_link_stats, - WMITLV_TAG_STRUC_wmi_lpi_mgmt_snooping_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_start_scan_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_stop_scan_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_result_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_state_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_bucket_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_bucket_channel_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_start_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_stop_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_wlan_change_bssid_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_monitor_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_get_cached_results_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_get_wlan_change_results_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_set_capabilities_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_get_capabilities_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_operation_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_start_stop_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_table_usage_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_wlan_descriptor_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_rssi_info_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_cached_results_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_wlan_change_results_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_wlan_change_result_bssid_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_capabilities_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_cache_capabilities_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_wlan_change_monitor_capabilities_event_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_hotlist_monitor_capabilities_event_fixed_param, - WMITLV_TAG_STRUC_wmi_d0_wow_enable_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param, - WMITLV_TAG_STRUC_wmi_unit_test_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_offload_tlv_param, - WMITLV_TAG_STRUC_wmi_roam_11i_offload_tlv_param, - WMITLV_TAG_STRUC_wmi_roam_11r_offload_tlv_param, - WMITLV_TAG_STRUC_wmi_roam_ese_offload_tlv_param, - WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, - WMITLV_TAG_STRUC_wmi_extwow_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extwow_set_app_type1_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extwow_set_app_type2_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_rate_ht_info, - WMITLV_TAG_STRUC_wmi_ric_request_fixed_param, + WMITLV_TAG_STRUC_wmi_chan_avoid_update_cmd_param, + WMITLV_TAG_STRUC_WOW_IOAC_PKT_PATTERN_T, + WMITLV_TAG_STRUC_WOW_IOAC_TMR_PATTERN_T, + WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_IOAC_KEEPALIVE_T, + WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_start_link_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_request_link_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_radio_link_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_channel_stats, + WMITLV_TAG_STRUC_wmi_radio_link_stats, + WMITLV_TAG_STRUC_wmi_rate_stats, + WMITLV_TAG_STRUC_wmi_peer_link_stats, + WMITLV_TAG_STRUC_wmi_wmm_ac_stats, + WMITLV_TAG_STRUC_wmi_iface_link_stats, + WMITLV_TAG_STRUC_wmi_lpi_mgmt_snooping_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_lpi_start_scan_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_lpi_stop_scan_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_lpi_result_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_state_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_bucket_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_bucket_channel_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_start_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_stop_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_wlan_change_bssid_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_monitor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_get_cached_results_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_get_wlan_change_results_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_set_capabilities_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_get_capabilities_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_operation_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_start_stop_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_table_usage_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_wlan_descriptor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_rssi_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_cached_results_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_wlan_change_results_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_wlan_change_result_bssid_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_capabilities_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_cache_capabilities_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_wlan_change_monitor_capabilities_event_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_hotlist_monitor_capabilities_event_fixed_param, + WMITLV_TAG_STRUC_wmi_d0_wow_enable_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param, + WMITLV_TAG_STRUC_wmi_unit_test_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_offload_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_11i_offload_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_11r_offload_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_ese_offload_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, + WMITLV_TAG_STRUC_wmi_extwow_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extwow_set_app_type1_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extwow_set_app_type2_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, + WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_rate_ht_info, + WMITLV_TAG_STRUC_wmi_ric_request_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_get_temperature_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_temperature_event_fixed_param, - WMITLV_TAG_STRUC_wmi_set_dhcp_server_offload_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tpc_chainmask_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ric_tspec, - WMITLV_TAG_STRUC_wmi_tpc_chainmask_config, - WMITLV_TAG_STRUCT_wmi_ipa_offload_enable_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_key_material, - WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_set_led_flashing_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mdns_offload_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mdns_set_fqdn_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mdns_set_resp_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mdns_get_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mdns_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_invoke_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_antenna_diversity_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sap_ofl_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param, - WMITLV_TAG_STRUC_wmi_sap_ofl_del_sta_event_fixed_param, - WMITLV_TAG_STRUC_wmi_apfind_cmd_param, - WMITLV_TAG_STRUC_wmi_apfind_event_hdr, - WMITLV_TAG_STRUC_wmi_ocb_set_sched_cmd_fixed_param, // DEPRECATED - WMITLV_TAG_STRUC_wmi_ocb_set_sched_event_fixed_param, // DEPRECATED - WMITLV_TAG_STRUC_wmi_ocb_set_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_set_config_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_set_utc_time_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_start_timing_advert_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_stop_timing_advert_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_dcc_get_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_dcc_channel_stats_request, - WMITLV_TAG_STRUC_wmi_dcc_get_stats_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_dcc_clear_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_dcc_update_ndl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_dcc_update_ndl_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_dcc_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ocb_channel, - WMITLV_TAG_STRUC_wmi_ocb_schedule_element, - WMITLV_TAG_STRUC_wmi_dcc_ndl_stats_per_channel, - WMITLV_TAG_STRUC_wmi_dcc_ndl_chan, - WMITLV_TAG_STRUC_wmi_qos_parameter, - WMITLV_TAG_STRUC_wmi_dcc_ndl_active_state_config, - WMITLV_TAG_STRUC_wmi_roam_scan_extended_threshold_param, - WMITLV_TAG_STRUC_wmi_roam_filter_fixed_param, - WMITLV_TAG_STRUC_wmi_passpoint_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_passpoint_event_hdr, - WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_hotlist_ssid_match_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_tsf_tstamp_action_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_tsf_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param, - WMITLV_TAG_STRUC_wmi_update_fw_mem_dump_fixed_param, - WMITLV_TAG_STRUC_wmi_fw_mem_dump_params, - WMITLV_TAG_STRUC_wmi_debug_mesg_flush_fixed_param, - WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_subnet_change_config_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_ie_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rssi_breach_monitor_config_fixed_param, - WMITLV_TAG_STRUC_wmi_rssi_breach_event_fixed_param, - WMITLV_TAG_STRUC_WOW_EVENT_INITIAL_WAKEUP_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_set_pcl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_event_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_hw_mode_transition_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_txrx_streams, - WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_vdev_mac_entry, - WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_response_event_fixed_param, - WMITLV_TAG_STRUC_WOW_IOAC_SOCK_PATTERN_T, - WMITLV_TAG_STRUC_wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_diag_event_log_config_fixed_param, - WMITLV_TAG_STRUC_wmi_diag_event_log_supported_event_fixed_params, - WMITLV_TAG_STRUC_wmi_packet_filter_config_fixed_param, - WMITLV_TAG_STRUC_wmi_packet_filter_enable_fixed_param, - WMITLV_TAG_STRUC_wmi_sap_set_blacklist_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_event_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_set_antenna_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_lro_info_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_earlystop_rssi_thres_param, - WMITLV_TAG_STRUC_wmi_service_ready_ext_event_fixed_param, - WMITLV_TAG_STRUC_wmi_mawc_sensor_report_ind_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mawc_enable_sensor_event_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_configure_mawc_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nlo_configure_mawc_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_extscan_configure_mawc_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_wow_hostwakeup_gpio_pin_pattern_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ap_ps_egap_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_event_fixed_param, - WMITLV_TAG_STRUC_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_scpc_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_chainmask_list, - WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_get_capability_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_capability_info_evt_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_get_vdev_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_vdev_stats_info_evt_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_set_vdev_instructions_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_del_vdev_instructions_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_delete_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_dense_thres_param, - WMITLV_TAG_STRUC_enlo_candidate_score_param, - WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_config_ratemask_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_fips_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_ant_switch_tbl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_ctl_table_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_fwtest_set_param_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_atf_request_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_get_ani_ofdm_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_inst_rssi_stats_resp_fixed_param, - WMITLV_TAG_STRUC_wmi_med_util_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_sta_ps_statechange_event_fixed_param, - WMITLV_TAG_STRUC_wmi_wds_addr_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_ratecode_list_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ani_cck_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param, - WMITLV_TAG_STRUC_wmi_atf_peer_info, - WMITLV_TAG_STRUC_wmi_pdev_get_tpc_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_QBOOST_CFG_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle, - WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_series, - WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param, - WMITLV_TAG_STRUC_wmi_pdev_set_ant_ctrl_chain, - WMITLV_TAG_STRUC_wmi_peer_cck_ofdm_rate_info, - WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info, - WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBr, - WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBm, - WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_freqNum, - WMITLV_TAG_STRUC_wmi_mu_report_total_mu, - WMITLV_TAG_STRUC_wmi_vdev_set_dscp_tid_map_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_set_mbo_fixed_param, - WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_iface_deleted_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_started_cluster_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_responder_req_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_end_req_fixed_param, - WMITLV_TAG_STRUC_wmi_ndi_cap_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_initiator_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_end_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_end_indication_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_quiet_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_pcl_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_antenna_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_hw_mode_transition_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_vdev_mac_entry, - WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_response_event_fixed_param, - WMITLV_TAG_STRUC_WMI_COEX_CONFIG_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_config_enhanced_mcast_filter_fixed_param, - WMITLV_TAG_STRUC_WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param, - WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_wal_power_debug_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES, - WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES, - WMITLV_TAG_STRUC_WMI_SOC_MAC_PHY_HW_MODE_CAPS, - WMITLV_TAG_STRUC_WMI_HAL_REG_CAPABILITIES_EXT, - WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES, - WMITLV_TAG_STRUC_wmi_vdev_wisa_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tx_power_level_stats_evt_fixed_param, - WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_parameters_tlv, - WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_config_fixed_param, - WMITLV_TAG_STRUC_wmi_wow_set_action_wake_up_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ndp_end_rsp_per_ndi, - WMITLV_TAG_STRUC_wmi_peer_bwf_request_fixed_param, - WMITLV_TAG_STRUC_wmi_bwf_peer_info, - WMITLV_TAG_STRUC_wmi_dbglog_time_stamp_sync_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rmc_set_leader_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rmc_manual_leader_event_fixed_param, - WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats, - WMITLV_TAG_STRUC_wmi_rssi_stats, - WMITLV_TAG_STRUC_wmi_p2p_lo_start_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_p2p_lo_stop_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_p2p_lo_stopped_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_reorder_queue_setup_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_set_multiple_mcast_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_bundle_event_fixed_param, - WMITLV_TAG_STRUC_wmi_read_data_from_flash_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_read_data_from_flash_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_reorder_timeout_val_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param, - WMITLV_TAG_STRUC_wmi_tlv_buf_len_param, - WMITLV_TAG_STRUC_wmi_service_available_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_antdiv_info_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_antdiv_info_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_antdiv_info, - WMITLV_TAG_STRUC_wmi_pdev_get_antdiv_status_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_antdiv_status_event_fixed_param, - WMITLV_TAG_STRUC_wmi_mnt_filter_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_chip_power_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_coex_get_antenna_isolation_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, - WMITLV_TAG_STRUC_wmi_chan_cca_stats, - WMITLV_TAG_STRUC_wmi_peer_signal_stats, - WMITLV_TAG_STRUC_wmi_tx_stats, - WMITLV_TAG_STRUC_wmi_peer_ac_tx_stats, - WMITLV_TAG_STRUC_wmi_rx_stats, - WMITLV_TAG_STRUC_wmi_peer_ac_rx_stats, - WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_chan_cca_stats_thresh, - WMITLV_TAG_STRUC_wmi_peer_signal_stats_thresh, - WMITLV_TAG_STRUC_wmi_tx_stats_thresh, - WMITLV_TAG_STRUC_wmi_rx_stats_thresh, - WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_set_dhcp_server_offload_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tpc_chainmask_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ric_tspec, + WMITLV_TAG_STRUC_wmi_tpc_chainmask_config, + WMITLV_TAG_STRUCT_wmi_ipa_offload_enable_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_key_material, + WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_set_led_flashing_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mdns_offload_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mdns_set_fqdn_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mdns_set_resp_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mdns_get_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mdns_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_invoke_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_antenna_diversity_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sap_ofl_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param, + WMITLV_TAG_STRUC_wmi_sap_ofl_del_sta_event_fixed_param, + WMITLV_TAG_STRUC_wmi_apfind_cmd_param, + WMITLV_TAG_STRUC_wmi_apfind_event_hdr, + WMITLV_TAG_STRUC_wmi_ocb_set_sched_cmd_fixed_param, /* DEPRECATED */ + WMITLV_TAG_STRUC_wmi_ocb_set_sched_event_fixed_param, /* DEPRECATED */ + WMITLV_TAG_STRUC_wmi_ocb_set_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_set_config_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_set_utc_time_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_start_timing_advert_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_stop_timing_advert_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_dcc_get_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_dcc_channel_stats_request, + WMITLV_TAG_STRUC_wmi_dcc_get_stats_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_dcc_clear_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_dcc_update_ndl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_dcc_update_ndl_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_dcc_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ocb_channel, + WMITLV_TAG_STRUC_wmi_ocb_schedule_element, + WMITLV_TAG_STRUC_wmi_dcc_ndl_stats_per_channel, + WMITLV_TAG_STRUC_wmi_dcc_ndl_chan, + WMITLV_TAG_STRUC_wmi_qos_parameter, + WMITLV_TAG_STRUC_wmi_dcc_ndl_active_state_config, + WMITLV_TAG_STRUC_wmi_roam_scan_extended_threshold_param, + WMITLV_TAG_STRUC_wmi_roam_filter_fixed_param, + WMITLV_TAG_STRUC_wmi_passpoint_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_passpoint_event_hdr, + WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_hotlist_ssid_match_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_tsf_tstamp_action_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_tsf_report_event_fixed_param, + WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param, + WMITLV_TAG_STRUC_wmi_update_fw_mem_dump_fixed_param, + WMITLV_TAG_STRUC_wmi_fw_mem_dump_params, + WMITLV_TAG_STRUC_wmi_debug_mesg_flush_fixed_param, + WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_subnet_change_config_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_ie_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rssi_breach_monitor_config_fixed_param, + WMITLV_TAG_STRUC_wmi_rssi_breach_event_fixed_param, + WMITLV_TAG_STRUC_WOW_EVENT_INITIAL_WAKEUP_fixed_param, + WMITLV_TAG_STRUC_wmi_soc_set_pcl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_event_fixed_param, + WMITLV_TAG_STRUC_wmi_soc_hw_mode_transition_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_txrx_streams, + WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_vdev_mac_entry, + WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_response_event_fixed_param, + WMITLV_TAG_STRUC_WOW_IOAC_SOCK_PATTERN_T, + WMITLV_TAG_STRUC_wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_diag_event_log_config_fixed_param, + WMITLV_TAG_STRUC_wmi_diag_event_log_supported_event_fixed_params, + WMITLV_TAG_STRUC_wmi_packet_filter_config_fixed_param, + WMITLV_TAG_STRUC_wmi_packet_filter_enable_fixed_param, + WMITLV_TAG_STRUC_wmi_sap_set_blacklist_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_event_fixed_param, + WMITLV_TAG_STRUC_wmi_soc_set_antenna_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_lro_info_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_earlystop_rssi_thres_param, + WMITLV_TAG_STRUC_wmi_service_ready_ext_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mawc_sensor_report_ind_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mawc_enable_sensor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_configure_mawc_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_nlo_configure_mawc_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_extscan_configure_mawc_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, + WMITLV_TAG_STRUC_wmi_wow_hostwakeup_gpio_pin_pattern_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ap_ps_egap_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_event_fixed_param, + WMITLV_TAG_STRUC_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_complete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_scpc_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_chainmask_list, + WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_complete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_bpf_get_capability_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_bpf_capability_info_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_bpf_get_vdev_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_bpf_vdev_stats_info_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_bpf_set_vdev_instructions_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_bpf_del_vdev_instructions_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_delete_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_dense_thres_param, + WMITLV_TAG_STRUC_enlo_candidate_score_param, + WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_config_ratemask_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_fips_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_ant_switch_tbl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_ctl_table_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_fwtest_set_param_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_atf_request_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_get_ani_ofdm_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_inst_rssi_stats_resp_fixed_param, + WMITLV_TAG_STRUC_wmi_med_util_report_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_sta_ps_statechange_event_fixed_param, + WMITLV_TAG_STRUC_wmi_wds_addr_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_ratecode_list_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ani_cck_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param, + WMITLV_TAG_STRUC_wmi_atf_peer_info, + WMITLV_TAG_STRUC_wmi_pdev_get_tpc_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_QBOOST_CFG_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle, + WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_series, + WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param, + WMITLV_TAG_STRUC_wmi_pdev_set_ant_ctrl_chain, + WMITLV_TAG_STRUC_wmi_peer_cck_ofdm_rate_info, + WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info, + WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBr, + WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBm, + WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_freqNum, + WMITLV_TAG_STRUC_wmi_mu_report_total_mu, + WMITLV_TAG_STRUC_wmi_vdev_set_dscp_tid_map_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_set_mbo_fixed_param, + WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_disc_iface_deleted_event_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_started_cluster_event_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_responder_req_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_end_req_fixed_param, + WMITLV_TAG_STRUC_wmi_ndi_cap_rsp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_initiator_rsp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_end_rsp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_end_indication_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_quiet_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_pcl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_antenna_mode_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_hw_mode_transition_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_vdev_mac_entry, + WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_response_event_fixed_param, + WMITLV_TAG_STRUC_WMI_COEX_CONFIG_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_config_enhanced_mcast_filter_fixed_param, + WMITLV_TAG_STRUC_WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param, + WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_wal_power_debug_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES, + WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES, + WMITLV_TAG_STRUC_WMI_SOC_MAC_PHY_HW_MODE_CAPS, + WMITLV_TAG_STRUC_WMI_HAL_REG_CAPABILITIES_EXT, + WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES, + WMITLV_TAG_STRUC_wmi_vdev_wisa_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tx_power_level_stats_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_parameters_tlv, + WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_config_fixed_param, + WMITLV_TAG_STRUC_wmi_wow_set_action_wake_up_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_ndp_end_rsp_per_ndi, + WMITLV_TAG_STRUC_wmi_peer_bwf_request_fixed_param, + WMITLV_TAG_STRUC_wmi_bwf_peer_info, + WMITLV_TAG_STRUC_wmi_dbglog_time_stamp_sync_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_place_holder_1, + WMITLV_TAG_STRUC_wmi_place_holder_2, + WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats, + WMITLV_TAG_STRUC_wmi_rssi_stats, + WMITLV_TAG_STRUC_wmi_p2p_lo_start_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_p2p_lo_stop_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_p2p_lo_stopped_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_reorder_queue_setup_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_set_multiple_mcast_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_bundle_event_fixed_param, + WMITLV_TAG_STRUC_wmi_read_data_from_flash_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_read_data_from_flash_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_reorder_timeout_val_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param, + WMITLV_TAG_STRUC_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param, + WMITLV_TAG_STRUC_wmi_tlv_buf_len_param, + WMITLV_TAG_STRUC_wmi_service_available_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_antdiv_info_req_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_antdiv_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_antdiv_info, + WMITLV_TAG_STRUC_wmi_pdev_get_antdiv_status_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_antdiv_status_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mnt_filter_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_chip_power_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_coex_get_antenna_isolation_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, + WMITLV_TAG_STRUC_wmi_chan_cca_stats, + WMITLV_TAG_STRUC_wmi_peer_signal_stats, + WMITLV_TAG_STRUC_wmi_tx_stats, + WMITLV_TAG_STRUC_wmi_peer_ac_tx_stats, + WMITLV_TAG_STRUC_wmi_rx_stats, + WMITLV_TAG_STRUC_wmi_peer_ac_rx_stats, + WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_chan_cca_stats_thresh, + WMITLV_TAG_STRUC_wmi_peer_signal_stats_thresh, + WMITLV_TAG_STRUC_wmi_tx_stats_thresh, + WMITLV_TAG_STRUC_wmi_rx_stats_thresh, + WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_rx_aggr_failure_event_fixed_param, + WMITLV_TAG_STRUC_wmi_rx_aggr_failure_info, + WMITLV_TAG_STRUC_wmi_vdev_encrypt_decrypt_data_req_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_encrypt_decrypt_data_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_band_to_mac, + WMITLV_TAG_STRUC_wmi_tbtt_offset_info, + WMITLV_TAG_STRUC_wmi_tbtt_offset_ext_event_fixed_param, + WMITLV_TAG_STRUC_wmi_sar_limits_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_sar_limit_cmd_row, + WMITLV_TAG_STRUC_wmi_pdev_dfs_phyerr_offload_enable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_adfs_ch_cfg_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_adfs_ocac_abort_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_adfs_ocac_complete_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_dfs_cac_complete_event_fixed_param, + } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. * Otherwise, these WMI TLV Functions will be process them. */ -#define WMITLV_ALL_CMD_LIST(OP) \ - OP(WMI_INIT_CMDID) \ - OP(WMI_PEER_CREATE_CMDID) \ - OP(WMI_PEER_DELETE_CMDID) \ - OP(WMI_PEER_FLUSH_TIDS_CMDID) \ - OP(WMI_PEER_SET_PARAM_CMDID) \ - OP(WMI_STA_POWERSAVE_MODE_CMDID) \ - OP(WMI_STA_POWERSAVE_PARAM_CMDID) \ - OP(WMI_STA_DTIM_PS_METHOD_CMDID) \ - OP(WMI_PDEV_SET_REGDOMAIN_CMDID) \ - OP(WMI_PEER_TID_ADDBA_CMDID) \ - OP(WMI_PEER_TID_DELBA_CMDID) \ - OP(WMI_PDEV_FTM_INTG_CMDID) \ - OP(WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID) \ - OP(WMI_WOW_ENABLE_CMDID) \ - OP(WMI_RMV_BCN_FILTER_CMDID) \ - OP(WMI_ROAM_SCAN_MODE) \ - OP(WMI_ROAM_SCAN_RSSI_THRESHOLD) \ - OP(WMI_ROAM_SCAN_PERIOD) \ - OP(WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD) \ - OP(WMI_START_SCAN_CMDID) \ - OP(WMI_VDEV_PLMREQ_START_CMDID) \ - OP(WMI_VDEV_PLMREQ_STOP_CMDID) \ - OP(WMI_PDEV_SET_CHANNEL_CMDID) \ - OP(WMI_PDEV_SET_WMM_PARAMS_CMDID) \ - OP(WMI_VDEV_START_REQUEST_CMDID) \ - OP(WMI_VDEV_RESTART_REQUEST_CMDID) \ - OP(WMI_P2P_GO_SET_BEACON_IE) \ - OP(WMI_GTK_OFFLOAD_CMDID) \ - OP(WMI_SCAN_CHAN_LIST_CMDID) \ - OP(WMI_STA_UAPSD_AUTO_TRIG_CMDID) \ - OP(WMI_PRB_TMPL_CMDID) \ - OP(WMI_BCN_TMPL_CMDID) \ - OP(WMI_VDEV_INSTALL_KEY_CMDID) \ - OP(WMI_PEER_ASSOC_CMDID) \ - OP(WMI_ADD_BCN_FILTER_CMDID) \ - OP(WMI_STA_KEEPALIVE_CMDID) \ - OP(WMI_SET_ARP_NS_OFFLOAD_CMDID) \ - OP(WMI_P2P_SET_VENDOR_IE_DATA_CMDID) \ - OP(WMI_AP_PS_PEER_PARAM_CMDID) \ - OP(WMI_WLAN_PROFILE_TRIGGER_CMDID) \ - OP(WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID) \ - OP(WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID) \ - OP(WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID) \ - OP(WMI_WOW_DEL_WAKE_PATTERN_CMDID) \ - OP(WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID) \ - OP(WMI_RTT_MEASREQ_CMDID) \ - OP(WMI_RTT_TSF_CMDID) \ - OP(WMI_OEM_REQ_CMDID) \ - OP(WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID) \ - OP(WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID) \ - OP(WMI_REQUEST_STATS_CMDID) \ - OP(WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID) \ - OP(WMI_CSA_OFFLOAD_ENABLE_CMDID) \ - OP(WMI_CSA_OFFLOAD_CHANSWITCH_CMDID) \ - OP(WMI_CHATTER_SET_MODE_CMDID) \ - OP(WMI_ECHO_CMDID) \ - OP(WMI_PDEV_UTF_CMDID) \ - OP(WMI_PDEV_QVIT_CMDID) \ - OP(WMI_VDEV_SET_KEEPALIVE_CMDID) \ - OP(WMI_VDEV_GET_KEEPALIVE_CMDID) \ - OP(WMI_FORCE_FW_HANG_CMDID) \ - OP(WMI_GPIO_CONFIG_CMDID) \ - OP(WMI_GPIO_OUTPUT_CMDID) \ - OP(WMI_PEER_ADD_WDS_ENTRY_CMDID) \ - OP(WMI_PEER_REMOVE_WDS_ENTRY_CMDID) \ - OP(WMI_BCN_TX_CMDID) \ - OP(WMI_PDEV_SEND_BCN_CMDID) \ - OP(WMI_MGMT_TX_CMDID) \ - OP(WMI_ADDBA_CLEAR_RESP_CMDID) \ - OP(WMI_ADDBA_SEND_CMDID) \ - OP(WMI_DELBA_SEND_CMDID) \ - OP(WMI_ADDBA_SET_RESP_CMDID) \ - OP(WMI_SEND_SINGLEAMSDU_CMDID) \ - OP(WMI_PDEV_PKTLOG_ENABLE_CMDID) \ - OP(WMI_PDEV_PKTLOG_DISABLE_CMDID) \ - OP(WMI_PDEV_SET_HT_CAP_IE_CMDID) \ - OP(WMI_PDEV_SET_VHT_CAP_IE_CMDID) \ - OP(WMI_PDEV_SET_DSCP_TID_MAP_CMDID) \ - OP(WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID) \ - OP(WMI_PDEV_GET_TPC_CONFIG_CMDID) \ - OP(WMI_PDEV_SET_BASE_MACADDR_CMDID) \ - OP(WMI_PEER_MCAST_GROUP_CMDID) \ - OP(WMI_ROAM_AP_PROFILE) \ - OP(WMI_SCAN_SCH_PRIO_TBL_CMDID) \ - OP(WMI_PDEV_DFS_ENABLE_CMDID) \ - OP(WMI_PDEV_DFS_DISABLE_CMDID) \ - OP(WMI_WOW_ADD_WAKE_PATTERN_CMDID) \ - OP(WMI_PDEV_SUSPEND_CMDID) \ - OP(WMI_PDEV_RESUME_CMDID) \ - OP(WMI_STOP_SCAN_CMDID) \ - OP(WMI_PDEV_SET_PARAM_CMDID) \ - OP(WMI_PDEV_SET_QUIET_MODE_CMDID) \ - OP(WMI_VDEV_CREATE_CMDID) \ - OP(WMI_VDEV_DELETE_CMDID) \ - OP(WMI_VDEV_UP_CMDID) \ - OP(WMI_VDEV_STOP_CMDID) \ - OP(WMI_VDEV_DOWN_CMDID) \ - OP(WMI_VDEV_SET_PARAM_CMDID) \ - OP(WMI_SCAN_UPDATE_REQUEST_CMDID) \ - OP(WMI_CHATTER_ADD_COALESCING_FILTER_CMDID) \ - OP(WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID) \ - OP(WMI_CHATTER_COALESCING_QUERY_CMDID) \ - OP(WMI_TXBF_CMDID) \ - OP(WMI_DBGLOG_CFG_CMDID) \ - OP(WMI_VDEV_WNM_SLEEPMODE_CMDID) \ - OP(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID) \ - OP(WMI_VDEV_WMM_ADDTS_CMDID) \ - OP(WMI_VDEV_WMM_DELTS_CMDID) \ - OP(WMI_VDEV_SET_WMM_PARAMS_CMDID) \ - OP(WMI_VDEV_SET_GTX_PARAMS_CMDID) \ - OP(WMI_TDLS_SET_STATE_CMDID) \ - OP(WMI_TDLS_PEER_UPDATE_CMDID) \ - OP(WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID) \ - OP(WMI_ROAM_CHAN_LIST) \ - OP(WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID)\ - OP(WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID) \ - OP(WMI_RESMGR_SET_CHAN_LATENCY_CMDID) \ - OP(WMI_BA_REQ_SSN_CMDID) \ - OP(WMI_STA_SMPS_FORCE_MODE_CMDID) \ - OP(WMI_SET_MCASTBCAST_FILTER_CMDID) \ - OP(WMI_P2P_SET_OPPPS_PARAM_CMDID) \ - OP(WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID) \ - OP(WMI_STA_SMPS_PARAM_CMDID) \ - OP(WMI_MCC_SCHED_TRAFFIC_STATS_CMDID) \ - OP(WMI_HB_SET_ENABLE_CMDID) \ - OP(WMI_HB_SET_TCP_PARAMS_CMDID) \ - OP(WMI_HB_SET_TCP_PKT_FILTER_CMDID) \ - OP(WMI_HB_SET_UDP_PARAMS_CMDID) \ - OP(WMI_HB_SET_UDP_PKT_FILTER_CMDID) \ - OP(WMI_PEER_INFO_REQ_CMDID) \ - OP(WMI_RMC_SET_MODE_CMDID) \ - OP(WMI_RMC_SET_ACTION_PERIOD_CMDID) \ - OP(WMI_RMC_CONFIG_CMDID) \ - OP(WMI_MHF_OFFLOAD_SET_MODE_CMDID) \ - OP(WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID) \ - OP(WMI_DFS_PHYERR_FILTER_ENA_CMDID) \ - OP(WMI_DFS_PHYERR_FILTER_DIS_CMDID) \ - OP(WMI_BATCH_SCAN_ENABLE_CMDID) \ - OP(WMI_BATCH_SCAN_DISABLE_CMDID) \ - OP(WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID)\ - OP(WMI_THERMAL_MGMT_CMDID)\ - OP(WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID)\ - OP(WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID) \ - OP(WMI_NAN_CMDID) \ - OP(WMI_MODEM_POWER_STATE_CMDID) \ - OP(WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID) \ - OP(WMI_ROAM_SCAN_CMD) \ - OP(WMI_REQUEST_STATS_EXT_CMDID) \ - OP(WMI_OBSS_SCAN_ENABLE_CMDID) \ - OP(WMI_OBSS_SCAN_DISABLE_CMDID) \ - OP(WMI_PDEV_SET_LED_CONFIG_CMDID) \ - OP(WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID) \ - OP(WMI_TPC_CHAINMASK_CONFIG_CMDID) \ - OP(WMI_CHAN_AVOID_UPDATE_CMDID) \ - OP(WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID) \ - OP(WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID) \ - OP(WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID) \ - OP(WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID) \ - OP(WMI_REQUEST_LINK_STATS_CMDID) \ - OP(WMI_START_LINK_STATS_CMDID) \ - OP(WMI_CLEAR_LINK_STATS_CMDID) \ - OP(WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID) \ - OP(WMI_LPI_START_SCAN_CMDID) \ - OP(WMI_LPI_STOP_SCAN_CMDID) \ - OP(WMI_EXTSCAN_START_CMDID) \ - OP(WMI_EXTSCAN_STOP_CMDID) \ - OP(WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID) \ - OP(WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID) \ - OP(WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID) \ - OP(WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID) \ - OP(WMI_EXTSCAN_SET_CAPABILITIES_CMDID) \ - OP(WMI_EXTSCAN_GET_CAPABILITIES_CMDID) \ - OP(WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID) \ - OP(WMI_D0_WOW_ENABLE_DISABLE_CMDID) \ - OP(WMI_UNIT_TEST_CMDID) \ - OP(WMI_ROAM_SYNCH_COMPLETE) \ - OP(WMI_EXTWOW_ENABLE_CMDID) \ - OP(WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID) \ - OP(WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID) \ - OP(WMI_ROAM_SET_RIC_REQUEST_CMDID) \ - OP(WMI_PDEV_GET_TEMPERATURE_CMDID) \ - OP(WMI_SET_DHCP_SERVER_OFFLOAD_CMDID) \ - OP(WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID)\ - OP(WMI_SCAN_PROB_REQ_OUI_CMDID) \ - OP(WMI_TDLS_SET_OFFCHAN_MODE_CMDID)\ - OP(WMI_PDEV_SET_LED_FLASHING_CMDID) \ - OP(WMI_ROAM_INVOKE_CMDID) \ - OP(WMI_MDNS_OFFLOAD_ENABLE_CMDID) \ - OP(WMI_MDNS_SET_FQDN_CMDID) \ - OP(WMI_MDNS_SET_RESPONSE_CMDID) \ - OP(WMI_MDNS_GET_STATS_CMDID) \ - OP(WMI_SET_ANTENNA_DIVERSITY_CMDID) \ - OP(WMI_SAP_OFL_ENABLE_CMDID) \ - OP(WMI_APFIND_CMDID) \ - OP(WMI_OCB_SET_SCHED_CMDID) \ - OP(WMI_OCB_SET_CONFIG_CMDID) \ - OP(WMI_OCB_SET_UTC_TIME_CMDID) \ - OP(WMI_OCB_START_TIMING_ADVERT_CMDID) \ - OP(WMI_OCB_STOP_TIMING_ADVERT_CMDID) \ - OP(WMI_OCB_GET_TSF_TIMER_CMDID) \ - OP(WMI_DCC_GET_STATS_CMDID) \ - OP(WMI_DCC_CLEAR_STATS_CMDID) \ - OP(WMI_DCC_UPDATE_NDL_CMDID) \ - OP(WMI_ROAM_FILTER_CMDID) \ - OP(WMI_PASSPOINT_LIST_CONFIG_CMDID) \ - OP(WMI_VDEV_TSF_TSTAMP_ACTION_CMDID) \ - OP(WMI_GET_FW_MEM_DUMP_CMDID) \ - OP(WMI_DEBUG_MESG_FLUSH_CMDID) \ - OP(WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID) \ - OP(WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID) \ - OP(WMI_VDEV_SET_IE_CMDID) \ - OP(WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID) \ - OP(WMI_SOC_SET_PCL_CMDID) \ - OP(WMI_SOC_SET_HW_MODE_CMDID) \ - OP(WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID) \ - OP(WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID) \ - OP(WMI_DIAG_EVENT_LOG_CONFIG_CMDID) \ - OP(WMI_PACKET_FILTER_CONFIG_CMDID) \ - OP(WMI_PACKET_FILTER_ENABLE_CMDID) \ - OP(WMI_SAP_SET_BLACKLIST_PARAM_CMDID) \ - OP(WMI_MGMT_TX_SEND_CMDID) \ - OP(WMI_SOC_SET_ANTENNA_MODE_CMDID) \ - OP(WMI_WOW_UDP_SVC_OFLD_CMDID) \ - OP(WMI_LRO_CONFIG_CMDID) \ - OP(WMI_MAWC_SENSOR_REPORT_IND_CMDID) \ - OP(WMI_ROAM_CONFIGURE_MAWC_CMDID) \ - OP(WMI_NLO_CONFIGURE_MAWC_CMDID) \ - OP(WMI_EXTSCAN_CONFIGURE_MAWC_CMDID) \ - OP(WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID) \ - OP(WMI_AP_PS_EGAP_PARAM_CMDID) \ - OP(WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID) \ - OP(WMI_TRANSFER_DATA_TO_FLASH_CMDID) \ - OP(WMI_OEM_REQUEST_CMDID) \ - OP(WMI_BPF_GET_CAPABILITY_CMDID) \ - OP(WMI_BPF_GET_VDEV_STATS_CMDID) \ - OP(WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID) \ - OP(WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID) \ - OP(WMI_PEER_UPDATE_WDS_ENTRY_CMDID) \ - OP(WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID) \ - OP(WMI_PDEV_FIPS_CMDID) \ - OP(WMI_PDEV_SMART_ANT_ENABLE_CMDID) \ - OP(WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID) \ - OP(WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID) \ - OP(WMI_PDEV_SET_CTL_TABLE_CMDID) \ - OP(WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID) \ - OP(WMI_PDEV_GET_TPC_CMDID) \ - OP(WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID) \ - OP(WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID) \ - OP(WMI_VDEV_RATEMASK_CMDID) \ - OP(WMI_VDEV_ATF_REQUEST_CMDID) \ - OP(WMI_VDEV_SET_DSCP_TID_MAP_CMDID) \ - OP(WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID) \ - OP(WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID) \ - OP(WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID) \ - OP(WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID) \ - OP(WMI_PEER_ATF_REQUEST_CMDID) \ - OP(WMI_FWTEST_CMDID) \ - OP(WMI_QBOOST_CFG_CMDID) \ - OP(WMI_ROAM_SET_MBO_PARAM_CMDID) \ - OP(WMI_MIB_STATS_ENABLE_CMDID) \ - OP(WMI_NDI_GET_CAP_REQ_CMDID) \ - OP(WMI_NDP_INITIATOR_REQ_CMDID) \ - OP(WMI_NDP_RESPONDER_REQ_CMDID) \ - OP(WMI_NDP_END_REQ_CMDID) \ - OP(WMI_PDEV_SET_PCL_CMDID) \ - OP(WMI_PDEV_SET_HW_MODE_CMDID) \ - OP(WMI_PDEV_SET_MAC_CONFIG_CMDID) \ - OP(WMI_PDEV_SET_ANTENNA_MODE_CMDID) \ - OP(WMI_VDEV_SET_QUIET_MODE_CMDID) \ - OP(WMI_COEX_CONFIG_CMDID) \ - OP(WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID) \ - OP(WMI_CHAN_AVOID_RPT_ALLOW_CMDID) \ - OP(WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID) \ - OP(WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID) \ - OP(WMI_PDEV_WAL_POWER_DEBUG_CMDID) \ - OP(WMI_VDEV_WISA_CMDID) \ - OP(WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID) \ - OP(WMI_WOW_SET_ACTION_WAKE_UP_CMDID) \ - OP(WMI_PEER_BWF_REQUEST_CMDID) \ - OP(WMI_DBGLOG_TIME_STAMP_SYNC_CMDID) \ - OP(WMI_RMC_SET_MANUAL_LEADER_CMDID) \ - OP(WMI_P2P_LISTEN_OFFLOAD_START_CMDID) \ - OP(WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID) \ - OP(WMI_PEER_REORDER_QUEUE_SETUP_CMDID) \ - OP(WMI_PEER_REORDER_QUEUE_REMOVE_CMDID) \ - OP(WMI_SET_MULTIPLE_MCAST_FILTER_CMDID) \ - OP(WMI_READ_DATA_FROM_FLASH_CMDID) \ - OP(WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID) \ - OP(WMI_PEER_SET_RX_BLOCKSIZE_CMDID) \ - OP(WMI_PDEV_SET_WAKEUP_CONFIG_CMDID) \ - OP(WMI_PEER_ANTDIV_INFO_REQ_CMDID) \ - OP(WMI_PDEV_GET_ANTDIV_STATUS_CMDID) \ - OP(WMI_MNT_FILTER_CMDID) \ - OP(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID) \ - OP(WMI_COEX_GET_ANTENNA_ISOLATION_CMDID) \ - OP(WMI_PDEV_SET_STATS_THRESHOLD_CMDID) \ - OP(WMI_REQUEST_WLAN_STATS_CMDID) \ - /* add new CMD_LIST elements above this line */ - +#define WMITLV_ALL_CMD_LIST(OP) \ + OP(WMI_INIT_CMDID) \ + OP(WMI_PEER_CREATE_CMDID) \ + OP(WMI_PEER_DELETE_CMDID) \ + OP(WMI_PEER_FLUSH_TIDS_CMDID) \ + OP(WMI_PEER_SET_PARAM_CMDID) \ + OP(WMI_STA_POWERSAVE_MODE_CMDID) \ + OP(WMI_STA_POWERSAVE_PARAM_CMDID) \ + OP(WMI_STA_DTIM_PS_METHOD_CMDID) \ + OP(WMI_PDEV_SET_REGDOMAIN_CMDID) \ + OP(WMI_PEER_TID_ADDBA_CMDID) \ + OP(WMI_PEER_TID_DELBA_CMDID) \ + OP(WMI_PDEV_FTM_INTG_CMDID) \ + OP(WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID) \ + OP(WMI_WOW_ENABLE_CMDID) \ + OP(WMI_RMV_BCN_FILTER_CMDID) \ + OP(WMI_ROAM_SCAN_MODE) \ + OP(WMI_ROAM_SCAN_RSSI_THRESHOLD) \ + OP(WMI_ROAM_SCAN_PERIOD) \ + OP(WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD) \ + OP(WMI_START_SCAN_CMDID) \ + OP(WMI_VDEV_PLMREQ_START_CMDID) \ + OP(WMI_VDEV_PLMREQ_STOP_CMDID) \ + OP(WMI_PDEV_SET_CHANNEL_CMDID) \ + OP(WMI_PDEV_SET_WMM_PARAMS_CMDID) \ + OP(WMI_VDEV_START_REQUEST_CMDID) \ + OP(WMI_VDEV_RESTART_REQUEST_CMDID) \ + OP(WMI_P2P_GO_SET_BEACON_IE) \ + OP(WMI_GTK_OFFLOAD_CMDID) \ + OP(WMI_SCAN_CHAN_LIST_CMDID) \ + OP(WMI_STA_UAPSD_AUTO_TRIG_CMDID) \ + OP(WMI_PRB_TMPL_CMDID) \ + OP(WMI_BCN_TMPL_CMDID) \ + OP(WMI_VDEV_INSTALL_KEY_CMDID) \ + OP(WMI_PEER_ASSOC_CMDID) \ + OP(WMI_ADD_BCN_FILTER_CMDID) \ + OP(WMI_STA_KEEPALIVE_CMDID) \ + OP(WMI_SET_ARP_NS_OFFLOAD_CMDID) \ + OP(WMI_P2P_SET_VENDOR_IE_DATA_CMDID) \ + OP(WMI_AP_PS_PEER_PARAM_CMDID) \ + OP(WMI_WLAN_PROFILE_TRIGGER_CMDID) \ + OP(WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID) \ + OP(WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID) \ + OP(WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID) \ + OP(WMI_WOW_DEL_WAKE_PATTERN_CMDID) \ + OP(WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID) \ + OP(WMI_RTT_MEASREQ_CMDID) \ + OP(WMI_RTT_TSF_CMDID) \ + OP(WMI_OEM_REQ_CMDID) \ + OP(WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID) \ + OP(WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID) \ + OP(WMI_REQUEST_STATS_CMDID) \ + OP(WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID) \ + OP(WMI_CSA_OFFLOAD_ENABLE_CMDID) \ + OP(WMI_CSA_OFFLOAD_CHANSWITCH_CMDID) \ + OP(WMI_CHATTER_SET_MODE_CMDID) \ + OP(WMI_ECHO_CMDID) \ + OP(WMI_PDEV_UTF_CMDID) \ + OP(WMI_PDEV_QVIT_CMDID) \ + OP(WMI_VDEV_SET_KEEPALIVE_CMDID) \ + OP(WMI_VDEV_GET_KEEPALIVE_CMDID) \ + OP(WMI_FORCE_FW_HANG_CMDID) \ + OP(WMI_GPIO_CONFIG_CMDID) \ + OP(WMI_GPIO_OUTPUT_CMDID) \ + OP(WMI_PEER_ADD_WDS_ENTRY_CMDID) \ + OP(WMI_PEER_REMOVE_WDS_ENTRY_CMDID) \ + OP(WMI_BCN_TX_CMDID) \ + OP(WMI_PDEV_SEND_BCN_CMDID) \ + OP(WMI_MGMT_TX_CMDID) \ + OP(WMI_ADDBA_CLEAR_RESP_CMDID) \ + OP(WMI_ADDBA_SEND_CMDID) \ + OP(WMI_DELBA_SEND_CMDID) \ + OP(WMI_ADDBA_SET_RESP_CMDID) \ + OP(WMI_SEND_SINGLEAMSDU_CMDID) \ + OP(WMI_PDEV_PKTLOG_ENABLE_CMDID) \ + OP(WMI_PDEV_PKTLOG_DISABLE_CMDID) \ + OP(WMI_PDEV_SET_HT_CAP_IE_CMDID) \ + OP(WMI_PDEV_SET_VHT_CAP_IE_CMDID) \ + OP(WMI_PDEV_SET_DSCP_TID_MAP_CMDID) \ + OP(WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID) \ + OP(WMI_PDEV_GET_TPC_CONFIG_CMDID) \ + OP(WMI_PDEV_SET_BASE_MACADDR_CMDID) \ + OP(WMI_PEER_MCAST_GROUP_CMDID) \ + OP(WMI_ROAM_AP_PROFILE) \ + OP(WMI_SCAN_SCH_PRIO_TBL_CMDID) \ + OP(WMI_PDEV_DFS_ENABLE_CMDID) \ + OP(WMI_PDEV_DFS_DISABLE_CMDID) \ + OP(WMI_WOW_ADD_WAKE_PATTERN_CMDID) \ + OP(WMI_PDEV_SUSPEND_CMDID) \ + OP(WMI_PDEV_RESUME_CMDID) \ + OP(WMI_STOP_SCAN_CMDID) \ + OP(WMI_PDEV_SET_PARAM_CMDID) \ + OP(WMI_PDEV_SET_QUIET_MODE_CMDID) \ + OP(WMI_VDEV_CREATE_CMDID) \ + OP(WMI_VDEV_DELETE_CMDID) \ + OP(WMI_VDEV_UP_CMDID) \ + OP(WMI_VDEV_STOP_CMDID) \ + OP(WMI_VDEV_DOWN_CMDID) \ + OP(WMI_VDEV_SET_PARAM_CMDID) \ + OP(WMI_SCAN_UPDATE_REQUEST_CMDID) \ + OP(WMI_CHATTER_ADD_COALESCING_FILTER_CMDID) \ + OP(WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID) \ + OP(WMI_CHATTER_COALESCING_QUERY_CMDID) \ + OP(WMI_TXBF_CMDID) \ + OP(WMI_DBGLOG_CFG_CMDID) \ + OP(WMI_VDEV_WNM_SLEEPMODE_CMDID) \ + OP(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID) \ + OP(WMI_VDEV_WMM_ADDTS_CMDID) \ + OP(WMI_VDEV_WMM_DELTS_CMDID) \ + OP(WMI_VDEV_SET_WMM_PARAMS_CMDID) \ + OP(WMI_VDEV_SET_GTX_PARAMS_CMDID) \ + OP(WMI_TDLS_SET_STATE_CMDID) \ + OP(WMI_TDLS_PEER_UPDATE_CMDID) \ + OP(WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID) \ + OP(WMI_ROAM_CHAN_LIST) \ + OP(WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID) \ + OP(WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID) \ + OP(WMI_RESMGR_SET_CHAN_LATENCY_CMDID) \ + OP(WMI_BA_REQ_SSN_CMDID) \ + OP(WMI_STA_SMPS_FORCE_MODE_CMDID) \ + OP(WMI_SET_MCASTBCAST_FILTER_CMDID) \ + OP(WMI_P2P_SET_OPPPS_PARAM_CMDID) \ + OP(WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID) \ + OP(WMI_STA_SMPS_PARAM_CMDID) \ + OP(WMI_MCC_SCHED_TRAFFIC_STATS_CMDID) \ + OP(WMI_HB_SET_ENABLE_CMDID) \ + OP(WMI_HB_SET_TCP_PARAMS_CMDID) \ + OP(WMI_HB_SET_TCP_PKT_FILTER_CMDID) \ + OP(WMI_HB_SET_UDP_PARAMS_CMDID) \ + OP(WMI_HB_SET_UDP_PKT_FILTER_CMDID) \ + OP(WMI_PEER_INFO_REQ_CMDID) \ + OP(WMI_RMC_SET_MODE_CMDID) \ + OP(WMI_RMC_SET_ACTION_PERIOD_CMDID) \ + OP(WMI_RMC_CONFIG_CMDID) \ + OP(WMI_MHF_OFFLOAD_SET_MODE_CMDID) \ + OP(WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID) \ + OP(WMI_DFS_PHYERR_FILTER_ENA_CMDID) \ + OP(WMI_DFS_PHYERR_FILTER_DIS_CMDID) \ + OP(WMI_BATCH_SCAN_ENABLE_CMDID) \ + OP(WMI_BATCH_SCAN_DISABLE_CMDID) \ + OP(WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID) \ + OP(WMI_THERMAL_MGMT_CMDID) \ + OP(WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID) \ + OP(WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID) \ + OP(WMI_NAN_CMDID) \ + OP(WMI_MODEM_POWER_STATE_CMDID) \ + OP(WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID) \ + OP(WMI_ROAM_SCAN_CMD) \ + OP(WMI_REQUEST_STATS_EXT_CMDID) \ + OP(WMI_OBSS_SCAN_ENABLE_CMDID) \ + OP(WMI_OBSS_SCAN_DISABLE_CMDID) \ + OP(WMI_PDEV_SET_LED_CONFIG_CMDID) \ + OP(WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID) \ + OP(WMI_TPC_CHAINMASK_CONFIG_CMDID) \ + OP(WMI_CHAN_AVOID_UPDATE_CMDID) \ + OP(WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID) \ + OP(WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID) \ + OP(WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID) \ + OP(WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID) \ + OP(WMI_REQUEST_LINK_STATS_CMDID) \ + OP(WMI_START_LINK_STATS_CMDID) \ + OP(WMI_CLEAR_LINK_STATS_CMDID) \ + OP(WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID) \ + OP(WMI_LPI_START_SCAN_CMDID) \ + OP(WMI_LPI_STOP_SCAN_CMDID) \ + OP(WMI_EXTSCAN_START_CMDID) \ + OP(WMI_EXTSCAN_STOP_CMDID) \ + OP(WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID) \ + OP(WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID) \ + OP(WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID) \ + OP(WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID) \ + OP(WMI_EXTSCAN_SET_CAPABILITIES_CMDID) \ + OP(WMI_EXTSCAN_GET_CAPABILITIES_CMDID) \ + OP(WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID) \ + OP(WMI_D0_WOW_ENABLE_DISABLE_CMDID) \ + OP(WMI_UNIT_TEST_CMDID) \ + OP(WMI_ROAM_SYNCH_COMPLETE) \ + OP(WMI_EXTWOW_ENABLE_CMDID) \ + OP(WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID) \ + OP(WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID) \ + OP(WMI_ROAM_SET_RIC_REQUEST_CMDID) \ + OP(WMI_PDEV_GET_TEMPERATURE_CMDID) \ + OP(WMI_SET_DHCP_SERVER_OFFLOAD_CMDID) \ + OP(WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID) \ + OP(WMI_SCAN_PROB_REQ_OUI_CMDID) \ + OP(WMI_TDLS_SET_OFFCHAN_MODE_CMDID) \ + OP(WMI_PDEV_SET_LED_FLASHING_CMDID) \ + OP(WMI_ROAM_INVOKE_CMDID) \ + OP(WMI_MDNS_OFFLOAD_ENABLE_CMDID) \ + OP(WMI_MDNS_SET_FQDN_CMDID) \ + OP(WMI_MDNS_SET_RESPONSE_CMDID) \ + OP(WMI_MDNS_GET_STATS_CMDID) \ + OP(WMI_SET_ANTENNA_DIVERSITY_CMDID) \ + OP(WMI_SAP_OFL_ENABLE_CMDID) \ + OP(WMI_APFIND_CMDID) \ + OP(WMI_OCB_SET_SCHED_CMDID) \ + OP(WMI_OCB_SET_CONFIG_CMDID) \ + OP(WMI_OCB_SET_UTC_TIME_CMDID) \ + OP(WMI_OCB_START_TIMING_ADVERT_CMDID) \ + OP(WMI_OCB_STOP_TIMING_ADVERT_CMDID) \ + OP(WMI_OCB_GET_TSF_TIMER_CMDID) \ + OP(WMI_DCC_GET_STATS_CMDID) \ + OP(WMI_DCC_CLEAR_STATS_CMDID) \ + OP(WMI_DCC_UPDATE_NDL_CMDID) \ + OP(WMI_ROAM_FILTER_CMDID) \ + OP(WMI_PASSPOINT_LIST_CONFIG_CMDID) \ + OP(WMI_VDEV_TSF_TSTAMP_ACTION_CMDID) \ + OP(WMI_GET_FW_MEM_DUMP_CMDID) \ + OP(WMI_DEBUG_MESG_FLUSH_CMDID) \ + OP(WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID) \ + OP(WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID) \ + OP(WMI_VDEV_SET_IE_CMDID) \ + OP(WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID) \ + OP(WMI_SOC_SET_PCL_CMDID) \ + OP(WMI_SOC_SET_HW_MODE_CMDID) \ + OP(WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID) \ + OP(WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID) \ + OP(WMI_DIAG_EVENT_LOG_CONFIG_CMDID) \ + OP(WMI_PACKET_FILTER_CONFIG_CMDID) \ + OP(WMI_PACKET_FILTER_ENABLE_CMDID) \ + OP(WMI_SAP_SET_BLACKLIST_PARAM_CMDID) \ + OP(WMI_MGMT_TX_SEND_CMDID) \ + OP(WMI_SOC_SET_ANTENNA_MODE_CMDID) \ + OP(WMI_WOW_UDP_SVC_OFLD_CMDID) \ + OP(WMI_LRO_CONFIG_CMDID) \ + OP(WMI_MAWC_SENSOR_REPORT_IND_CMDID) \ + OP(WMI_ROAM_CONFIGURE_MAWC_CMDID) \ + OP(WMI_NLO_CONFIGURE_MAWC_CMDID) \ + OP(WMI_EXTSCAN_CONFIGURE_MAWC_CMDID) \ + OP(WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID) \ + OP(WMI_AP_PS_EGAP_PARAM_CMDID) \ + OP(WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID) \ + OP(WMI_TRANSFER_DATA_TO_FLASH_CMDID) \ + OP(WMI_OEM_REQUEST_CMDID) \ + OP(WMI_BPF_GET_CAPABILITY_CMDID) \ + OP(WMI_BPF_GET_VDEV_STATS_CMDID) \ + OP(WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID) \ + OP(WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID) \ + OP(WMI_PEER_UPDATE_WDS_ENTRY_CMDID) \ + OP(WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID) \ + OP(WMI_PDEV_FIPS_CMDID) \ + OP(WMI_PDEV_SMART_ANT_ENABLE_CMDID) \ + OP(WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID) \ + OP(WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID) \ + OP(WMI_PDEV_SET_CTL_TABLE_CMDID) \ + OP(WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID) \ + OP(WMI_PDEV_GET_TPC_CMDID) \ + OP(WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID) \ + OP(WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID) \ + OP(WMI_VDEV_RATEMASK_CMDID) \ + OP(WMI_VDEV_ATF_REQUEST_CMDID) \ + OP(WMI_VDEV_SET_DSCP_TID_MAP_CMDID) \ + OP(WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID) \ + OP(WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID) \ + OP(WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID) \ + OP(WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID) \ + OP(WMI_PEER_ATF_REQUEST_CMDID) \ + OP(WMI_FWTEST_CMDID) \ + OP(WMI_QBOOST_CFG_CMDID) \ + OP(WMI_ROAM_SET_MBO_PARAM_CMDID) \ + OP(WMI_MIB_STATS_ENABLE_CMDID) \ + OP(WMI_NDI_GET_CAP_REQ_CMDID) \ + OP(WMI_NDP_INITIATOR_REQ_CMDID) \ + OP(WMI_NDP_RESPONDER_REQ_CMDID) \ + OP(WMI_NDP_END_REQ_CMDID) \ + OP(WMI_PDEV_SET_PCL_CMDID) \ + OP(WMI_PDEV_SET_HW_MODE_CMDID) \ + OP(WMI_PDEV_SET_MAC_CONFIG_CMDID) \ + OP(WMI_PDEV_SET_ANTENNA_MODE_CMDID) \ + OP(WMI_VDEV_SET_QUIET_MODE_CMDID) \ + OP(WMI_COEX_CONFIG_CMDID) \ + OP(WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID) \ + OP(WMI_CHAN_AVOID_RPT_ALLOW_CMDID) \ + OP(WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID) \ + OP(WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID) \ + OP(WMI_PDEV_WAL_POWER_DEBUG_CMDID) \ + OP(WMI_VDEV_WISA_CMDID) \ + OP(WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID) \ + OP(WMI_WOW_SET_ACTION_WAKE_UP_CMDID) \ + OP(WMI_PEER_BWF_REQUEST_CMDID) \ + OP(WMI_DBGLOG_TIME_STAMP_SYNC_CMDID) \ + OP(WMI_P2P_LISTEN_OFFLOAD_START_CMDID) \ + OP(WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID) \ + OP(WMI_PEER_REORDER_QUEUE_SETUP_CMDID) \ + OP(WMI_PEER_REORDER_QUEUE_REMOVE_CMDID) \ + OP(WMI_SET_MULTIPLE_MCAST_FILTER_CMDID) \ + OP(WMI_READ_DATA_FROM_FLASH_CMDID) \ + OP(WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID) \ + OP(WMI_PEER_SET_RX_BLOCKSIZE_CMDID) \ + OP(WMI_PDEV_SET_WAKEUP_CONFIG_CMDID) \ + OP(WMI_PEER_ANTDIV_INFO_REQ_CMDID) \ + OP(WMI_PDEV_GET_ANTDIV_STATUS_CMDID) \ + OP(WMI_MNT_FILTER_CMDID) \ + OP(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID) \ + OP(WMI_COEX_GET_ANTENNA_ISOLATION_CMDID) \ + OP(WMI_PDEV_SET_STATS_THRESHOLD_CMDID) \ + OP(WMI_REQUEST_WLAN_STATS_CMDID) \ + OP(WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID) \ + OP(WMI_SAR_LIMITS_CMDID) \ + OP(WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID) \ + OP(WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID) \ + OP(WMI_VDEV_ADFS_CH_CFG_CMDID) \ + OP(WMI_VDEV_ADFS_OCAC_ABORT_CMDID) \ + /* add new CMD_LIST elements above this line */ /* * IMPORTANT: Please add _ALL_ WMI Events Here. * Otherwise, these WMI TLV Functions will be process them. */ -#define WMITLV_ALL_EVT_LIST(OP) \ - OP(WMI_SERVICE_READY_EVENTID) \ - OP(WMI_SERVICE_READY_EXT_EVENTID) \ - OP(WMI_READY_EVENTID) \ - OP(WMI_SCAN_EVENTID) \ - OP(WMI_PDEV_TPC_CONFIG_EVENTID) \ - OP(WMI_CHAN_INFO_EVENTID) \ - OP(WMI_PHYERR_EVENTID) \ - OP(WMI_VDEV_START_RESP_EVENTID) \ - OP(WMI_VDEV_STOPPED_EVENTID) \ - OP(WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID) \ - OP(WMI_PEER_STA_KICKOUT_EVENTID) \ - OP(WMI_MGMT_RX_EVENTID) \ - OP(WMI_TBTTOFFSET_UPDATE_EVENTID) \ - OP(WMI_TX_DELBA_COMPLETE_EVENTID) \ - OP(WMI_TX_ADDBA_COMPLETE_EVENTID) \ - OP(WMI_ROAM_EVENTID) \ - OP(WMI_WOW_WAKEUP_HOST_EVENTID) \ - OP(WMI_RTT_ERROR_REPORT_EVENTID) \ - OP(WMI_OEM_MEASUREMENT_REPORT_EVENTID) \ - OP(WMI_OEM_ERROR_REPORT_EVENTID) \ - OP(WMI_OEM_CAPABILITY_EVENTID) \ - OP(WMI_ECHO_EVENTID) \ - OP(WMI_PDEV_FTM_INTG_EVENTID) \ - OP(WMI_VDEV_GET_KEEPALIVE_EVENTID) \ - OP(WMI_GPIO_INPUT_EVENTID) \ - OP(WMI_CSA_HANDLING_EVENTID) \ - OP(WMI_DEBUG_MESG_EVENTID) \ - OP(WMI_GTK_OFFLOAD_STATUS_EVENTID) \ - OP(WMI_DCS_INTERFERENCE_EVENTID) \ - OP(WMI_WLAN_PROFILE_DATA_EVENTID) \ - OP(WMI_PDEV_UTF_EVENTID) \ - OP(WMI_DEBUG_PRINT_EVENTID) \ - OP(WMI_RTT_MEASUREMENT_REPORT_EVENTID) \ - OP(WMI_HOST_SWBA_EVENTID) \ - OP(WMI_UPDATE_STATS_EVENTID) \ - OP(WMI_PDEV_QVIT_EVENTID) \ - OP(WMI_WLAN_FREQ_AVOID_EVENTID) \ - OP(WMI_GTK_REKEY_FAIL_EVENTID) \ - OP(WMI_NLO_MATCH_EVENTID) \ - OP(WMI_NLO_SCAN_COMPLETE_EVENTID) \ - OP(WMI_APFIND_EVENTID) \ - OP(WMI_CHATTER_PC_QUERY_EVENTID) \ - OP(WMI_UPLOADH_EVENTID) \ - OP(WMI_CAPTUREH_EVENTID) \ - OP(WMI_TDLS_PEER_EVENTID) \ - OP(WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID) \ - OP(WMI_BA_RSP_SSN_EVENTID) \ - OP(WMI_OFFLOAD_BCN_TX_STATUS_EVENTID) \ - OP(WMI_P2P_NOA_EVENTID) \ - OP(WMI_TX_PAUSE_EVENTID) \ - OP(WMI_RFKILL_STATE_CHANGE_EVENTID) \ - OP(WMI_PEER_INFO_EVENTID) \ - OP(WMI_PEER_TX_FAIL_CNT_THR_EVENTID) \ - OP(WMI_DFS_RADAR_EVENTID) \ - OP(WMI_BATCH_SCAN_ENABLED_EVENTID) \ - OP(WMI_BATCH_SCAN_RESULT_EVENTID) \ - OP(WMI_THERMAL_MGMT_EVENTID) \ - OP(WMI_NAN_EVENTID) \ - OP(WMI_PDEV_L1SS_TRACK_EVENTID) \ - OP(WMI_DIAG_DATA_CONTAINER_EVENTID) \ - OP(WMI_PEER_ESTIMATED_LINKSPEED_EVENTID) \ - OP(WMI_AGGR_STATE_TRIG_EVENTID) \ - OP(WMI_STATS_EXT_EVENTID) \ - OP(WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID) \ - OP(WMI_HOST_AUTO_SHUTDOWN_EVENTID) \ - OP(WMI_UPDATE_WHAL_MIB_STATS_EVENTID) \ - OP(WMI_IFACE_LINK_STATS_EVENTID) \ - OP(WMI_PEER_LINK_STATS_EVENTID) \ - OP(WMI_RADIO_LINK_STATS_EVENTID) \ - OP(WMI_LPI_RESULT_EVENTID) \ - OP(WMI_PEER_STATE_EVENTID) \ - OP(WMI_EXTSCAN_START_STOP_EVENTID) \ - OP(WMI_EXTSCAN_OPERATION_EVENTID) \ - OP(WMI_EXTSCAN_TABLE_USAGE_EVENTID) \ - OP(WMI_EXTSCAN_CACHED_RESULTS_EVENTID) \ - OP(WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID) \ - OP(WMI_EXTSCAN_HOTLIST_MATCH_EVENTID) \ - OP(WMI_EXTSCAN_CAPABILITIES_EVENTID) \ - OP(WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID) \ - OP(WMI_D0_WOW_DISABLE_ACK_EVENTID) \ - OP(WMI_ROAM_SYNCH_EVENTID) \ - OP(WMI_LPI_STATUS_EVENTID) \ - OP(WMI_LPI_HANDOFF_EVENTID) \ - OP(WMI_UPDATE_VDEV_RATE_STATS_EVENTID) \ - OP(WMI_PDEV_TEMPERATURE_EVENTID) \ - OP(WMI_DIAG_EVENTID) \ - OP(WMI_MDNS_STATS_EVENTID) \ - OP(WMI_PDEV_RESUME_EVENTID) \ - OP(WMI_SAP_OFL_ADD_STA_EVENTID) \ - OP(WMI_SAP_OFL_DEL_STA_EVENTID) \ - OP(WMI_OCB_SET_SCHED_EVENTID) \ - OP(WMI_OCB_SET_CONFIG_RESP_EVENTID) \ - OP(WMI_OCB_GET_TSF_TIMER_RESP_EVENTID) \ - OP(WMI_DCC_GET_STATS_RESP_EVENTID) \ - OP(WMI_DCC_UPDATE_NDL_RESP_EVENTID) \ - OP(WMI_DCC_STATS_EVENTID) \ - OP(WMI_PASSPOINT_MATCH_EVENTID) \ - OP(WMI_VDEV_TSF_REPORT_EVENTID) \ - OP(WMI_UPDATE_FW_MEM_DUMP_EVENTID) \ - OP(WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID) \ - OP(WMI_RSSI_BREACH_EVENTID) \ - OP(WMI_WOW_INITIAL_WAKEUP_EVENTID) \ - OP(WMI_SOC_SET_HW_MODE_RESP_EVENTID) \ - OP(WMI_SOC_HW_MODE_TRANSITION_EVENTID) \ - OP(WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID) \ - OP(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID) \ - OP(WMI_MGMT_TX_COMPLETION_EVENTID) \ - OP(WMI_MAWC_ENABLE_SENSOR_EVENTID) \ - OP(WMI_PEER_ASSOC_CONF_EVENTID) \ - OP(WMI_AP_PS_EGAP_INFO_EVENTID) \ - OP(WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID) \ - OP(WMI_OEM_RESPONSE_EVENTID) \ - OP(WMI_PDEV_UTF_SCPC_EVENTID) \ - OP(WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID) \ - OP(WMI_BPF_CAPABILIY_INFO_EVENTID) \ - OP(WMI_BPF_VDEV_STATS_INFO_EVENTID) \ - OP(WMI_VDEV_DELETE_RESP_EVENTID) \ - OP(WMI_PEER_DELETE_RESP_EVENTID) \ - OP(WMI_PDEV_FIPS_EVENTID) \ - OP(WMI_PDEV_CHANNEL_HOPPING_EVENTID) \ - OP(WMI_PDEV_ANI_CCK_LEVEL_EVENTID) \ - OP(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID) \ - OP(WMI_PDEV_TPC_EVENTID) \ - OP(WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID) \ - OP(WMI_PEER_RATECODE_LIST_EVENTID) \ - OP(WMI_WDS_PEER_EVENTID) \ - OP(WMI_PEER_STA_PS_STATECHG_EVENTID) \ - OP(WMI_INST_RSSI_STATS_EVENTID) \ - OP(WMI_NAN_DISC_IFACE_CREATED_EVENTID) \ - OP(WMI_NAN_DISC_IFACE_DELETED_EVENTID) \ - OP(WMI_NAN_STARTED_CLUSTER_EVENTID) \ - OP(WMI_NAN_JOINED_CLUSTER_EVENTID) \ - OP(WMI_NDI_CAP_RSP_EVENTID) \ - OP(WMI_NDP_INITIATOR_RSP_EVENTID) \ - OP(WMI_NDP_RESPONDER_RSP_EVENTID) \ - OP(WMI_NDP_END_RSP_EVENTID) \ - OP(WMI_NDP_INDICATION_EVENTID) \ - OP(WMI_NDP_CONFIRM_EVENTID) \ - OP(WMI_NDP_END_INDICATION_EVENTID) \ - OP(WMI_PDEV_SET_HW_MODE_RESP_EVENTID) \ - OP(WMI_PDEV_HW_MODE_TRANSITION_EVENTID) \ - OP(WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID) \ - OP(WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID) \ - OP(WMI_RMC_NEW_LEADER_EVENTID) \ - OP(WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID) \ - OP(WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID) \ - OP(WMI_READ_DATA_FROM_FLASH_EVENTID) \ - OP(WMI_SERVICE_AVAILABLE_EVENTID) \ - OP(WMI_PEER_ANTDIV_INFO_EVENTID) \ - OP(WMI_PDEV_ANTDIV_STATUS_EVENTID) \ - OP(WMI_PDEV_CHIP_POWER_STATS_EVENTID) \ - OP(WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID) \ - OP(WMI_REPORT_STATS_EVENTID) \ - /* add new EVT_LIST elements above this line */ - +#define WMITLV_ALL_EVT_LIST(OP) \ + OP(WMI_SERVICE_READY_EVENTID) \ + OP(WMI_SERVICE_READY_EXT_EVENTID) \ + OP(WMI_READY_EVENTID) \ + OP(WMI_SCAN_EVENTID) \ + OP(WMI_PDEV_TPC_CONFIG_EVENTID) \ + OP(WMI_CHAN_INFO_EVENTID) \ + OP(WMI_PHYERR_EVENTID) \ + OP(WMI_VDEV_START_RESP_EVENTID) \ + OP(WMI_VDEV_STOPPED_EVENTID) \ + OP(WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID) \ + OP(WMI_PEER_STA_KICKOUT_EVENTID) \ + OP(WMI_MGMT_RX_EVENTID) \ + OP(WMI_TBTTOFFSET_UPDATE_EVENTID) \ + OP(WMI_TX_DELBA_COMPLETE_EVENTID) \ + OP(WMI_TX_ADDBA_COMPLETE_EVENTID) \ + OP(WMI_ROAM_EVENTID) \ + OP(WMI_WOW_WAKEUP_HOST_EVENTID) \ + OP(WMI_RTT_ERROR_REPORT_EVENTID) \ + OP(WMI_OEM_MEASUREMENT_REPORT_EVENTID) \ + OP(WMI_OEM_ERROR_REPORT_EVENTID) \ + OP(WMI_OEM_CAPABILITY_EVENTID) \ + OP(WMI_ECHO_EVENTID) \ + OP(WMI_PDEV_FTM_INTG_EVENTID) \ + OP(WMI_VDEV_GET_KEEPALIVE_EVENTID) \ + OP(WMI_GPIO_INPUT_EVENTID) \ + OP(WMI_CSA_HANDLING_EVENTID) \ + OP(WMI_DEBUG_MESG_EVENTID) \ + OP(WMI_GTK_OFFLOAD_STATUS_EVENTID) \ + OP(WMI_DCS_INTERFERENCE_EVENTID) \ + OP(WMI_WLAN_PROFILE_DATA_EVENTID) \ + OP(WMI_PDEV_UTF_EVENTID) \ + OP(WMI_DEBUG_PRINT_EVENTID) \ + OP(WMI_RTT_MEASUREMENT_REPORT_EVENTID) \ + OP(WMI_HOST_SWBA_EVENTID) \ + OP(WMI_UPDATE_STATS_EVENTID) \ + OP(WMI_PDEV_QVIT_EVENTID) \ + OP(WMI_WLAN_FREQ_AVOID_EVENTID) \ + OP(WMI_GTK_REKEY_FAIL_EVENTID) \ + OP(WMI_NLO_MATCH_EVENTID) \ + OP(WMI_NLO_SCAN_COMPLETE_EVENTID) \ + OP(WMI_APFIND_EVENTID) \ + OP(WMI_CHATTER_PC_QUERY_EVENTID) \ + OP(WMI_UPLOADH_EVENTID) \ + OP(WMI_CAPTUREH_EVENTID) \ + OP(WMI_TDLS_PEER_EVENTID) \ + OP(WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID) \ + OP(WMI_BA_RSP_SSN_EVENTID) \ + OP(WMI_OFFLOAD_BCN_TX_STATUS_EVENTID) \ + OP(WMI_P2P_NOA_EVENTID) \ + OP(WMI_TX_PAUSE_EVENTID) \ + OP(WMI_RFKILL_STATE_CHANGE_EVENTID) \ + OP(WMI_PEER_INFO_EVENTID) \ + OP(WMI_PEER_TX_FAIL_CNT_THR_EVENTID) \ + OP(WMI_DFS_RADAR_EVENTID) \ + OP(WMI_BATCH_SCAN_ENABLED_EVENTID) \ + OP(WMI_BATCH_SCAN_RESULT_EVENTID) \ + OP(WMI_THERMAL_MGMT_EVENTID) \ + OP(WMI_NAN_EVENTID) \ + OP(WMI_PDEV_L1SS_TRACK_EVENTID) \ + OP(WMI_DIAG_DATA_CONTAINER_EVENTID) \ + OP(WMI_PEER_ESTIMATED_LINKSPEED_EVENTID) \ + OP(WMI_AGGR_STATE_TRIG_EVENTID) \ + OP(WMI_STATS_EXT_EVENTID) \ + OP(WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID) \ + OP(WMI_HOST_AUTO_SHUTDOWN_EVENTID) \ + OP(WMI_UPDATE_WHAL_MIB_STATS_EVENTID) \ + OP(WMI_IFACE_LINK_STATS_EVENTID) \ + OP(WMI_PEER_LINK_STATS_EVENTID) \ + OP(WMI_RADIO_LINK_STATS_EVENTID) \ + OP(WMI_LPI_RESULT_EVENTID) \ + OP(WMI_PEER_STATE_EVENTID) \ + OP(WMI_EXTSCAN_START_STOP_EVENTID) \ + OP(WMI_EXTSCAN_OPERATION_EVENTID) \ + OP(WMI_EXTSCAN_TABLE_USAGE_EVENTID) \ + OP(WMI_EXTSCAN_CACHED_RESULTS_EVENTID) \ + OP(WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID) \ + OP(WMI_EXTSCAN_HOTLIST_MATCH_EVENTID) \ + OP(WMI_EXTSCAN_CAPABILITIES_EVENTID) \ + OP(WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID) \ + OP(WMI_D0_WOW_DISABLE_ACK_EVENTID) \ + OP(WMI_ROAM_SYNCH_EVENTID) \ + OP(WMI_LPI_STATUS_EVENTID) \ + OP(WMI_LPI_HANDOFF_EVENTID) \ + OP(WMI_UPDATE_VDEV_RATE_STATS_EVENTID) \ + OP(WMI_PDEV_TEMPERATURE_EVENTID) \ + OP(WMI_DIAG_EVENTID) \ + OP(WMI_MDNS_STATS_EVENTID) \ + OP(WMI_PDEV_RESUME_EVENTID) \ + OP(WMI_SAP_OFL_ADD_STA_EVENTID) \ + OP(WMI_SAP_OFL_DEL_STA_EVENTID) \ + OP(WMI_OCB_SET_SCHED_EVENTID) \ + OP(WMI_OCB_SET_CONFIG_RESP_EVENTID) \ + OP(WMI_OCB_GET_TSF_TIMER_RESP_EVENTID) \ + OP(WMI_DCC_GET_STATS_RESP_EVENTID) \ + OP(WMI_DCC_UPDATE_NDL_RESP_EVENTID) \ + OP(WMI_DCC_STATS_EVENTID) \ + OP(WMI_PASSPOINT_MATCH_EVENTID)\ + OP(WMI_VDEV_TSF_REPORT_EVENTID) \ + OP(WMI_UPDATE_FW_MEM_DUMP_EVENTID) \ + OP(WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID) \ + OP(WMI_RSSI_BREACH_EVENTID) \ + OP(WMI_WOW_INITIAL_WAKEUP_EVENTID) \ + OP(WMI_SOC_SET_HW_MODE_RESP_EVENTID) \ + OP(WMI_SOC_HW_MODE_TRANSITION_EVENTID) \ + OP(WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID) \ + OP(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID) \ + OP(WMI_MGMT_TX_COMPLETION_EVENTID) \ + OP(WMI_MAWC_ENABLE_SENSOR_EVENTID) \ + OP(WMI_PEER_ASSOC_CONF_EVENTID) \ + OP(WMI_AP_PS_EGAP_INFO_EVENTID) \ + OP(WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID) \ + OP(WMI_OEM_RESPONSE_EVENTID) \ + OP(WMI_PDEV_UTF_SCPC_EVENTID) \ + OP(WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID) \ + OP(WMI_BPF_CAPABILIY_INFO_EVENTID) \ + OP(WMI_BPF_VDEV_STATS_INFO_EVENTID) \ + OP(WMI_VDEV_DELETE_RESP_EVENTID) \ + OP(WMI_PEER_DELETE_RESP_EVENTID) \ + OP(WMI_PDEV_FIPS_EVENTID) \ + OP(WMI_PDEV_CHANNEL_HOPPING_EVENTID) \ + OP(WMI_PDEV_ANI_CCK_LEVEL_EVENTID) \ + OP(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID) \ + OP(WMI_PDEV_TPC_EVENTID) \ + OP(WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID) \ + OP(WMI_PEER_RATECODE_LIST_EVENTID) \ + OP(WMI_WDS_PEER_EVENTID) \ + OP(WMI_PEER_STA_PS_STATECHG_EVENTID) \ + OP(WMI_INST_RSSI_STATS_EVENTID) \ + OP(WMI_NAN_DISC_IFACE_CREATED_EVENTID) \ + OP(WMI_NAN_DISC_IFACE_DELETED_EVENTID) \ + OP(WMI_NAN_STARTED_CLUSTER_EVENTID) \ + OP(WMI_NAN_JOINED_CLUSTER_EVENTID) \ + OP(WMI_NDI_CAP_RSP_EVENTID) \ + OP(WMI_NDP_INITIATOR_RSP_EVENTID) \ + OP(WMI_NDP_RESPONDER_RSP_EVENTID) \ + OP(WMI_NDP_END_RSP_EVENTID) \ + OP(WMI_NDP_INDICATION_EVENTID) \ + OP(WMI_NDP_CONFIRM_EVENTID) \ + OP(WMI_NDP_END_INDICATION_EVENTID) \ + OP(WMI_PDEV_SET_HW_MODE_RESP_EVENTID) \ + OP(WMI_PDEV_HW_MODE_TRANSITION_EVENTID) \ + OP(WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID) \ + OP(WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID) \ + OP(WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID) \ + OP(WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID) \ + OP(WMI_READ_DATA_FROM_FLASH_EVENTID) \ + OP(WMI_SERVICE_AVAILABLE_EVENTID) \ + OP(WMI_PEER_ANTDIV_INFO_EVENTID) \ + OP(WMI_PDEV_ANTDIV_STATUS_EVENTID) \ + OP(WMI_PDEV_CHIP_POWER_STATS_EVENTID) \ + OP(WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID) \ + OP(WMI_REPORT_STATS_EVENTID) \ + OP(WMI_REPORT_RX_AGGR_FAILURE_EVENTID) \ + OP(WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID) \ + OP(WMI_TBTTOFFSET_EXT_UPDATE_EVENTID) \ + OP(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID) \ + OP(WMI_VDEV_DFS_CAC_COMPLETE_EVENTID) \ + OP(WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID) \ + /* add new EVT_LIST elements above this line */ /* TLV definitions of WMI commands */ /* Init Cmd */ -#define WMITLV_TABLE_WMI_INIT_CMDID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param, wmi_init_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resource_config, wmi_resource_config, resource_config, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_host_memory_chunk, host_mem_chunks, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, wmi_pdev_set_hw_mode_cmd_fixed_param, hw_mode, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_INIT_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param, wmi_init_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resource_config, wmi_resource_config, resource_config, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wlan_host_memory_chunk, host_mem_chunks, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, wmi_pdev_set_hw_mode_cmd_fixed_param, hw_mode, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_band_to_mac, wmi_pdev_band_to_mac, band_to_mac, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID); /* Peer create Cmd */ #define WMITLV_TABLE_WMI_PEER_CREATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID); /* Peer delete Cmd */ #define WMITLV_TABLE_WMI_PEER_DELETE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID); /* Peer flush Cmd*/ #define WMITLV_TABLE_WMI_PEER_FLUSH_TIDS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param, wmi_peer_flush_tids_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param, wmi_peer_flush_tids_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_FLUSH_TIDS_CMDID); /* Peer Set Param Cmd */ #define WMITLV_TABLE_WMI_PEER_SET_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param, wmi_peer_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param, wmi_peer_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SET_PARAM_CMDID); /* STA Powersave Mode Cmd */ #define WMITLV_TABLE_WMI_STA_POWERSAVE_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_powersave_mode_cmd_fixed_param, wmi_sta_powersave_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_powersave_mode_cmd_fixed_param, wmi_sta_powersave_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_POWERSAVE_MODE_CMDID); /* STA Powersave Param Cmd */ #define WMITLV_TABLE_WMI_STA_POWERSAVE_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_powersave_param_cmd_fixed_param, wmi_sta_powersave_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_powersave_param_cmd_fixed_param, wmi_sta_powersave_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_POWERSAVE_PARAM_CMDID); /* STA DTIM PS METHOD Cmd */ #define WMITLV_TABLE_WMI_STA_DTIM_PS_METHOD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param, wmi_sta_dtim_ps_method_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param, wmi_sta_dtim_ps_method_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_DTIM_PS_METHOD_CMDID); /* Pdev Set Reg Domain Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_REGDOMAIN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param, wmi_pdev_set_regdomain_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param, wmi_pdev_set_regdomain_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_REGDOMAIN_CMDID); - /* Peer TID ADD BA Cmd */ #define WMITLV_TABLE_WMI_PEER_TID_ADDBA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_addba_cmd_fixed_param, wmi_peer_tid_addba_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_addba_cmd_fixed_param, wmi_peer_tid_addba_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_ADDBA_CMDID); /* Peer TID DEL BA Cmd */ #define WMITLV_TABLE_WMI_PEER_TID_DELBA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_delba_cmd_fixed_param, wmi_peer_tid_delba_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_delba_cmd_fixed_param, wmi_peer_tid_delba_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_DELBA_CMDID); - /* Peer Req Add BA Ssn for staId/tid pair Cmd */ #define WMITLV_TABLE_WMI_BA_REQ_SSN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_fixed_param, wmi_ba_req_ssn_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_ARRAY_STRUC, wmi_ba_req_ssn, ba_req_ssn_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_fixed_param, wmi_ba_req_ssn_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_ARRAY_STRUC, wmi_ba_req_ssn, ba_req_ssn_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_BA_REQ_SSN_CMDID); - /* PDEV FTM integration Cmd */ #define WMITLV_TABLE_WMI_PDEV_FTM_INTG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ftm_intg_cmd_fixed_param, wmi_ftm_intg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ftm_intg_cmd_fixed_param, wmi_ftm_intg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FTM_INTG_CMDID); /* WOW Wakeup from sleep Cmd */ -#define WMITLV_TABLE_WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param, wmi_wow_hostwakeup_from_sleep_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param, wmi_wow_hostwakeup_from_sleep_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID); /* WOW Enable Cmd */ -#define WMITLV_TABLE_WMI_WOW_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_enable_cmd_fixed_param, wmi_wow_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_ENABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_enable_cmd_fixed_param, wmi_wow_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_ENABLE_CMDID); /* WOW ICMPv6 NA filtering command */ -#define WMITLV_TABLE_WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param, wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param, wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID); /* Remove Bcn Filter Cmd */ #define WMITLV_TABLE_WMI_RMV_BCN_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmv_bcn_filter_cmd_fixed_param, wmi_rmv_bcn_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmv_bcn_filter_cmd_fixed_param, wmi_rmv_bcn_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RMV_BCN_FILTER_CMDID); /** Service bit WMI_SERVICE_ROAM_OFFLOAD for Roaming feature */ /* Roam scan mode Cmd */ #define WMITLV_TABLE_WMI_ROAM_SCAN_MODE(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_mode_fixed_param, wmi_roam_scan_mode_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param, wmi_start_scan_cmd_fixed_param, scan_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_offload_tlv_param, offload_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_11i_offload_tlv_param, offload_11i_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_11r_offload_tlv_param, offload_11r_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ese_offload_tlv_param, offload_ese_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tlv_buf_len_param, assoc_ie_len_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, assoc_ie_buf, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_mode_fixed_param, wmi_roam_scan_mode_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param, wmi_start_scan_cmd_fixed_param, scan_params, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_offload_tlv_param, offload_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_11i_offload_tlv_param, offload_11i_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_11r_offload_tlv_param, offload_11r_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ese_offload_tlv_param, offload_ese_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_tlv_buf_len_param, assoc_ie_len_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, assoc_ie_buf, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_MODE); /* Roam scan Rssi Threshold Cmd */ #define WMITLV_TABLE_WMI_ROAM_SCAN_RSSI_THRESHOLD(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_rssi_threshold_fixed_param, wmi_roam_scan_rssi_threshold_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_scan_extended_threshold_param, extended_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_earlystop_rssi_thres_param, earlystop_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_dense_thres_param, dense_param, WMITLV_SIZE_VAR) + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_roam_scan_rssi_threshold_fixed_param, wmi_roam_scan_rssi_threshold_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_scan_extended_threshold_param, extended_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_earlystop_rssi_thres_param, earlystop_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_dense_thres_param, dense_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_RSSI_THRESHOLD); /* Roam Scan Period Cmd */ #define WMITLV_TABLE_WMI_ROAM_SCAN_PERIOD(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_period_fixed_param, wmi_roam_scan_period_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_period_fixed_param, wmi_roam_scan_period_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_PERIOD); /* Roam scan change Rssi Threshold Cmd */ -#define WMITLV_TABLE_WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_rssi_change_threshold_fixed_param, wmi_roam_scan_rssi_change_threshold_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_rssi_change_threshold_fixed_param, wmi_roam_scan_rssi_change_threshold_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD); - /* Roam Scan Channel list Cmd */ #define WMITLV_TABLE_WMI_ROAM_CHAN_LIST(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_chan_list_fixed_param, wmi_roam_chan_list_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_chan_list_fixed_param, wmi_roam_chan_list_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CHAN_LIST); /* Roam scan mode Cmd */ #define WMITLV_TABLE_WMI_ROAM_SCAN_CMD(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_cmd_fixed_param, wmi_roam_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_cmd_fixed_param, wmi_roam_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_CMD); /* Roam mbo configuration */ -#define WMITLV_TABLE_WMI_ROAM_SET_MBO_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_set_mbo_fixed_param, wmi_roam_set_mbo_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cellular_cap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_supported_operating_class_param, supp_op_class_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, supp_op_class_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mbo_non_preferred_channel_report_param, non_prefer_ch_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, non_prefer_ch_attr, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_ROAM_SET_MBO_PARAM_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_roam_set_mbo_fixed_param, wmi_roam_set_mbo_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cellular_cap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_supported_operating_class_param, supp_op_class_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, supp_op_class_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_mbo_non_preferred_channel_report_param, non_prefer_ch_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, non_prefer_ch_attr, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SET_MBO_PARAM_CMDID); -#define WMITLV_TABLE_WMI_VDEV_PLMREQ_START_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_plmreq_start_cmd_fixed_param, wmi_vdev_plmreq_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_VDEV_PLMREQ_START_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_plmreq_start_cmd_fixed_param, wmi_vdev_plmreq_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PLMREQ_START_CMDID); #define WMITLV_TABLE_WMI_VDEV_PLMREQ_STOP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_plmreq_stop_cmd_fixed_param, wmi_vdev_plmreq_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_plmreq_stop_cmd_fixed_param, wmi_vdev_plmreq_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PLMREQ_STOP_CMDID); + /* Start scan Cmd */ #define WMITLV_TABLE_WMI_START_SCAN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param, wmi_start_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param, wmi_start_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_START_SCAN_CMDID); /* Scan adaptive dwell mode configuration */ -#define WMITLV_TABLE_WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_config_fixed_param, wmi_scan_adaptive_dwell_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_adaptive_dwell_parameters_tlv, param, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_config_fixed_param, wmi_scan_adaptive_dwell_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_adaptive_dwell_parameters_tlv, param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID); /* Start ExtScan Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_START_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_start_cmd_fixed_param, wmi_extscan_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_bucket, bucket_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_bucket_channel, channel_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_start_cmd_fixed_param, wmi_extscan_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_bucket, bucket_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_bucket_channel, channel_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_START_CMDID); /* Stop ExtScan Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_STOP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_stop_cmd_fixed_param, wmi_extscan_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_stop_cmd_fixed_param, wmi_extscan_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_STOP_CMDID); /* Start ExtScan BSSID Monitoring Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param, wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_bssid_param, wlan_change_descriptor_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param, wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_bssid_param, wlan_change_descriptor_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID); +WMITLV_CREATE_PARAM_STRUC + (WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID); /* Start Hot List Monitoring Cmd */ -#define WMITLV_TABLE_WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_monitor_cmd_fixed_param, wmi_extscan_configure_hotlist_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_entry, hotlist, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_monitor_cmd_fixed_param, wmi_extscan_configure_hotlist_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_entry, hotlist, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID); /* Get ExtScan BSSID/RSSI list Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_get_cached_results_cmd_fixed_param, wmi_extscan_get_cached_results_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_get_cached_results_cmd_fixed_param, wmi_extscan_get_cached_results_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID); /* Get ExtScan BSSID monitor results Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_get_wlan_change_results_cmd_fixed_param, wmi_extscan_get_wlan_change_results_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_get_wlan_change_results_cmd_fixed_param, wmi_extscan_get_wlan_change_results_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID); /* Set ExtScan Capabilities Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_SET_CAPABILITIES_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_set_capabilities_cmd_fixed_param, wmi_extscan_set_capabilities_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_cache_capabilities, extscan_cache_capabilities, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_monitor_capabilities, wlan_change_capabilities, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_monitor_capabilities, hotlist_capabilities, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_set_capabilities_cmd_fixed_param, wmi_extscan_set_capabilities_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_cache_capabilities, extscan_cache_capabilities, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_monitor_capabilities, wlan_change_capabilities, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_monitor_capabilities, hotlist_capabilities, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_SET_CAPABILITIES_CMDID); /* Get ExtScan Capabilities Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_GET_CAPABILITIES_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_get_capabilities_cmd_fixed_param, wmi_extscan_get_capabilities_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_get_capabilities_cmd_fixed_param, wmi_extscan_get_capabilities_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_GET_CAPABILITIES_CMDID); /* Start SSID Hot List Monitoring Cmd */ #define WMITLV_TABLE_WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param, wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_ssid_entry, hotlist_ssid, WMITLV_SIZE_VAR) - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param, wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_ssid_entry, hotlist_ssid, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID); /* P2P set vendor ID data Cmd */ #define WMITLV_TABLE_WMI_P2P_SET_VENDOR_IE_DATA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_set_vendor_ie_data_cmd_fixed_param, wmi_p2p_set_vendor_ie_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_set_vendor_ie_data_cmd_fixed_param, wmi_p2p_set_vendor_ie_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_SET_VENDOR_IE_DATA_CMDID); - /* P2P set OppPS parameters Cmd */ #define WMITLV_TABLE_WMI_P2P_SET_OPPPS_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_set_oppps_cmd_fixed_param, wmi_p2p_set_oppps_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_set_oppps_cmd_fixed_param, wmi_p2p_set_oppps_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_SET_OPPPS_PARAM_CMDID); /* P2P set listen offload start parameters Cmd */ -#define WMITLV_TABLE_WMI_P2P_LISTEN_OFFLOAD_START_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_lo_start_cmd_fixed_param, wmi_p2p_lo_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, device_types_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, prob_resp_data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_P2P_LISTEN_OFFLOAD_START_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_p2p_lo_start_cmd_fixed_param, wmi_p2p_lo_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, device_types_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, prob_resp_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_LISTEN_OFFLOAD_START_CMDID); /* P2P set listen offload stop parameters Cmd */ -#define WMITLV_TABLE_WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_lo_stop_cmd_fixed_param, wmi_p2p_lo_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_p2p_lo_stop_cmd_fixed_param, wmi_p2p_lo_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID); /* P2P set listen offload stopped parameters Event */ -#define WMITLV_TABLE_WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_lo_stopped_event_fixed_param, wmi_p2p_lo_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_p2p_lo_stopped_event_fixed_param, wmi_p2p_lo_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID); /* Pdev set channel Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_CHANNEL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CHANNEL_CMDID); /* Echo Cmd */ -#define WMITLV_TABLE_WMI_ECHO_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_echo_cmd_fixed_param, wmi_echo_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_ECHO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_echo_cmd_fixed_param, wmi_echo_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ECHO_CMDID); /* Pdev set wmm params */ #define WMITLV_TABLE_WMI_PDEV_SET_WMM_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_wmm_params_cmd_fixed_param, wmi_pdev_set_wmm_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_be, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_bk, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_vi, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_vo, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_wmm_params_cmd_fixed_param, wmi_pdev_set_wmm_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_be, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_bk, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_vi, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wmm_params, wmi_wmm_params, wmm_params_ac_vo, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID); /* Vdev start request Cmd */ #define WMITLV_TABLE_WMI_VDEV_START_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, noa_descriptors, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, noa_descriptors, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_REQUEST_CMDID); /* Vdev restart request cmd */ #define WMITLV_TABLE_WMI_VDEV_RESTART_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, noa_descriptors, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, noa_descriptors, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_RESTART_REQUEST_CMDID); /* P2P Go set beacon IE cmd */ #define WMITLV_TABLE_WMI_P2P_GO_SET_BEACON_IE(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_go_set_beacon_ie_fixed_param, wmi_p2p_go_set_beacon_ie_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_go_set_beacon_ie_fixed_param, wmi_p2p_go_set_beacon_ie_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_GO_SET_BEACON_IE); /* GTK offload Cmd */ #define WMITLV_TABLE_WMI_GTK_OFFLOAD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param, WMI_GTK_OFFLOAD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param, WMI_GTK_OFFLOAD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_CMDID); /* PMF 11w offload Set SA query cmd */ -#define WMITLV_TABLE_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param, WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, \ + WMITLV_TAG_STRUC_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param, \ + WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param, fixed_param, \ + WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID); /* Scan channel list Cmd */ #define WMITLV_TABLE_WMI_SCAN_CHAN_LIST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param, wmi_scan_chan_list_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, chan_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param, wmi_scan_chan_list_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, chan_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CHAN_LIST_CMDID); /* STA UAPSD Auto trigger Cmd */ #define WMITLV_TABLE_WMI_STA_UAPSD_AUTO_TRIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_cmd_fixed_param, wmi_sta_uapsd_auto_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sta_uapsd_auto_trig_param, ac_param, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_cmd_fixed_param, wmi_sta_uapsd_auto_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sta_uapsd_auto_trig_param, ac_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_STA_UAPSD_AUTO_TRIG_CMDID); /* Probe template Cmd */ #define WMITLV_TABLE_WMI_PRB_TMPL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param, wmi_prb_tmpl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_prb_info, wmi_bcn_prb_info, bcn_prb_info, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param, wmi_prb_tmpl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_prb_info, wmi_bcn_prb_info, bcn_prb_info, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PRB_TMPL_CMDID); /* Beacon template Cmd */ #define WMITLV_TABLE_WMI_BCN_TMPL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_tmpl_cmd_fixed_param, wmi_bcn_tmpl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_prb_info, wmi_bcn_prb_info, bcn_prb_info, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_tmpl_cmd_fixed_param, wmi_bcn_tmpl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_prb_info, wmi_bcn_prb_info, bcn_prb_info, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_BCN_TMPL_CMDID); /* VDEV install key complete Cmd */ #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_CMDID); - /* VDEV WNM SLEEP MODE Cmd */ #define WMITLV_TABLE_WMI_VDEV_WNM_SLEEPMODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_WNM_SLEEPMODE_CMDID); #define WMITLV_TABLE_WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param, WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param, WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID); /* Peer Assoc Cmd */ #define WMITLV_TABLE_WMI_PEER_ASSOC_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_vht_rates, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_legacy_rates, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_ht_rates, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_vht_rates, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID); /* Peer Set Rate Report Condition Cmd */ -#define WMITLV_TABLE_WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, wmi_peer_set_rate_report_condition_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, wmi_peer_set_rate_report_condition_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID); /* Add Beacon filter Cmd */ #define WMITLV_TABLE_WMI_ADD_BCN_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_add_bcn_filter_cmd_fixed_param, wmi_add_bcn_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ie_map, WMITLV_SIZE_FIX, BCN_FLT_MAX_ELEMS_IE_LIST) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_add_bcn_filter_cmd_fixed_param, wmi_add_bcn_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ie_map, WMITLV_SIZE_FIX, BCN_FLT_MAX_ELEMS_IE_LIST) WMITLV_CREATE_PARAM_STRUC(WMI_ADD_BCN_FILTER_CMDID); /* Sta keepalive cmd */ -#define WMITLV_TABLE_WMI_STA_KEEPALIVE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_STA_KEEPALIVE_CMD_fixed_param, WMI_STA_KEEPALIVE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_STA_KEEPALVE_ARP_RESPONSE, WMI_STA_KEEPALVE_ARP_RESPONSE, arp_resp, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_STA_KEEPALIVE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_STA_KEEPALIVE_CMD_fixed_param, WMI_STA_KEEPALIVE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_STA_KEEPALVE_ARP_RESPONSE, WMI_STA_KEEPALVE_ARP_RESPONSE, arp_resp, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_KEEPALIVE_CMDID); /* ARP NS offload Cmd */ #define WMITLV_TABLE_WMI_SET_ARP_NS_OFFLOAD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param, WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_NS_OFFLOAD_TUPLE, ns_tuples, WMITLV_SIZE_FIX, WMI_MAX_NS_OFFLOADS) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_ARP_OFFLOAD_TUPLE, arp_tuples, WMITLV_SIZE_FIX, WMI_MAX_ARP_OFFLOADS) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_NS_OFFLOAD_TUPLE, ns_ext_tuples, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param, WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_NS_OFFLOAD_TUPLE, ns_tuples, WMITLV_SIZE_FIX, WMI_MAX_NS_OFFLOADS) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_ARP_OFFLOAD_TUPLE, arp_tuples, WMITLV_SIZE_FIX, WMI_MAX_ARP_OFFLOADS) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_NS_OFFLOAD_TUPLE, ns_ext_tuples, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SET_ARP_NS_OFFLOAD_CMDID); /* AP PS peer param Cmd */ #define WMITLV_TABLE_WMI_AP_PS_PEER_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_ps_peer_cmd_fixed_param, wmi_ap_ps_peer_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_ps_peer_cmd_fixed_param, wmi_ap_ps_peer_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_AP_PS_PEER_PARAM_CMDID); /* AP PS enhanced green ap param Cmd */ -#define WMITLV_TABLE_WMI_AP_PS_EGAP_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_ps_egap_param_cmd_fixed_param, wmi_ap_ps_egap_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_AP_PS_EGAP_PARAM_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len,\ + WMITLV_TAG_STRUC_wmi_ap_ps_egap_param_cmd_fixed_param,\ + wmi_ap_ps_egap_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_AP_PS_EGAP_PARAM_CMDID); /* Profile Trigger Cmd */ #define WMITLV_TABLE_WMI_WLAN_PROFILE_TRIGGER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_trigger_cmd_fixed_param, wmi_wlan_profile_trigger_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_trigger_cmd_fixed_param, wmi_wlan_profile_trigger_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_PROFILE_TRIGGER_CMDID); /* WLAN Profile set hist interval Cmd */ #define WMITLV_TABLE_WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_set_hist_intvl_cmd_fixed_param, wmi_wlan_profile_set_hist_intvl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_set_hist_intvl_cmd_fixed_param, wmi_wlan_profile_set_hist_intvl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID); /* WLAN Profile get profile data Cmd */ #define WMITLV_TABLE_WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_get_prof_data_cmd_fixed_param, wmi_wlan_profile_get_prof_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_get_prof_data_cmd_fixed_param, wmi_wlan_profile_get_prof_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID); /* WLAN Profile enable profile ID Cmd */ #define WMITLV_TABLE_WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_enable_profile_id_cmd_fixed_param, wmi_wlan_profile_enable_profile_id_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_enable_profile_id_cmd_fixed_param, wmi_wlan_profile_enable_profile_id_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID); /* WOW Delete Wake Pattern Cmd */ #define WMITLV_TABLE_WMI_WOW_DEL_WAKE_PATTERN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_DEL_PATTERN_CMD_fixed_param, WMI_WOW_DEL_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_DEL_PATTERN_CMD_fixed_param, WMI_WOW_DEL_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_DEL_WAKE_PATTERN_CMDID); -#define WMITLV_TABLE_WMI_WOW_UDP_SVC_OFLD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param, WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, pattern, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, response, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_WOW_UDP_SVC_OFLD_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param, WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, pattern, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, response, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_UDP_SVC_OFLD_CMDID); -#define WMITLV_TABLE_WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_hostwakeup_gpio_pin_pattern_config_cmd_fixed_param, WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len,\ + WMITLV_TAG_STRUC_wmi_wow_hostwakeup_gpio_pin_pattern_config_cmd_fixed_param,\ + WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD_fixed_param, fixed_param,\ + WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID); -#define WMITLV_TABLE_WMI_WOW_SET_ACTION_WAKE_UP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wow_set_action_wake_up_cmd_fixed_param, WMI_WOW_SET_ACTION_WAKE_UP_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_SET_ACTION_WAKE_UP_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_wow_set_action_wake_up_cmd_fixed_param, WMI_WOW_SET_ACTION_WAKE_UP_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_SET_ACTION_WAKE_UP_CMDID); /* Wow enable/disable wake up Cmd */ #define WMITLV_TABLE_WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_ADD_DEL_EVT_CMD_fixed_param, WMI_WOW_ADD_DEL_EVT_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_ADD_DEL_EVT_CMD_fixed_param, WMI_WOW_ADD_DEL_EVT_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID); /* RTT measurement request Cmd */ #define WMITLV_TABLE_WMI_RTT_MEASREQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) - - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RTT_MEASREQ_CMDID); /* RTT TSF Cmd */ #define WMITLV_TABLE_WMI_RTT_TSF_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RTT_TSF_CMDID); /* RTT OEM req Cmd */ #define WMITLV_TABLE_WMI_OEM_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_REQ_CMDID); /* RTT OEM request Cmd - DEPRECATED */ -#define WMITLV_TABLE_WMI_OEM_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) - +#define WMITLV_TABLE_WMI_OEM_REQUEST_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_REQUEST_CMDID); /* Spectral scan configure Cmd */ #define WMITLV_TABLE_WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_spectral_configure_cmd_fixed_param, wmi_vdev_spectral_configure_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_spectral_configure_cmd_fixed_param, wmi_vdev_spectral_configure_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID); /* Spectral scan enable Cmd */ -#define WMITLV_TABLE_WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_spectral_enable_cmd_fixed_param, wmi_vdev_spectral_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_spectral_enable_cmd_fixed_param, wmi_vdev_spectral_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID); /* Request stats Cmd */ #define WMITLV_TABLE_WMI_REQUEST_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param, wmi_request_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param, wmi_request_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_STATS_CMDID); -/* Request for memory dump stats Cmd */ +/* flush debug messages */ #define WMITLV_TABLE_WMI_GET_FW_MEM_DUMP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param, wmi_get_fw_mem_dump_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_fw_mem_dump, fw_mem_dump_params, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param, wmi_get_fw_mem_dump_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_fw_mem_dump,fw_mem_dump_params, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_GET_FW_MEM_DUMP_CMDID); -/* flush debug messages */ -#define WMITLV_TABLE_WMI_DEBUG_MESG_FLUSH_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_debug_mesg_flush_fixed_param, wmi_debug_mesg_flush_fixed_param, fixed_param, WMITLV_SIZE_FIX) +/* Request for memory dump stats Cmd */ +#define WMITLV_TABLE_WMI_DEBUG_MESG_FLUSH_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_debug_mesg_flush_fixed_param, wmi_debug_mesg_flush_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DEBUG_MESG_FLUSH_CMDID); -/* Request to config the DIAG Events and LOGs*/ -#define WMITLV_TABLE_WMI_DIAG_EVENT_LOG_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_diag_event_log_config_fixed_param, wmi_diag_event_log_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, diag_events_logs_list, WMITLV_SIZE_VAR) +/* Request to config the DIAG Events and LOGs */ +#define WMITLV_TABLE_WMI_DIAG_EVENT_LOG_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_diag_event_log_config_fixed_param, wmi_diag_event_log_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, diag_events_logs_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENT_LOG_CONFIG_CMDID); /* Set config params */ #define WMITLV_TABLE_WMI_START_LINK_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_start_link_stats_cmd_fixed_param, wmi_start_link_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_start_link_stats_cmd_fixed_param, wmi_start_link_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_START_LINK_STATS_CMDID); /* Request to clear link stats */ #define WMITLV_TABLE_WMI_CLEAR_LINK_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param, wmi_clear_link_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param, wmi_clear_link_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CLEAR_LINK_STATS_CMDID); -/* Request stats Cmd */ +/* Request Link stats Cmd */ #define WMITLV_TABLE_WMI_REQUEST_LINK_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_link_stats_cmd_fixed_param, wmi_request_link_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_link_stats_cmd_fixed_param, wmi_request_link_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_LINK_STATS_CMDID); /* Network list offload config Cmd */ #define WMITLV_TABLE_WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, wmi_nlo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, nlo_configured_parameters, nlo_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, nlo_channel_prediction_cfg, channel_prediction_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_enlo_candidate_score_param, enlo_candidate_score_params, candidate_score_params, WMITLV_SIZE_FIX) + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, wmi_nlo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, nlo_configured_parameters, nlo_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, nlo_channel_prediction_cfg, channel_prediction_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_enlo_candidate_score_param, enlo_candidate_score_params, candidate_score_params, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID); /* Passpoint list offload config Cmd */ #define WMITLV_TABLE_WMI_PASSPOINT_LIST_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_passpoint_config_cmd_fixed_param, wmi_passpoint_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - + WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_passpoint_config_cmd_fixed_param, wmi_passpoint_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PASSPOINT_LIST_CONFIG_CMDID); /* CSA offload enable Cmd */ #define WMITLV_TABLE_WMI_CSA_OFFLOAD_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_offload_enable_cmd_fixed_param, wmi_csa_offload_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_offload_enable_cmd_fixed_param, wmi_csa_offload_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CSA_OFFLOAD_ENABLE_CMDID); /* CSA offload channel switch Cmd */ #define WMITLV_TABLE_WMI_CSA_OFFLOAD_CHANSWITCH_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_offload_chanswitch_cmd_fixed_param, wmi_csa_offload_chanswitch_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_offload_chanswitch_cmd_fixed_param, wmi_csa_offload_chanswitch_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CSA_OFFLOAD_CHANSWITCH_CMDID); /* Chatter set mode Cmd */ #define WMITLV_TABLE_WMI_CHATTER_SET_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_set_mode_cmd_fixed_param, wmi_chatter_set_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_set_mode_cmd_fixed_param, wmi_chatter_set_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CHATTER_SET_MODE_CMDID); - /* PDEV UTF Cmd */ -#define WMITLV_TABLE_WMI_PDEV_UTF_CMDID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_UTF_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UTF_CMDID); /* PDEV QVIT Cmd */ -#define WMITLV_TABLE_WMI_PDEV_QVIT_CMDID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_QVIT_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_QVIT_CMDID); -#define WMITLV_TABLE_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param, WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param, WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WAKEUP_CONFIG_CMDID); /* Vdev Set keep alive Cmd */ -#define WMITLV_TABLE_WMI_VDEV_SET_KEEPALIVE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_keepalive_cmd_fixed_param, wmi_vdev_set_keepalive_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_SET_KEEPALIVE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_keepalive_cmd_fixed_param, wmi_vdev_set_keepalive_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_KEEPALIVE_CMDID); /* Vdev Get keep alive Cmd */ #define WMITLV_TABLE_WMI_VDEV_GET_KEEPALIVE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_cmd_fixed_param, wmi_vdev_get_keepalive_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_cmd_fixed_param, wmi_vdev_get_keepalive_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_KEEPALIVE_CMDID); - /*FWTEST Set TBTT mode Cmd*/ #define WMITLV_TABLE_WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param, wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param, wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID); /* FWTEST set NoA parameters Cmd */ #define WMITLV_TABLE_WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_set_noa_cmd_fixed_param, wmi_p2p_set_noa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, noa_descriptor, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_set_noa_cmd_fixed_param, wmi_p2p_set_noa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, noa_descriptor, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID); /* Unit test FW */ -#define WMITLV_TABLE_WMI_UNIT_TEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_unit_test_cmd_fixed_param, wmi_unit_test_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, args, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_UNIT_TEST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_unit_test_cmd_fixed_param, wmi_unit_test_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, args, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_UNIT_TEST_CMDID); /* Force Fw Hang Cmd */ #define WMITLV_TABLE_WMI_FORCE_FW_HANG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_FORCE_FW_HANG_CMD_fixed_param, WMI_FORCE_FW_HANG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_FORCE_FW_HANG_CMD_fixed_param, WMI_FORCE_FW_HANG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_FORCE_FW_HANG_CMDID); - /* Set Mcast address Cmd */ #define WMITLV_TABLE_WMI_SET_MCASTBCAST_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param, WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param, WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SET_MCASTBCAST_FILTER_CMDID); /* Enhanced Mcast add/delete filter list cmd */ -#define WMITLV_TABLE_WMI_SET_MULTIPLE_MCAST_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_set_multiple_mcast_filter_cmd_fixed_param, WMI_SET_MULTIPLE_MCAST_FILTER_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mcast_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SET_MULTIPLE_MCAST_FILTER_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_set_multiple_mcast_filter_cmd_fixed_param, WMI_SET_MULTIPLE_MCAST_FILTER_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mcast_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SET_MULTIPLE_MCAST_FILTER_CMDID); /* Set dbglog time stamp sync cmd */ -#define WMITLV_TABLE_WMI_DBGLOG_TIME_STAMP_SYNC_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dbglog_time_stamp_sync_cmd_fixed_param, WMI_DBGLOG_TIME_STAMP_SYNC_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_DBGLOG_TIME_STAMP_SYNC_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_dbglog_time_stamp_sync_cmd_fixed_param, WMI_DBGLOG_TIME_STAMP_SYNC_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DBGLOG_TIME_STAMP_SYNC_CMDID); /* GPIO config Cmd */ #define WMITLV_TABLE_WMI_GPIO_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_config_cmd_fixed_param, wmi_gpio_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_config_cmd_fixed_param, wmi_gpio_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_CONFIG_CMDID); /* GPIO output Cmd */ #define WMITLV_TABLE_WMI_GPIO_OUTPUT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, wmi_gpio_output_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, wmi_gpio_output_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_OUTPUT_CMDID); /* Peer add WDA entry Cmd */ #define WMITLV_TABLE_WMI_PEER_ADD_WDS_ENTRY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_add_wds_entry_cmd_fixed_param, wmi_peer_add_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_add_wds_entry_cmd_fixed_param, wmi_peer_add_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ADD_WDS_ENTRY_CMDID); /*Peer remove WDS entry Cmd */ #define WMITLV_TABLE_WMI_PEER_REMOVE_WDS_ENTRY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param, wmi_peer_remove_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param, wmi_peer_remove_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REMOVE_WDS_ENTRY_CMDID); /* Beacon tx Cmd */ -#define WMITLV_TABLE_WMI_BCN_TX_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_tx_hdr, wmi_bcn_tx_hdr, hdr, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_BCN_TX_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_tx_hdr, wmi_bcn_tx_hdr, hdr, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_BCN_TX_CMDID); /* PDEV send Beacon Cmd */ #define WMITLV_TABLE_WMI_PDEV_SEND_BCN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_send_from_host_cmd_fixed_param, wmi_bcn_send_from_host_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_send_from_host_cmd_fixed_param, wmi_bcn_send_from_host_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SEND_BCN_CMDID); /* Management tx Cmd */ -#define WMITLV_TABLE_WMI_MGMT_TX_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_hdr, wmi_mgmt_tx_hdr, hdr, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_MGMT_TX_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_hdr, wmi_mgmt_tx_hdr, hdr, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_CMDID); /* Management tx send cmd */ -#define WMITLV_TABLE_WMI_MGMT_TX_SEND_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param, wmi_mgmt_tx_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) - +#define WMITLV_TABLE_WMI_MGMT_TX_SEND_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param, wmi_mgmt_tx_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_SEND_CMDID); /* ADD clear response Cmd */ #define WMITLV_TABLE_WMI_ADDBA_CLEAR_RESP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_addba_clear_resp_cmd_fixed_param, wmi_addba_clear_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_addba_clear_resp_cmd_fixed_param, wmi_addba_clear_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ADDBA_CLEAR_RESP_CMDID); /* ADD BA send Cmd */ #define WMITLV_TABLE_WMI_ADDBA_SEND_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_addba_send_cmd_fixed_param, wmi_addba_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_addba_send_cmd_fixed_param, wmi_addba_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ADDBA_SEND_CMDID); /* DEL BA send Cmd */ #define WMITLV_TABLE_WMI_DELBA_SEND_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_delba_send_cmd_fixed_param, wmi_delba_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_delba_send_cmd_fixed_param, wmi_delba_send_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DELBA_SEND_CMDID); /* ADD BA set response Cmd */ #define WMITLV_TABLE_WMI_ADDBA_SET_RESP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_addba_setresponse_cmd_fixed_param, wmi_addba_setresponse_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_addba_setresponse_cmd_fixed_param, wmi_addba_setresponse_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ADDBA_SET_RESP_CMDID); /* Send single AMSDU Cmd */ #define WMITLV_TABLE_WMI_SEND_SINGLEAMSDU_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_send_singleamsdu_cmd_fixed_param, wmi_send_singleamsdu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_send_singleamsdu_cmd_fixed_param, wmi_send_singleamsdu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SEND_SINGLEAMSDU_CMDID); /* PDev Packet Log enable Cmd */ #define WMITLV_TABLE_WMI_PDEV_PKTLOG_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param, wmi_pdev_pktlog_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param, wmi_pdev_pktlog_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_PKTLOG_ENABLE_CMDID); /* PDev Packet Log disable Cmd */ #define WMITLV_TABLE_WMI_PDEV_PKTLOG_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_disable_cmd_fixed_param, wmi_pdev_pktlog_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_disable_cmd_fixed_param, wmi_pdev_pktlog_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_PKTLOG_DISABLE_CMDID); /* PDev set HT Cap IE Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_HT_CAP_IE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_ht_ie_cmd_fixed_param, wmi_pdev_set_ht_ie_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_ht_ie_cmd_fixed_param, wmi_pdev_set_ht_ie_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_HT_CAP_IE_CMDID); /* PDev set VHT Cap IE Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_VHT_CAP_IE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_vht_ie_cmd_fixed_param, wmi_pdev_set_vht_ie_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_vht_ie_cmd_fixed_param, wmi_pdev_set_vht_ie_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_VHT_CAP_IE_CMDID); /* PDev Set DSCP to TID map Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_DSCP_TID_MAP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param, wmi_pdev_set_dscp_tid_map_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param, wmi_pdev_set_dscp_tid_map_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_DSCP_TID_MAP_CMDID); /* PDev Green AP PS enable Cmd */ #define WMITLV_TABLE_WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_green_ap_ps_enable_cmd_fixed_param, wmi_pdev_green_ap_ps_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_green_ap_ps_enable_cmd_fixed_param, wmi_pdev_green_ap_ps_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID); /* PDEV Get TPC Config Cmd */ #define WMITLV_TABLE_WMI_PDEV_GET_TPC_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_tpc_config_cmd_fixed_param, wmi_pdev_get_tpc_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_tpc_config_cmd_fixed_param, wmi_pdev_get_tpc_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_CONFIG_CMDID); /* PDEV Set Base Mac Address Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_BASE_MACADDR_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param, wmi_pdev_set_base_macaddr_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param, wmi_pdev_set_base_macaddr_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_BASE_MACADDR_CMDID); /* MIB Stats*/ -#define WMITLV_TABLE_WMI_MIB_STATS_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param, wmi_mib_stats_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_MIB_STATS_ENABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param, wmi_mib_stats_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MIB_STATS_ENABLE_CMDID); /* Peer multicast group Cmd */ #define WMITLV_TABLE_WMI_PEER_MCAST_GROUP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_mcast_group_cmd_fixed_param, wmi_peer_mcast_group_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_mcast_group_cmd_fixed_param, wmi_peer_mcast_group_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_MCAST_GROUP_CMDID); /* Roam AP profile Cmd */ -#define WMITLV_TABLE_WMI_ROAM_AP_PROFILE(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param, wmi_roam_ap_profile_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_profile, wmi_ap_profile, ap_profile, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_ROAM_AP_PROFILE(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param, wmi_roam_ap_profile_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_profile, wmi_ap_profile, ap_profile, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE); /* Roam sync complete Cmd */ #define WMITLV_TABLE_WMI_ROAM_SYNCH_COMPLETE(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_COMPLETE); #define WMITLV_TABLE_WMI_ROAM_SET_RIC_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ric_request_fixed_param, wmi_ric_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ric_tspec, ric_tspec_list, WMITLV_SIZE_VAR) - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ric_request_fixed_param, wmi_ric_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ric_tspec, ric_tspec_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SET_RIC_REQUEST_CMDID); /* Scan scheduler priority Table Cmd */ -#define WMITLV_TABLE_WMI_SCAN_SCH_PRIO_TBL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_sch_priority_table_cmd_fixed_param, wmi_scan_sch_priority_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, mapping_table, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SCAN_SCH_PRIO_TBL_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_sch_priority_table_cmd_fixed_param, wmi_scan_sch_priority_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, mapping_table, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_SCH_PRIO_TBL_CMDID); /* PDEV DFS enable Cmd */ #define WMITLV_TABLE_WMI_PDEV_DFS_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_enable_cmd_fixed_param, wmi_pdev_dfs_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_enable_cmd_fixed_param, wmi_pdev_dfs_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_ENABLE_CMDID); /* PDEV DFS disable Cmd */ #define WMITLV_TABLE_WMI_PDEV_DFS_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_disable_cmd_fixed_param, wmi_pdev_dfs_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_disable_cmd_fixed_param, wmi_pdev_dfs_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_DISABLE_CMDID); /* DFS phyerr parse/filter offload enable Cmd */ #define WMITLV_TABLE_WMI_DFS_PHYERR_FILTER_ENA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_ena_cmd_fixed_param, wmi_dfs_phyerr_filter_ena_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_ena_cmd_fixed_param, wmi_dfs_phyerr_filter_ena_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DFS_PHYERR_FILTER_ENA_CMDID); /* DFS phyerr parse/filter offload disable Cmd */ #define WMITLV_TABLE_WMI_DFS_PHYERR_FILTER_DIS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_dis_cmd_fixed_param, wmi_dfs_phyerr_filter_dis_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_dis_cmd_fixed_param, wmi_dfs_phyerr_filter_dis_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DFS_PHYERR_FILTER_DIS_CMDID); +/* DFS phyerr processing offload enable cmd */ +#define WMITLV_TABLE_WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_dfs_phyerr_offload_enable_cmd_fixed_param, wmi_pdev_dfs_phyerr_offload_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID); + +/* DFS phyerr processing offload disble cmd */ +#define WMITLV_TABLE_WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID); + +/* set ADFS channel config cmd */ +#define WMITLV_TABLE_WMI_VDEV_ADFS_CH_CFG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_adfs_ch_cfg_cmd_fixed_param, wmi_vdev_adfs_ch_cfg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ADFS_CH_CFG_CMDID); + +/* DFS abort ADFS ocac currently in progress */ +#define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_ABORT_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_adfs_ocac_abort_cmd_fixed_param, wmi_vdev_adfs_ocac_abort_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ADFS_OCAC_ABORT_CMDID); + /* WOW Add Wake Pattern Cmd */ #define WMITLV_TABLE_WMI_WOW_ADD_WAKE_PATTERN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_ADD_PATTERN_CMD_fixed_param, WMI_WOW_ADD_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_BITMAP_PATTERN_T, pattern_info_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IPV4_SYNC_PATTERN_T, pattern_info_ipv4, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IPV6_SYNC_PATTERN_T, pattern_info_ipv6, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_MAGIC_PATTERN_CMD, pattern_info_magic_pattern, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pattern_info_timeout, WMITLV_SIZE_VAR) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ra_ratelimit_interval, WMITLV_SIZE_FIX, 1) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_ADD_PATTERN_CMD_fixed_param, WMI_WOW_ADD_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_BITMAP_PATTERN_T, pattern_info_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IPV4_SYNC_PATTERN_T, pattern_info_ipv4, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IPV6_SYNC_PATTERN_T, pattern_info_ipv6, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_MAGIC_PATTERN_CMD, pattern_info_magic_pattern, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pattern_info_timeout, WMITLV_SIZE_VAR) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ra_ratelimit_interval, WMITLV_SIZE_FIX, 1) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_ADD_WAKE_PATTERN_CMDID); /* IOAC add keep alive cmd. */ #define WMITLV_TABLE_WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param, WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_WOW_IOAC_KEEPALIVE_T, keepalive_set, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param, WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_WOW_IOAC_KEEPALIVE_T, keepalive_set, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID); /* IOAC del keep alive cmd. */ #define WMITLV_TABLE_WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param, WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param, WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID); /* WOW IOAC Add Wake Pattern Cmd */ -#define WMITLV_TABLE_WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param, WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IOAC_PKT_PATTERN_T, pattern_info_pkt, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IOAC_TMR_PATTERN_T, pattern_info_tmr, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_IOAC_SOCK_PATTERN_T, pattern_info_sock, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param, WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, WOW_IOAC_PKT_PATTERN_T, pattern_info_pkt, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, WOW_IOAC_TMR_PATTERN_T, pattern_info_tmr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, WOW_IOAC_SOCK_PATTERN_T, pattern_info_sock, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID); /* WOW IOAC Delete Wake Pattern Cmd */ -#define WMITLV_TABLE_WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param, WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param, WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID); /* extwow enable Cmd */ #define WMITLV_TABLE_WMI_EXTWOW_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extwow_enable_cmd_fixed_param, wmi_extwow_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extwow_enable_cmd_fixed_param, wmi_extwow_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTWOW_ENABLE_CMDID); /* extwow set wakeup params cmd for app type1 */ #define WMITLV_TABLE_WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extwow_set_app_type1_params_cmd_fixed_param, wmi_extwow_set_app_type1_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extwow_set_app_type1_params_cmd_fixed_param, wmi_extwow_set_app_type1_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID); /* extwow set wakeup params cmd for app type2 */ #define WMITLV_TABLE_WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extwow_set_app_type2_params_cmd_fixed_param, wmi_extwow_set_app_type2_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extwow_set_app_type2_params_cmd_fixed_param, wmi_extwow_set_app_type2_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID); /* Stop scan Cmd */ -#define WMITLV_TABLE_WMI_STOP_SCAN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param, wmi_stop_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_STOP_SCAN_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param, wmi_stop_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STOP_SCAN_CMDID); #define WMITLV_TABLE_WMI_PDEV_SET_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param, wmi_pdev_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param, wmi_pdev_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_PARAM_CMDID); /* PDev set quiet Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_QUIET_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_quiet_cmd_fixed_param, wmi_pdev_set_quiet_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_quiet_cmd_fixed_param, wmi_pdev_set_quiet_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_QUIET_MODE_CMDID); /* VDev set quiet Cmd */ -#define WMITLV_TABLE_WMI_VDEV_SET_QUIET_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_quiet_cmd_fixed_param, wmi_vdev_set_quiet_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_SET_QUIET_MODE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_quiet_cmd_fixed_param, wmi_vdev_set_quiet_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_QUIET_MODE_CMDID); /* Setting custom aggregation size using command */ -#define WMITLV_TABLE_WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param, wmi_vdev_set_custom_aggr_size_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param, wmi_vdev_set_custom_aggr_size_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID); /* Vdev create Cmd */ -#define WMITLV_TABLE_WMI_VDEV_CREATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, wmi_vdev_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_txrx_streams, cfg_txrx_streams, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_VDEV_CREATE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, wmi_vdev_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_txrx_streams, cfg_txrx_streams, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CREATE_CMDID); /* Vdev delete Cmd */ #define WMITLV_TABLE_WMI_VDEV_DELETE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_delete_cmd_fixed_param, wmi_vdev_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_delete_cmd_fixed_param, wmi_vdev_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_CMDID); /* Vdev up Cmd */ -#define WMITLV_TABLE_WMI_VDEV_UP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_UP_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UP_CMDID); /* Vdev stop cmd */ -#define WMITLV_TABLE_WMI_VDEV_STOP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_STOP_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOP_CMDID); /* Vdev down Cmd */ -#define WMITLV_TABLE_WMI_VDEV_DOWN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_DOWN_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DOWN_CMDID); /* Vdev set param Cmd */ #define WMITLV_TABLE_WMI_VDEV_SET_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_param_cmd_fixed_param, wmi_vdev_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_param_cmd_fixed_param, wmi_vdev_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_PARAM_CMDID); /* Pdev suspend Cmd */ -#define WMITLV_TABLE_WMI_PDEV_SUSPEND_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param, wmi_pdev_suspend_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SUSPEND_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param, wmi_pdev_suspend_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SUSPEND_CMDID); /* Pdev Resume Cmd */ -#define WMITLV_TABLE_WMI_PDEV_RESUME_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_resume_cmd_fixed_param, wmi_pdev_resume_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_RESUME_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_resume_cmd_fixed_param, wmi_pdev_resume_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_CMDID); #define WMITLV_TABLE_WMI_SCAN_UPDATE_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_scan_update_request_cmd_fixed_param, wmi_scan_update_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_scan_update_request_cmd_fixed_param, wmi_scan_update_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_UPDATE_REQUEST_CMDID); -#define WMITLV_TABLE_WMI_SCAN_PROB_REQ_OUI_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, wmi_scan_prob_req_oui_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SCAN_PROB_REQ_OUI_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, wmi_scan_prob_req_oui_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_PROB_REQ_OUI_CMDID); #define WMITLV_TABLE_WMI_CHATTER_ADD_COALESCING_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, wmi_chatter_coalescing_add_filter_cmd_fixed_param, fixed_param,WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, chatter_pkt_coalescing_filter, coalescing_filter, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, wmi_chatter_coalescing_add_filter_cmd_fixed_param, fixed_param,WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, chatter_pkt_coalescing_filter, coalescing_filter, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CHATTER_ADD_COALESCING_FILTER_CMDID); #define WMITLV_TABLE_WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_coalescing_delete_filter_cmd_fixed_param,wmi_chatter_coalescing_delete_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_coalescing_delete_filter_cmd_fixed_param,wmi_chatter_coalescing_delete_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_CREATE_PARAM_STRUC(WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID); #define WMITLV_TABLE_WMI_CHATTER_COALESCING_QUERY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_coalescing_query_cmd_fixed_param, wmi_chatter_coalescing_query_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_coalescing_query_cmd_fixed_param, wmi_chatter_coalescing_query_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_CREATE_PARAM_STRUC(WMI_CHATTER_COALESCING_QUERY_CMDID); #define WMITLV_TABLE_WMI_TXBF_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_txbf_cmd_fixed_param, wmi_txbf_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_txbf_cmd_fixed_param, wmi_txbf_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_CREATE_PARAM_STRUC(WMI_TXBF_CMDID); #define WMITLV_TABLE_WMI_DBGLOG_CFG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_debug_log_config_cmd_fixed_param, wmi_debug_log_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_FXAR(id,op,buf,len,WMITLV_TAG_ARRAY_UINT32, A_UINT32, module_id_bitmap, WMITLV_SIZE_FIX, MAX_MODULE_ID_BITMAP_WORDS) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_debug_log_config_cmd_fixed_param, wmi_debug_log_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_FXAR(id,op,buf,len,WMITLV_TAG_ARRAY_UINT32, A_UINT32, module_id_bitmap, WMITLV_SIZE_FIX, MAX_MODULE_ID_BITMAP_WORDS) \ WMITLV_CREATE_PARAM_STRUC(WMI_DBGLOG_CFG_CMDID); -#define WMITLV_TABLE_WMI_VDEV_WMM_ADDTS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_wmm_addts_cmd_fixed_param, wmi_vdev_wmm_addts_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_WMM_ADDTS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_wmm_addts_cmd_fixed_param, wmi_vdev_wmm_addts_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_WMM_ADDTS_CMDID); -#define WMITLV_TABLE_WMI_VDEV_WMM_DELTS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_wmm_delts_cmd_fixed_param, wmi_vdev_wmm_delts_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_WMM_DELTS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_wmm_delts_cmd_fixed_param, wmi_vdev_wmm_delts_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_WMM_DELTS_CMDID); -#define WMITLV_TABLE_WMI_VDEV_SET_WMM_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_wmm_params_cmd_fixed_param, wmi_vdev_set_wmm_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_SET_WMM_PARAMS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_wmm_params_cmd_fixed_param, wmi_vdev_set_wmm_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_WMM_PARAMS_CMDID); -#define WMITLV_TABLE_WMI_VDEV_SET_GTX_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_gtx_params_cmd_fixed_param, wmi_vdev_set_gtx_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_SET_GTX_PARAMS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_gtx_params_cmd_fixed_param, wmi_vdev_set_gtx_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_GTX_PARAMS_CMDID); /* TDLS Enable/Disable Cmd */ #define WMITLV_TABLE_WMI_TDLS_SET_STATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_state_cmd_fixed_param, \ - wmi_tdls_set_state_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_state_cmd_fixed_param, \ + wmi_tdls_set_state_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_SET_STATE_CMDID); /* TDLS Peer Update Cmd */ #define WMITLV_TABLE_WMI_TDLS_PEER_UPDATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param, wmi_tdls_peer_update_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_peer_capabilities, wmi_tdls_peer_capabilities, peer_caps, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, peer_chan_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param, wmi_tdls_peer_update_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_peer_capabilities, wmi_tdls_peer_capabilities, peer_caps, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, peer_chan_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_PEER_UPDATE_CMDID); /* Enable/Disable TDLS Offchannel Cmd */ #define WMITLV_TABLE_WMI_TDLS_SET_OFFCHAN_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, \ - wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, \ + wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_SET_OFFCHAN_MODE_CMDID); - /* Resmgr Enable/Disable Adaptive OCS CMD */ #define WMITLV_TABLE_WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param, \ - wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param, \ + wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID); +WMITLV_CREATE_PARAM_STRUC + (WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID); /* Resmgr Set Channel Time Quota CMD */ #define WMITLV_TABLE_WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resmgr_set_chan_time_quota_cmd_fixed_param, \ - wmi_resmgr_set_chan_time_quota_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resmgr_set_chan_time_quota_cmd_fixed_param, \ + wmi_resmgr_set_chan_time_quota_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID); /* Resmgr Set Channel Latency CMD */ #define WMITLV_TABLE_WMI_RESMGR_SET_CHAN_LATENCY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resmgr_set_chan_latency_cmd_fixed_param, \ - wmi_resmgr_set_chan_latency_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_resmgr_set_chan_latency_cmd_fixed_param, \ + wmi_resmgr_set_chan_latency_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RESMGR_SET_CHAN_LATENCY_CMDID); /* STA SMPS Force Mode CMD */ #define WMITLV_TABLE_WMI_STA_SMPS_FORCE_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_cmd_fixed_param, \ - wmi_sta_smps_force_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_cmd_fixed_param, \ + wmi_sta_smps_force_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_SMPS_FORCE_MODE_CMDID); /* wlan hb enable/disable CMD */ #define WMITLV_TABLE_WMI_HB_SET_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_enable_cmd_fixed_param, \ - wmi_hb_set_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_enable_cmd_fixed_param, \ + wmi_hb_set_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HB_SET_ENABLE_CMDID); /* wlan hb set tcp params CMD */ -#define WMITLV_TABLE_WMI_HB_SET_TCP_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_tcp_params_cmd_fixed_param, \ - wmi_hb_set_tcp_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_HB_SET_TCP_PARAMS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_tcp_params_cmd_fixed_param, \ + wmi_hb_set_tcp_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HB_SET_TCP_PARAMS_CMDID); /* wlan hb set tcp pkt filter CMD */ #define WMITLV_TABLE_WMI_HB_SET_TCP_PKT_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_tcp_pkt_filter_cmd_fixed_param, \ - wmi_hb_set_tcp_pkt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_tcp_pkt_filter_cmd_fixed_param, \ + wmi_hb_set_tcp_pkt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HB_SET_TCP_PKT_FILTER_CMDID); /* wlan set udp params CMD */ -#define WMITLV_TABLE_WMI_HB_SET_UDP_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_udp_params_cmd_fixed_param, \ - wmi_hb_set_udp_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_HB_SET_UDP_PARAMS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_udp_params_cmd_fixed_param, \ + wmi_hb_set_udp_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HB_SET_UDP_PARAMS_CMDID); /* wlan hb set udp pkt filter CMD */ #define WMITLV_TABLE_WMI_HB_SET_UDP_PKT_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_udp_pkt_filter_cmd_fixed_param, \ - wmi_hb_set_udp_pkt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hb_set_udp_pkt_filter_cmd_fixed_param, \ + wmi_hb_set_udp_pkt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HB_SET_UDP_PKT_FILTER_CMDID); /* STA SMPS Param CMD */ #define WMITLV_TABLE_WMI_STA_SMPS_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_smps_param_cmd_fixed_param, \ - wmi_sta_smps_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_smps_param_cmd_fixed_param, \ + wmi_sta_smps_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_SMPS_PARAM_CMDID); /* MCC Adaptive Scheduler Traffic Stats */ #define WMITLV_TABLE_WMI_MCC_SCHED_TRAFFIC_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mcc_sched_traffic_stats_cmd_fixed_param, wmi_mcc_sched_traffic_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_mcc_sched_sta_traffic_stats, mcc_sched_sta_traffic_stats_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mcc_sched_traffic_stats_cmd_fixed_param, wmi_mcc_sched_traffic_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_mcc_sched_sta_traffic_stats, mcc_sched_sta_traffic_stats_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MCC_SCHED_TRAFFIC_STATS_CMDID); -#define WMITLV_TABLE_WMI_BATCH_SCAN_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_enable_cmd_fixed_param, wmi_batch_scan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - +#define WMITLV_TABLE_WMI_BATCH_SCAN_ENABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_enable_cmd_fixed_param, wmi_batch_scan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_BATCH_SCAN_ENABLE_CMDID); #define WMITLV_TABLE_WMI_PEER_INFO_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_info_req_cmd_fixed_param, \ - wmi_peer_info_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_info_req_cmd_fixed_param, \ + wmi_peer_info_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_INFO_REQ_CMDID); -#define WMITLV_TABLE_WMI_PEER_ANTDIV_INFO_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_antdiv_info_req_cmd_fixed_param, \ - wmi_peer_antdiv_info_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - +#define WMITLV_TABLE_WMI_PEER_ANTDIV_INFO_REQ_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_antdiv_info_req_cmd_fixed_param, \ + wmi_peer_antdiv_info_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ANTDIV_INFO_REQ_CMDID); #define WMITLV_TABLE_WMI_RMC_SET_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmc_set_mode_cmd_fixed_param, \ - wmi_rmc_set_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmc_set_mode_cmd_fixed_param, \ + wmi_rmc_set_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RMC_SET_MODE_CMDID); #define WMITLV_TABLE_WMI_RMC_SET_ACTION_PERIOD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmc_set_action_period_cmd_fixed_param, \ - wmi_rmc_set_action_period_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmc_set_action_period_cmd_fixed_param, \ + wmi_rmc_set_action_period_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RMC_SET_ACTION_PERIOD_CMDID); #define WMITLV_TABLE_WMI_RMC_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmc_config_cmd_fixed_param, \ - wmi_rmc_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rmc_config_cmd_fixed_param, \ + wmi_rmc_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RMC_CONFIG_CMDID); #define WMITLV_TABLE_WMI_MHF_OFFLOAD_SET_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mhf_offload_set_mode_cmd_fixed_param, \ - wmi_mhf_offload_set_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mhf_offload_set_mode_cmd_fixed_param, \ + wmi_mhf_offload_set_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MHF_OFFLOAD_SET_MODE_CMDID); #define WMITLV_TABLE_WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mhf_offload_plumb_routing_table_cmd_fixed_param, \ - wmi_mhf_offload_plumb_routing_table_cmd, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mhf_offload_routing_table_entry, \ - routing_tbl_entries, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID); - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mhf_offload_plumb_routing_table_cmd_fixed_param, \ + wmi_mhf_offload_plumb_routing_table_cmd, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mhf_offload_routing_table_entry, \ + routing_tbl_entries, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID) #define WMITLV_TABLE_WMI_BATCH_SCAN_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_disable_cmd_fixed_param, wmi_batch_scan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_disable_cmd_fixed_param, wmi_batch_scan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_BATCH_SCAN_DISABLE_CMDID); -#define WMITLV_TABLE_WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_trigger_result_cmd_fixed_param, wmi_batch_scan_trigger_result_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_trigger_result_cmd_fixed_param, wmi_batch_scan_trigger_result_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID); /* LPI mgmt snooping config Cmd */ #define WMITLV_TABLE_WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_mgmt_snooping_config_cmd_fixed_param, wmi_lpi_mgmt_snooping_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_mgmt_snooping_config_cmd_fixed_param, wmi_lpi_mgmt_snooping_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID); /* LPI start scan Cmd */ #define WMITLV_TABLE_WMI_LPI_START_SCAN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_start_scan_cmd_fixed_param, wmi_lpi_start_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_start_scan_cmd_fixed_param, wmi_lpi_start_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_START_SCAN_CMDID); /* LPI stop scan Cmd */ #define WMITLV_TABLE_WMI_LPI_STOP_SCAN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_stop_scan_cmd_fixed_param, wmi_lpi_stop_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_stop_scan_cmd_fixed_param, wmi_lpi_stop_scan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_STOP_SCAN_CMDID); #define WMITLV_TABLE_WMI_LPI_RESULT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_result_event_fixed_param, wmi_lpi_result_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_result_event_fixed_param, wmi_lpi_result_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_RESULT_EVENTID); /* LPI Status Event */ -#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, wmi_lpi_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, wmi_lpi_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_STATUS_EVENTID); /* LPI Handoff Event */ -#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, wmi_lpi_handoff_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, wmi_lpi_handoff_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_HANDOFF_EVENTID); /* Thermal Manager Params*/ #define WMITLV_TABLE_WMI_THERMAL_MGMT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, wmi_thermal_mgmt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, wmi_thermal_mgmt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_THERMAL_MGMT_CMDID); - #define WMITLV_TABLE_WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, pattern, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, pattern, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID); #define WMITLV_TABLE_WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID); /* NaN Request */ #define WMITLV_TABLE_WMI_NAN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_cmd_param, wmi_nan_cmd_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_cmd_param, wmi_nan_cmd_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID); /* NAN Data Get Capabilities Cmd */ -#define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NDI_GET_CAP_REQ_CMDID); -/** NAN Data Initiator Request Cmd +/* + * NAN Data Initiator Request Cmd * * TLV (tag length value ) parameters follow the ndp_initiator_req * structure. The TLV's are: @@ -2491,1269 +2532,1305 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDI_GET_CAP_REQ_CMDID); * A_UINT8 ndp_cfg[]; * A_UINT8 ndp_app_info[]; */ -#define WMITLV_TABLE_WMI_NDP_INITIATOR_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param, wmi_ndp_initiator_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, channel, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_INITIATOR_REQ_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param, wmi_ndp_initiator_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, channel, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INITIATOR_REQ_CMDID); -/** NAN Data Responder Request Cmd +/* + * NAN Data Responder Request Cmd * TLV (tag length value ) parameters follow the ndp_responder_req * structure. The TLV's are: * A_UINT8 ndp_cfg[]; * A_UINT8 ndp_app_info[]; */ -#define WMITLV_TABLE_WMI_NDP_RESPONDER_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_responder_req_fixed_param, wmi_ndp_responder_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_RESPONDER_REQ_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param, wmi_ndp_responder_req_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_RESPONDER_REQ_CMDID); -/** NAN Data End Request Cmd +/* + * NAN Data End Request Cmd * * TLV (tag length value ) parameters follow the ndp_end_req * structure. The TLV's are: * wmi_ndp_end_req wmi_ndp_end_req_list[]; */ -#define WMITLV_TABLE_WMI_NDP_END_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_end_req_fixed_param, wmi_ndp_end_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_req_PROTOTYPE, ndp_end_req_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_END_REQ_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_end_req_fixed_param, wmi_ndp_end_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_req_PROTOTYPE, ndp_end_req_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_REQ_CMDID); /* Modem power state cmd */ -#define WMITLV_TABLE_WMI_MODEM_POWER_STATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_modem_power_state_cmd_param, wmi_modem_power_state_cmd_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_MODEM_POWER_STATE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_modem_power_state_cmd_param, wmi_modem_power_state_cmd_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MODEM_POWER_STATE_CMDID); +/* SAR limit update cmd */ +#define WMITLV_TABLE_WMI_SAR_LIMITS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_sar_limits_cmd_fixed_param, wmi_sar_limits_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_sar_limit_cmd_row, sar_limits, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_SAR_LIMITS_CMDID); + /* get estimated link speed cmd */ #define WMITLV_TABLE_WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_get_estimated_linkspeed_cmd_fixed_param, wmi_peer_get_estimated_linkspeed_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_get_estimated_linkspeed_cmd_fixed_param, wmi_peer_get_estimated_linkspeed_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID); /* ext stats Request */ -#define WMITLV_TABLE_WMI_REQUEST_STATS_EXT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_req_stats_ext_cmd_fixed_param, wmi_req_stats_ext_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_REQUEST_STATS_EXT_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_req_stats_ext_cmd_fixed_param, wmi_req_stats_ext_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_STATS_EXT_CMDID); /* 2.4Ghz HT40 OBSS scan enable */ #define WMITLV_TABLE_WMI_OBSS_SCAN_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_obss_scan_enable_cmd_fixed_param, wmi_obss_scan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, channels, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_field, WMITLV_SIZE_VAR) + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_obss_scan_enable_cmd_fixed_param, wmi_obss_scan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, channels, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_field, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OBSS_SCAN_ENABLE_CMDID); /* 2.4Ghz HT40 OBSS scan disable */ -#define WMITLV_TABLE_WMI_OBSS_SCAN_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_obss_scan_disable_cmd_fixed_param, wmi_obss_scan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_OBSS_SCAN_DISABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_obss_scan_disable_cmd_fixed_param, wmi_obss_scan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OBSS_SCAN_DISABLE_CMDID); /* Pdev Set LED Config Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_LED_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_led_config_cmd_fixed_param, wmi_pdev_set_led_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_led_config_cmd_fixed_param, wmi_pdev_set_led_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_LED_CONFIG_CMDID); /* host auto shut down config cmd */ #define WMITLV_TABLE_WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_auto_shutdown_cfg_cmd_fixed_param, wmi_host_auto_shutdown_cfg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_auto_shutdown_cfg_cmd_fixed_param, wmi_host_auto_shutdown_cfg_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID); /* tpc chainmask config cmd */ #define WMITLV_TABLE_WMI_TPC_CHAINMASK_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tpc_chainmask_config_cmd_fixed_param, wmi_tpc_chainmask_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_chainmask_config, config_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tpc_chainmask_config_cmd_fixed_param, wmi_tpc_chainmask_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_chainmask_config, config_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_TPC_CHAINMASK_CONFIG_CMDID); - /* Ch avoidance update cmd */ -#define WMITLV_TABLE_WMI_CHAN_AVOID_UPDATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_avoid_update_cmd_param, wmi_chan_avoid_update_cmd_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_CHAN_AVOID_UPDATE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_avoid_update_cmd_param, wmi_chan_avoid_update_cmd_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_AVOID_UPDATE_CMDID); /* Ch avoidance report allow/disallow cmd*/ -#define WMITLV_TABLE_WMI_CHAN_AVOID_RPT_ALLOW_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param, WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_CHAN_AVOID_RPT_ALLOW_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param, WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_AVOID_RPT_ALLOW_CMDID); + /* D0-WOW Enable Disable Cmd */ -#define WMITLV_TABLE_WMI_D0_WOW_ENABLE_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_d0_wow_enable_disable_cmd_fixed_param, wmi_d0_wow_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_D0_WOW_ENABLE_DISABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_d0_wow_enable_disable_cmd_fixed_param, wmi_d0_wow_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_D0_WOW_ENABLE_DISABLE_CMDID); /* Pdev get chip temperature Cmd */ #define WMITLV_TABLE_WMI_PDEV_GET_TEMPERATURE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_temperature_cmd_fixed_param, wmi_pdev_get_temperature_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TEMPERATURE_CMDID); + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_temperature_cmd_fixed_param, wmi_pdev_get_temperature_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TEMPERATURE_CMDID); /* Pdev get ANT DIV feature status Cmd */ -#define WMITLV_TABLE_WMI_PDEV_GET_ANTDIV_STATUS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_antdiv_status_cmd_fixed_param, wmi_pdev_get_antdiv_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_GET_ANTDIV_STATUS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_get_antdiv_status_cmd_fixed_param, wmi_pdev_get_antdiv_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_ANTDIV_STATUS_CMDID); +/* DISA feature : vdev encrypt decrypt request */ +#define WMITLV_TABLE_WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_encrypt_decrypt_data_req_cmd_fixed_param, wmi_vdev_encrypt_decrypt_data_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID); + /* Set antenna diversity Cmd */ #define WMITLV_TABLE_WMI_SET_ANTENNA_DIVERSITY_CMDID(id,op,buf,len) \ -WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_antenna_diversity_cmd_fixed_param, wmi_pdev_set_antenna_diversity_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_antenna_diversity_cmd_fixed_param, wmi_pdev_set_antenna_diversity_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SET_ANTENNA_DIVERSITY_CMDID); +#define WMITLV_TABLE_WMI_LRO_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_lro_info_cmd_fixed_param, wmi_lro_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_LRO_CONFIG_CMDID); + +#define WMITLV_TABLE_WMI_TRANSFER_DATA_TO_FLASH_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param, wmi_transfer_data_to_flash_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_TRANSFER_DATA_TO_FLASH_CMDID); + +#define WMITLV_TABLE_WMI_READ_DATA_FROM_FLASH_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_read_data_from_flash_cmd_fixed_param, wmi_read_data_from_flash_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_READ_DATA_FROM_FLASH_CMDID); + +#define WMITLV_TABLE_WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_config_enhanced_mcast_filter_fixed_param, wmi_config_enhanced_mcast_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID); + +#define WMITLV_TABLE_WMI_VDEV_WISA_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_wisa_cmd_fixed_param, wmi_vdev_wisa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_WISA_CMDID); + +/* MAWC sensor report indication cmd */ +#define WMITLV_TABLE_WMI_MAWC_SENSOR_REPORT_IND_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mawc_sensor_report_ind_cmd_fixed_param, wmi_mawc_sensor_report_ind_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MAWC_SENSOR_REPORT_IND_CMDID); + +/* Roam configure MAWC cmd */ +#define WMITLV_TABLE_WMI_ROAM_CONFIGURE_MAWC_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_roam_configure_mawc_cmd_fixed_param, wmi_roam_configure_mawc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CONFIGURE_MAWC_CMDID); + +/* NLO configure MAWC cmd */ +#define WMITLV_TABLE_WMI_NLO_CONFIGURE_MAWC_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_nlo_configure_mawc_cmd_fixed_param, wmi_nlo_configure_mawc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_NLO_CONFIGURE_MAWC_CMDID); + +/* Extscan configure MAWC cmd */ +#define WMITLV_TABLE_WMI_EXTSCAN_CONFIGURE_MAWC_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_extscan_configure_mawc_cmd_fixed_param, wmi_extscan_configure_mawc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CONFIGURE_MAWC_CMDID); + +/* COEX config cmd */ +#define WMITLV_TABLE_WMI_COEX_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_COEX_CONFIG_CMD_fixed_param, WMI_COEX_CONFIG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_COEX_CONFIG_CMDID); + +/* Coex get antenna isolation cmd */ +#define WMITLV_TABLE_WMI_COEX_GET_ANTENNA_ISOLATION_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_coex_get_antenna_isolation_cmd_fixed_param, wmi_coex_get_antenna_isolation_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_ANTENNA_ISOLATION_CMDID); + +/* bpf offload capability get cmd */ +#define WMITLV_TABLE_WMI_BPF_GET_CAPABILITY_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_bpf_get_capability_cmd_fixed_param, wmi_bpf_get_capability_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_CAPABILITY_CMDID); + +/* bpf offload get vdev status cmd */ +#define WMITLV_TABLE_WMI_BPF_GET_VDEV_STATS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_bpf_get_vdev_stats_cmd_fixed_param, wmi_bpf_get_vdev_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_VDEV_STATS_CMDID); + +/* bpf offload set vdev instructions cmd */ +#define WMITLV_TABLE_WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_bpf_set_vdev_instructions_cmd_fixed_param, wmi_bpf_set_vdev_instructions_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, buf_inst, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID); + +/* bpf offload delete vdev instructions cmd */ +#define WMITLV_TABLE_WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_bpf_del_vdev_instructions_cmd_fixed_param, wmi_bpf_del_vdev_instructions_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID); + +/* Enable/Disable Smart Antenna */ +#define WMITLV_TABLE_WMI_PDEV_SMART_ANT_ENABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, wmi_pdev_smart_ant_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_ENABLE_CMDID); + +/* Set Smart Antenna RX antenna */ +#define WMITLV_TABLE_WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param, wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID); + +/* Override the antenna switch table */ +#define WMITLV_TABLE_WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_ant_switch_tbl_cmd_fixed_param, wmi_pdev_set_ant_switch_tbl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_ant_ctrl_chain, ant_ctrl_chain, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID); + +/* Override the CTL table */ +#define WMITLV_TABLE_WMI_PDEV_SET_CTL_TABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_ctl_table_cmd_fixed_param, wmi_pdev_set_ctl_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ctl_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CTL_TABLE_CMDID); + +/* Override the array gain table */ +#define WMITLV_TABLE_WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param, wmi_pdev_set_mimogain_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, arraygain_tbl, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID); + +/* FIPS cmd */ +#define WMITLV_TABLE_WMI_PDEV_FIPS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_fips_cmd_fixed_param, wmi_pdev_fips_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_CMDID); + +/* get CCK ANI level */ +#define WMITLV_TABLE_WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param, wmi_pdev_get_ani_cck_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID); + +/* get OFDM ANI level */ +#define WMITLV_TABLE_WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_get_ani_ofdm_config_cmd_fixed_param, wmi_pdev_get_ani_ofdm_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID); + +/* TxPPDU TPC cmd */ +#define WMITLV_TABLE_WMI_PDEV_GET_TPC_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_get_tpc_cmd_fixed_param, wmi_pdev_get_tpc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_CMDID); + +#define WMITLV_TABLE_WMI_VDEV_RATEMASK_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_config_ratemask_fixed_param, wmi_vdev_config_ratemask_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_RATEMASK_CMDID); + +/* ATF VDEV REQUEST commands */ +#define WMITLV_TABLE_WMI_VDEV_ATF_REQUEST_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_atf_request_fixed_param, wmi_vdev_atf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ATF_REQUEST_CMDID); + +/* Command to send the DSCP-to-TID map to the target for VAP */ +#define WMITLV_TABLE_WMI_VDEV_SET_DSCP_TID_MAP_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_dscp_tid_map_cmd_fixed_param, wmi_vdev_set_dscp_tid_map_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_DSCP_TID_MAP_CMDID); + +/* Configure filter for Neighbor Rx Pkt (smart mesh selective listening) */ +#define WMITLV_TABLE_WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param, wmi_vdev_filter_nrp_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID); + +/* update a wds (4 address) entry */ +#define WMITLV_TABLE_WMI_PEER_UPDATE_WDS_ENTRY_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, wmi_peer_update_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UPDATE_WDS_ENTRY_CMDID); + +/* add a proxy sta entry */ +#define WMITLV_TABLE_WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID); + +/* Set Smart Antenna TX antenna */ +#define WMITLV_TABLE_WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len,WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param, wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_smart_ant_set_tx_antenna_series, antenna_series, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID); + +/* Set Smart Antenna TX train info */ +#define WMITLV_TABLE_WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param, wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_smart_ant_set_train_antenna_param, antenna_param, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID); + +/* Set SA node config options */ +#define WMITLV_TABLE_WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param, wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, args, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID); + +/* Q-Boost configuration test commands */ +#define WMITLV_TABLE_WMI_QBOOST_CFG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_QBOOST_CFG_CMD_fixed_param, WMI_QBOOST_CFG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_QBOOST_CFG_CMDID); + +/* set debug and tuning parameters */ +#define WMITLV_TABLE_WMI_FWTEST_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_fwtest_set_param_cmd_fixed_param, wmi_fwtest_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_CMDID); + +/* ATF PEER REQUEST commands. */ +#define WMITLV_TABLE_WMI_PEER_ATF_REQUEST_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param, wmi_peer_atf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ATF_REQUEST_CMDID) + /* Set rssi monitoring config Cmd */ -#define WMITLV_TABLE_WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID(id,op,buf,len) \ -WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rssi_breach_monitor_config_fixed_param, wmi_rssi_breach_monitor_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rssi_breach_monitor_config_fixed_param, wmi_rssi_breach_monitor_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID); /* DHCP server offload param Cmd */ #define WMITLV_TABLE_WMI_SET_DHCP_SERVER_OFFLOAD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_dhcp_server_offload_cmd_fixed_param, wmi_set_dhcp_server_offload_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_dhcp_server_offload_cmd_fixed_param, wmi_set_dhcp_server_offload_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SET_DHCP_SERVER_OFFLOAD_CMDID); /* IPA Offload Enable Disable Cmd */ -#define WMITLV_TABLE_WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUCT_wmi_ipa_offload_enable_disable_cmd_fixed_param, wmi_ipa_offload_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUCT_wmi_ipa_offload_enable_disable_cmd_fixed_param, wmi_ipa_offload_enable_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID); /* Set LED flashing parameter Cmd */ #define WMITLV_TABLE_WMI_PDEV_SET_LED_FLASHING_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_led_flashing_cmd_fixed_param, wmi_set_led_flashing_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_led_flashing_cmd_fixed_param, wmi_set_led_flashing_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_LED_FLASHING_CMDID); /* mDNS responder offload param Cmd */ #define WMITLV_TABLE_WMI_MDNS_OFFLOAD_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_offload_cmd_fixed_param, wmi_mdns_offload_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_offload_cmd_fixed_param, wmi_mdns_offload_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_OFFLOAD_ENABLE_CMDID); #define WMITLV_TABLE_WMI_MDNS_SET_FQDN_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_set_fqdn_cmd_fixed_param, wmi_mdns_set_fqdn_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, fqdn_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_set_fqdn_cmd_fixed_param, wmi_mdns_set_fqdn_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, fqdn_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_SET_FQDN_CMDID); #define WMITLV_TABLE_WMI_MDNS_SET_RESPONSE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_set_resp_cmd_fixed_param, wmi_mdns_set_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, resp_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_set_resp_cmd_fixed_param, wmi_mdns_set_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, resp_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_SET_RESPONSE_CMDID); #define WMITLV_TABLE_WMI_MDNS_GET_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_get_stats_cmd_fixed_param, wmi_mdns_get_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_get_stats_cmd_fixed_param, wmi_mdns_get_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_GET_STATS_CMDID); /* roam invoke Cmd */ #define WMITLV_TABLE_WMI_ROAM_INVOKE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_invoke_cmd_fixed_param, wmi_roam_invoke_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_invoke_cmd_fixed_param, wmi_roam_invoke_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_INVOKE_CMDID); /* SAP Authentication offload param Cmd */ #define WMITLV_TABLE_WMI_SAP_OFL_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_enable_cmd_fixed_param, wmi_sap_ofl_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, psk, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_enable_cmd_fixed_param, wmi_sap_ofl_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, psk, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SAP_OFL_ENABLE_CMDID); /* SAP set blacklist param cmd */ -#define WMITLV_TABLE_WMI_SAP_SET_BLACKLIST_PARAM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_set_blacklist_param_cmd_fixed_param, wmi_sap_set_blacklist_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SAP_SET_BLACKLIST_PARAM_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_sap_set_blacklist_param_cmd_fixed_param, wmi_sap_set_blacklist_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SAP_SET_BLACKLIST_PARAM_CMDID); /* APFIND Request */ #define WMITLV_TABLE_WMI_APFIND_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_apfind_cmd_param, wmi_apfind_cmd_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_apfind_cmd_param, wmi_apfind_cmd_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_APFIND_CMDID); /* Set OCB schedule cmd, DEPRECATED */ #define WMITLV_TABLE_WMI_OCB_SET_SCHED_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ocb_set_sched_cmd_fixed_param, wmi_ocb_set_sched_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ocb_set_sched_cmd_fixed_param, wmi_ocb_set_sched_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_SET_SCHED_CMDID); /* Set OCB configuration cmd */ #define WMITLV_TABLE_WMI_OCB_SET_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_set_config_cmd_fixed_param, wmi_ocb_set_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, chan_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ocb_channel, ocb_chan_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_qos_parameter, qos_parameter_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_chan, chan_cfg, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_active_state_config, ndl_active_state_config_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ocb_schedule_element, schedule_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_set_config_cmd_fixed_param, wmi_ocb_set_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, chan_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ocb_channel, ocb_chan_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_qos_parameter, qos_parameter_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_chan, chan_cfg, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_active_state_config, ndl_active_state_config_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ocb_schedule_element, schedule_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_SET_CONFIG_CMDID); /* Set UTC time cmd */ #define WMITLV_TABLE_WMI_OCB_SET_UTC_TIME_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_set_utc_time_cmd_fixed_param, wmi_ocb_set_utc_time_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_set_utc_time_cmd_fixed_param, wmi_ocb_set_utc_time_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_SET_UTC_TIME_CMDID); /* Start timing advertisement cmd */ #define WMITLV_TABLE_WMI_OCB_START_TIMING_ADVERT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_start_timing_advert_cmd_fixed_param, wmi_ocb_start_timing_advert_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_start_timing_advert_cmd_fixed_param, wmi_ocb_start_timing_advert_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_START_TIMING_ADVERT_CMDID); /* Stop timing advertisement cmd */ #define WMITLV_TABLE_WMI_OCB_STOP_TIMING_ADVERT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_stop_timing_advert_cmd_fixed_param, wmi_ocb_stop_timing_advert_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_stop_timing_advert_cmd_fixed_param, wmi_ocb_stop_timing_advert_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_STOP_TIMING_ADVERT_CMDID); /* Get TSF timer cmd */ #define WMITLV_TABLE_WMI_OCB_GET_TSF_TIMER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_cmd_fixed_param, wmi_ocb_get_tsf_timer_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_cmd_fixed_param, wmi_ocb_get_tsf_timer_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_GET_TSF_TIMER_CMDID); /* Get DCC stats cmd */ #define WMITLV_TABLE_WMI_DCC_GET_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_get_stats_cmd_fixed_param, wmi_dcc_get_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_channel_stats_request, channel_stats_request, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_get_stats_cmd_fixed_param, wmi_dcc_get_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_channel_stats_request, channel_stats_request, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DCC_GET_STATS_CMDID); /* Clear DCC stats cmd */ #define WMITLV_TABLE_WMI_DCC_CLEAR_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_clear_stats_cmd_fixed_param, wmi_dcc_clear_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_clear_stats_cmd_fixed_param, wmi_dcc_clear_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DCC_CLEAR_STATS_CMDID); /* Update DCC NDL cmd */ #define WMITLV_TABLE_WMI_DCC_UPDATE_NDL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_update_ndl_cmd_fixed_param, wmi_dcc_update_ndl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_chan, chan_ndl_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_active_state_config, ndl_active_state_config_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_update_ndl_cmd_fixed_param, wmi_dcc_update_ndl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_chan, chan_ndl_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_active_state_config, ndl_active_state_config_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DCC_UPDATE_NDL_CMDID); -/* Roam filter cmd */ #define WMITLV_TABLE_WMI_ROAM_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_filter_fixed_param, wmi_roam_filter_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_black_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_white_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_preferred_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, bssid_preferred_factor, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_filter_fixed_param, wmi_roam_filter_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_black_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_ssid, ssid_white_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_preferred_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, bssid_preferred_factor, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_FILTER_CMDID); - /* TSF timestamp action cmd */ #define WMITLV_TABLE_WMI_VDEV_TSF_TSTAMP_ACTION_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_tsf_tstamp_action_cmd_fixed_param, wmi_vdev_tsf_tstamp_action_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TSF_TSTAMP_ACTION_CMDID); /* LFR subnet change config Cmd */ -#define WMITLV_TABLE_WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_subnet_change_config_fixed_param, wmi_roam_subnet_change_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, skip_subnet_change_detection_bssid_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_roam_subnet_change_config_fixed_param, wmi_roam_subnet_change_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, skip_subnet_change_detection_bssid_list, WMITLV_SIZE_VAR) + WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID); /* Set the SOC Preferred Channel List (PCL) Cmd - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_SET_PCL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_set_pcl_cmd_fixed_param, wmi_soc_set_pcl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SOC_SET_PCL_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_set_pcl_cmd_fixed_param, wmi_soc_set_pcl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_SET_PCL_CMDID); /* Set the PDEV Preferred Channel List (PCL) Cmd */ -#define WMITLV_TABLE_WMI_PDEV_SET_PCL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_pcl_cmd_fixed_param, wmi_pdev_set_pcl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_weight, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_SET_PCL_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_pcl_cmd_fixed_param, wmi_pdev_set_pcl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_weight, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_PCL_CMDID); /* Set the SOC Hardware Mode Cmd - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_SET_HW_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_cmd_fixed_param, wmi_soc_set_hw_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SOC_SET_HW_MODE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_cmd_fixed_param, wmi_soc_set_hw_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_SET_HW_MODE_CMDID); /* Set the PDEV Hardware Mode Cmd */ -#define WMITLV_TABLE_WMI_PDEV_SET_HW_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, wmi_pdev_set_hw_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SET_HW_MODE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param, wmi_pdev_set_hw_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_HW_MODE_CMDID); /* Set the SOC Dual MAC Config Cmd - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_cmd_fixed_param, wmi_soc_set_dual_mac_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_cmd_fixed_param, wmi_soc_set_dual_mac_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID); /* Set the PDEV MAC Config Cmd */ -#define WMITLV_TABLE_WMI_PDEV_SET_MAC_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_cmd_fixed_param, wmi_pdev_set_mac_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SET_MAC_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_cmd_fixed_param, wmi_pdev_set_mac_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_MAC_CONFIG_CMDID); /* Set the SOC Antenna Mode Cmd - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_SET_ANTENNA_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_set_antenna_mode_cmd_fixed_param, wmi_soc_set_antenna_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SOC_SET_ANTENNA_MODE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_set_antenna_mode_cmd_fixed_param, wmi_soc_set_antenna_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_SET_ANTENNA_MODE_CMDID); /* Set the PDEV Antenna Mode Cmd */ -#define WMITLV_TABLE_WMI_PDEV_SET_ANTENNA_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_antenna_mode_cmd_fixed_param, wmi_pdev_set_antenna_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SET_ANTENNA_MODE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_antenna_mode_cmd_fixed_param, wmi_pdev_set_antenna_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_ANTENNA_MODE_CMDID); -#define WMITLV_TABLE_WMI_LRO_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lro_info_cmd_fixed_param, wmi_lro_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_LRO_CONFIG_CMDID); - -#define WMITLV_TABLE_WMI_TRANSFER_DATA_TO_FLASH_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param, wmi_transfer_data_to_flash_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_TRANSFER_DATA_TO_FLASH_CMDID); - -#define WMITLV_TABLE_WMI_READ_DATA_FROM_FLASH_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_read_data_from_flash_cmd_fixed_param, wmi_read_data_from_flash_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_READ_DATA_FROM_FLASH_CMDID); - -#define WMITLV_TABLE_WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_config_enhanced_mcast_filter_fixed_param, wmi_config_enhanced_mcast_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_WISA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_wisa_cmd_fixed_param, wmi_vdev_wisa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_WISA_CMDID); - -/* MAWC sensor report indication cmd */ -#define WMITLV_TABLE_WMI_MAWC_SENSOR_REPORT_IND_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mawc_sensor_report_ind_cmd_fixed_param, wmi_mawc_sensor_report_ind_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_MAWC_SENSOR_REPORT_IND_CMDID); - -/* Roam configure MAWC cmd */ -#define WMITLV_TABLE_WMI_ROAM_CONFIGURE_MAWC_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_configure_mawc_cmd_fixed_param, wmi_roam_configure_mawc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CONFIGURE_MAWC_CMDID); - -/* NLO configure MAWC cmd */ -#define WMITLV_TABLE_WMI_NLO_CONFIGURE_MAWC_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_configure_mawc_cmd_fixed_param, wmi_nlo_configure_mawc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NLO_CONFIGURE_MAWC_CMDID); - -/* Extscan configure MAWC cmd */ -#define WMITLV_TABLE_WMI_EXTSCAN_CONFIGURE_MAWC_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_configure_mawc_cmd_fixed_param, wmi_extscan_configure_mawc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CONFIGURE_MAWC_CMDID); - -/* COEX config cmd */ -#define WMITLV_TABLE_WMI_COEX_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_COEX_CONFIG_CMD_fixed_param, WMI_COEX_CONFIG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_COEX_CONFIG_CMDID); - -/* Coex get antenna isolation cmd */ -#define WMITLV_TABLE_WMI_COEX_GET_ANTENNA_ISOLATION_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_get_antenna_isolation_cmd_fixed_param, wmi_coex_get_antenna_isolation_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_ANTENNA_ISOLATION_CMDID); - -/* bpf offload capability get cmd */ -#define WMITLV_TABLE_WMI_BPF_GET_CAPABILITY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_get_capability_cmd_fixed_param, wmi_bpf_get_capability_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_CAPABILITY_CMDID); - -/* bpf offload get vdev status cmd */ -#define WMITLV_TABLE_WMI_BPF_GET_VDEV_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_get_vdev_stats_cmd_fixed_param, wmi_bpf_get_vdev_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_VDEV_STATS_CMDID); - -/* bpf offload set vdev instructions cmd */ -#define WMITLV_TABLE_WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_set_vdev_instructions_cmd_fixed_param, wmi_bpf_set_vdev_instructions_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, buf_inst, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID); - -/* bpf offload delete vdev instructions cmd */ -#define WMITLV_TABLE_WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_del_vdev_instructions_cmd_fixed_param, wmi_bpf_del_vdev_instructions_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID); - -/* Enable/Disable Smart Antenna */ -#define WMITLV_TABLE_WMI_PDEV_SMART_ANT_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, wmi_pdev_smart_ant_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_ENABLE_CMDID); - -/* Set Smart Antenna RX antenna */ -#define WMITLV_TABLE_WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param, wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID); - -/* Override the antenna switch table */ -#define WMITLV_TABLE_WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_ant_switch_tbl_cmd_fixed_param, wmi_pdev_set_ant_switch_tbl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_ant_ctrl_chain, ant_ctrl_chain, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID); - -/* Override the CTL table */ -#define WMITLV_TABLE_WMI_PDEV_SET_CTL_TABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_ctl_table_cmd_fixed_param, wmi_pdev_set_ctl_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ctl_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CTL_TABLE_CMDID); - -/* Override the array gain table */ -#define WMITLV_TABLE_WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param, wmi_pdev_set_mimogain_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, arraygain_tbl, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID); - -/* FIPS cmd */ -#define WMITLV_TABLE_WMI_PDEV_FIPS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_cmd_fixed_param, wmi_pdev_fips_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_CMDID); - -/* get CCK ANI level */ -#define WMITLV_TABLE_WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param, wmi_pdev_get_ani_cck_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID); - -/* get OFDM ANI level */ -#define WMITLV_TABLE_WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_ani_ofdm_config_cmd_fixed_param, wmi_pdev_get_ani_ofdm_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID); - -/* TxPPDU TPC cmd */ -#define WMITLV_TABLE_WMI_PDEV_GET_TPC_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_tpc_cmd_fixed_param, wmi_pdev_get_tpc_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_RATEMASK_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_config_ratemask_fixed_param, wmi_vdev_config_ratemask_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_RATEMASK_CMDID); - -/* ATF VDEV REQUEST commands */ -#define WMITLV_TABLE_WMI_VDEV_ATF_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_atf_request_fixed_param, wmi_vdev_atf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ATF_REQUEST_CMDID); - -/* Command to send the DSCP-to-TID map to the target for VAP */ -#define WMITLV_TABLE_WMI_VDEV_SET_DSCP_TID_MAP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_dscp_tid_map_cmd_fixed_param, wmi_vdev_set_dscp_tid_map_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_DSCP_TID_MAP_CMDID); - -/* Configure filter for Neighbor Rx Pkt (smart mesh selective listening) */ -#define WMITLV_TABLE_WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param, wmi_vdev_filter_nrp_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID); - -/* update a wds (4 address) entry */ -#define WMITLV_TABLE_WMI_PEER_UPDATE_WDS_ENTRY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, wmi_peer_update_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UPDATE_WDS_ENTRY_CMDID); - -/* add a proxy sta entry */ -#define WMITLV_TABLE_WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID); - -/* Set Smart Antenna TX antenna */ -#define WMITLV_TABLE_WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param, wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_smart_ant_set_tx_antenna_series, antenna_series, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID); - -/* Set Smart Antenna TX train info */ -#define WMITLV_TABLE_WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param, wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_smart_ant_set_train_antenna_param, antenna_param, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID); - -/* Set SA node config options */ -#define WMITLV_TABLE_WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param, wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, args, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID); - -/* Q-Boost configuration test commands */ -#define WMITLV_TABLE_WMI_QBOOST_CFG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_QBOOST_CFG_CMD_fixed_param, WMI_QBOOST_CFG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_QBOOST_CFG_CMDID); - -/* set debug and tuning parameters */ -#define WMITLV_TABLE_WMI_FWTEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_fwtest_set_param_cmd_fixed_param, wmi_fwtest_set_param_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_CMDID); - -/* ATF PEER REQUEST commands. */ -#define WMITLV_TABLE_WMI_PEER_ATF_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param, wmi_peer_atf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ATF_REQUEST_CMDID); - /* enable/disable and set the periodicity of periodic channel stats */ -#define WMITLV_TABLE_WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param, wmi_set_periodic_channel_stats_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param, wmi_set_periodic_channel_stats_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID); /* wal power debug command per pdev */ -#define WMITLV_TABLE_WMI_PDEV_WAL_POWER_DEBUG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wal_power_debug_cmd_fixed_param, wmi_pdev_wal_power_debug_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, args, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_WAL_POWER_DEBUG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_wal_power_debug_cmd_fixed_param, wmi_pdev_wal_power_debug_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, args, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WAL_POWER_DEBUG_CMDID); /* pdev set reorder timeout val */ -#define WMITLV_TABLE_WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_reorder_timeout_val_cmd_fixed_param, wmi_pdev_set_reorder_timeout_val_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_reorder_timeout_val_cmd_fixed_param, wmi_pdev_set_reorder_timeout_val_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID); /* peer set rx blocksize cmd */ -#define WMITLV_TABLE_WMI_PEER_SET_RX_BLOCKSIZE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param, wmi_peer_set_rx_blocksize_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_SET_RX_BLOCKSIZE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param, wmi_peer_set_rx_blocksize_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SET_RX_BLOCKSIZE_CMDID); /* Bandwidth Fairness (BWF) peer configure commands */ -#define WMITLV_TABLE_WMI_PEER_BWF_REQUEST_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_bwf_request_fixed_param, wmi_peer_bwf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_bwf_peer_info, peer_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PEER_BWF_REQUEST_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_bwf_request_fixed_param, wmi_peer_bwf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_bwf_peer_info, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BWF_REQUEST_CMDID); -#define WMITLV_TABLE_WMI_RMC_SET_MANUAL_LEADER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rmc_set_leader_cmd_fixed_param, wmi_rmc_set_leader_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_RMC_SET_MANUAL_LEADER_CMDID); - /* peer reorder queue setup cmd */ -#define WMITLV_TABLE_WMI_PEER_REORDER_QUEUE_SETUP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_reorder_queue_setup_cmd_fixed_param, wmi_peer_reorder_queue_setup_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_REORDER_QUEUE_SETUP_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_reorder_queue_setup_cmd_fixed_param, wmi_peer_reorder_queue_setup_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REORDER_QUEUE_SETUP_CMDID); /* peer reorder queue remove cmd */ -#define WMITLV_TABLE_WMI_PEER_REORDER_QUEUE_REMOVE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param, wmi_peer_reorder_queue_remove_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_REORDER_QUEUE_REMOVE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param, wmi_peer_reorder_queue_remove_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REORDER_QUEUE_REMOVE_CMDID); /* Filter in monitor mode paramters Cmd */ -#define WMITLV_TABLE_WMI_MNT_FILTER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mnt_filter_cmd_fixed_param, wmi_mnt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_MNT_FILTER_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mnt_filter_cmd_fixed_param, wmi_mnt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MNT_FILTER_CMDID); /* WLAN GET Chip power Stats*/ -#define WMITLV_TABLE_WMI_PDEV_GET_CHIP_POWER_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, wmi_pdev_get_chip_power_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_GET_CHIP_POWER_STATS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, wmi_pdev_get_chip_power_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID); /* pdev set stats threshold cmd*/ -#define WMITLV_TABLE_WMI_PDEV_SET_STATS_THRESHOLD_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param, wmi_pdev_set_stats_threshold_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_cca_stats_thresh, wmi_chan_cca_stats_thresh, cca_thresh, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_signal_stats_thresh, wmi_peer_signal_stats_thresh, signal_thresh, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_stats_thresh, wmi_tx_stats_thresh, tx_thresh, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rx_stats_thresh, wmi_rx_stats_thresh, rx_thresh, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_STATS_THRESHOLD_CMDID); - -/* Request wlan stats cmd */ -#define WMITLV_TABLE_WMI_REQUEST_WLAN_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param, wmi_request_wlan_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_WLAN_STATS_CMDID); +#define WMITLV_TABLE_WMI_PDEV_SET_STATS_THRESHOLD_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param, wmi_pdev_set_stats_threshold_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_chan_cca_stats_thresh, wmi_chan_cca_stats_thresh, cca_thresh, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_signal_stats_thresh, wmi_peer_signal_stats_thresh, signal_thresh, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_tx_stats_thresh, wmi_tx_stats_thresh, tx_thresh, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rx_stats_thresh, wmi_rx_stats_thresh, rx_thresh, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_STATS_THRESHOLD_CMDID); +/* Request wlan stats cmd */ +#define WMITLV_TABLE_WMI_REQUEST_WLAN_STATS_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id , op, buf, len, WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param, wmi_request_wlan_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_WLAN_STATS_CMDID); /************************** TLV definitions of WMI events *******************************/ /* Service Ready event */ -#define WMITLV_TABLE_WMI_SERVICE_READY_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_event_fixed_param, wmi_service_ready_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_HAL_REG_CAPABILITIES, HAL_REG_CAPABILITIES, hal_reg_capabilities, WMITLV_SIZE_FIX) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, wmi_service_bitmap, WMITLV_SIZE_FIX, WMI_SERVICE_BM_SIZE) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_host_mem_req, mem_reqs, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, wlan_dbs_hw_mode_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SERVICE_READY_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_event_fixed_param, wmi_service_ready_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_HAL_REG_CAPABILITIES, HAL_REG_CAPABILITIES, hal_reg_capabilities, WMITLV_SIZE_FIX) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, wmi_service_bitmap, WMITLV_SIZE_FIX, WMI_SERVICE_BM_SIZE) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wlan_host_mem_req, mem_reqs, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, wlan_dbs_hw_mode_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EVENTID); /* service available event */ -#define WMITLV_TABLE_WMI_SERVICE_AVAILABLE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_available_event_fixed_param, wmi_service_available_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SERVICE_AVAILABLE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_service_available_event_fixed_param, wmi_service_available_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_AVAILABLE_EVENTID); /* Service Ready Extension event */ -#define WMITLV_TABLE_WMI_SERVICE_READY_EXT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext_event_fixed_param, wmi_service_ready_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SOC_MAC_PHY_HW_MODE_CAPS, WMI_SOC_MAC_PHY_HW_MODE_CAPS, soc_hw_mode_caps, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_HW_MODE_CAPABILITIES, hw_mode_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES, mac_phy_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES, WMI_SOC_HAL_REG_CAPABILITIES, soc_hal_reg_caps, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_HAL_REG_CAPABILITIES_EXT, hal_reg_caps, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SERVICE_READY_EXT_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_service_ready_ext_event_fixed_param, wmi_service_ready_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_SOC_MAC_PHY_HW_MODE_CAPS, WMI_SOC_MAC_PHY_HW_MODE_CAPS, soc_hw_mode_caps, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, WMI_HW_MODE_CAPABILITIES, hw_mode_caps, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES, mac_phy_caps, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES, WMI_SOC_HAL_REG_CAPABILITIES, soc_hal_reg_caps, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, WMI_HAL_REG_CAPABILITIES_EXT, hal_reg_caps, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); /* Ready event */ -#define WMITLV_TABLE_WMI_READY_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ready_event_fixed_param, wmi_ready_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_READY_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ready_event_fixed_param, wmi_ready_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_READY_EVENTID); /* Scan Event */ -#define WMITLV_TABLE_WMI_SCAN_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_event_fixed_param, wmi_scan_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SCAN_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_event_fixed_param, wmi_scan_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_EVENTID); /* ExtScan Start/Stop Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_START_STOP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_start_stop_event_fixed_param, wmi_extscan_start_stop_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_EXTSCAN_START_STOP_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_start_stop_event_fixed_param, wmi_extscan_start_stop_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_START_STOP_EVENTID); /* ExtScan Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_OPERATION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_operation_event_fixed_param, wmi_extscan_operation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, bucket_id, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_EXTSCAN_OPERATION_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_operation_event_fixed_param, wmi_extscan_operation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, bucket_id, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_OPERATION_EVENTID); /* ExtScan Table Usage Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_TABLE_USAGE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_table_usage_event_fixed_param, wmi_extscan_table_usage_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_EXTSCAN_TABLE_USAGE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_table_usage_event_fixed_param, wmi_extscan_table_usage_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_TABLE_USAGE_EVENTID); /* ExtScan Result Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_CACHED_RESULTS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_cached_results_event_fixed_param, wmi_extscan_cached_results_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_descriptor, bssid_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_rssi_info, rssi_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_EXTSCAN_CACHED_RESULTS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_cached_results_event_fixed_param, wmi_extscan_cached_results_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_descriptor, bssid_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_rssi_info, rssi_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CACHED_RESULTS_EVENTID); /* ExtScan Monitor RSSI List Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_wlan_change_results_event_fixed_param, wmi_extscan_wlan_change_results_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_result_bssid, bssid_signal_descriptor_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, rssi_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_wlan_change_results_event_fixed_param, wmi_extscan_wlan_change_results_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_result_bssid, bssid_signal_descriptor_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, rssi_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID); /* ExtScan Hot List Match Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_HOTLIST_MATCH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param, wmi_extscan_hotlist_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_descriptor, hotlist_match, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_EXTSCAN_HOTLIST_MATCH_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param, wmi_extscan_hotlist_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_descriptor, hotlist_match, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_HOTLIST_MATCH_EVENTID); /* ExtScan Hot List Match Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_CAPABILITIES_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_capabilities_event_fixed_param, wmi_extscan_capabilities_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_cache_capabilities, extscan_cache_capabilities, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_monitor_capabilities, wlan_change_capabilities, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_monitor_capabilities, hotlist_capabilities, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_EXTSCAN_CAPABILITIES_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_capabilities_event_fixed_param, wmi_extscan_capabilities_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_cache_capabilities, extscan_cache_capabilities, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_change_monitor_capabilities, wlan_change_capabilities, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_hotlist_monitor_capabilities, hotlist_capabilities, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_CAPABILITIES_EVENTID); /* ExtScan Hot List Match Event */ -#define WMITLV_TABLE_WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_hotlist_ssid_match_event_fixed_param, wmi_extscan_hotlist_ssid_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_descriptor, hotlist_ssid_match, WMITLV_SIZE_VAR) - +#define WMITLV_TABLE_WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_extscan_hotlist_ssid_match_event_fixed_param, wmi_extscan_hotlist_ssid_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_extscan_wlan_descriptor, hotlist_ssid_match, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID); /* Update_whal_mib_stats Event */ -#define WMITLV_TABLE_WMI_UPDATE_WHAL_MIB_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_update_whal_mib_stats_event_fixed_param, wmi_update_whal_mib_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_UPDATE_WHAL_MIB_STATS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_update_whal_mib_stats_event_fixed_param, wmi_update_whal_mib_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_WHAL_MIB_STATS_EVENTID); /* PDEV TPC Config Event */ -#define WMITLV_TABLE_WMI_PDEV_TPC_CONFIG_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param, wmi_pdev_tpc_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ratesArray, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_TPC_CONFIG_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param, wmi_pdev_tpc_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ratesArray, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TPC_CONFIG_EVENTID); /* Channel Info Event */ -#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID); /* Phy Error Event */ -#define WMITLV_TABLE_WMI_PHYERR_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr, wmi_comb_phyerr_rx_hdr, hdr, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PHYERR_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr, wmi_comb_phyerr_rx_hdr, hdr, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PHYERR_EVENTID); /* TX Pause/Unpause event */ -#define WMITLV_TABLE_WMI_TX_PAUSE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_pause_event_fixed_param, wmi_tx_pause_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_TX_PAUSE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_pause_event_fixed_param, wmi_tx_pause_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TX_PAUSE_EVENTID); /* Mgmt TX completion event */ -#define WMITLV_TABLE_WMI_MGMT_TX_COMPLETION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_event_fixed_param, wmi_mgmt_tx_compl_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_MGMT_TX_COMPLETION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_event_fixed_param, wmi_mgmt_tx_compl_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_COMPLETION_EVENTID); /* Bundled Mgmt TX completion event */ -#define WMITLV_TABLE_WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_bundle_event_fixed_param, wmi_mgmt_tx_compl_bundle_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, desc_ids, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, status, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_bundle_event_fixed_param, wmi_mgmt_tx_compl_bundle_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, desc_ids, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, status, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID); /* VDEV Start response Event */ -#define WMITLV_TABLE_WMI_VDEV_START_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_START_RESP_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_RESP_EVENTID); /* VDEV Stopped Event */ -#define WMITLV_TABLE_WMI_VDEV_STOPPED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_STOPPED_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOPPED_EVENTID); /* VDEV delete response Event */ -#define WMITLV_TABLE_WMI_VDEV_DELETE_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_delete_resp_event_fixed_param, wmi_vdev_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_DELETE_RESP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_delete_resp_event_fixed_param, wmi_vdev_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_RESP_EVENTID); /* VDEV Install Key Complete Event */ -#define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID); /* Peer STA Kickout Event */ -#define WMITLV_TABLE_WMI_PEER_STA_KICKOUT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_sta_kickout_event_fixed_param, wmi_peer_sta_kickout_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_STA_KICKOUT_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_sta_kickout_event_fixed_param, wmi_peer_sta_kickout_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID); /* Management Rx Event */ -#define WMITLV_TABLE_WMI_MGMT_RX_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr, wmi_mgmt_rx_hdr, hdr, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_MGMT_RX_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr, wmi_mgmt_rx_hdr, hdr, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID); /* TBTT offset Event */ -#define WMITLV_TABLE_WMI_TBTTOFFSET_UPDATE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param, wmi_tbtt_offset_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tbttoffset_list, WMITLV_SIZE_FIX, WMI_MAX_AP_VDEV) +#define WMITLV_TABLE_WMI_TBTTOFFSET_UPDATE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param, wmi_tbtt_offset_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tbttoffset_list, WMITLV_SIZE_FIX, WMI_MAX_AP_VDEV) WMITLV_CREATE_PARAM_STRUC(WMI_TBTTOFFSET_UPDATE_EVENTID); +/* TBTT EXT offset Event */ +#define WMITLV_TABLE_WMI_TBTTOFFSET_EXT_UPDATE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_tbtt_offset_ext_event_fixed_param, wmi_tbtt_offset_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_tbtt_offset_info, tbtt_offset_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_TBTTOFFSET_EXT_UPDATE_EVENTID); + /* TX DELBA Complete Event */ -#define WMITLV_TABLE_WMI_TX_DELBA_COMPLETE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_delba_complete_event_fixed_param, wmi_tx_delba_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_TX_DELBA_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_delba_complete_event_fixed_param, wmi_tx_delba_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TX_DELBA_COMPLETE_EVENTID); /* Tx ADDBA Complete Event */ -#define WMITLV_TABLE_WMI_TX_ADDBA_COMPLETE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_addba_complete_event_fixed_param, wmi_tx_addba_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_TX_ADDBA_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_addba_complete_event_fixed_param, wmi_tx_addba_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TX_ADDBA_COMPLETE_EVENTID); /* ADD BA Req ssn Event */ -#define WMITLV_TABLE_WMI_BA_RSP_SSN_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ba_rsp_ssn_event_fixed_param, wmi_ba_rsp_ssn_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_ba_event_ssn, ba_event_ssn_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_BA_RSP_SSN_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ba_rsp_ssn_event_fixed_param, wmi_ba_rsp_ssn_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_ba_event_ssn, ba_event_ssn_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_BA_RSP_SSN_EVENTID); /* Aggregation Request event */ -#define WMITLV_TABLE_WMI_AGGR_STATE_TRIG_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_aggr_state_trig_event_fixed_param, wmi_aggr_state_trig_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_AGGR_STATE_TRIG_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_aggr_state_trig_event_fixed_param, wmi_aggr_state_trig_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID); /* Roam Event */ -#define WMITLV_TABLE_WMI_ROAM_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, wmi_roam_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_ROAM_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, wmi_roam_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); /* Roam Synch Event */ -#define WMITLV_TABLE_WMI_ROAM_SYNCH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param, wmi_roam_synch_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bcn_probe_rsp_frame, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reassoc_rsp_frame, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_key_material, key, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, status, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reassoc_req_frame, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_ROAM_SYNCH_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param, wmi_roam_synch_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bcn_probe_rsp_frame, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reassoc_rsp_frame, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_key_material, key, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, status, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reassoc_req_frame, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID); /* WOW Wakeup Host Event */ /* NOTE: Make sure wow_bitmap_info can be zero or one elements only */ -#define WMITLV_TABLE_WMI_WOW_WAKEUP_HOST_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param, WOW_EVENT_INFO_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_EVENT_INFO_SECTION_BITMAP, wow_bitmap_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, wow_packet_buffer, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hb_ind_event_fixed_param, hb_indevt, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, wow_gtkigtk, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_WOW_WAKEUP_HOST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param, WOW_EVENT_INFO_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WOW_EVENT_INFO_SECTION_BITMAP, wow_bitmap_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, wow_packet_buffer, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hb_ind_event_fixed_param, hb_indevt, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, wow_gtkigtk, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_WAKEUP_HOST_EVENTID); -#define WMITLV_TABLE_WMI_WOW_INITIAL_WAKEUP_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WOW_EVENT_INITIAL_WAKEUP_fixed_param, WOW_INITIAL_WAKEUP_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WOW_INITIAL_WAKEUP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_WOW_EVENT_INITIAL_WAKEUP_fixed_param, WOW_INITIAL_WAKEUP_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WOW_INITIAL_WAKEUP_EVENTID); + /* RTT error report Event */ -#define WMITLV_TABLE_WMI_RTT_ERROR_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_RTT_ERROR_REPORT_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RTT_ERROR_REPORT_EVENTID); /* Echo Event */ -#define WMITLV_TABLE_WMI_ECHO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_echo_event_fixed_param, wmi_echo_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_ECHO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_echo_event_fixed_param, wmi_echo_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ECHO_EVENTID); /* FTM Integration Event */ #define WMITLV_TABLE_WMI_PDEV_FTM_INTG_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ftm_intg_event_fixed_param, wmi_ftm_intg_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ftm_intg_event_fixed_param, wmi_ftm_intg_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FTM_INTG_EVENTID); /* VDEV get Keepalive Event */ -#define WMITLV_TABLE_WMI_VDEV_GET_KEEPALIVE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param, wmi_vdev_get_keepalive_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_VDEV_GET_KEEPALIVE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param, wmi_vdev_get_keepalive_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_KEEPALIVE_EVENTID); /* GPIO Input Event */ #define WMITLV_TABLE_WMI_GPIO_INPUT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_INPUT_EVENTID); /* CSA Handling Event */ -#define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CSA_HANDLING_EVENTID); /* Rfkill state change Event */ -#define WMITLV_TABLE_WMI_RFKILL_STATE_CHANGE_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rfkill_event_fixed_param, wmi_rfkill_mode_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_RFKILL_STATE_CHANGE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rfkill_event_fixed_param, wmi_rfkill_mode_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RFKILL_STATE_CHANGE_EVENTID); - /* Debug Message Event */ -#define WMITLV_TABLE_WMI_DEBUG_MESG_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_DEBUG_MESG_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DEBUG_MESG_EVENTID); -#define WMITLV_TABLE_WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param, wmi_debug_mesg_flush_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param, wmi_debug_mesg_flush_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID); -#define WMITLV_TABLE_WMI_RSSI_BREACH_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rssi_breach_event_fixed_param, wmi_rssi_breach_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_RSSI_BREACH_EVENTID(id, op, buf, len)\ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rssi_breach_event_fixed_param, wmi_rssi_breach_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RSSI_BREACH_EVENTID); -#define WMITLV_TABLE_WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_complete_event_fixed_param, wmi_transfer_data_to_flash_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID(id, op, buf, len)\ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_complete_event_fixed_param, wmi_transfer_data_to_flash_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID); -#define WMITLV_TABLE_WMI_READ_DATA_FROM_FLASH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_read_data_from_flash_event_fixed_param, wmi_read_data_from_flash_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_READ_DATA_FROM_FLASH_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_read_data_from_flash_event_fixed_param, wmi_read_data_from_flash_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_READ_DATA_FROM_FLASH_EVENTID); /* Diagnostics Event */ -#define WMITLV_TABLE_WMI_DIAG_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_DIAG_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENTID); /* IGTK Offload Event */ -#define WMITLV_TABLE_WMI_GTK_OFFLOAD_STATUS_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_GTK_OFFLOAD_STATUS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_STATUS_EVENTID); /* DCA interferance Event */ -#define WMITLV_TABLE_WMI_DCS_INTERFERENCE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, wmi_dcs_interference_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_cw_int, cw_int, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_im_tgt_stats_t, wlan_stat, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_DCS_INTERFERENCE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, wmi_dcs_interference_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_cw_int, cw_int, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_im_tgt_stats_t, wlan_stat, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DCS_INTERFERENCE_EVENTID); /* Profile data Event */ #define WMITLV_TABLE_WMI_WLAN_PROFILE_DATA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_ctx_t, wmi_wlan_profile_ctx_t, profile_ctx, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wlan_profile_t, profile_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_profile_ctx_t, wmi_wlan_profile_ctx_t, profile_ctx, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wlan_profile_t, profile_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_PROFILE_DATA_EVENTID); /* PDEV UTF Event */ -#define WMITLV_TABLE_WMI_PDEV_UTF_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_UTF_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UTF_EVENTID); /* Update SCPC calibrated data Event */ -#define WMITLV_TABLE_WMI_PDEV_UTF_SCPC_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scpc_event_fixed_param, wmi_scpc_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_UTF_SCPC_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_scpc_event_fixed_param, wmi_scpc_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UTF_SCPC_EVENTID); /* Debug print Event */ #define WMITLV_TABLE_WMI_DEBUG_PRINT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DEBUG_PRINT_EVENTID); /* RTT measurement report Event - DEPRECATED */ #define WMITLV_TABLE_WMI_RTT_MEASUREMENT_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RTT_MEASUREMENT_REPORT_EVENTID); -/*oem measurement report Event - DEPRECATED */ +/* oem measurement report Event - DEPRECATED */ #define WMITLV_TABLE_WMI_OEM_MEASUREMENT_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_MEASUREMENT_REPORT_EVENTID); -/*oem error report event - DEPRECATED */ +/* oem error report event - DEPRECATED */ #define WMITLV_TABLE_WMI_OEM_ERROR_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_ERROR_REPORT_EVENTID); -/*oem capability report event - DEPRECATED */ +/* oem capability report event - DEPRECATED */ #define WMITLV_TABLE_WMI_OEM_CAPABILITY_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_CAPABILITY_EVENTID); -/*oem response event*/ -#define WMITLV_TABLE_WMI_OEM_RESPONSE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +/* oem response event */ +#define WMITLV_TABLE_WMI_OEM_RESPONSE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_RESPONSE_EVENTID); /* HOST SWBA Event */ #define WMITLV_TABLE_WMI_HOST_SWBA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, wmi_host_swba_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tim_info, tim_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, wmi_host_swba_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tim_info, tim_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_HOST_SWBA_EVENTID); - /* Update stats Event */ -#define WMITLV_TABLE_WMI_UPDATE_STATS_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stats_event_fixed_param, wmi_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats, wmi_per_chain_rssi_stats, chain_stats, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_stats, rssi_stats, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_UPDATE_STATS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_stats_event_fixed_param, wmi_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats, wmi_per_chain_rssi_stats, chain_stats, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_stats, rssi_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_STATS_EVENTID); /* For vdev based ht/vht info upload*/ -#define WMITLV_TABLE_WMI_UPDATE_VDEV_RATE_STATS_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, wmi_vdev_rate_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_rate_ht_info, ht_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_UPDATE_VDEV_RATE_STATS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, wmi_vdev_rate_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_rate_ht_info, ht_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_VDEV_RATE_STATS_EVENTID); +/* report rx aggregation failure information */ +#define WMITLV_TABLE_WMI_REPORT_RX_AGGR_FAILURE_EVENTID(id, op, buf, len)\ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rx_aggr_failure_event_fixed_param, wmi_rx_aggr_failure_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_rx_aggr_failure_info, failure_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_REPORT_RX_AGGR_FAILURE_EVENTID); + /* Update memory dump complete Event */ #define WMITLV_TABLE_WMI_UPDATE_FW_MEM_DUMP_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_update_fw_mem_dump_fixed_param, wmi_update_fw_mem_dump_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_update_fw_mem_dump_fixed_param, wmi_update_fw_mem_dump_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_FW_MEM_DUMP_EVENTID); /* Event indicating the DIAG LOGs/Events supported by FW */ -#define WMITLV_TABLE_WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_diag_event_log_supported_event_fixed_params, wmi_diag_event_log_supported_event_fixed_params, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, diag_events_logs_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_diag_event_log_supported_event_fixed_params, wmi_diag_event_log_supported_event_fixed_params, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, diag_events_logs_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID); + /* Update iface link stats Event */ -#define WMITLV_TABLE_WMI_IFACE_LINK_STATS_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param, wmi_iface_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_IFACE_LINK_STATS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param, wmi_iface_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_LINK_STATS_EVENTID); /* Update Peer link stats Event */ -#define WMITLV_TABLE_WMI_PEER_LINK_STATS_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_stats_event_fixed_param, wmi_peer_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_link_stats, peer_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rate_stats, peer_rate_stats, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PEER_LINK_STATS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_stats_event_fixed_param, wmi_peer_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_link_stats, peer_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rate_stats, peer_rate_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_LINK_STATS_EVENTID); /* Update radio stats Event */ -#define WMITLV_TABLE_WMI_RADIO_LINK_STATS_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_radio_link_stats_event_fixed_param, wmi_radio_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_radio_link_stats, radio_stats, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel_stats, channel_stats, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_RADIO_LINK_STATS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_radio_link_stats_event_fixed_param, wmi_radio_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_radio_link_stats, radio_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_channel_stats, channel_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_LINK_STATS_EVENTID); /* PDEV QVIT Event */ -#define WMITLV_TABLE_WMI_PDEV_QVIT_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_QVIT_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_QVIT_EVENTID); /* WLAN Frequency avoid Event */ -#define WMITLV_TABLE_WMI_WLAN_FREQ_AVOID_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_avoid_freq_ranges_event_fixed_param, wmi_avoid_freq_ranges_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_avoid_freq_range_desc, avd_freq_range, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_WLAN_FREQ_AVOID_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_avoid_freq_ranges_event_fixed_param, wmi_avoid_freq_ranges_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_avoid_freq_range_desc, avd_freq_range, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_FREQ_AVOID_EVENTID); /* GTK rekey fail Event */ -#define WMITLV_TABLE_WMI_GTK_REKEY_FAIL_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gtk_rekey_fail_event_fixed_param, wmi_gtk_rekey_fail_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_GTK_REKEY_FAIL_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gtk_rekey_fail_event_fixed_param, wmi_gtk_rekey_fail_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GTK_REKEY_FAIL_EVENTID); /* NLO match event */ -#define WMITLV_TABLE_WMI_NLO_MATCH_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_event, wmi_nlo_event, fixed_param, WMITLV_SIZE_FIX) - WMITLV_CREATE_PARAM_STRUC(WMI_NLO_MATCH_EVENTID); +#define WMITLV_TABLE_WMI_NLO_MATCH_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_event, wmi_nlo_event, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_NLO_MATCH_EVENTID); /* NLO scan complete event */ -#define WMITLV_TABLE_WMI_NLO_SCAN_COMPLETE_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_event, wmi_nlo_event, fixed_param, WMITLV_SIZE_FIX) - WMITLV_CREATE_PARAM_STRUC(WMI_NLO_SCAN_COMPLETE_EVENTID); +#define WMITLV_TABLE_WMI_NLO_SCAN_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_event, wmi_nlo_event, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_NLO_SCAN_COMPLETE_EVENTID); /* APFIND event */ #define WMITLV_TABLE_WMI_APFIND_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_apfind_event_hdr, wmi_apfind_event_hdr, hdr, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) - WMITLV_CREATE_PARAM_STRUC(WMI_APFIND_EVENTID); + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_apfind_event_hdr, wmi_apfind_event_hdr, hdr, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_APFIND_EVENTID); /* WMI_PASSPOINT_MATCH_EVENTID */ #define WMITLV_TABLE_WMI_PASSPOINT_MATCH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_passpoint_event_hdr, wmi_passpoint_event_hdr, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) - WMITLV_CREATE_PARAM_STRUC(WMI_PASSPOINT_MATCH_EVENTID); + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_passpoint_event_hdr, wmi_passpoint_event_hdr, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PASSPOINT_MATCH_EVENTID); /* Chatter query reply event */ #define WMITLV_TABLE_WMI_CHATTER_PC_QUERY_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_query_reply_event_fixed_param, wmi_chatter_query_reply_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) - WMITLV_CREATE_PARAM_STRUC(WMI_CHATTER_PC_QUERY_EVENTID); + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chatter_query_reply_event_fixed_param, wmi_chatter_query_reply_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CHATTER_PC_QUERY_EVENTID); /* Upload H_CV info event */ #define WMITLV_TABLE_WMI_UPLOADH_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_upload_h_hdr, wmi_upload_h_hdr, hdr, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) - WMITLV_CREATE_PARAM_STRUC(WMI_UPLOADH_EVENTID); + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_upload_h_hdr, wmi_upload_h_hdr, hdr, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_UPLOADH_EVENTID); /* Capture H info event */ #define WMITLV_TABLE_WMI_CAPTUREH_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_capture_h_event_hdr, wmi_capture_h_event_hdr, fixed_param, WMITLV_SIZE_FIX) - WMITLV_CREATE_PARAM_STRUC(WMI_CAPTUREH_EVENTID); - + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_capture_h_event_hdr, wmi_capture_h_event_hdr, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CAPTUREH_EVENTID); /* TDLS Peer Update event */ -#define WMITLV_TABLE_WMI_TDLS_PEER_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_peer_event_fixed_param, wmi_tdls_peer_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) - WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_PEER_EVENTID); +#define WMITLV_TABLE_WMI_TDLS_PEER_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_peer_event_fixed_param, wmi_tdls_peer_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_PEER_EVENTID); /* VDEV MCC Beacon Interval Change Request Event */ -#define WMITLV_TABLE_WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_mcc_bcn_intvl_change_event_fixed_param, wmi_vdev_mcc_bcn_intvl_change_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID); +#define WMITLV_TABLE_WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_mcc_bcn_intvl_change_event_fixed_param, wmi_vdev_mcc_bcn_intvl_change_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC + (WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID); -#define WMITLV_TABLE_WMI_BATCH_SCAN_ENABLED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_enabled_event_fixed_param, wmi_batch_scan_enabled_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_BATCH_SCAN_ENABLED_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_enabled_event_fixed_param, wmi_batch_scan_enabled_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_BATCH_SCAN_ENABLED_EVENTID); #define WMITLV_TABLE_WMI_BATCH_SCAN_RESULT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_result_event_fixed_param, wmi_batch_scan_result_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_ARRAY_STRUC, wmi_batch_scan_result_scan_list, scan_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_ARRAY_STRUC, wmi_batch_scan_result_network_info, network_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_batch_scan_result_event_fixed_param, wmi_batch_scan_result_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_ARRAY_STRUC, wmi_batch_scan_result_scan_list, scan_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_ARRAY_STRUC, wmi_batch_scan_result_network_info, network_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_BATCH_SCAN_RESULT_EVENTID); #define WMITLV_TABLE_WMI_OFFLOAD_BCN_TX_STATUS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_offload_bcn_tx_status_event_fixed_param, wmi_offload_bcn_tx_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_offload_bcn_tx_status_event_fixed_param, wmi_offload_bcn_tx_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OFFLOAD_BCN_TX_STATUS_EVENTID); /* NOA Event */ -#define WMITLV_TABLE_WMI_P2P_NOA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_noa_event_fixed_param, wmi_p2p_noa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_noa_info, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_P2P_NOA_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_noa_event_fixed_param, wmi_p2p_noa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_p2p_noa_info, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_NOA_EVENTID); -/* AP PS enhanced green ap Event */ -#define WMITLV_TABLE_WMI_AP_PS_EGAP_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_event_fixed_param, wmi_ap_ps_egap_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ap_ps_egap_info_chainmask_list, chainmask_list, WMITLV_SIZE_VAR) + /* AP PS enhanced green ap Event */ +#define WMITLV_TABLE_WMI_AP_PS_EGAP_INFO_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len,\ + WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_event_fixed_param,\ + wmi_ap_ps_egap_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC,\ + wmi_ap_ps_egap_info_chainmask_list, chainmask_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_AP_PS_EGAP_INFO_EVENTID); -#define WMITLV_TABLE_WMI_PEER_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_info_event_fixed_param, wmi_peer_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_info, peer_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PEER_INFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_info_event_fixed_param, wmi_peer_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_info, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_INFO_EVENTID); -#define WMITLV_TABLE_WMI_PEER_ANTDIV_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_antdiv_info_event_fixed_param, wmi_peer_antdiv_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_antdiv_info, peer_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PEER_ANTDIV_INFO_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_antdiv_info_event_fixed_param, wmi_peer_antdiv_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_antdiv_info, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ANTDIV_INFO_EVENTID); -#define WMITLV_TABLE_WMI_PEER_TX_FAIL_CNT_THR_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tx_fail_cnt_thr_event_fixed_param, wmi_peer_tx_fail_cnt_thr_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_TX_FAIL_CNT_THR_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tx_fail_cnt_thr_event_fixed_param, wmi_peer_tx_fail_cnt_thr_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_FAIL_CNT_THR_EVENTID); /* DFS radar Event */ #define WMITLV_TABLE_WMI_DFS_RADAR_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dfs_radar_event_fixed_param, wmi_dfs_radar_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dfs_radar_event_fixed_param, wmi_dfs_radar_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DFS_RADAR_EVENTID); +#define WMITLV_TABLE_WMI_PDEV_DFS_RADAR_DETECTION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID); + +#define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_adfs_ocac_complete_event_fixed_param, wmi_vdev_adfs_ocac_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID); + +#define WMITLV_TABLE_WMI_VDEV_DFS_CAC_COMPLETE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_dfs_cac_complete_event_fixed_param, wmi_vdev_dfs_cac_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DFS_CAC_COMPLETE_EVENTID); + /* Thermal Event */ #define WMITLV_TABLE_WMI_THERMAL_MGMT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_event_fixed_param, wmi_thermal_mgmt_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_event_fixed_param, wmi_thermal_mgmt_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_THERMAL_MGMT_EVENTID); /* NAN Response/Indication Event */ -#define WMITLV_TABLE_WMI_NAN_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_event_hdr, wmi_nan_event_hdr, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NAN_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_event_hdr, wmi_nan_event_hdr, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_EVENTID); /* NAN discovery interface created event */ -#define WMITLV_TABLE_WMI_NAN_DISC_IFACE_CREATED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param, wmi_nan_disc_iface_created_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NAN_DISC_IFACE_CREATED_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param, wmi_nan_disc_iface_created_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_IFACE_CREATED_EVENTID); /* NAN discovery interface deleted event */ -#define WMITLV_TABLE_WMI_NAN_DISC_IFACE_DELETED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_iface_deleted_event_fixed_param, wmi_nan_disc_iface_deleted_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NAN_DISC_IFACE_DELETED_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_nan_disc_iface_deleted_event_fixed_param, wmi_nan_disc_iface_deleted_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_IFACE_DELETED_EVENTID); /* NAN device started new cluster event */ -#define WMITLV_TABLE_WMI_NAN_STARTED_CLUSTER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_started_cluster_event_fixed_param, wmi_nan_started_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NAN_STARTED_CLUSTER_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_nan_started_cluster_event_fixed_param, wmi_nan_started_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_STARTED_CLUSTER_EVENTID); /* NAN device joined to cluster event */ -#define WMITLV_TABLE_WMI_NAN_JOINED_CLUSTER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NAN_JOINED_CLUSTER_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_JOINED_CLUSTER_EVENTID); /* Coex report antenna isolation event */ -#define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID); /* NDP capabilities response event */ -#define WMITLV_TABLE_WMI_NDI_CAP_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_cap_rsp_event_fixed_param, wmi_ndi_cap_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NDI_CAP_RSP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndi_cap_rsp_event_fixed_param, wmi_ndi_cap_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NDI_CAP_RSP_EVENTID); /* NDP initiator response event */ -#define WMITLV_TABLE_WMI_NDP_INITIATOR_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_initiator_rsp_event_fixed_param, wmi_ndp_initiator_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NDP_INITIATOR_RSP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_initiator_rsp_event_fixed_param, wmi_ndp_initiator_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INITIATOR_RSP_EVENTID); /* NDP responder response event */ -#define WMITLV_TABLE_WMI_NDP_RESPONDER_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param, wmi_ndp_responder_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_NDP_RESPONDER_RSP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param, wmi_ndp_responder_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_RESPONDER_RSP_EVENTID); -/** NDP end response event +/** + * NDP end response event * * TLV (tag length value ) parameters follow the ndp_end_rsp * structure. The TLV's are: * wmi_ndp_end_rsp_per_ndi ndp_end_rsp_per_ndi_list[]; * wmi_active_ndp_instance_id active_ndp_instances_id[]; */ -#define WMITLV_TABLE_WMI_NDP_END_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_end_rsp_event_fixed_param, wmi_ndp_end_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_rsp_per_ndi_PROTOTYPE, ndp_end_rsp_per_ndi_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_active_ndp_instance_id_PROTOTYPE, active_ndp_instances_id, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_END_RSP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_end_rsp_event_fixed_param, wmi_ndp_end_rsp_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_rsp_per_ndi_PROTOTYPE, ndp_end_rsp_per_ndi_list, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_active_ndp_instance_id_PROTOTYPE, active_ndp_instances_id, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_RSP_EVENTID); -/** NDP indication event +/** + * NDP indication event * * TLV (tag length value ) parameters follow the ndp_indication * structure. The TLV's are: * A_UINT8 ndp_cfg[]; * A_UINT8 ndp_app_info[]; */ -#define WMITLV_TABLE_WMI_NDP_INDICATION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param, wmi_ndp_indication_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_INDICATION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param, wmi_ndp_indication_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INDICATION_EVENTID); -/** NDP confirm event +/** + * NDP confirm event * TLV (tag length value ) parameters follow the ndp_confirm * structure. The TLV's are: * A_UINT8 ndp_cfg[]; * A_UINT8 ndp_app_info[]; */ -#define WMITLV_TABLE_WMI_NDP_CONFIRM_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param, wmi_ndp_confirm_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_CONFIRM_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param, wmi_ndp_confirm_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CONFIRM_EVENTID); -/** NDP end indication event +/** + * NDP end indication event * * TLV (tag length value ) parameters follow the ndp_end_indication * structure. The TLV's are: * wmi_ndp_end_indication ndp_end_indication_list[]; */ -#define WMITLV_TABLE_WMI_NDP_END_INDICATION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_indication_PROTOTYPE, ndp_end_indication_list, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_NDP_END_INDICATION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_indication_PROTOTYPE, ndp_end_indication_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_INDICATION_EVENTID); /* L1SS track Event */ -#define WMITLV_TABLE_WMI_PDEV_L1SS_TRACK_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_l1ss_track_event_fixed_param, wmi_pdev_l1ss_track_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_L1SS_TRACK_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_l1ss_track_event_fixed_param, wmi_pdev_l1ss_track_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_L1SS_TRACK_EVENTID); #define WMITLV_TABLE_WMI_DIAG_DATA_CONTAINER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_diag_data_container_event_fixed_param, wmi_diag_data_container_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_diag_data_container_event_fixed_param, wmi_diag_data_container_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_DATA_CONTAINER_EVENTID); /* Estimated Link Speed Indication*/ #define WMITLV_TABLE_WMI_PEER_ESTIMATED_LINKSPEED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_estimated_linkspeed_event_fixed_param, wmi_peer_estimated_linkspeed_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_estimated_linkspeed_event_fixed_param, wmi_peer_estimated_linkspeed_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ESTIMATED_LINKSPEED_EVENTID); -/* NAN Response/Indication Event */ -#define WMITLV_TABLE_WMI_STATS_EXT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, wmi_stats_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_STATS_EXT_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, wmi_stats_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_STATS_EXT_EVENTID); #define WMITLV_TABLE_WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_offload_prb_rsp_tx_status_event_fixed_param, wmi_offload_prb_rsp_tx_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_offload_prb_rsp_tx_status_event_fixed_param, wmi_offload_prb_rsp_tx_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID); /* host auto shut down event */ #define WMITLV_TABLE_WMI_HOST_AUTO_SHUTDOWN_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_auto_shutdown_event_fixed_param, wmi_host_auto_shutdown_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_auto_shutdown_event_fixed_param, wmi_host_auto_shutdown_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HOST_AUTO_SHUTDOWN_EVENTID); /* peer state Event */ -#define WMITLV_TABLE_WMI_PEER_STATE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_state_event_fixed_param, wmi_peer_state_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_STATE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_state_event_fixed_param, wmi_peer_state_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATE_EVENTID); /* peer delete response Event */ -#define WMITLV_TABLE_WMI_PEER_DELETE_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_DELETE_RESP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_RESP_EVENTID); /* peer assoc conf Event */ -#define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID); /* D0-WOW Disable Ack event */ #define WMITLV_TABLE_WMI_D0_WOW_DISABLE_ACK_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param, wmi_d0_wow_disable_ack_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param, wmi_d0_wow_disable_ack_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_D0_WOW_DISABLE_ACK_EVENTID); /* Pdev get chip temperature event */ #define WMITLV_TABLE_WMI_PDEV_TEMPERATURE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_temperature_event_fixed_param, wmi_pdev_temperature_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_temperature_event_fixed_param, wmi_pdev_temperature_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TEMPERATURE_EVENTID); /* Pdev get ANT DIV feature status event */ -#define WMITLV_TABLE_WMI_PDEV_ANTDIV_STATUS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_antdiv_status_event_fixed_param, wmi_pdev_antdiv_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_ANTDIV_STATUS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_antdiv_status_event_fixed_param, wmi_pdev_antdiv_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANTDIV_STATUS_EVENTID); /* mDNS offload stats event */ #define WMITLV_TABLE_WMI_MDNS_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_stats_event_fixed_param, wmi_mdns_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mdns_stats_event_fixed_param, wmi_mdns_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_STATS_EVENTID); /* pdev resume event */ #define WMITLV_TABLE_WMI_PDEV_RESUME_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param, wmi_pdev_resume_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param, wmi_pdev_resume_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_EVENTID); /* SAP Authentication offload event */ #define WMITLV_TABLE_WMI_SAP_OFL_ADD_STA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param, wmi_sap_ofl_add_sta_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param, wmi_sap_ofl_add_sta_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SAP_OFL_ADD_STA_EVENTID); #define WMITLV_TABLE_WMI_SAP_OFL_DEL_STA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_del_sta_event_fixed_param, wmi_sap_ofl_del_sta_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_del_sta_event_fixed_param, wmi_sap_ofl_del_sta_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SAP_OFL_DEL_STA_EVENTID); -/* Set OCB schedule event, DEPRECATED */ +/* Set OCB schedule cmd, DEPRECATED */ #define WMITLV_TABLE_WMI_OCB_SET_SCHED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ocb_set_sched_event_fixed_param, wmi_ocb_set_sched_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ocb_set_sched_event_fixed_param, wmi_ocb_set_sched_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_SET_SCHED_EVENTID); /* Set OCB configuration response event */ #define WMITLV_TABLE_WMI_OCB_SET_CONFIG_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_set_config_resp_event_fixed_param, wmi_ocb_set_config_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_set_config_resp_event_fixed_param, wmi_ocb_set_config_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_SET_CONFIG_RESP_EVENTID); /* Get TSF timer response event */ #define WMITLV_TABLE_WMI_OCB_GET_TSF_TIMER_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_resp_event_fixed_param, wmi_ocb_get_tsf_timer_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_resp_event_fixed_param, wmi_ocb_get_tsf_timer_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_OCB_GET_TSF_TIMER_RESP_EVENTID); /* Get DCC stats response event */ #define WMITLV_TABLE_WMI_DCC_GET_STATS_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_get_stats_resp_event_fixed_param, wmi_dcc_get_stats_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_stats_per_channel, stats_per_channel_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_get_stats_resp_event_fixed_param, wmi_dcc_get_stats_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_stats_per_channel, stats_per_channel_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DCC_GET_STATS_RESP_EVENTID); /* Update DCC NDL response event */ #define WMITLV_TABLE_WMI_DCC_UPDATE_NDL_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_update_ndl_resp_event_fixed_param, wmi_dcc_update_ndl_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_update_ndl_resp_event_fixed_param, wmi_dcc_update_ndl_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_DCC_UPDATE_NDL_RESP_EVENTID); /* DCC stats event */ #define WMITLV_TABLE_WMI_DCC_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_stats_event_fixed_param, wmi_dcc_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_stats_per_channel, stats_per_channel_list, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcc_stats_event_fixed_param, wmi_dcc_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dcc_ndl_stats_per_channel, stats_per_channel_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_DCC_STATS_EVENTID); /* Read TSF timer response event */ @@ -3762,176 +3839,173 @@ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_tsf_report_event_fixed_para WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TSF_REPORT_EVENTID); /* Vdev capabilities IE to be transmitted in mgmt frames */ -#define WMITLV_TABLE_WMI_VDEV_SET_IE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_ie_cmd_fixed_param, wmi_vdev_set_ie_cmd_fixed_param, vdev_ie, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_VDEV_SET_IE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_ie_cmd_fixed_param, wmi_vdev_set_ie_cmd_fixed_param, vdev_ie, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_IE_CMDID); /* SOC Set Hardware Mode Response event - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_SET_HW_MODE_RESP_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_event_fixed_param, wmi_soc_set_hw_mode_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_soc_set_hw_mode_response_vdev_mac_entry, wmi_soc_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SOC_SET_HW_MODE_RESP_EVENTID(id, op, buf, len) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_event_fixed_param, wmi_soc_set_hw_mode_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_soc_set_hw_mode_response_vdev_mac_entry, wmi_soc_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_SET_HW_MODE_RESP_EVENTID); /* PDEV Set Hardware Mode Response event */ -#define WMITLV_TABLE_WMI_PDEV_SET_HW_MODE_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_event_fixed_param, wmi_pdev_set_hw_mode_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_SET_HW_MODE_RESP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_event_fixed_param, wmi_pdev_set_hw_mode_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_HW_MODE_RESP_EVENTID); /* SOC Hardware Mode Transition event - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_HW_MODE_TRANSITION_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_hw_mode_transition_event_fixed_param, wmi_soc_hw_mode_transition_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_soc_set_hw_mode_response_vdev_mac_entry, wmi_soc_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_SOC_HW_MODE_TRANSITION_EVENTID(id, op, buf, len) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_hw_mode_transition_event_fixed_param, wmi_soc_hw_mode_transition_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_soc_set_hw_mode_response_vdev_mac_entry, wmi_soc_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_HW_MODE_TRANSITION_EVENTID); /* PDEV Hardware Mode Transition event */ -#define WMITLV_TABLE_WMI_PDEV_HW_MODE_TRANSITION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_hw_mode_transition_event_fixed_param, wmi_pdev_hw_mode_transition_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_HW_MODE_TRANSITION_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_hw_mode_transition_event_fixed_param, wmi_pdev_hw_mode_transition_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_HW_MODE_TRANSITION_EVENTID); /* SOC Set Dual MAC Config Response event - DEPRECATED */ -#define WMITLV_TABLE_WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_response_event_fixed_param, wmi_soc_set_dual_mac_config_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_response_event_fixed_param, wmi_soc_set_dual_mac_config_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID); /* PDEV Set Dual MAC Config Response event */ -#define WMITLV_TABLE_WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_response_event_fixed_param, wmi_pdev_set_mac_config_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_response_event_fixed_param, wmi_pdev_set_mac_config_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID); /* Packet Filter configure command*/ -#define WMITLV_TABLE_WMI_PACKET_FILTER_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_packet_filter_config_fixed_param, WMI_PACKET_FILTER_CONFIG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PACKET_FILTER_CONFIG_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_packet_filter_config_fixed_param, WMI_PACKET_FILTER_CONFIG_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PACKET_FILTER_CONFIG_CMDID); /* Packet Filter enable command*/ -#define WMITLV_TABLE_WMI_PACKET_FILTER_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_packet_filter_enable_fixed_param, WMI_PACKET_FILTER_ENABLE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PACKET_FILTER_ENABLE_CMDID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_packet_filter_enable_fixed_param, WMI_PACKET_FILTER_ENABLE_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PACKET_FILTER_ENABLE_CMDID); /* MAWC enable/disable sensor event */ -#define WMITLV_TABLE_WMI_MAWC_ENABLE_SENSOR_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mawc_enable_sensor_event_fixed_param, wmi_mawc_enable_sensor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_MAWC_ENABLE_SENSOR_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_mawc_enable_sensor_event_fixed_param, wmi_mawc_enable_sensor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MAWC_ENABLE_SENSOR_EVENTID); /* SMPS force mode complete Event */ -#define WMITLV_TABLE_WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_complete_event_fixed_param, wmi_sta_smps_force_mode_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_complete_event_fixed_param, wmi_sta_smps_force_mode_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID); /* bpf offload capability info event */ -#define WMITLV_TABLE_WMI_BPF_CAPABILIY_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_capability_info_evt_fixed_param, wmi_bpf_capability_info_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_BPF_CAPABILIY_INFO_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_bpf_capability_info_evt_fixed_param, wmi_bpf_capability_info_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_BPF_CAPABILIY_INFO_EVENTID); /* bpf offload vdev status info event */ -#define WMITLV_TABLE_WMI_BPF_VDEV_STATS_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_vdev_stats_info_evt_fixed_param, wmi_bpf_vdev_stats_info_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_BPF_VDEV_STATS_INFO_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_bpf_vdev_stats_info_evt_fixed_param, wmi_bpf_vdev_stats_info_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_BPF_VDEV_STATS_INFO_EVENTID); /* FIPS event */ -#define WMITLV_TABLE_WMI_PDEV_FIPS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param, wmi_pdev_fips_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_FIPS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param, wmi_pdev_fips_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_FIPS_EVENTID); -#define WMITLV_TABLE_WMI_PDEV_CHANNEL_HOPPING_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param, wmi_pdev_channel_hopping_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_CHANNEL_HOPPING_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param, wmi_pdev_channel_hopping_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHANNEL_HOPPING_EVENTID); -#define WMITLV_TABLE_WMI_PDEV_ANI_CCK_LEVEL_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ani_cck_event_fixed_param, wmi_ani_cck_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PDEV_ANI_CCK_LEVEL_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ani_cck_event_fixed_param, wmi_ani_cck_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANI_CCK_LEVEL_EVENTID); -#define WMITLV_TABLE_WMI_PDEV_CHIP_POWER_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_chip_power_stats_event_fixed_param, wmi_pdev_chip_power_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, debug_registers, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_CHIP_POWER_STATS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_chip_power_stats_event_fixed_param, wmi_pdev_chip_power_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, debug_registers, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_STATS_EVENTID); -#define WMITLV_TABLE_WMI_PDEV_ANI_OFDM_LEVEL_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param, wmi_ani_ofdm_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + +#define WMITLV_TABLE_WMI_PDEV_ANI_OFDM_LEVEL_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param, wmi_ani_ofdm_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID); -#define WMITLV_TABLE_WMI_PDEV_TPC_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param, wmi_pdev_tpc_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tpc, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_TPC_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param, wmi_pdev_tpc_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tpc, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TPC_EVENTID); -#define WMITLV_TABLE_WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, wmi_pdev_nfcal_power_all_channels_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBr, nfdbr, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBm, nfdbm, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_freqNum, freqnum, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, wmi_pdev_nfcal_power_all_channels_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBr, nfdbr, WMITLV_SIZE_VAR) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBm, nfdbm, WMITLV_SIZE_VAR) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_freqNum, freqnum, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID); -#define WMITLV_TABLE_WMI_PEER_RATECODE_LIST_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_ratecode_list_event_fixed_param, wmi_peer_ratecode_list_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_cck_ofdm_rate_info, ratecode_legacy, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_mcs_rate_info, ratecode_mcs, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_PEER_RATECODE_LIST_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_ratecode_list_event_fixed_param, wmi_peer_ratecode_list_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_cck_ofdm_rate_info, ratecode_legacy, WMITLV_SIZE_VAR) \ +WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_mcs_rate_info, ratecode_mcs, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_RATECODE_LIST_EVENTID); -#define WMITLV_TABLE_WMI_WDS_PEER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wds_addr_event_fixed_param, wmi_wds_addr_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_WDS_PEER_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_wds_addr_event_fixed_param, wmi_wds_addr_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WDS_PEER_EVENTID); -#define WMITLV_TABLE_WMI_PEER_STA_PS_STATECHG_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_sta_ps_statechange_event_fixed_param, wmi_peer_sta_ps_statechange_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_PEER_STA_PS_STATECHG_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_peer_sta_ps_statechange_event_fixed_param, wmi_peer_sta_ps_statechange_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_PS_STATECHG_EVENTID); -#define WMITLV_TABLE_WMI_INST_RSSI_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_inst_rssi_stats_resp_fixed_param, wmi_inst_rssi_stats_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) +#define WMITLV_TABLE_WMI_INST_RSSI_STATS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_inst_rssi_stats_resp_fixed_param, wmi_inst_rssi_stats_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_INST_RSSI_STATS_EVENTID); -#define WMITLV_TABLE_WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tx_power_level_stats_evt_fixed_param, wmi_tx_power_level_stats_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_time_per_power_level, WMITLV_SIZE_VAR) +#define WMITLV_TABLE_WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_tx_power_level_stats_evt_fixed_param, wmi_tx_power_level_stats_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_time_per_power_level, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID); -#define WMITLV_TABLE_WMI_RMC_NEW_LEADER_EVENTID(id, op, buf, len) \ - WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rmc_manual_leader_event_fixed_param, wmi_rmc_manual_leader_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_RMC_NEW_LEADER_EVENTID); - /* Layout of WMI_REPORT_STATS_EVENTID message: * fixed_param; - * wmi_chan_cca_stats chan_cca_stats[]; Array size is specified by num_chan_cca_stats - * wmi_peer_signal_stats peer_signal_stats[]; Array size is specified by num_peer_signal_stats - * wmi_peer_ac_tx_stats peer_ac_tx_stats[]; Array size is specified by num_peer_ac_tx_stats - * wmi_tx_stats tx_stats[][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) - * A_UINT32 tx_mpdu_aggr[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_mpdu_aggr_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_mpdu_aggr_array_size + A-MPDU size index + * wmi_chan_cca_stats chan_cca_stats[]; Array length is specified by num_chan_cca_stats + * wmi_peer_signal_stats peer_signal_stats[]; Array length is specified by num_peer_signal_stats + * wmi_peer_ac_tx_stats peer_ac_tx_stats[]; Array length is specified by num_peer_ac_tx_stats + * wmi_tx_stats tx_stats[][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) + * A_UINT32 tx_mpdu_aggr[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_mpdu_aggr_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_mpdu_aggr_array_len + A-MPDU size index * Contains a histogram of how many A-MPDUs of a given size (i.e. number of MPDUs) have been transmitted. - * Element 0 contains the number of MPDUs within a single-MPDU A-MPDU. - * Element 1 contains the number of MPDUs within a 2-MPDU A-MPDU (number of A-MPDUs x2). - * Element 2 contains the number of MPDUs within a 3-MPDU A-MPDU (number of A-MPDUs x3). - * Element tx_mpdu_aggr_array_size-1 contains the number of MPDUs within A-MPDUs with >= tx_mpdu_aggr_array_size MPDUs. - * A_UINT32 tx_msdu_acked_mcs[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_msdu_acked_mcs_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_msdu_acked_mcs_array_size + MCS index - * Contains a count of how many tx MSDUs have been acked for each MCS of each AC of each peer. - * A_UINT32 tx_msdu_failed_mcs[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_msdu_failed_mcs_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_msdu_failed_mcs_array_size + MCS index - * Contains a count of how many MSDUs failed tx due to no ack for each MCS of each AC of each peer. - * A_UINT32 tx_msdu_delay[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_msdu_delay_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_msdu_delay_array_size + delay index - * Contains a histogram of how many MSDUs encountered each level of delay due to retries or air interface contention. - * The time represented by each array element (i.e. histogram bin) is specified by tx_delay_bin_size_ms. - * Element 0 contains the count of MSDUs delayed by less than tx_delay_bin_size_ms. - * Element 1 contains the count of MSDUs delayed by more than 1x tx_delay_bin_size_ms but less than 2x. - * Element tx_msdu_delay_array_size-1 contains the count of MSDUs delayed by - * >= tx_delay_bin_size_ms * (tx_msdu_delay_array_size-1) - * wmi_peer_ac_rx_stats peer_ac_rx_stats[]; Array size is specified by num_peer_ac_rx_stats - * wmi_rx_stats rx_stats[][]; Array size is num_peer_ac_rx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) - * A_UINT32 rx_mpdu_aggr[][][]; Array size is num_peer_ac_rx_stats * WLAN_MAX_AC * rx_mpdu_aggr_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mpdu_aggr_array_size + A-MPDU size index + * Element 0 contains the number of PPDUs with a single-MPDU A-MPDU. + * Element 1 contains the number of PPDUs with 2 MPDUs. + * Element 2 contains the number of PPDUs with 3 MPDUs. + * Element tx_mpdu_aggr_array_len-1 contains the number of PPDUs with >= tx_mpdu_aggr_array_len MPDUs. + * A_UINT32 tx_succ_mcs[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_succ_mcs_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_succ_mcs_array_len + MCS index + * Contains a count of how many tx PPDUs have been acked for each MCS of each AC of each peer. + * A_UINT32 tx_fail_mcs[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_fail_mcs_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_fail_mcs_array_len + MCS index + * Contains a count of how many PPDUs failed tx due to no ack for each MCS of each AC of each peer. + * A_UINT32 tx_ppdu_delay[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_ppdu_delay_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_ppdu_delay_array_len + delay index + * Contains a histogram of how many PPDUs encountered each level of delay due to retries or air interface contention. + * The time represented by each array element (i.e. histogram bin) is specified by tx_ppdu_delay_bin_size_ms. + * Element 0 contains the count of PPDUs delayed by less than tx_ppdu_delay_bin_size_ms. + * Element 1 contains the count of PPDUs delayed by more than 1x tx_ppdu_delay_bin_size_ms but less than 2x. + * Element tx_delay_array_len-1 contains the count of PPDUs delayed by + * >= tx_ppdu_delay_bin_size_ms * (tx_ppdu_delay_array_len-1) + * wmi_peer_ac_rx_stats peer_ac_rx_stats[]; Array length is specified by num_peer_ac_rx_stats + * wmi_rx_stats rx_stats[][]; Array length is num_peer_ac_rx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) + * A_UINT32 rx_mpdu_aggr[][][]; Array length is num_peer_ac_rx_stats * WLAN_MAX_AC * rx_mpdu_aggr_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mpdu_aggr_array_len + A-MPDU size index * Contains a histogram of how many A-MPDUs of a given size (i.e. number of MPDUs) have been received. - * Element 0 contains the number of MPDUs within a single-MPDU A-MPDU. - * Element 1 contains the number of MPDUs within a 2-MPDU A-MPDU (number of A-MPDUs x2). - * Element 2 contains the number of MPDUs within a 3-MPDU A-MPDU (number of A-MPDUs x3). - * Element rx_mpdu_aggr_array_size-1 contains the number of MPDUs within A-MPDUs with >= rx_mpdu_aggr_array_size MPDUs. - * A_UINT32 rx_msdu_mcs[][][]; Array size is (num_peer_ac_rx_stats * WLAN_MAX_AC) * rx_msdu_mcs_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_msdu_mcs_array_size + MCS index - * Contains a count of rx MSDUs for each MCS of each AC of each peer. + * Element 0 contains the number of PPDUs with a single MPDU. + * Element 1 contains the number of PPDUs with 2 MPDUs. + * Element 2 contains the number of PPDUs with 3 MPDUs. + * Element rx_mpdu_aggr_array_len-1 contains the number of PPDUs with >= rx_mpdu_aggr_array_len MPDUs. + * A_UINT32 rx_mcs[][][]; Array length is (num_peer_ac_rx_stats * WLAN_MAX_AC) * rx_mcs_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mcs_array_len + MCS index + * Contains a count of rx PPDUs for each MCS of each AC of each peer. * For example, if there were 2 peers (X and Y) whose stats were being reported, * the message and its TLV arrays would look like this: * 1. fixed_param @@ -3956,30 +4030,30 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RMC_NEW_LEADER_EVENTID); * 20. tx_mpdu_aggr[1][1][] for peer Y, AC 1 * 21. tx_mpdu_aggr[1][2][] for peer Y, AC 2 * 22. tx_mpdu_aggr[1][3][] for peer Y, AC 3 - * 23. tx_msdu_acked_mcs[0][0][] for peer X, AC 0 - * 24. tx_msdu_acked_mcs[0][1][] for peer X, AC 1 - * 25. tx_msdu_acked_mcs[0][2][] for peer X, AC 2 - * 26. tx_msdu_acked_mcs[0][3][] for peer X, AC 3 - * 27. tx_msdu_acked_mcs[1][0][] for peer Y, AC 0 - * 28. tx_msdu_acked_mcs[1][1][] for peer Y, AC 1 - * 29. tx_msdu_acked_mcs[1][2][] for peer Y, AC 2 - * 30. tx_msdu_acked_mcs[1][3][] for peer Y, AC 3 - * 31. tx_msdu_failed_mcs[0][0][] for peer X, AC 0 - * 32. tx_msdu_failed_mcs[0][1][] for peer X, AC 1 - * 33. tx_msdu_failed_mcs[0][2][] for peer X, AC 2 - * 34. tx_msdu_failed_mcs[0][3][] for peer X, AC 3 - * 35. tx_msdu_failed_mcs[1][0][] for peer Y, AC 0 - * 36. tx_msdu_failed_mcs[1][1][] for peer Y, AC 1 - * 37. tx_msdu_failed_mcs[1][2][] for peer Y, AC 2 - * 38. tx_msdu_failed_mcs[1][3][] for peer Y, AC 3 - * 39. tx_msdu_delay[0][0][] for peer X, AC 0 - * 40. tx_msdu_delay[0][1][] for peer X, AC 1 - * 41. tx_msdu_delay[0][2][] for peer X, AC 2 - * 42. tx_msdu_delay[0][3][] for peer X, AC 3 - * 43. tx_msdu_delay[1][0][] for peer Y, AC 0 - * 44. tx_msdu_delay[1][1][] for peer Y, AC 1 - * 45. tx_msdu_delay[1][2][] for peer Y, AC 2 - * 46. tx_msdu_delay[1][3][] for peer Y, AC 3 + * 23. tx_succ_mcs[0][0][] for peer X, AC 0 + * 24. tx_succ_mcs[0][1][] for peer X, AC 1 + * 25. tx_succ_mcs[0][2][] for peer X, AC 2 + * 26. tx_succ_mcs[0][3][] for peer X, AC 3 + * 27. tx_succ_mcs[1][0][] for peer Y, AC 0 + * 28. tx_succ_mcs[1][1][] for peer Y, AC 1 + * 29. tx_succ_mcs[1][2][] for peer Y, AC 2 + * 30. tx_succ_mcs[1][3][] for peer Y, AC 3 + * 31. tx_fail_mcs[0][0][] for peer X, AC 0 + * 32. tx_fail_mcs[0][1][] for peer X, AC 1 + * 33. tx_fail_mcs[0][2][] for peer X, AC 2 + * 34. tx_fail_mcs[0][3][] for peer X, AC 3 + * 35. tx_fail_mcs[1][0][] for peer Y, AC 0 + * 36. tx_fail_mcs[1][1][] for peer Y, AC 1 + * 37. tx_fail_mcs[1][2][] for peer Y, AC 2 + * 38. tx_fail_mcs[1][3][] for peer Y, AC 3 + * 39. tx_ppdu_delay[0][0][] for peer X, AC 0 + * 40. tx_ppdu_delay[0][1][] for peer X, AC 1 + * 41. tx_ppdu_delay[0][2][] for peer X, AC 2 + * 42. tx_ppdu_delay[0][3][] for peer X, AC 3 + * 43. tx_ppdu_delay[1][0][] for peer Y, AC 0 + * 44. tx_ppdu_delay[1][1][] for peer Y, AC 1 + * 45. tx_ppdu_delay[1][2][] for peer Y, AC 2 + * 46. tx_ppdu_delay[1][3][] for peer Y, AC 3 * 47. peer_ac_rx_stats[0] for X * 48. peer_ac_rx_stats[1] for Y * 49. rx_stats[0][0] for peer X, AC 0 @@ -3998,35 +4072,37 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RMC_NEW_LEADER_EVENTID); * 62. rx_mpdu_aggr[1][1][] for peer Y, AC 1 * 63. rx_mpdu_aggr[1][2][] for peer Y, AC 2 * 64. rx_mpdu_aggr[1][3][] for peer Y, AC 3 - * 65. rx_msdu_mcs[0][0][] for peer X, AC 0 - * 66. rx_msdu_mcs[0][1][] for peer X, AC 1 - * 67. rx_msdu_mcs[0][2][] for peer X, AC 2 - * 68. rx_msdu_mcs[0][3][] for peer X, AC 3 - * 69. rx_msdu_mcs[1][0][] for peer Y, AC 0 - * 70. rx_msdu_mcs[1][1][] for peer Y, AC 1 - * 71. rx_msdu_mcs[1][2][] for peer Y, AC 2 - * 72. rx_msdu_mcs[1][3][] for peer Y, AC 3 + * 65. rx_mcs[0][0][] for peer X, AC 0 + * 66. rx_mcs[0][1][] for peer X, AC 1 + * 67. rx_mcs[0][2][] for peer X, AC 2 + * 68. rx_mcs[0][3][] for peer X, AC 3 + * 69. rx_mcs[1][0][] for peer Y, AC 0 + * 70. rx_mcs[1][1][] for peer Y, AC 1 + * 71. rx_mcs[1][2][] for peer Y, AC 2 + * 72. rx_mcs[1][3][] for peer Y, AC 3 **/ #define WMITLV_TABLE_WMI_REPORT_STATS_EVENTID(id, op, buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param, wmi_report_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_chan_cca_stats, chan_cca_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_signal_stats, peer_signal_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_ac_tx_stats, peer_ac_tx_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_stats, tx_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_mpdu_aggr, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_msdu_acked_mcs, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_msdu_failed_mcs, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_msdu_delay, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_ac_rx_stats, peer_ac_rx_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rx_stats, rx_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rx_mpdu_aggr, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rx_msdu_mcs, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_REPORT_STATS_EVENTID); + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param, wmi_report_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_chan_cca_stats, chan_cca_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_signal_stats, peer_signal_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_ac_tx_stats, peer_ac_tx_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_stats, tx_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_mpdu_aggr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_succ_mcs, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_fail_mcs, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tx_ppdu_delay, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_ac_rx_stats, peer_ac_rx_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_STRUC, wmi_rx_stats, rx_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rx_mpdu_aggr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rx_mcs, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_REPORT_STATS_EVENTID); +#define WMITLV_TABLE_WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_encrypt_decrypt_data_resp_event_fixed_param, wmi_vdev_encrypt_decrypt_data_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, enc80211_frame, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID); #ifdef __cplusplus } #endif - #endif /*_WMI_TLV_DEFS_H_*/ - diff --git a/fw/wmi_tlv_helper.h b/fw/wmi_tlv_helper.h old mode 100755 new mode 100644 index efdd5775d8b0..7631e5df9ec0 --- a/fw/wmi_tlv_helper.h +++ b/fw/wmi_tlv_helper.h @@ -24,6 +24,7 @@ * under proprietary terms before Copyright ownership was assigned * to the Linux Foundation. */ + #ifndef _WMI_TLV_HELPER_H_ #define _WMI_TLV_HELPER_H_ @@ -42,7 +43,7 @@ * (5) Either WMITLV_SIZE_FIX or WMITLV_SIZE_VAR to indicate if this TLV is variable size. * * Note: It is important that the last TLV_ELEM does not have the "\" character. -*/ + */ /* Size of the TLV Header which is the Tag and Length fields */ #define WMI_TLV_HDR_SIZE (1 * sizeof(A_UINT32)) @@ -75,20 +76,19 @@ typedef struct { A_UINT32 tag_struct_size; A_UINT32 tag_varied_size; A_UINT32 tag_array_size; - A_UINT32 cmd_num_tlv; + A_UINT32 cmd_num_tlv; } wmitlv_attributes_struc; - /* Template structure definition for a variable size array of UINT32 */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */ - A_UINT32 uint32_array[1]; /* variable length Array of UINT32 */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */ + A_UINT32 uint32_array[1]; /* variable length Array of UINT32 */ } wmitlv_array_uint32; /* Template structure definition for a variable size array of unknown structure */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */ - A_UINT32 struc_array[1]; /* variable length Array of structures */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */ + A_UINT32 struc_array[1]; /* variable length Array of structures */ } wmitlv_array_struc; /* @@ -97,60 +97,64 @@ typedef struct { */ #define WMITLV_ARR_SIZE_INVALID 0x1FE -#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id) \ - WMI_TLV_HLPR_NUM_TLVS_FOR_##wmi_cmd_event_id - +#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id) \ + WMI_TLV_HLPR_NUM_TLVS_FOR_ ## wmi_cmd_event_id void -wmitlv_set_static_param_tlv_buf(void *param_tlv_buf, A_UINT32 max_tlvs_accomodated); +wmitlv_set_static_param_tlv_buf(void *param_tlv_buf, + A_UINT32 max_tlvs_accomodated); void -wmitlv_free_allocated_command_tlvs( - A_UINT32 cmd_id, - void **wmi_cmd_struct_ptr); +wmitlv_free_allocated_command_tlvs(A_UINT32 cmd_id, void **wmi_cmd_struct_ptr); void -wmitlv_free_allocated_event_tlvs( - A_UINT32 event_id, - void **wmi_cmd_struct_ptr); +wmitlv_free_allocated_event_tlvs(A_UINT32 event_id, void **wmi_cmd_struct_ptr); int -wmitlv_check_command_tlv_params( - void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id); +wmitlv_check_command_tlv_params(void *os_ctx, void *param_struc_ptr, + A_UINT32 param_buf_len, + A_UINT32 wmi_cmd_event_id); int -wmitlv_check_event_tlv_params( - void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id); +wmitlv_check_event_tlv_params(void *os_ctx, void *param_struc_ptr, + A_UINT32 param_buf_len, + A_UINT32 wmi_cmd_event_id); int -wmitlv_check_and_pad_command_tlvs( - void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr); +wmitlv_check_and_pad_command_tlvs(void *os_ctx, void *param_struc_ptr, + A_UINT32 param_buf_len, + A_UINT32 wmi_cmd_event_id, + void **wmi_cmd_struct_ptr); int -wmitlv_check_and_pad_event_tlvs( - void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr); +wmitlv_check_and_pad_event_tlvs(void *os_ctx, void *param_struc_ptr, + A_UINT32 param_buf_len, + A_UINT32 wmi_cmd_event_id, + void **wmi_cmd_struct_ptr); /** This structure is the element for the Version WhiteList * table. */ typedef struct { - A_UINT32 major; - A_UINT32 minor; - A_UINT32 namespace_0; - A_UINT32 namespace_1; - A_UINT32 namespace_2; - A_UINT32 namespace_3; + A_UINT32 major; + A_UINT32 minor; + A_UINT32 namespace_0; + A_UINT32 namespace_1; + A_UINT32 namespace_2; + A_UINT32 namespace_3; } wmi_whitelist_version_info; -struct _wmi_abi_version; /* Forward declaration to make the ARM compiler happy */ +struct _wmi_abi_version; /* Forward declaration to make the ARM compiler happy */ int -wmi_cmp_and_set_abi_version(int num_whitelist, wmi_whitelist_version_info *version_whitelist_table, - struct _wmi_abi_version *my_vers, - struct _wmi_abi_version *opp_vers, - struct _wmi_abi_version *out_vers); +wmi_cmp_and_set_abi_version(int num_whitelist, + wmi_whitelist_version_info * + version_whitelist_table, + struct _wmi_abi_version *my_vers, + struct _wmi_abi_version *opp_vers, + struct _wmi_abi_version *out_vers); int -wmi_versions_are_compatible(struct _wmi_abi_version *vers1, struct _wmi_abi_version *vers2); +wmi_versions_are_compatible(struct _wmi_abi_version *vers1, + struct _wmi_abi_version *vers2); #endif /*_WMI_TLV_HELPER_H_*/ - diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h old mode 100755 new mode 100644 index 28864bd1b33b..efe0c4fe5a09 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -27,7 +27,7 @@ /** * @addtogroup WMIAPI - *@{ + ***@{ */ /** @file @@ -63,51 +63,52 @@ #ifndef _WMI_UNIFIED_H_ #define _WMI_UNIFIED_H_ - #ifdef __cplusplus extern "C" { #endif #include #include +#include #define ATH_MAC_LEN 6 /**< length of MAC in bytes */ -#define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */ -#define WMI_EVENT_STATUS_FAILURE 1 /* Failure return status to host */ +#define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */ +#define WMI_EVENT_STATUS_FAILURE 1 /* Failure return status to host */ -#define MAX_TX_RATE_VALUES 10 /*Max Tx Rates*/ -#define MAX_RSSI_VALUES 10 /*Max Rssi values*/ +#define MAX_TX_RATE_VALUES 10 /*Max Tx Rates */ +#define MAX_RSSI_VALUES 10 /*Max Rssi values */ #define WMI_MAX_CHAINS 8 /* The WLAN_MAX_AC macro cannot be changed without breaking - WMI compatibility. */ -/* The maximum value of access category */ + * WMI compatibility. + * The maximum value of access category + */ #define WLAN_MAX_AC 4 /* * These don't necessarily belong here; but as the MS/SM macros require * ar6000_internal.h to be included, it may not be defined as yet. */ -#define WMI_F_MS(_v, _f) \ - (((_v) & (_f)) >> (_f##_S)) +#define WMI_F_MS(_v, _f) \ + (((_v) & (_f)) >> (_f ## _S)) /* * This breaks the "good macro practice" of only referencing each * macro field once (to avoid things like field++ from causing issues.) */ -#define WMI_F_RMW(_var, _v, _f) \ - do { \ - (_var) &= ~(_f); \ - (_var) |= (((_v) << (_f##_S)) & (_f)); \ - } while (0) +#define WMI_F_RMW(_var, _v, _f) \ + do { \ + (_var) &= ~(_f); \ + (_var) |= (((_v) << (_f ## _S)) & (_f)); \ + } while (0) -#define WMI_GET_BITS(_val,_index,_num_bits) \ - (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) +#define WMI_GET_BITS(_val, _index, _num_bits) \ + (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) -#define WMI_SET_BITS(_var,_index,_num_bits,_val) do { \ - (_var) &= ~(((1 << (_num_bits)) - 1) << (_index)); \ - (_var) |= (((_val) & ((1 << (_num_bits)) - 1)) << (_index)); \ - } while (0) +#define WMI_SET_BITS(_var, _index, _num_bits, _val) do { \ + (_var) &= ~(((1 << (_num_bits)) - 1) << (_index)); \ + (_var) |= (((_val) & ((1 << (_num_bits)) - 1)) << (_index)); \ + } while (0) /** * A packed array is an array where each entry in the array is less than @@ -117,125 +118,124 @@ extern "C" { * The first 2 11-bit values will be stored in the first A_UINT32, * and the last 2 11-bit values will be stored in the second A_UINT32. */ -#define WMI_PACKED_ARR_SIZE(num_entries,bits_per_entry) \ - (((num_entries) / (32 / (bits_per_entry))) + \ - (((num_entries) % (32 / (bits_per_entry))) ? 1 : 0)) +#define WMI_PACKED_ARR_SIZE(num_entries, bits_per_entry) \ + (((num_entries) / (32 / (bits_per_entry))) + \ + (((num_entries) % (32 / (bits_per_entry))) ? 1 : 0)) static INLINE A_UINT32 wmi_packed_arr_get_bits(A_UINT32 *arr, - A_UINT32 entry_index, A_UINT32 bits_per_entry) + A_UINT32 entry_index, A_UINT32 bits_per_entry) { - A_UINT32 entries_per_uint = (32 / bits_per_entry); - A_UINT32 uint_index = (entry_index / entries_per_uint); - A_UINT32 num_entries_in_prev_uints = (uint_index * entries_per_uint); - A_UINT32 index_in_uint = (entry_index - num_entries_in_prev_uints); - A_UINT32 start_bit_in_uint = (index_in_uint * bits_per_entry); - return (arr[uint_index] >> start_bit_in_uint) & - ((1 << bits_per_entry) - 1); + A_UINT32 entries_per_uint = (32 / bits_per_entry); + A_UINT32 uint_index = (entry_index / entries_per_uint); + A_UINT32 num_entries_in_prev_uints = (uint_index * entries_per_uint); + A_UINT32 index_in_uint = (entry_index - num_entries_in_prev_uints); + A_UINT32 start_bit_in_uint = (index_in_uint * bits_per_entry); + return (arr[uint_index] >> start_bit_in_uint) & + ((1 << bits_per_entry) - 1); } static INLINE void wmi_packed_arr_set_bits(A_UINT32 *arr, A_UINT32 entry_index, - A_UINT32 bits_per_entry, A_UINT32 val) + A_UINT32 bits_per_entry, A_UINT32 val) { - A_UINT32 entries_per_uint = (32 / bits_per_entry); - A_UINT32 uint_index = (entry_index / entries_per_uint); - A_UINT32 num_entries_in_prev_uints = (uint_index * entries_per_uint); - A_UINT32 index_in_uint = (entry_index - num_entries_in_prev_uints); - A_UINT32 start_bit_in_uint = (index_in_uint * bits_per_entry); + A_UINT32 entries_per_uint = (32 / bits_per_entry); + A_UINT32 uint_index = (entry_index / entries_per_uint); + A_UINT32 num_entries_in_prev_uints = (uint_index * entries_per_uint); + A_UINT32 index_in_uint = (entry_index - num_entries_in_prev_uints); + A_UINT32 start_bit_in_uint = (index_in_uint * bits_per_entry); - arr[uint_index] &= ~(((1 << bits_per_entry) - 1) << start_bit_in_uint); - arr[uint_index] |= - ((val & ((1 << bits_per_entry) - 1)) << start_bit_in_uint); + arr[uint_index] &= ~(((1 << bits_per_entry) - 1) << start_bit_in_uint); + arr[uint_index] |= + ((val & ((1 << bits_per_entry) - 1)) << start_bit_in_uint); } /** 2 word representation of MAC addr */ typedef struct { - /** upper 4 bytes of MAC address */ - A_UINT32 mac_addr31to0; - /** lower 2 bytes of MAC address */ - A_UINT32 mac_addr47to32; + /** upper 4 bytes of MAC address */ + A_UINT32 mac_addr31to0; + /** lower 2 bytes of MAC address */ + A_UINT32 mac_addr47to32; } wmi_mac_addr; /** macro to convert MAC address from WMI word format to char array */ -#define WMI_MAC_ADDR_TO_CHAR_ARRAY(pwmi_mac_addr,c_macaddr) do { \ - (c_macaddr)[0] = (((pwmi_mac_addr)->mac_addr31to0) >> 0) & 0xff; \ - (c_macaddr)[1] = (((pwmi_mac_addr)->mac_addr31to0) >> 8) & 0xff; \ - (c_macaddr)[2] = (((pwmi_mac_addr)->mac_addr31to0) >> 16) & 0xff; \ - (c_macaddr)[3] = (((pwmi_mac_addr)->mac_addr31to0) >> 24) & 0xff; \ - (c_macaddr)[4] = (((pwmi_mac_addr)->mac_addr47to32) >> 0) & 0xff; \ - (c_macaddr)[5] = (((pwmi_mac_addr)->mac_addr47to32) >> 8) & 0xff; \ - } while (0) +#define WMI_MAC_ADDR_TO_CHAR_ARRAY(pwmi_mac_addr, c_macaddr) do { \ + (c_macaddr)[0] = ((pwmi_mac_addr)->mac_addr31to0) & 0xff; \ + (c_macaddr)[1] = (((pwmi_mac_addr)->mac_addr31to0) >> 8) & 0xff; \ + (c_macaddr)[2] = (((pwmi_mac_addr)->mac_addr31to0) >> 16) & 0xff; \ + (c_macaddr)[3] = (((pwmi_mac_addr)->mac_addr31to0) >> 24) & 0xff; \ + (c_macaddr)[4] = ((pwmi_mac_addr)->mac_addr47to32) & 0xff; \ + (c_macaddr)[5] = (((pwmi_mac_addr)->mac_addr47to32) >> 8) & 0xff; \ +} while (0) /** macro to convert MAC address from char array to WMI word format */ -#define WMI_CHAR_ARRAY_TO_MAC_ADDR(c_macaddr,pwmi_mac_addr) do { \ - (pwmi_mac_addr)->mac_addr31to0 = \ - (((c_macaddr)[0] << 0) | \ - ((c_macaddr)[1] << 8) | \ - ((c_macaddr)[2] << 16) | \ - ((c_macaddr)[3] << 24)); \ - (pwmi_mac_addr)->mac_addr47to32 = ((c_macaddr)[4] | ((c_macaddr)[5] << 8));\ - } while (0) +#define WMI_CHAR_ARRAY_TO_MAC_ADDR(c_macaddr, pwmi_mac_addr) do { \ + (pwmi_mac_addr)->mac_addr31to0 = \ + ((c_macaddr)[0] | ((c_macaddr)[1] << 8) \ + | ((c_macaddr)[2] << 16) | ((c_macaddr)[3] << 24)); \ + (pwmi_mac_addr)->mac_addr47to32 = \ + ((c_macaddr)[4] | ((c_macaddr)[5] << 8)); \ +} while (0) /* * wmi command groups. */ typedef enum { - /* 0 to 2 are reserved */ - WMI_GRP_START = 0x3, - WMI_GRP_SCAN = WMI_GRP_START, /* 0x3 */ - WMI_GRP_PDEV, /* 0x4 */ - WMI_GRP_VDEV, /* 0x5 */ - WMI_GRP_PEER, /* 0x6 */ - WMI_GRP_MGMT, /* 0x7 */ - WMI_GRP_BA_NEG, /* 0x8 */ - WMI_GRP_STA_PS, /* 0x9 */ - WMI_GRP_DFS, /* 0xa */ - WMI_GRP_ROAM, /* 0xb */ - WMI_GRP_OFL_SCAN, /* 0xc */ - WMI_GRP_P2P, /* 0xd */ - WMI_GRP_AP_PS, /* 0xe */ - WMI_GRP_RATE_CTRL, /* 0xf */ - WMI_GRP_PROFILE, /* 0x10 */ - WMI_GRP_SUSPEND, /* 0x11 */ - WMI_GRP_BCN_FILTER, /* 0x12 */ - WMI_GRP_WOW, /* 0x13 */ - WMI_GRP_RTT, /* 0x14 */ - WMI_GRP_SPECTRAL, /* 0x15 */ - WMI_GRP_STATS, /* 0x16 */ - WMI_GRP_ARP_NS_OFL, /* 0x17 */ - WMI_GRP_NLO_OFL, /* 0x18 */ - WMI_GRP_GTK_OFL, /* 0x19 */ - WMI_GRP_CSA_OFL, /* 0x1a */ - WMI_GRP_CHATTER, /* 0x1b */ - WMI_GRP_TID_ADDBA, /* 0x1c */ - WMI_GRP_MISC, /* 0x1d */ - WMI_GRP_GPIO, /* 0x1e */ - WMI_GRP_FWTEST, /* 0x1f */ - WMI_GRP_TDLS, /* 0x20 */ - WMI_GRP_RESMGR, /* 0x21 */ - WMI_GRP_STA_SMPS, /* 0x22 */ - WMI_GRP_WLAN_HB, /* 0x23 */ - WMI_GRP_RMC, /* 0x24 */ - WMI_GRP_MHF_OFL, /* 0x25 */ - WMI_GRP_LOCATION_SCAN, /* 0x26 */ - WMI_GRP_OEM, /* 0x27 */ - WMI_GRP_NAN, /* 0x28 */ - WMI_GRP_COEX, /* 0x29 */ - WMI_GRP_OBSS_OFL, /* 0x2a */ - WMI_GRP_LPI, /* 0x2b */ - WMI_GRP_EXTSCAN, /* 0x2c */ - WMI_GRP_DHCP_OFL, /* 0x2d */ - WMI_GRP_IPA, /* 0x2e */ - WMI_GRP_MDNS_OFL, /* 0x2f */ - WMI_GRP_SAP_OFL, /* 0x30 */ - WMI_GRP_OCB, /* 0x31 */ - WMI_GRP_SOC, /* 0x32 */ - WMI_GRP_PKT_FILTER, /* 0x33 */ - WMI_GRP_MAWC, /* 0x34 */ - WMI_GRP_PMF_OFFLOAD, /* 0x35 */ - WMI_GRP_BPF_OFFLOAD, /* 0x36 Berkeley Packet Filter */ - WMI_GRP_NAN_DATA, /* 0x37 */ - WMI_GRP_PROTOTYPE, /* 0x38 */ - WMI_GRP_MONITOR, /* 0x39 */ + /* 0 to 2 are reserved */ + WMI_GRP_START = 0x3, + WMI_GRP_SCAN = WMI_GRP_START, /* 0x3 */ + WMI_GRP_PDEV, /* 0x4 */ + WMI_GRP_VDEV, /* 0x5 */ + WMI_GRP_PEER, /* 0x6 */ + WMI_GRP_MGMT, /* 0x7 */ + WMI_GRP_BA_NEG, /* 0x8 */ + WMI_GRP_STA_PS, /* 0x9 */ + WMI_GRP_DFS, /* 0xa */ + WMI_GRP_ROAM, /* 0xb */ + WMI_GRP_OFL_SCAN, /* 0xc */ + WMI_GRP_P2P, /* 0xd */ + WMI_GRP_AP_PS, /* 0xe */ + WMI_GRP_RATE_CTRL, /* 0xf */ + WMI_GRP_PROFILE, /* 0x10 */ + WMI_GRP_SUSPEND, /* 0x11 */ + WMI_GRP_BCN_FILTER, /* 0x12 */ + WMI_GRP_WOW, /* 0x13 */ + WMI_GRP_RTT, /* 0x14 */ + WMI_GRP_SPECTRAL, /* 0x15 */ + WMI_GRP_STATS, /* 0x16 */ + WMI_GRP_ARP_NS_OFL, /* 0x17 */ + WMI_GRP_NLO_OFL, /* 0x18 */ + WMI_GRP_GTK_OFL, /* 0x19 */ + WMI_GRP_CSA_OFL, /* 0x1a */ + WMI_GRP_CHATTER, /* 0x1b */ + WMI_GRP_TID_ADDBA, /* 0x1c */ + WMI_GRP_MISC, /* 0x1d */ + WMI_GRP_GPIO, /* 0x1e */ + WMI_GRP_FWTEST, /* 0x1f */ + WMI_GRP_TDLS, /* 0x20 */ + WMI_GRP_RESMGR, /* 0x21 */ + WMI_GRP_STA_SMPS, /* 0x22 */ + WMI_GRP_WLAN_HB, /* 0x23 */ + WMI_GRP_RMC, /* 0x24 */ + WMI_GRP_MHF_OFL, /* 0x25 */ + WMI_GRP_LOCATION_SCAN, /* 0x26 */ + WMI_GRP_OEM, /* 0x27 */ + WMI_GRP_NAN, /* 0x28 */ + WMI_GRP_COEX, /* 0x29 */ + WMI_GRP_OBSS_OFL, /* 0x2a */ + WMI_GRP_LPI, /* 0x2b */ + WMI_GRP_EXTSCAN, /* 0x2c */ + WMI_GRP_DHCP_OFL, /* 0x2d */ + WMI_GRP_IPA, /* 0x2e */ + WMI_GRP_MDNS_OFL, /* 0x2f */ + WMI_GRP_SAP_OFL, /* 0x30 */ + WMI_GRP_OCB, /* 0x31 */ + WMI_GRP_SOC, /* 0x32 */ + WMI_GRP_PKT_FILTER, /* 0x33 */ + WMI_GRP_MAWC, /* 0x34 */ + WMI_GRP_PMF_OFFLOAD, /* 0x35 */ + WMI_GRP_BPF_OFFLOAD, /* 0x36 Berkeley Packet Filter */ + WMI_GRP_NAN_DATA, /* 0x37 */ + WMI_GRP_PROTOTYPE, /* 0x38 */ + WMI_GRP_MONITOR, /* 0x39 */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -245,1167 +245,1233 @@ typedef enum { * Command IDs and commange events */ typedef enum { - /** initialize the wlan sub system */ - WMI_INIT_CMDID = 0x1, + /** initialize the wlan sub system */ + WMI_INIT_CMDID = 0x1, - /* Scan specific commands */ + /* Scan specific commands */ - /** start scan request to FW */ - WMI_START_SCAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SCAN), - /** stop scan request to FW */ - WMI_STOP_SCAN_CMDID, - /** full list of channels as defined by the regulatory that will be used by scanner */ - WMI_SCAN_CHAN_LIST_CMDID, - /** overwrite default priority table in scan scheduler */ - WMI_SCAN_SCH_PRIO_TBL_CMDID, - /** This command to adjust the priority and min.max_rest_time - * of an on ongoing scan request. - */ - WMI_SCAN_UPDATE_REQUEST_CMDID, + /** start scan request to FW */ + WMI_START_SCAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SCAN), + /** stop scan request to FW */ + WMI_STOP_SCAN_CMDID, + /** full list of channels as defined by the regulatory that will be used by scanner */ + WMI_SCAN_CHAN_LIST_CMDID, + /** overwrite default priority table in scan scheduler */ + WMI_SCAN_SCH_PRIO_TBL_CMDID, + /** This command to adjust the priority and min.max_rest_time + * of an on ongoing scan request. + */ + WMI_SCAN_UPDATE_REQUEST_CMDID, - /** set OUI to be used in probe request if enabled */ - WMI_SCAN_PROB_REQ_OUI_CMDID, - /** config adaptive dwell scan */ - WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, + /** set OUI to be used in probe request if enabled */ + WMI_SCAN_PROB_REQ_OUI_CMDID, + /** config adaptive dwell scan */ + WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, - /* PDEV(physical device) specific commands */ - /** set regulatorty ctl id used by FW to determine the exact ctl power limits */ - WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PDEV), - /** set channel. mainly used for supporting monitor mode */ - WMI_PDEV_SET_CHANNEL_CMDID, - /** set pdev specific parameters */ - WMI_PDEV_SET_PARAM_CMDID, - /** enable packet log */ - WMI_PDEV_PKTLOG_ENABLE_CMDID, - /** disable packet log*/ - WMI_PDEV_PKTLOG_DISABLE_CMDID, - /** set wmm parameters */ - WMI_PDEV_SET_WMM_PARAMS_CMDID, - /** set HT cap ie that needs to be carried probe requests HT/VHT channels */ - WMI_PDEV_SET_HT_CAP_IE_CMDID, - /** set VHT cap ie that needs to be carried on probe requests on VHT channels */ - WMI_PDEV_SET_VHT_CAP_IE_CMDID, + /* PDEV(physical device) specific commands */ + /** set regulatorty ctl id used by FW to determine the exact ctl power limits */ + WMI_PDEV_SET_REGDOMAIN_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_PDEV), + /** set channel. mainly used for supporting monitor mode */ + WMI_PDEV_SET_CHANNEL_CMDID, + /** set pdev specific parameters */ + WMI_PDEV_SET_PARAM_CMDID, + /** enable packet log */ + WMI_PDEV_PKTLOG_ENABLE_CMDID, + /** disable packet log*/ + WMI_PDEV_PKTLOG_DISABLE_CMDID, + /** set wmm parameters */ + WMI_PDEV_SET_WMM_PARAMS_CMDID, + /** set HT cap ie that needs to be carried probe requests HT/VHT channels */ + WMI_PDEV_SET_HT_CAP_IE_CMDID, + /** set VHT cap ie that needs to be carried on probe requests on VHT channels */ + WMI_PDEV_SET_VHT_CAP_IE_CMDID, - /** Command to send the DSCP-to-TID map to the target */ - WMI_PDEV_SET_DSCP_TID_MAP_CMDID, - /** set quiet ie parameters. primarily used in AP mode */ - WMI_PDEV_SET_QUIET_MODE_CMDID, - /** Enable/Disable Green AP Power Save */ - WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, - /** get TPC config for the current operating channel */ - WMI_PDEV_GET_TPC_CONFIG_CMDID, + /** Command to send the DSCP-to-TID map to the target */ + WMI_PDEV_SET_DSCP_TID_MAP_CMDID, + /** set quiet ie parameters. primarily used in AP mode */ + WMI_PDEV_SET_QUIET_MODE_CMDID, + /** Enable/Disable Green AP Power Save */ + WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, + /** get TPC config for the current operating channel */ + WMI_PDEV_GET_TPC_CONFIG_CMDID, - /** set the base MAC address for the physical device before a VDEV is created. - * For firmware that doesn't support this feature and this command, the pdev - * MAC address will not be changed. */ - WMI_PDEV_SET_BASE_MACADDR_CMDID, + /** set the base MAC address for the physical device before a VDEV is created. + * For firmware that doesn't support this feature and this command, the pdev + * MAC address will not be changed. */ + WMI_PDEV_SET_BASE_MACADDR_CMDID, - /* eeprom content dump , the same to bdboard data */ - WMI_PDEV_DUMP_CMDID, - /* set LED configuration */ - WMI_PDEV_SET_LED_CONFIG_CMDID, - /* Get Current temprature of chip in Celcius degree*/ - WMI_PDEV_GET_TEMPERATURE_CMDID, - /* Set LED flashing behavior */ - WMI_PDEV_SET_LED_FLASHING_CMDID, - /** Enable/Disable Smart Antenna */ - WMI_PDEV_SMART_ANT_ENABLE_CMDID, - /** Set Smart Antenna RX antenna*/ - WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, - /** Override the antenna switch table */ - WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, - /** Override the CTL table */ - WMI_PDEV_SET_CTL_TABLE_CMDID, - /** Override the array gain table */ - WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, - /** FIPS test mode command */ - WMI_PDEV_FIPS_CMDID, - /** get CCK ANI level */ - WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, - /** get OFDM ANI level */ - WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, - /** NF Cal Power dBr/dBm */ - WMI_PDEV_GET_NFCAL_POWER_CMDID, - /** TxPPDU TPC */ - WMI_PDEV_GET_TPC_CMDID, - /** Set to enable MIB stats collection */ - WMI_MIB_STATS_ENABLE_CMDID, - /** Set preferred channel list for DBS Mgr */ - WMI_PDEV_SET_PCL_CMDID, - /** Set HW mode. Eg: single MAC, DBS & SBS, see soc_hw_mode_t for values */ - WMI_PDEV_SET_HW_MODE_CMDID, - /** Set DFS, SCAN modes and other FW configurations */ - WMI_PDEV_SET_MAC_CONFIG_CMDID, - /** Set per band and per pdev antenna chains */ - WMI_PDEV_SET_ANTENNA_MODE_CMDID, - /** Periodic channel stats request command */ - WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, - /** WMI command for power debug framework */ - WMI_PDEV_WAL_POWER_DEBUG_CMDID, - /** set per-AC rx reorder timeouts */ - WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, - /** WMI command for WOW gpio and type */ - WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, - /* Get current ANT's per chain's RSSI info */ - WMI_PDEV_GET_ANTDIV_STATUS_CMDID, - /** WMI command for getting Chip Power Stats */ - WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, - /** set stats reporting thresholds - see WMI_REPORT_STATS_EVENTID */ - WMI_PDEV_SET_STATS_THRESHOLD_CMDID, + /* eeprom content dump , the same to bdboard data */ + WMI_PDEV_DUMP_CMDID, + /* set LED configuration */ + WMI_PDEV_SET_LED_CONFIG_CMDID, + /* Get Current temprature of chip in Celcius degree */ + WMI_PDEV_GET_TEMPERATURE_CMDID, + /* Set LED flashing behavior */ + WMI_PDEV_SET_LED_FLASHING_CMDID, + /** Enable/Disable Smart Antenna */ + WMI_PDEV_SMART_ANT_ENABLE_CMDID, + /** Set Smart Antenna RX antenna*/ + WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, + /** Override the antenna switch table */ + WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, + /** Override the CTL table */ + WMI_PDEV_SET_CTL_TABLE_CMDID, + /** Override the array gain table */ + WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, + /** FIPS test mode command */ + WMI_PDEV_FIPS_CMDID, + /** get CCK ANI level */ + WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, + /** get OFDM ANI level */ + WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, + /** NF Cal Power dBr/dBm */ + WMI_PDEV_GET_NFCAL_POWER_CMDID, + /** TxPPDU TPC */ + WMI_PDEV_GET_TPC_CMDID, + /* Set to enable MIB stats collection */ + WMI_MIB_STATS_ENABLE_CMDID, - /* VDEV (virtual device) specific commands */ - /** vdev create */ - WMI_VDEV_CREATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_VDEV), - /** vdev delete */ - WMI_VDEV_DELETE_CMDID, - /** vdev start request */ - WMI_VDEV_START_REQUEST_CMDID, - /** vdev restart request (RX only, NO TX, used for CAC period)*/ - WMI_VDEV_RESTART_REQUEST_CMDID, - /** vdev up request */ - WMI_VDEV_UP_CMDID, - /** vdev stop request */ - WMI_VDEV_STOP_CMDID, - /** vdev down request */ - WMI_VDEV_DOWN_CMDID, - /* set a vdev param */ - WMI_VDEV_SET_PARAM_CMDID, - /* set a key (used for setting per peer unicast and per vdev multicast) */ - WMI_VDEV_INSTALL_KEY_CMDID, + /** Set preferred channel list for DBS Mgr */ + WMI_PDEV_SET_PCL_CMDID, + /** Set HW mode. Eg: single MAC, DBS & SBS, + * see soc_hw_mode_t for values + */ + WMI_PDEV_SET_HW_MODE_CMDID, + /** Set DFS, SCAN modes and other FW configurations */ + WMI_PDEV_SET_MAC_CONFIG_CMDID, + /** Set per band and per pdev antenna chains */ + WMI_PDEV_SET_ANTENNA_MODE_CMDID, + /** Periodic channel stats request command */ + WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, + /** WMI command for power debug framework */ + WMI_PDEV_WAL_POWER_DEBUG_CMDID, + /** set per-AC rx reorder timeouts */ + WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, + /** WMI command for WOW gpio and type */ + WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, + /* Get current ANT's per chain's RSSI info */ + WMI_PDEV_GET_ANTDIV_STATUS_CMDID, + /** WMI command for getting Chip Power Stats */ + WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, + /** set stats reporting thresholds - see WMI_REPORT_STATS_EVENTID */ + WMI_PDEV_SET_STATS_THRESHOLD_CMDID, - /* wnm sleep mode command */ - WMI_VDEV_WNM_SLEEPMODE_CMDID, - WMI_VDEV_WMM_ADDTS_CMDID, - WMI_VDEV_WMM_DELTS_CMDID, - WMI_VDEV_SET_WMM_PARAMS_CMDID, - WMI_VDEV_SET_GTX_PARAMS_CMDID, - WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, + /* VDEV (virtual device) specific commands */ + /** vdev create */ + WMI_VDEV_CREATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_VDEV), + /** vdev delete */ + WMI_VDEV_DELETE_CMDID, + /** vdev start request */ + WMI_VDEV_START_REQUEST_CMDID, + /** vdev restart request (RX only, NO TX, used for CAC period)*/ + WMI_VDEV_RESTART_REQUEST_CMDID, + /** vdev up request */ + WMI_VDEV_UP_CMDID, + /** vdev stop request */ + WMI_VDEV_STOP_CMDID, + /** vdev down request */ + WMI_VDEV_DOWN_CMDID, + /* set a vdev param */ + WMI_VDEV_SET_PARAM_CMDID, + /* set a key (used for setting per peer unicast and per vdev multicast) */ + WMI_VDEV_INSTALL_KEY_CMDID, - WMI_VDEV_PLMREQ_START_CMDID, - WMI_VDEV_PLMREQ_STOP_CMDID, - /* TSF timestamp action for specified vdev */ - WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, - /** set the additional IEs in probe requests for scan or - * assoc req etc for frames FW locally generates */ - WMI_VDEV_SET_IE_CMDID, + /* wnm sleep mode command */ + WMI_VDEV_WNM_SLEEPMODE_CMDID, + WMI_VDEV_WMM_ADDTS_CMDID, + WMI_VDEV_WMM_DELTS_CMDID, + WMI_VDEV_SET_WMM_PARAMS_CMDID, + WMI_VDEV_SET_GTX_PARAMS_CMDID, + WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, - WMI_VDEV_RATEMASK_CMDID, - /** ATF VDEV REQUEST commands. */ - WMI_VDEV_ATF_REQUEST_CMDID, - /** Command to send the DSCP-to-TID map to the target for VAP */ - WMI_VDEV_SET_DSCP_TID_MAP_CMDID, - /* Configure filter for Neighbor Rx Pkt (smart mesh selective listening) */ - WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, - /** set quiet ie parameters. primarily used in AP mode */ - WMI_VDEV_SET_QUIET_MODE_CMDID, - /** To set custom aggregation size for per vdev */ - WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, + WMI_VDEV_PLMREQ_START_CMDID, + WMI_VDEV_PLMREQ_STOP_CMDID, + /* TSF timestamp action for specified vdev */ + WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, + /* + * set the additional IEs in probe requests for scan or + * assoc req etc for frames FW locally generates + */ + WMI_VDEV_SET_IE_CMDID, - /* peer specific commands */ + WMI_VDEV_RATEMASK_CMDID, + /** ATF VDEV REQUEST commands. */ + WMI_VDEV_ATF_REQUEST_CMDID, + /** Command to send the DSCP-to-TID map to the target for VAP */ + WMI_VDEV_SET_DSCP_TID_MAP_CMDID, + /* + * Configure filter for Neighbor Rx Pkt + * (smart mesh selective listening) + */ + WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, + /** set quiet ie parameters. primarily used in AP mode */ + WMI_VDEV_SET_QUIET_MODE_CMDID, + /** To set custom aggregation size for per vdev */ + WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, - /** create a peer */ - WMI_PEER_CREATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PEER), - /** delete a peer */ - WMI_PEER_DELETE_CMDID, - /** flush specific tid queues of a peer */ - WMI_PEER_FLUSH_TIDS_CMDID, - /** set a parameter of a peer */ - WMI_PEER_SET_PARAM_CMDID, - /** set peer to associated state. will cary all parameters determined during assocication time */ - WMI_PEER_ASSOC_CMDID, - /**add a wds (4 address) entry. used only for testing WDS feature on AP products */ - WMI_PEER_ADD_WDS_ENTRY_CMDID, - /**remove wds (4 address) entry. used only for testing WDS feature on AP products */ - WMI_PEER_REMOVE_WDS_ENTRY_CMDID, - /** set up mcast group infor for multicast to unicast conversion */ - WMI_PEER_MCAST_GROUP_CMDID, - /** request peer info from FW. FW shall respond with PEER_INFO_EVENTID */ - WMI_PEER_INFO_REQ_CMDID, - /** request the estimated link speed for the peer. FW shall respond with - * WMI_PEER_ESTIMATED_LINKSPEED_EVENTID. - */ - WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, - /** Set the conditions to report peer justified rate to driver - * The justified rate means the the user-rate is justified by PER. - */ - WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, + /* DISA feature: Encrypt-decrypt data request */ + WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, - /** update a wds (4 address) entry */ - WMI_PEER_UPDATE_WDS_ENTRY_CMDID, - /** add a proxy sta entry */ - WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, - /** Set Smart Antenna TX antenna */ - WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, - /** Set Smart Antenna TX train info */ - WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, - /** Set SA node config options */ - WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, - /** ATF PEER REQUEST commands */ - WMI_PEER_ATF_REQUEST_CMDID, - /** bandwidth fairness (BWF) peer configuration request command */ - WMI_PEER_BWF_REQUEST_CMDID, - /** rx reorder queue setup for peer/tid */ - WMI_PEER_REORDER_QUEUE_SETUP_CMDID, - /** rx reorder queue remove for peer/tid */ - WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, - /** specify a limit for rx A-MPDU block size */ - WMI_PEER_SET_RX_BLOCKSIZE_CMDID, - /** request peer antdiv info from FW. FW shall respond with PEER_ANTDIV_INFO_EVENTID */ - WMI_PEER_ANTDIV_INFO_REQ_CMDID, + /* peer specific commands */ + + /** create a peer */ + WMI_PEER_CREATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PEER), + /** delete a peer */ + WMI_PEER_DELETE_CMDID, + /** flush specific tid queues of a peer */ + WMI_PEER_FLUSH_TIDS_CMDID, + /** set a parameter of a peer */ + WMI_PEER_SET_PARAM_CMDID, + /** set peer to associated state. will cary all parameters determined during assocication time */ + WMI_PEER_ASSOC_CMDID, + /**add a wds (4 address ) entry. used only for testing WDS feature on AP products */ + WMI_PEER_ADD_WDS_ENTRY_CMDID, + /**remove wds (4 address ) entry. used only for testing WDS feature on AP products */ + WMI_PEER_REMOVE_WDS_ENTRY_CMDID, + /** set up mcast group infor for multicast to unicast conversion */ + WMI_PEER_MCAST_GROUP_CMDID, + /** request peer info from FW. FW shall respond with PEER_INFO_EVENTID */ + WMI_PEER_INFO_REQ_CMDID, + + /** request the estimated link speed for the peer. FW shall respond with + * WMI_PEER_ESTIMATED_LINKSPEED_EVENTID. + */ + WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, + /* + * Set the conditions to report peer justified rate to driver + * The justified rate means the the user-rate is justified by PER. + */ + WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, + /** update a wds (4 address) entry */ + WMI_PEER_UPDATE_WDS_ENTRY_CMDID, + /** add a proxy sta entry */ + WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, + /** Set Smart Antenna TX antenna */ + WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, + /** Set Smart Antenna TX train info */ + WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, + /** Set SA node config options */ + WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, + /** ATF PEER REQUEST commands */ + WMI_PEER_ATF_REQUEST_CMDID, + /** bandwidth fairness (BWF) peer configuration request command */ + WMI_PEER_BWF_REQUEST_CMDID, + /** rx reorder queue setup for peer/tid */ + WMI_PEER_REORDER_QUEUE_SETUP_CMDID, + /** rx reorder queue remove for peer/tid */ + WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, + /** specify a limit for rx A-MPDU block size */ + WMI_PEER_SET_RX_BLOCKSIZE_CMDID, + /** + * request peer antdiv info from FW. FW shall respond with + * PEER_ANTDIV_INFO_EVENTID + */ + WMI_PEER_ANTDIV_INFO_REQ_CMDID, - /* beacon/management specific commands */ + /* beacon/management specific commands */ - /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */ - WMI_BCN_TX_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MGMT), - /** transmit beacon by value */ - WMI_PDEV_SEND_BCN_CMDID, - /** set the beacon template. used in beacon offload mode to setup the - * the common beacon template with the FW to be used by FW to generate beacons */ - WMI_BCN_TMPL_CMDID, - /** set beacon filter with FW */ - WMI_BCN_FILTER_RX_CMDID, - /* enable/disable filtering of probe requests in the firmware */ - WMI_PRB_REQ_FILTER_RX_CMDID, - /** transmit management frame by value. will be deprecated */ - WMI_MGMT_TX_CMDID, - /** set the probe response template. used in beacon offload mode to setup the - * the common probe response template with the FW to be used by FW to generate - * probe responses */ - WMI_PRB_TMPL_CMDID, - /** Transmit Mgmt frame by reference */ - WMI_MGMT_TX_SEND_CMDID, + /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */ + WMI_BCN_TX_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MGMT), + /** transmit beacon by value */ + WMI_PDEV_SEND_BCN_CMDID, + /** set the beacon template. used in beacon offload mode to setup the + * the common beacon template with the FW to be used by FW to generate beacons */ + WMI_BCN_TMPL_CMDID, + /** set beacon filter with FW */ + WMI_BCN_FILTER_RX_CMDID, + /* enable/disable filtering of probe requests in the firmware */ + WMI_PRB_REQ_FILTER_RX_CMDID, + /** transmit management frame by value. will be deprecated */ + WMI_MGMT_TX_CMDID, + /** set the probe response template. used in beacon offload mode to setup the + * the common probe response template with the FW to be used by FW to generate + * probe responses */ + WMI_PRB_TMPL_CMDID, + /** Transmit Mgmt frame by reference */ + WMI_MGMT_TX_SEND_CMDID, - /** commands to directly control ba negotiation directly from host. only used in test mode */ + /** commands to directly control ba negotiation directly from host. only used in test mode */ - /** turn off FW Auto addba mode and let host control addba */ - WMI_ADDBA_CLEAR_RESP_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_BA_NEG), - /** send add ba request */ - WMI_ADDBA_SEND_CMDID, - WMI_ADDBA_STATUS_CMDID, - /** send del ba */ - WMI_DELBA_SEND_CMDID, - /** set add ba response will be used by FW to generate addba response*/ - WMI_ADDBA_SET_RESP_CMDID, - /** send single VHT MPDU with AMSDU */ - WMI_SEND_SINGLEAMSDU_CMDID, + /** turn off FW Auto addba mode and let host control addba */ + WMI_ADDBA_CLEAR_RESP_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_BA_NEG), + /** send add ba request */ + WMI_ADDBA_SEND_CMDID, + WMI_ADDBA_STATUS_CMDID, + /** send del ba */ + WMI_DELBA_SEND_CMDID, + /** set add ba response will be used by FW to generate addba response*/ + WMI_ADDBA_SET_RESP_CMDID, + /** send single VHT MPDU with AMSDU */ + WMI_SEND_SINGLEAMSDU_CMDID, - /** Station power save specific config */ - /** enable/disable station powersave */ - WMI_STA_POWERSAVE_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_STA_PS), - /** set station power save specific parameter */ - WMI_STA_POWERSAVE_PARAM_CMDID, - /** set station mimo powersave mode */ - WMI_STA_MIMO_PS_MODE_CMDID, + /** Station power save specific config */ + /** enable/disable station powersave */ + WMI_STA_POWERSAVE_MODE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_STA_PS), + /** set station power save specific parameter */ + WMI_STA_POWERSAVE_PARAM_CMDID, + /** set station mimo powersave mode */ + WMI_STA_MIMO_PS_MODE_CMDID, + /** DFS-specific commands */ + /** enable DFS (radar detection)*/ + WMI_PDEV_DFS_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_DFS), + /** disable DFS (radar detection)*/ + WMI_PDEV_DFS_DISABLE_CMDID, + /** enable DFS phyerr/parse filter offload */ + WMI_DFS_PHYERR_FILTER_ENA_CMDID, + /** enable DFS phyerr/parse filter offload */ + WMI_DFS_PHYERR_FILTER_DIS_CMDID, + /** enable DFS phyerr processing offload */ + WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, + /** disable DFS phyerr processing offload */ + WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, + /** set ADFS channel config */ + WMI_VDEV_ADFS_CH_CFG_CMDID, + /** abort ADFS off-channel-availability-check currently in progress */ + WMI_VDEV_ADFS_OCAC_ABORT_CMDID, - /** DFS-specific commands */ - /** enable DFS (radar detection)*/ - WMI_PDEV_DFS_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_DFS), - /** disable DFS (radar detection)*/ - WMI_PDEV_DFS_DISABLE_CMDID, - /** enable DFS phyerr/parse filter offload */ - WMI_DFS_PHYERR_FILTER_ENA_CMDID, - /** enable DFS phyerr/parse filter offload */ - WMI_DFS_PHYERR_FILTER_DIS_CMDID, - - /* Roaming specific commands */ - /** set roam scan mode */ - WMI_ROAM_SCAN_MODE = WMI_CMD_GRP_START_ID(WMI_GRP_ROAM), - /** set roam scan rssi threshold below which roam scan is enabled */ - WMI_ROAM_SCAN_RSSI_THRESHOLD, - /** set roam scan period for periodic roam scan mode */ - WMI_ROAM_SCAN_PERIOD, - /** set roam scan trigger rssi change threshold */ - WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, - /** set roam AP profile */ - WMI_ROAM_AP_PROFILE, - /** set channel list for roam scans */ - WMI_ROAM_CHAN_LIST, - /** Stop scan command */ + /* Roaming specific commands */ + /** set roam scan mode */ + WMI_ROAM_SCAN_MODE = WMI_CMD_GRP_START_ID(WMI_GRP_ROAM), + /** set roam scan rssi threshold below which roam scan is enabled */ + WMI_ROAM_SCAN_RSSI_THRESHOLD, + /** set roam scan period for periodic roam scan mode */ + WMI_ROAM_SCAN_PERIOD, + /** set roam scan trigger rssi change threshold */ + WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, + /** set roam AP profile */ + WMI_ROAM_AP_PROFILE, + /** set channel list for roam scans */ + WMI_ROAM_CHAN_LIST, + /** Stop scan command */ WMI_ROAM_SCAN_CMD, - /** roaming sme offload sync complete */ - WMI_ROAM_SYNCH_COMPLETE, - /** set ric request element for 11r roaming */ + /** roaming sme offload sync complete */ + WMI_ROAM_SYNCH_COMPLETE, + /** set ric request element for 11r roaming */ WMI_ROAM_SET_RIC_REQUEST_CMDID, /** Invoke roaming forcefully */ - WMI_ROAM_INVOKE_CMDID, - /** roaming filter cmd to allow further filtering of roaming candidate */ - WMI_ROAM_FILTER_CMDID, - /** set gateway ip, mac and retries for subnet change detection */ - WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, - /** configure thresholds for MAWC */ - WMI_ROAM_CONFIGURE_MAWC_CMDID, - /** configure MultiBand Operation(refer WFA MBO spec) parameter */ - WMI_ROAM_SET_MBO_PARAM_CMDID, /* DEPRECATED */ + WMI_ROAM_INVOKE_CMDID, + /** roaming filter cmd to allow further filtering of roaming candidate */ + WMI_ROAM_FILTER_CMDID, + /** set gateway ip, mac and retries for subnet change detection */ + WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, + /** configure thresholds for MAWC */ + WMI_ROAM_CONFIGURE_MAWC_CMDID, + /** configure MultiBand Operation(refer WFA MBO spec) parameter */ + WMI_ROAM_SET_MBO_PARAM_CMDID, /* DEPRECATED */ - /** offload scan specific commands */ - /** set offload scan AP profile */ - WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_CMD_GRP_START_ID(WMI_GRP_OFL_SCAN), - /** remove offload scan AP profile */ - WMI_OFL_SCAN_REMOVE_AP_PROFILE, - /** set offload scan period */ - WMI_OFL_SCAN_PERIOD, + /** offload scan specific commands */ + /** set offload scan AP profile */ + WMI_OFL_SCAN_ADD_AP_PROFILE = + WMI_CMD_GRP_START_ID(WMI_GRP_OFL_SCAN), + /** remove offload scan AP profile */ + WMI_OFL_SCAN_REMOVE_AP_PROFILE, + /** set offload scan period */ + WMI_OFL_SCAN_PERIOD, - /* P2P specific commands */ - /**set P2P device info. FW will used by FW to create P2P IE to be carried in probe response - * generated during p2p listen and for p2p discoverability */ - WMI_P2P_DEV_SET_DEVICE_INFO = WMI_CMD_GRP_START_ID(WMI_GRP_P2P), - /** enable/disable p2p discoverability on STA/AP VDEVs */ - WMI_P2P_DEV_SET_DISCOVERABILITY, - /** set p2p ie to be carried in beacons generated by FW for GO */ - WMI_P2P_GO_SET_BEACON_IE, - /** set p2p ie to be carried in probe response frames generated by FW for GO */ - WMI_P2P_GO_SET_PROBE_RESP_IE, - /** set the vendor specific p2p ie data. FW will use this to parse the P2P NoA - * attribute in the beacons/probe responses received. - * Note: This command is currently used only for Apple P2P implementation. - */ - WMI_P2P_SET_VENDOR_IE_DATA_CMDID, - /** set the configure of p2p find offload */ - WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, - /** set the vendor specific p2p ie data for p2p find offload using */ - WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, - /** set the BSSID/device name pattern of p2p find offload */ - WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, - /** set OppPS related parameters **/ - WMI_P2P_SET_OPPPS_PARAM_CMDID, - /** set listen offload start related parameters */ - WMI_P2P_LISTEN_OFFLOAD_START_CMDID, - /** set listen offload stop related parameters */ - WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, + /* P2P specific commands */ + /**set P2P device info. FW will used by FW to create P2P IE to be carried in probe response + * generated during p2p listen and for p2p discoverability */ + WMI_P2P_DEV_SET_DEVICE_INFO = WMI_CMD_GRP_START_ID(WMI_GRP_P2P), + /** enable/disable p2p discoverability on STA/AP VDEVs */ + WMI_P2P_DEV_SET_DISCOVERABILITY, + /** set p2p ie to be carried in beacons generated by FW for GO */ + WMI_P2P_GO_SET_BEACON_IE, + /** set p2p ie to be carried in probe response frames generated by FW for GO */ + WMI_P2P_GO_SET_PROBE_RESP_IE, + /** set the vendor specific p2p ie data. FW will use this to parse the P2P NoA + * attribute in the beacons/probe responses received. + */ + WMI_P2P_SET_VENDOR_IE_DATA_CMDID, + /** set the configure of p2p find offload */ + WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, + /** set the vendor specific p2p ie data for p2p find offload using */ + WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, + /** set the BSSID/device name pattern of p2p find offload */ + WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, + /** set OppPS related parameters **/ + WMI_P2P_SET_OPPPS_PARAM_CMDID, + /** set listen offload start related parameters */ + WMI_P2P_LISTEN_OFFLOAD_START_CMDID, + /** set listen offload stop related parameters */ + WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, - /** AP power save specific config */ - /** set AP power save specific param */ - WMI_AP_PS_PEER_PARAM_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_AP_PS), - /** set AP UAPSD coex pecific param */ - WMI_AP_PS_PEER_UAPSD_COEX_CMDID, - /** set Enhanced Green AP param */ - WMI_AP_PS_EGAP_PARAM_CMDID, + /** AP power save specific config */ + /** set AP power save specific param */ + WMI_AP_PS_PEER_PARAM_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_AP_PS), + /** set AP UAPSD coex pecific param */ + WMI_AP_PS_PEER_UAPSD_COEX_CMDID, - /** Rate-control specific commands */ - WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RATE_CTRL), + /** set Enhanced Green AP param */ + WMI_AP_PS_EGAP_PARAM_CMDID, - /** WLAN Profiling commands. */ - WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PROFILE), - WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, - WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, - WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, - WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, + /** Rate-control specific commands */ + WMI_PEER_RATE_RETRY_SCHED_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_RATE_CTRL), - /** Suspend resume command Ids */ - WMI_PDEV_SUSPEND_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SUSPEND), - WMI_PDEV_RESUME_CMDID, + /** WLAN Profiling commands. */ + WMI_WLAN_PROFILE_TRIGGER_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_PROFILE), + WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, + WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, + WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, + WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, - /* Beacon filter commands */ - /** add a beacon filter */ - WMI_ADD_BCN_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_BCN_FILTER), - /** remove a beacon filter */ - WMI_RMV_BCN_FILTER_CMDID, + /** Suspend resume command Ids */ + WMI_PDEV_SUSPEND_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SUSPEND), + WMI_PDEV_RESUME_CMDID, - /* WOW Specific WMI commands*/ - /** add pattern for awake */ - WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_WOW), - /** deleta a wake pattern */ - WMI_WOW_DEL_WAKE_PATTERN_CMDID, - /** enable/deisable wake event */ - WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, - /** enable WOW */ - WMI_WOW_ENABLE_CMDID, - /** host woke up from sleep event to FW. Generated in response to WOW Hardware event */ - WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, - /* IOAC add keep alive cmd. */ - WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, - /* IOAC del keep alive cmd. */ - WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, - /* IOAC add pattern for awake */ - WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, - /* IOAC deleta a wake pattern */ - WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, - /* D0-WOW enable or disable cmd */ - WMI_D0_WOW_ENABLE_DISABLE_CMDID, - /* enable extend WoW */ - WMI_EXTWOW_ENABLE_CMDID, - /* Extend WoW command to configure app type1 parameter */ - WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, - /* Extend WoW command to configure app type2 parameter */ - WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, - /* enable ICMPv6 Network advertisement filtering */ - WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, - /* - * Set a pattern to match UDP packet in WOW mode. - * If match, construct a tx frame in a local buffer - * to send through the peer AP to the entity in the - * IP network that sent the UDP packet to this STA. - */ - WMI_WOW_UDP_SVC_OFLD_CMDID, - /* configure WOW host wakeup PIN pattern */ - WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, + /* Beacon filter commands */ + /** add a beacon filter */ + WMI_ADD_BCN_FILTER_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_BCN_FILTER), + /** remove a beacon filter */ + WMI_RMV_BCN_FILTER_CMDID, - /* Set which action category should wake the host from suspend */ - WMI_WOW_SET_ACTION_WAKE_UP_CMDID, + /* WOW Specific WMI commands */ + /** add pattern for awake */ + WMI_WOW_ADD_WAKE_PATTERN_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_WOW), + /** deleta a wake pattern */ + WMI_WOW_DEL_WAKE_PATTERN_CMDID, + /** enable/deisable wake event */ + WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, + /** enable WOW */ + WMI_WOW_ENABLE_CMDID, + /** host woke up from sleep event to FW. Generated in response to WOW Hardware event */ + WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, + /* IOAC add keep alive cmd. */ + WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, + /* IOAC del keep alive cmd. */ + WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, + /* IOAC add pattern for awake */ + WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, + /* IOAC deleta a wake pattern */ + WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, + /* D0-WOW enable or disable cmd */ + WMI_D0_WOW_ENABLE_DISABLE_CMDID, + /* enable extend WoW */ + WMI_EXTWOW_ENABLE_CMDID, + /* Extend WoW command to configure app type1 parameter */ + WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, + /* Extend WoW command to configure app type2 parameter */ + WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, + /* enable ICMPv6 Network advertisement filtering */ + WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, + /* + * Set a pattern to match UDP packet in WOW mode. + * If match, construct a tx frame in a local buffer + * to send through the peer AP to the entity in the + * IP network that sent the UDP packet to this STA. + */ + WMI_WOW_UDP_SVC_OFLD_CMDID, - /* RTT measurement related cmd */ - /** request to make an RTT measurement */ - WMI_RTT_MEASREQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RTT), - /** request to report a tsf measurement */ - WMI_RTT_TSF_CMDID, + /* configure WOW host wakeup PIN pattern */ + WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, - /** spectral scan command */ - /** configure spectral scan */ - WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SPECTRAL), - /** enable/disable spectral scan and trigger */ - WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, + /* Set which action category should wake the host from suspend */ + WMI_WOW_SET_ACTION_WAKE_UP_CMDID, - /* F/W stats */ - /** one time request for stats */ - WMI_REQUEST_STATS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_STATS), - /** Push MCC Adaptive Scheduler Stats to Firmware */ - WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, - /** one time request for txrx stats */ - WMI_REQUEST_STATS_EXT_CMDID, - /* Link Layer stats */ - /** Request for link layer stats */ - WMI_REQUEST_LINK_STATS_CMDID, - /** Request for setting params to link layer stats */ - WMI_START_LINK_STATS_CMDID, - /** Request to clear stats*/ - WMI_CLEAR_LINK_STATS_CMDID, + /* RTT measurement related cmd */ + /** request to make an RTT measurement */ + WMI_RTT_MEASREQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RTT), + /** request to report a tsf measurement */ + WMI_RTT_TSF_CMDID, - /** Request for getting the Firmware Memory Dump */ - WMI_GET_FW_MEM_DUMP_CMDID, + /** spectral scan command */ + /** configure spectral scan */ + WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_SPECTRAL), + /** enable/disable spectral scan and trigger */ + WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, - /** Request to flush of the buffered debug messages */ - WMI_DEBUG_MESG_FLUSH_CMDID, + /* F/W stats */ + /** one time request for stats */ + WMI_REQUEST_STATS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_STATS), + /** Push MCC Adaptive Scheduler Stats to Firmware */ + WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, + /** one time request for txrx stats */ + WMI_REQUEST_STATS_EXT_CMDID, - /** Cmd to configure the verbose level */ - WMI_DIAG_EVENT_LOG_CONFIG_CMDID, + /* Link Layer stats */ + /** Request for link layer stats */ + WMI_REQUEST_LINK_STATS_CMDID, + /** Request for setting params to link layer stats */ + WMI_START_LINK_STATS_CMDID, + /** Request to clear stats*/ + WMI_CLEAR_LINK_STATS_CMDID, - /** One time request for wlan stats */ - WMI_REQUEST_WLAN_STATS_CMDID, + /** Request for getting the Firmware Memory Dump */ + WMI_GET_FW_MEM_DUMP_CMDID, - /** ARP OFFLOAD REQUEST*/ - WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ARP_NS_OFL), + /** Request to flush of the buffered debug messages */ + WMI_DEBUG_MESG_FLUSH_CMDID, - /** Proactive ARP Response Add Pattern Command*/ - WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, + /** Cmd to configure the verbose level */ + WMI_DIAG_EVENT_LOG_CONFIG_CMDID, - /** Proactive ARP Response Del Pattern Command*/ - WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, + /** One time request for wlan stats */ + WMI_REQUEST_WLAN_STATS_CMDID, - /** NS offload confid*/ - WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NLO_OFL), + /** ARP OFFLOAD REQUEST*/ + WMI_SET_ARP_NS_OFFLOAD_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_ARP_NS_OFL), - /** APFIND Config */ - WMI_APFIND_CMDID, + /** Proactive ARP Response Add Pattern Command*/ + WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, - /** Passpoint list config */ - WMI_PASSPOINT_LIST_CONFIG_CMDID, + /** Proactive ARP Response Del Pattern Command*/ + WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, - /** configure supprssing parameters for MAWC */ - WMI_NLO_CONFIGURE_MAWC_CMDID, + /** NS offload config*/ + WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_NLO_OFL), - /* GTK offload Specific WMI commands*/ - WMI_GTK_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_GTK_OFL), + /** APFIND Config */ + WMI_APFIND_CMDID, - /* CSA offload Specific WMI commands*/ - /** csa offload enable */ - WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CSA_OFL), - /** chan switch command */ - WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, + /** Passpoint list config */ + WMI_PASSPOINT_LIST_CONFIG_CMDID, - /* Chatter commands*/ - /* Change chatter mode of operation */ - WMI_CHATTER_SET_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CHATTER), - /** chatter add coalescing filter command */ - WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, - /** chatter delete coalescing filter command */ - WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, - /** chatter coalecing query command */ - WMI_CHATTER_COALESCING_QUERY_CMDID, + /** configure supprssing parameters for MAWC */ + WMI_NLO_CONFIGURE_MAWC_CMDID, - /**addba specific commands */ - /** start the aggregation on this TID */ - WMI_PEER_TID_ADDBA_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TID_ADDBA), - /** stop the aggregation on this TID */ - WMI_PEER_TID_DELBA_CMDID, + /* GTK offload Specific WMI commands */ + WMI_GTK_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_GTK_OFL), - /** set station mimo powersave method */ - WMI_STA_DTIM_PS_METHOD_CMDID, - /** Configure the Station UAPSD AC Auto Trigger Parameters */ - WMI_STA_UAPSD_AUTO_TRIG_CMDID, - /** Configure the Keep Alive Parameters */ - WMI_STA_KEEPALIVE_CMDID, + /* CSA offload Specific WMI commands */ + /** csa offload enable */ + WMI_CSA_OFFLOAD_ENABLE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_CSA_OFL), + /** chan switch command */ + WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, - /* Request ssn from target for a sta/tid pair */ - WMI_BA_REQ_SSN_CMDID, + /* Chatter commands */ + /* Change chatter mode of operation */ + WMI_CHATTER_SET_MODE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_CHATTER), + /** chatter add coalescing filter command */ + WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, + /** chatter delete coalescing filter command */ + WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, + /** chatter coalecing query command */ + WMI_CHATTER_COALESCING_QUERY_CMDID, + /**addba specific commands */ + /** start the aggregation on this TID */ + WMI_PEER_TID_ADDBA_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_TID_ADDBA), + /** stop the aggregation on this TID */ + WMI_PEER_TID_DELBA_CMDID, - /* misc command group */ - /** echo command mainly used for testing */ - WMI_ECHO_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MISC), + /** set station mimo powersave method */ + WMI_STA_DTIM_PS_METHOD_CMDID, + /** Configure the Station UAPSD AC Auto Trigger Parameters */ + WMI_STA_UAPSD_AUTO_TRIG_CMDID, + /** Configure the Keep Alive Parameters */ + WMI_STA_KEEPALIVE_CMDID, - /* !!IMPORTANT!! - * If you need to add a new WMI command to the WMI_GRP_MISC sub-group, - * please make sure you add it BEHIND WMI_PDEV_UTF_CMDID, - * as we MUST have a fixed value here to maintain compatibility between - * UTF and the ART2 driver - */ - /** UTF WMI commands */ - WMI_PDEV_UTF_CMDID, + /* Request ssn from target for a sta/tid pair */ + WMI_BA_REQ_SSN_CMDID, + /* misc command group */ + /** echo command mainly used for testing */ + WMI_ECHO_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MISC), - /** set debug log config */ - WMI_DBGLOG_CFG_CMDID, - /* QVIT specific command id */ - WMI_PDEV_QVIT_CMDID, - /* Factory Testing Mode request command - * used for integrated chipsets */ - WMI_PDEV_FTM_INTG_CMDID, - /* set and get keepalive parameters command */ - WMI_VDEV_SET_KEEPALIVE_CMDID, - WMI_VDEV_GET_KEEPALIVE_CMDID, - /* For fw recovery test command */ - WMI_FORCE_FW_HANG_CMDID, - /* Set Mcast/Bdcast filter */ - WMI_SET_MCASTBCAST_FILTER_CMDID, - /** set thermal management params **/ - WMI_THERMAL_MGMT_CMDID, - /** set host auto shutdown params **/ - WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, - /** set tpc chainmask config command */ - WMI_TPC_CHAINMASK_CONFIG_CMDID, - /** set Antenna diversity command */ - WMI_SET_ANTENNA_DIVERSITY_CMDID, - /** Set OCB Sched Request, deprecated */ - WMI_OCB_SET_SCHED_CMDID, - /** Set rssi monitoring config command */ - WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, - /** Enable/disable Large Receive Offload processing; provide cfg params */ - WMI_LRO_CONFIG_CMDID, - /** transfer data from host to firmware to write flash */ - WMI_TRANSFER_DATA_TO_FLASH_CMDID, - /** Command to enable/disable filtering of multicast IP with unicast mac */ - WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, - /** Command to control WISA mode */ - WMI_VDEV_WISA_CMDID, - /** set debug log time stamp sync up with host */ - WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, - /** Command for host to set/delete multiple mcast filters */ - WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, - /** upload a requested section of data from firmware flash to host */ - WMI_READ_DATA_FROM_FLASH_CMDID, + /* !!IMPORTANT!! + * If you need to add a new WMI command to the WMI_GRP_MISC sub-group, + * please make sure you add it BEHIND WMI_PDEV_UTF_CMDID, + * as we MUST have a fixed value here to maintain compatibility between + * UTF and the ART2 driver + */ + /** UTF WMI commands */ + WMI_PDEV_UTF_CMDID, - /* GPIO Configuration */ - WMI_GPIO_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_GPIO), - WMI_GPIO_OUTPUT_CMDID, + /** set debug log config */ + WMI_DBGLOG_CFG_CMDID, + /* QVIT specific command id */ + WMI_PDEV_QVIT_CMDID, + /* Factory Testing Mode request command + * used for integrated chipsets */ + WMI_PDEV_FTM_INTG_CMDID, + /* set and get keepalive parameters command */ + WMI_VDEV_SET_KEEPALIVE_CMDID, + WMI_VDEV_GET_KEEPALIVE_CMDID, + /* For fw recovery test command */ + WMI_FORCE_FW_HANG_CMDID, + /* Set Mcast/Bdcast filter */ + WMI_SET_MCASTBCAST_FILTER_CMDID, + /** set thermal management params **/ + WMI_THERMAL_MGMT_CMDID, + /** set host auto shutdown params **/ + WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, + /** set tpc chainmask config command */ + WMI_TPC_CHAINMASK_CONFIG_CMDID, + /** set Antenna diversity command */ + WMI_SET_ANTENNA_DIVERSITY_CMDID, + /** Set OCB Sched Request, deprecated */ + WMI_OCB_SET_SCHED_CMDID, + /* Set rssi monitoring config command */ + WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, + /* Enable/disable Large Receive Offload processing; + * provide cfg params */ + WMI_LRO_CONFIG_CMDID, + /*transfer data from host to firmware to write flash */ + WMI_TRANSFER_DATA_TO_FLASH_CMDID, + /** Command to enable/disable filtering of multicast IP with unicast mac */ + WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, + /** Command to control WISA mode */ + WMI_VDEV_WISA_CMDID, + /** set debug log time stamp sync up with host */ + WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, + /** Command for host to set/delete multiple mcast filters */ + WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, + /** upload a requested section of data from firmware flash to host */ + WMI_READ_DATA_FROM_FLASH_CMDID, - /* Txbf configuration command */ - WMI_TXBF_CMDID, + /* GPIO Configuration */ + WMI_GPIO_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_GPIO), + WMI_GPIO_OUTPUT_CMDID, - /* FWTEST Commands */ - WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_FWTEST), + /* Txbf configuration command */ + WMI_TXBF_CMDID, + + /* FWTEST Commands */ + WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_FWTEST), /** set NoA descs **/ WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, /* UNIT Tests */ WMI_UNIT_TEST_CMDID, - /* set debug and tuning parameters */ - WMI_FWTEST_CMDID, - /* Q-Boost configuration test commands */ - WMI_QBOOST_CFG_CMDID, + /* set debug and tuning parameters */ + WMI_FWTEST_CMDID, + /* Q-Boost configuration test commands */ + WMI_QBOOST_CFG_CMDID, - /** TDLS Configuration */ - /** enable/disable TDLS */ - WMI_TDLS_SET_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDLS), - /** set tdls peer state */ - WMI_TDLS_PEER_UPDATE_CMDID, - /** TDLS Offchannel control */ - WMI_TDLS_SET_OFFCHAN_MODE_CMDID, + /** TDLS Configuration */ + /** enable/disable TDLS */ + WMI_TDLS_SET_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDLS), + /** set tdls peer state */ + WMI_TDLS_PEER_UPDATE_CMDID, + /** TDLS Offchannel control */ + WMI_TDLS_SET_OFFCHAN_MODE_CMDID, - /** Resmgr Configuration */ - /** Adaptive OCS is enabled by default in the FW. This command is used to - * disable FW based adaptive OCS. - */ - WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RESMGR), - /** set the requested channel time quota for the home channels */ - WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, - /** set the requested latency for the home channels */ - WMI_RESMGR_SET_CHAN_LATENCY_CMDID, + /** Resmgr Configuration */ + /** Adaptive OCS is enabled by default in the FW. This command is used to + * disable FW based adaptive OCS. + */ + WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_RESMGR), + /** set the requested channel time quota for the home channels */ + WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, + /** set the requested latency for the home channels */ + WMI_RESMGR_SET_CHAN_LATENCY_CMDID, - /** STA SMPS Configuration */ - /** force SMPS mode */ - WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_STA_SMPS), - /** set SMPS parameters */ - WMI_STA_SMPS_PARAM_CMDID, + /** STA SMPS Configuration */ + /** force SMPS mode */ + WMI_STA_SMPS_FORCE_MODE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_STA_SMPS), + /** set SMPS parameters */ + WMI_STA_SMPS_PARAM_CMDID, - /* Wlan HB commands*/ - /* enalbe/disable wlan HB */ - WMI_HB_SET_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_WLAN_HB), - /* set tcp parameters for wlan HB */ - WMI_HB_SET_TCP_PARAMS_CMDID, - /* set tcp pkt filter for wlan HB */ - WMI_HB_SET_TCP_PKT_FILTER_CMDID, - /* set udp parameters for wlan HB */ - WMI_HB_SET_UDP_PARAMS_CMDID, - /* set udp pkt filter for wlan HB */ - WMI_HB_SET_UDP_PKT_FILTER_CMDID, + /* Wlan HB commands */ + /* enalbe/disable wlan HB */ + WMI_HB_SET_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_WLAN_HB), + /* set tcp parameters for wlan HB */ + WMI_HB_SET_TCP_PARAMS_CMDID, + /* set tcp pkt filter for wlan HB */ + WMI_HB_SET_TCP_PKT_FILTER_CMDID, + /* set udp parameters for wlan HB */ + WMI_HB_SET_UDP_PARAMS_CMDID, + /* set udp pkt filter for wlan HB */ + WMI_HB_SET_UDP_PKT_FILTER_CMDID, - /** Wlan RMC commands*/ - /** enable/disable RMC */ - WMI_RMC_SET_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RMC), - /** configure action frame period */ - WMI_RMC_SET_ACTION_PERIOD_CMDID, - /** For debug/future enhancement purposes only, - * configures/finetunes RMC algorithms */ - WMI_RMC_CONFIG_CMDID, - /** select manual leader */ - WMI_RMC_SET_MANUAL_LEADER_CMDID, + /** Wlan RMC commands*/ + /** enable/disable RMC */ + WMI_RMC_SET_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_RMC), + /** configure action frame period */ + WMI_RMC_SET_ACTION_PERIOD_CMDID, + /** For debug/future enhancement purposes only, + * configures/finetunes RMC algorithms */ + WMI_RMC_CONFIG_CMDID, - /** WLAN MHF offload commands */ - /** enable/disable MHF offload */ - WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MHF_OFL), - /** Plumb routing table for MHF offload */ - WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, + /** WLAN MHF offload commands */ + /** enable/disable MHF offload */ + WMI_MHF_OFFLOAD_SET_MODE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_MHF_OFL), + /** Plumb routing table for MHF offload */ + WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, - /*location scan commands*/ - /*start batch scan*/ - WMI_BATCH_SCAN_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_LOCATION_SCAN), - /*stop batch scan*/ - WMI_BATCH_SCAN_DISABLE_CMDID, - /*get batch scan result*/ - WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, - /* OEM related cmd */ - WMI_OEM_REQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_OEM), - WMI_OEM_REQUEST_CMDID, /* UNUSED */ + /*location scan commands */ + /*start batch scan */ + WMI_BATCH_SCAN_ENABLE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_LOCATION_SCAN), + /*stop batch scan */ + WMI_BATCH_SCAN_DISABLE_CMDID, + /*get batch scan result */ + WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, + /* OEM related cmd */ + WMI_OEM_REQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_OEM), + WMI_OEM_REQUEST_CMDID, /* UNUSED */ - /** Nan Request */ - WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN), + /** Nan Request */ + WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN), - /** Modem power state command */ - WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX), - WMI_CHAN_AVOID_UPDATE_CMDID, - WMI_COEX_CONFIG_CMDID, - WMI_CHAN_AVOID_RPT_ALLOW_CMDID, - WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, + /** Modem power state command */ + WMI_MODEM_POWER_STATE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_COEX), + WMI_CHAN_AVOID_UPDATE_CMDID, + WMI_COEX_CONFIG_CMDID, + WMI_CHAN_AVOID_RPT_ALLOW_CMDID, + WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, + WMI_SAR_LIMITS_CMDID, - /** - * OBSS scan offload enable/disable commands - * OBSS scan enable CMD will send to FW after VDEV UP, if these conditions are true: - * 1. WMI_SERVICE_OBSS_SCAN is reported by FW in service ready, - * 2. STA connect to a 2.4Ghz ht20/ht40 AP, - * 3. AP enable 20/40 coexistence (OBSS_IE-74 can be found in beacon or association response) - * If OBSS parameters from beacon changed, also use enable CMD to update parameters. - * OBSS scan disable CMD will send to FW if have enabled when tearing down connection. - */ - WMI_OBSS_SCAN_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_OBSS_OFL), - WMI_OBSS_SCAN_DISABLE_CMDID, + /** + * OBSS scan offload enable/disable commands + * OBSS scan enable CMD will send to FW after VDEV UP, if these conditions are true: + * 1. WMI_SERVICE_OBSS_SCAN is reported by FW in service ready, + * 2. STA connect to a 2.4Ghz ht20/ht40 AP, + * 3. AP enable 20/40 coexistence (OBSS_IE-74 can be found in beacon or association response) + * If OBSS parameters from beacon changed, also use enable CMD to update parameters. + * OBSS scan disable CMD will send to FW if have enabled when tearing down connection. + */ + WMI_OBSS_SCAN_ENABLE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_OBSS_OFL), + WMI_OBSS_SCAN_DISABLE_CMDID, - /**LPI commands*/ - /**LPI mgmt snooping config command*/ - WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_LPI), - /**LPI scan start command*/ - WMI_LPI_START_SCAN_CMDID, - /**LPI scan stop command*/ - WMI_LPI_STOP_SCAN_CMDID, + /**LPI commands*/ + /**LPI mgmt snooping config command*/ + WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_LPI), + /**LPI scan start command*/ + WMI_LPI_START_SCAN_CMDID, + /**LPI scan stop command*/ + WMI_LPI_STOP_SCAN_CMDID, - /** ExtScan commands */ - WMI_EXTSCAN_START_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_EXTSCAN), - WMI_EXTSCAN_STOP_CMDID, - WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, - WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, - WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, - WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, - WMI_EXTSCAN_SET_CAPABILITIES_CMDID, - WMI_EXTSCAN_GET_CAPABILITIES_CMDID, - WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, - WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, + /** ExtScan commands */ + WMI_EXTSCAN_START_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_EXTSCAN), + WMI_EXTSCAN_STOP_CMDID, + WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, + WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, + WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, + WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, + WMI_EXTSCAN_SET_CAPABILITIES_CMDID, + WMI_EXTSCAN_GET_CAPABILITIES_CMDID, + WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, + WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, - /** DHCP server offload commands */ - WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_DHCP_OFL), + /** DHCP server offload commands */ + WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_DHCP_OFL), - /** IPA Offload features related commands */ - WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_IPA), + /** IPA Offload features related commands */ + WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_IPA), - /** mDNS responder offload commands */ - WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MDNS_OFL), - WMI_MDNS_SET_FQDN_CMDID, - WMI_MDNS_SET_RESPONSE_CMDID, - WMI_MDNS_GET_STATS_CMDID, + /** mDNS responder offload commands */ + WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MDNS_OFL), + WMI_MDNS_SET_FQDN_CMDID, + WMI_MDNS_SET_RESPONSE_CMDID, + WMI_MDNS_GET_STATS_CMDID, - /* enable/disable AP Authentication offload */ - WMI_SAP_OFL_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SAP_OFL), - WMI_SAP_SET_BLACKLIST_PARAM_CMDID, + /* enable/disable AP Authentication offload */ + WMI_SAP_OFL_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SAP_OFL), + WMI_SAP_SET_BLACKLIST_PARAM_CMDID, - /** Out-of-context-of-BSS (OCB) commands */ - WMI_OCB_SET_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_OCB), - WMI_OCB_SET_UTC_TIME_CMDID, - WMI_OCB_START_TIMING_ADVERT_CMDID, - WMI_OCB_STOP_TIMING_ADVERT_CMDID, - WMI_OCB_GET_TSF_TIMER_CMDID, - WMI_DCC_GET_STATS_CMDID, - WMI_DCC_CLEAR_STATS_CMDID, - WMI_DCC_UPDATE_NDL_CMDID, + /** Out-of-context-of-BSS (OCB) commands */ + WMI_OCB_SET_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_OCB), + WMI_OCB_SET_UTC_TIME_CMDID, + WMI_OCB_START_TIMING_ADVERT_CMDID, + WMI_OCB_STOP_TIMING_ADVERT_CMDID, + WMI_OCB_GET_TSF_TIMER_CMDID, + WMI_DCC_GET_STATS_CMDID, + WMI_DCC_CLEAR_STATS_CMDID, + WMI_DCC_UPDATE_NDL_CMDID, + /* System-On-Chip commands */ + WMI_SOC_SET_PCL_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SOC), + WMI_SOC_SET_HW_MODE_CMDID, + WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, + WMI_SOC_SET_ANTENNA_MODE_CMDID, - /* System-On-Chip commands */ - WMI_SOC_SET_PCL_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SOC), - WMI_SOC_SET_HW_MODE_CMDID, - WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, - WMI_SOC_SET_ANTENNA_MODE_CMDID, + /* packet filter commands */ + WMI_PACKET_FILTER_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PKT_FILTER), + WMI_PACKET_FILTER_ENABLE_CMDID, + /** Motion Aided WiFi Connectivity (MAWC) commands */ + WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MAWC), - /* packet filter commands */ - WMI_PACKET_FILTER_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PKT_FILTER), - WMI_PACKET_FILTER_ENABLE_CMDID, + /** WMI commands related to PMF 11w Offload */ + WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = + WMI_CMD_GRP_START_ID(WMI_GRP_PMF_OFFLOAD), - /** Motion Aided WiFi Connectivity (MAWC) commands */ - WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MAWC), + /** WMI commands related to pkt filter (BPF) offload */ + WMI_BPF_GET_CAPABILITY_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_BPF_OFFLOAD), + WMI_BPF_GET_VDEV_STATS_CMDID, + WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, + WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, - /** WMI commands related to PMF 11w Offload */ - WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PMF_OFFLOAD), + /** WMI commands related to monitor mode. */ + WMI_MNT_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MONITOR), - /** WMI commands related to pkt filter (BPF) offload */ - WMI_BPF_GET_CAPABILITY_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_BPF_OFFLOAD), - WMI_BPF_GET_VDEV_STATS_CMDID, - WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, - WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, - - /** WMI commands related to monitor mode. */ - WMI_MNT_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MONITOR), - - /** - * Nan Data commands - * NDI - NAN Data Interface - * NDP - NAN Data Path - */ - /* Commands in prototyping phase */ - WMI_NDI_GET_CAP_REQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PROTOTYPE), - WMI_NDP_INITIATOR_REQ_CMDID, - WMI_NDP_RESPONDER_REQ_CMDID, - WMI_NDP_END_REQ_CMDID, + /** + * Nan Data commands + * NDI - NAN Data Interface + * NDP - NAN Data Path + */ + /* Commands in prototyping phase */ + WMI_NDI_GET_CAP_REQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PROTOTYPE), + WMI_NDP_INITIATOR_REQ_CMDID, + WMI_NDP_RESPONDER_REQ_CMDID, + WMI_NDP_END_REQ_CMDID, } WMI_CMD_ID; typedef enum { - /** WMI service is ready; after this event WMI messages can be sent/received */ - WMI_SERVICE_READY_EVENTID = 0x1, - /** WMI is ready; after this event the wlan subsystem is initialized and can process commands. */ - WMI_READY_EVENTID, + /** WMI service is ready; after this event WMI messages can be sent/received */ + WMI_SERVICE_READY_EVENTID = 0x1, + /** WMI is ready; after this event the wlan subsystem is initialized and can process commands. */ + WMI_READY_EVENTID, - /** Specify what WMI services the target supports (for services beyond - * what fits in the WMI_SERVICE_READY_EVENT message's wmi_service_bitmap) - */ - WMI_SERVICE_AVAILABLE_EVENTID, + /** + * Specify what WMI services the target supports + * (for services beyond what fits in the WMI_SERVICE_READY_EVENT + * message's wmi_service_bitmap) + */ + WMI_SERVICE_AVAILABLE_EVENTID, - /** Scan specific events */ - WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), + /** Scan specific events */ + WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), - /* PDEV specific events */ - /** TPC config for the current operating channel */ - WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), - /** Channel stats event */ - WMI_CHAN_INFO_EVENTID, + /* PDEV specific events */ + /** TPC config for the current operating channel */ + WMI_PDEV_TPC_CONFIG_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), + /** Channel stats event */ + WMI_CHAN_INFO_EVENTID, - /** PHY Error specific WMI event */ - WMI_PHYERR_EVENTID, + /** PHY Error specific WMI event */ + WMI_PHYERR_EVENTID, - /** eeprom dump event */ - WMI_PDEV_DUMP_EVENTID, + /** eeprom dump event */ + WMI_PDEV_DUMP_EVENTID, - /** traffic pause event */ - WMI_TX_PAUSE_EVENTID, + /** traffic pause event */ + WMI_TX_PAUSE_EVENTID, - /** DFS radar event */ - WMI_DFS_RADAR_EVENTID, + /** DFS radar event */ + WMI_DFS_RADAR_EVENTID, - /** track L1SS entry and residency event */ - WMI_PDEV_L1SS_TRACK_EVENTID, + /** track L1SS entry and residency event */ + WMI_PDEV_L1SS_TRACK_EVENTID, /** Report current temprature of the chip in Celcius degree */ WMI_PDEV_TEMPERATURE_EVENTID, - /** Extension of WMI_SERVICE_READY msg with extra target capability info */ - WMI_SERVICE_READY_EXT_EVENTID, - - /** FIPS test mode event */ - WMI_PDEV_FIPS_EVENTID, - - /** Channel hopping avoidance */ - WMI_PDEV_CHANNEL_HOPPING_EVENTID, - - /** CCK ANI level event */ - WMI_PDEV_ANI_CCK_LEVEL_EVENTID, - - /** OFDM ANI level event */ - WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, - - /** Tx PPDU params */ - WMI_PDEV_TPC_EVENTID, - - /** NF Cal Power in DBR/DBM for all channels */ - WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, - - /** SOC/PDEV events */ - WMI_PDEV_SET_HW_MODE_RESP_EVENTID, - WMI_PDEV_HW_MODE_TRANSITION_EVENTID, - WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, - /** Report ANT DIV feature's status */ - WMI_PDEV_ANTDIV_STATUS_EVENTID, - /** Chip level Power stats */ - WMI_PDEV_CHIP_POWER_STATS_EVENTID, - - /* VDEV specific events */ - /** VDEV started event in response to VDEV_START request */ - WMI_VDEV_START_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VDEV), - /** vdev stopped event , generated in response to VDEV_STOP request */ - WMI_VDEV_STOPPED_EVENTID, - /* Indicate the set key (used for setting per - * peer unicast and per vdev multicast) - * operation has completed */ - WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, - /* NOTE: WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID would be deprecated. Please - don't use this for any new implementations */ - /* Firmware requests dynamic change to a specific beacon interval for a specific vdev ID in MCC scenario. - This request is valid only for vdevs operating in soft AP or P2P GO mode */ - WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, - - /* Return the TSF timestamp of specified vdev */ - WMI_VDEV_TSF_REPORT_EVENTID, - - /* FW response to Host for vdev delete cmdid */ - WMI_VDEV_DELETE_RESP_EVENTID, - - /* peer specific events */ - /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */ - WMI_PEER_STA_KICKOUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PEER), - - /** Peer Info Event with data_rate, rssi, tx_fail_cnt etc */ - WMI_PEER_INFO_EVENTID, - - /** Event indicating that TX fail count reaching threshold */ - WMI_PEER_TX_FAIL_CNT_THR_EVENTID, - - /* Return the estimate link speed for the Peer specified in the - * WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID command. - */ - WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, - /* Return the peer state - * WMI_PEER_SET_PARAM_CMDID, WMI_PEER_AUTHORIZE - */ - WMI_PEER_STATE_EVENTID, - - /* Peer Assoc Conf event to confirm fw had received PEER_ASSOC_CMD. - * After that, host will send Mx message. - * Otherwise, host will pause any Mx(STA:M2/M4) message - */ - WMI_PEER_ASSOC_CONF_EVENTID, - - /* FW response to Host for peer delete cmdid */ - WMI_PEER_DELETE_RESP_EVENTID, - - /** Valid rate code list for peer */ - WMI_PEER_RATECODE_LIST_EVENTID, - WMI_WDS_PEER_EVENTID, - WMI_PEER_STA_PS_STATECHG_EVENTID, - /** Peer Ant Div Info Event with rssi per chain, etc */ - WMI_PEER_ANTDIV_INFO_EVENTID, - - /* beacon/mgmt specific events */ - /** RX management frame. the entire frame is carried along with the event. */ - WMI_MGMT_RX_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MGMT), - /** software beacon alert event to Host requesting host to Queue a beacon for transmission - use only in host beacon mode */ - WMI_HOST_SWBA_EVENTID, - /** beacon tbtt offset event indicating the tsf offset of the tbtt from the theritical value. - tbtt offset is normally 0 and will be non zero if there are multiple VDEVs operating in - staggered beacon transmission mode */ - WMI_TBTTOFFSET_UPDATE_EVENTID, - - /** event after the first beacon is transmitted following - a change in the template.*/ - WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, - /** event after the first probe response is transmitted following - a change in the template.*/ - WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, - /** Event for Mgmt TX completion event */ - WMI_MGMT_TX_COMPLETION_EVENTID, - /** Event for Mgmt TX bundle completion event */ - WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, - - - /*ADDBA Related WMI Events*/ - /** Indication the completion of the prior - WMI_PEER_TID_DELBA_CMDID(initiator) */ - WMI_TX_DELBA_COMPLETE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_BA_NEG), - /** Indication the completion of the prior - *WMI_PEER_TID_ADDBA_CMDID(initiator) */ - WMI_TX_ADDBA_COMPLETE_EVENTID, - - /* Seq num returned from hw for a sta/tid pair */ - WMI_BA_RSP_SSN_EVENTID, - - /* Aggregation state requested by BTC */ - WMI_AGGR_STATE_TRIG_EVENTID, - - /** Roam event to trigger roaming on host */ - WMI_ROAM_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ROAM), - - /** matching AP found from list of profiles */ - WMI_PROFILE_MATCH, - /** roam synch event */ - WMI_ROAM_SYNCH_EVENTID, - - /** P2P disc found */ - WMI_P2P_DISC_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_P2P), - /** send noa info to host when noa is changed for beacon tx offload enable */ - WMI_P2P_NOA_EVENTID, - /** send p2p listen offload stopped event with different reason */ - WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, - - /** Send EGAP Info to host */ - WMI_AP_PS_EGAP_INFO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_AP_PS), - - /* send pdev resume event to host after pdev resume. */ - WMI_PDEV_RESUME_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SUSPEND), - - /** WOW wake up host event.generated in response to WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID. - will cary wake reason */ - WMI_WOW_WAKEUP_HOST_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_WOW), - WMI_D0_WOW_DISABLE_ACK_EVENTID, - WMI_WOW_INITIAL_WAKEUP_EVENTID, - - /*RTT related event ID*/ - /** RTT measurement report */ - WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_RTT), - /** TSF measurement report */ - WMI_TSF_MEASUREMENT_REPORT_EVENTID, - /** RTT error report */ - WMI_RTT_ERROR_REPORT_EVENTID, - - /*STATS specific events*/ - /** txrx stats event requested by host */ - WMI_STATS_EXT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_STATS), - /** FW iface link stats Event */ - WMI_IFACE_LINK_STATS_EVENTID, - /** FW iface peer link stats Event */ - WMI_PEER_LINK_STATS_EVENTID, - /** FW Update radio stats Event */ - WMI_RADIO_LINK_STATS_EVENTID, - - /** Firmware memory dump Complete event*/ - WMI_UPDATE_FW_MEM_DUMP_EVENTID, - - /** Event indicating the DIAG logs/events supported by FW */ - WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, - - /** Instantaneous RSSI event */ - WMI_INST_RSSI_STATS_EVENTID, - - /** FW update tx power levels event */ - WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, - - /** This event is used to report wlan stats to host. - * It is triggered under 3 conditions: - * (a) Periodic timer timed out, based on the period specified - * by WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD - * (b) Whenever any of the (enabled) stats thresholds specified - * in the WMI_PDEV_SET_STATS_THRESHOLD_CMD message is exceeded - * within the current stats period. - * (c) In response to the one-time wlan stats request of - * WMI_REQUEST_WLAN_STATS_CMDID from host. - * - * If this event is triggered by condition a or b, - * the stats counters are cleared at the start of each period. - * But if it is triggered by condition c, stats counters won't be cleared. - */ - WMI_REPORT_STATS_EVENTID, - - - /* NLO specific events */ - /** NLO match event after the first match */ - WMI_NLO_MATCH_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_NLO_OFL), - - /** NLO scan complete event */ - WMI_NLO_SCAN_COMPLETE_EVENTID, - - /** APFIND specific events */ - WMI_APFIND_EVENTID, - - /** passpoint network match event */ - WMI_PASSPOINT_MATCH_EVENTID, - - /** GTK offload stautus event requested by host */ - WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GTK_OFL), - - /** GTK offload failed to rekey event */ - WMI_GTK_REKEY_FAIL_EVENTID, - /* CSA IE received event */ - WMI_CSA_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL), - - /*chatter query reply event*/ - WMI_CHATTER_PC_QUERY_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHATTER), - - /** echo event in response to echo command */ - WMI_ECHO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MISC), - - /* !!IMPORTANT!! - * If you need to add a new WMI event ID to the WMI_GRP_MISC sub-group, - * please make sure you add it BEHIND WMI_PDEV_UTF_EVENTID, - * as we MUST have a fixed value here to maintain compatibility between - * UTF and the ART2 driver - */ - /** UTF specific WMI event */ - WMI_PDEV_UTF_EVENTID, - - /** event carries buffered debug messages */ - WMI_DEBUG_MESG_EVENTID, - /** FW stats(periodic or on shot) */ - WMI_UPDATE_STATS_EVENTID, - /** debug print message used for tracing FW code while debugging */ - WMI_DEBUG_PRINT_EVENTID, - /** DCS wlan or non-wlan interference event - */ - WMI_DCS_INTERFERENCE_EVENTID, - /** VI spoecific event */ - WMI_PDEV_QVIT_EVENTID, - /** FW code profile data in response to profile request */ - WMI_WLAN_PROFILE_DATA_EVENTID, - /* Factory Testing Mode request event - * used for integrated chipsets */ - WMI_PDEV_FTM_INTG_EVENTID, - /* avoid list of frequencies . - */ - WMI_WLAN_FREQ_AVOID_EVENTID, - /* Indicate the keepalive parameters */ - WMI_VDEV_GET_KEEPALIVE_EVENTID, - /*Thermal Management event*/ - WMI_THERMAL_MGMT_EVENTID, - - /* Container for DIAG event and log data */ - WMI_DIAG_DATA_CONTAINER_EVENTID, - - /* host auto shutdown event */ - WMI_HOST_AUTO_SHUTDOWN_EVENTID, - - /*update mib counters together with WMI_UPDATE_STATS_EVENTID*/ - WMI_UPDATE_WHAL_MIB_STATS_EVENTID, - - /*update ht/vht info based on vdev (rx and tx NSS and preamble)*/ - WMI_UPDATE_VDEV_RATE_STATS_EVENTID, - - WMI_DIAG_EVENTID, - - /** Set OCB Sched Response, deprecated */ - WMI_OCB_SET_SCHED_EVENTID, - - /** event to indicate the flush of the buffered debug messages is complete*/ - WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, - - /** event to report mix/max RSSI breach events */ - WMI_RSSI_BREACH_EVENTID, - - /** event to report completion of data storage into flash memory */ - WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, - - /** event to report SCPC calibrated data to host */ - WMI_PDEV_UTF_SCPC_EVENTID, - - /** event to provide requested data from the target's flash memory */ - WMI_READ_DATA_FROM_FLASH_EVENTID, - - /* GPIO Event */ - WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), - /** upload H_CV info WMI event - * to indicate uploaded H_CV info to host - */ - WMI_UPLOADH_EVENTID, - - /** capture H info WMI event - * to indicate captured H info to host - */ - WMI_CAPTUREH_EVENTID, - /* hw RFkill */ - WMI_RFKILL_STATE_CHANGE_EVENTID, - - /* TDLS Event */ - WMI_TDLS_PEER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TDLS), - - /** STA SMPS Event */ - /** force SMPS mode */ - WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_STA_SMPS), - - /*location scan event*/ - /*report the firmware's capability of batch scan*/ - WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LOCATION_SCAN), - /*batch scan result*/ - WMI_BATCH_SCAN_RESULT_EVENTID, - /* OEM Event */ - WMI_OEM_CAPABILITY_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_OEM), /*DEPRECATED*/ - WMI_OEM_MEASUREMENT_REPORT_EVENTID, /* DEPRECATED */ - WMI_OEM_ERROR_REPORT_EVENTID, /* DEPRECATED */ - WMI_OEM_RESPONSE_EVENTID, - - /* NAN Event */ - WMI_NAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_NAN), - WMI_NAN_DISC_IFACE_CREATED_EVENTID, - WMI_NAN_DISC_IFACE_DELETED_EVENTID, - WMI_NAN_STARTED_CLUSTER_EVENTID, - WMI_NAN_JOINED_CLUSTER_EVENTID, - - /* Coex Event */ - WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX), - - /* LPI Event */ - WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI), - WMI_LPI_STATUS_EVENTID, - WMI_LPI_HANDOFF_EVENTID, - - /* ExtScan events */ - WMI_EXTSCAN_START_STOP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_EXTSCAN), - WMI_EXTSCAN_OPERATION_EVENTID, - WMI_EXTSCAN_TABLE_USAGE_EVENTID, - WMI_EXTSCAN_CACHED_RESULTS_EVENTID, - WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, - WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, - WMI_EXTSCAN_CAPABILITIES_EVENTID, - WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, - - /* mDNS offload events */ - WMI_MDNS_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MDNS_OFL), - - /* SAP Authentication offload events */ - WMI_SAP_OFL_ADD_STA_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SAP_OFL), - WMI_SAP_OFL_DEL_STA_EVENTID, - - /** Out-of-context-of-bss (OCB) events */ - WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_OCB), - WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, - WMI_DCC_GET_STATS_RESP_EVENTID, - WMI_DCC_UPDATE_NDL_RESP_EVENTID, - WMI_DCC_STATS_EVENTID, - - /* System-On-Chip events */ - WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SOC), - WMI_SOC_HW_MODE_TRANSITION_EVENTID, - WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, - - /** Motion Aided WiFi Connectivity (MAWC) events */ - WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MAWC), - - /** pkt filter (BPF) offload relevant events */ - WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_BPF_OFFLOAD), - WMI_BPF_VDEV_STATS_INFO_EVENTID, - - - /* RMC specific event */ - /* RMC manual leader selected event */ - WMI_RMC_NEW_LEADER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_RMC), - - - /** Events in Prototyping phase */ - WMI_NDI_CAP_RSP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PROTOTYPE), - WMI_NDP_INITIATOR_RSP_EVENTID, - WMI_NDP_RESPONDER_RSP_EVENTID, - WMI_NDP_END_RSP_EVENTID, - WMI_NDP_INDICATION_EVENTID, - WMI_NDP_CONFIRM_EVENTID, - WMI_NDP_END_INDICATION_EVENTID, + /* Extension of WMI_SERVICE_READY msg with + * extra target capability info + */ + WMI_SERVICE_READY_EXT_EVENTID, + + /** FIPS test mode event */ + WMI_PDEV_FIPS_EVENTID, + + /** Channel hopping avoidance */ + WMI_PDEV_CHANNEL_HOPPING_EVENTID, + + /** CCK ANI level event */ + WMI_PDEV_ANI_CCK_LEVEL_EVENTID, + + /** OFDM ANI level event */ + WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, + + /** Tx PPDU params */ + WMI_PDEV_TPC_EVENTID, + + /** NF Cal Power in DBR/DBM for all channels */ + WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, + + /** SOC/PDEV events */ + WMI_PDEV_SET_HW_MODE_RESP_EVENTID, + WMI_PDEV_HW_MODE_TRANSITION_EVENTID, + WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, + /** Report ANT DIV feature's status */ + WMI_PDEV_ANTDIV_STATUS_EVENTID, + /** Chip level Power stats */ + WMI_PDEV_CHIP_POWER_STATS_EVENTID, + + /* VDEV specific events */ + /** VDEV started event in response to VDEV_START request */ + WMI_VDEV_START_RESP_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_VDEV), + /** vdev stopped event , generated in response to VDEV_STOP request */ + WMI_VDEV_STOPPED_EVENTID, + /* Indicate the set key (used for setting per + * peer unicast and per vdev multicast) + * operation has completed */ + WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, + /* NOTE: WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID would be deprecated. Please + don't use this for any new implementations */ + /* Firmware requests dynamic change to a specific beacon interval for a specific vdev ID in MCC scenario. + This request is valid only for vdevs operating in soft AP or P2P GO mode */ + WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, + + /* Return the TSF timestamp of specified vdev */ + WMI_VDEV_TSF_REPORT_EVENTID, + + /* FW response to Host for vdev delete cmdid */ + WMI_VDEV_DELETE_RESP_EVENTID, + + /** + * DISA feature: FW response to Host with encrypted/decrypted + * 802.11 DISA frame + */ + WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, + + /* peer specific events */ + /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */ + WMI_PEER_STA_KICKOUT_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_PEER), + + /** Peer Info Event with data_rate, rssi, tx_fail_cnt etc */ + WMI_PEER_INFO_EVENTID, + + /** Event indicating that TX fail count reaching threshold */ + WMI_PEER_TX_FAIL_CNT_THR_EVENTID, + /** Return the estimate link speed for the Peer specified in the + * WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID command. + */ + WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, + /* Return the peer state + * WMI_PEER_SET_PARAM_CMDID, WMI_PEER_AUTHORIZE + */ + WMI_PEER_STATE_EVENTID, + + /* Peer Assoc Conf event to confirm fw had received PEER_ASSOC_CMD. + * After that, host will send Mx message. + * Otherwise, host will pause any Mx(STA:M2/M4) message + */ + WMI_PEER_ASSOC_CONF_EVENTID, + + /* FW response to Host for peer delete cmdid */ + WMI_PEER_DELETE_RESP_EVENTID, + + /** Valid rate code list for peer */ + WMI_PEER_RATECODE_LIST_EVENTID, + WMI_WDS_PEER_EVENTID, + WMI_PEER_STA_PS_STATECHG_EVENTID, + /** Peer Ant Div Info Event with rssi per chain, etc */ + WMI_PEER_ANTDIV_INFO_EVENTID, + + /* beacon/mgmt specific events */ + /** RX management frame. the entire frame is carried along with the event. */ + WMI_MGMT_RX_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MGMT), + /** software beacon alert event to Host requesting host to Queue a beacon for transmission + use only in host beacon mode */ + WMI_HOST_SWBA_EVENTID, + /** beacon tbtt offset event indicating the tsf offset of the tbtt from the theritical value. + tbtt offset is normally 0 and will be non zero if there are multiple VDEVs operating in + staggered beacon transmission mode */ + WMI_TBTTOFFSET_UPDATE_EVENTID, + + /** event after the first beacon is transmitted following + a change in the template.*/ + WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, + /** event after the first probe response is transmitted following + a change in the template.*/ + WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, + /** Event for Mgmt TX completion event */ + WMI_MGMT_TX_COMPLETION_EVENTID, + /** Event for Mgmt TX bundle completion event */ + WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, + /** vdev_map used in WMI_TBTTOFFSET_UPDATE_EVENTID supports max 32 vdevs + * Use this event if number of vdevs > 32. + */ + WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, + + /*ADDBA Related WMI Events */ + /** Indication the completion of the prior + WMI_PEER_TID_DELBA_CMDID(initiator) */ + WMI_TX_DELBA_COMPLETE_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_BA_NEG), + /** Indication the completion of the prior + *WMI_PEER_TID_ADDBA_CMDID(initiator) */ + WMI_TX_ADDBA_COMPLETE_EVENTID, + + /* Seq num returned from hw for a sta/tid pair */ + WMI_BA_RSP_SSN_EVENTID, + + /* Aggregation state requested by BTC */ + WMI_AGGR_STATE_TRIG_EVENTID, + + /** Roam event to trigger roaming on host */ + WMI_ROAM_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ROAM), + + /** matching AP found from list of profiles */ + WMI_PROFILE_MATCH, + /** roam synch event */ + WMI_ROAM_SYNCH_EVENTID, + + /** P2P disc found */ + WMI_P2P_DISC_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_P2P), + /*send noa info to host when noa is changed for beacon tx offload enable */ + WMI_P2P_NOA_EVENTID, + /** send p2p listen offload stopped event with different reason */ + WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, + + /** Send EGAP Info to host */ + WMI_AP_PS_EGAP_INFO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_AP_PS), + + /* send pdev resume event to host after pdev resume. */ + WMI_PDEV_RESUME_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SUSPEND), + + /** WOW wake up host event.generated in response to WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID. + will cary wake reason */ + WMI_WOW_WAKEUP_HOST_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_WOW), + WMI_D0_WOW_DISABLE_ACK_EVENTID, + WMI_WOW_INITIAL_WAKEUP_EVENTID, + + /*RTT related event ID */ + /** RTT measurement report */ + WMI_RTT_MEASUREMENT_REPORT_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_RTT), + /** TSF measurement report */ + WMI_TSF_MEASUREMENT_REPORT_EVENTID, + /** RTT error report */ + WMI_RTT_ERROR_REPORT_EVENTID, + /*STATS specific events */ + /** txrx stats event requested by host */ + WMI_STATS_EXT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_STATS), + /** FW iface link stats Event */ + WMI_IFACE_LINK_STATS_EVENTID, + /** FW iface peer link stats Event */ + WMI_PEER_LINK_STATS_EVENTID, + /** FW Update radio stats Event */ + WMI_RADIO_LINK_STATS_EVENTID, + /** Firmware memory dump Complete event*/ + WMI_UPDATE_FW_MEM_DUMP_EVENTID, + + /** Event indicating the DIAG logs/events supported by FW */ + WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, + + /** Instantaneous RSSI event */ + WMI_INST_RSSI_STATS_EVENTID, + + /** FW update tx power levels event */ + WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, + + /** This event is used to report wlan stats to host. + * It is triggered under 3 conditions: + * (a) Periodic timer timed out, based on the period specified + * by WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD + * (b) Whenever any of the (enabled) stats thresholds specified + * in the WMI_PDEV_SET_STATS_THRESHOLD_CMD message is exceeded + * within the current stats period. + * (c) In response to the one-time wlan stats request of + * WMI_REQUEST_WLAN_STATS_CMDID from host. + * + * If this event is triggered by condition a or b, + * the stats counters are cleared at the start of each period. + * But if it is triggered by condition c, stats counters won't be cleared. + */ + WMI_REPORT_STATS_EVENTID, + + /** NLO specific events */ + /** NLO match event after the first match */ + WMI_NLO_MATCH_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_NLO_OFL), + + /** NLO scan complete event */ + WMI_NLO_SCAN_COMPLETE_EVENTID, + + /** APFIND specific events */ + WMI_APFIND_EVENTID, + + /** passpoint network match event */ + WMI_PASSPOINT_MATCH_EVENTID, + + /** GTK offload stautus event requested by host */ + WMI_GTK_OFFLOAD_STATUS_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_GTK_OFL), + + /** GTK offload failed to rekey event */ + WMI_GTK_REKEY_FAIL_EVENTID, + /* CSA IE received event */ + WMI_CSA_HANDLING_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL), + + /*chatter query reply event */ + WMI_CHATTER_PC_QUERY_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_CHATTER), + /** DFS related events */ + WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_DFS), + /** Indicate channel-availability-check completion event to host */ + WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, + /** Indicate off-channel-availability-check completion event to host */ + WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, + /** echo event in response to echo command */ + WMI_ECHO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MISC), + + /* !!IMPORTANT!! + * If you need to add a new WMI event ID to the WMI_GRP_MISC sub-group, + * please make sure you add it BEHIND WMI_PDEV_UTF_EVENTID, + * as we MUST have a fixed value here to maintain compatibility between + * UTF and the ART2 driver + */ + /** UTF specific WMI event */ + WMI_PDEV_UTF_EVENTID, + + /** event carries buffered debug messages */ + WMI_DEBUG_MESG_EVENTID, + /** FW stats(periodic or on shot) */ + WMI_UPDATE_STATS_EVENTID, + /** debug print message used for tracing FW code while debugging */ + WMI_DEBUG_PRINT_EVENTID, + /** DCS wlan or non-wlan interference event + */ + WMI_DCS_INTERFERENCE_EVENTID, + /** VI spoecific event */ + WMI_PDEV_QVIT_EVENTID, + /** FW code profile data in response to profile request */ + WMI_WLAN_PROFILE_DATA_EVENTID, + /* Factory Testing Mode request event + * used for integrated chipsets */ + WMI_PDEV_FTM_INTG_EVENTID, + /* avoid list of frequencies . + */ + WMI_WLAN_FREQ_AVOID_EVENTID, + /* Indicate the keepalive parameters */ + WMI_VDEV_GET_KEEPALIVE_EVENTID, + /* Thermal Management event */ + WMI_THERMAL_MGMT_EVENTID, + + /* Container for QXDM/DIAG events */ + WMI_DIAG_DATA_CONTAINER_EVENTID, + + /* host auto shutdown event */ + WMI_HOST_AUTO_SHUTDOWN_EVENTID, + + /*update mib counters together with WMI_UPDATE_STATS_EVENTID */ + WMI_UPDATE_WHAL_MIB_STATS_EVENTID, + + /*update ht/vht info based on vdev (rx and tx NSS and preamble) */ + WMI_UPDATE_VDEV_RATE_STATS_EVENTID, + + WMI_DIAG_EVENTID, + + /** Set OCB Sched Response, deprecated */ + WMI_OCB_SET_SCHED_EVENTID, + + /* event to indicate the flush of the buffered debug messages is complete*/ + WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, + /* event to report mix/max RSSI breach events */ + WMI_RSSI_BREACH_EVENTID, + /* event to report completion of data storage into flash memory */ + WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, + + /** event to report SCPC calibrated data to host */ + WMI_PDEV_UTF_SCPC_EVENTID, + + /** event to provide requested data from the target's flash memory */ + WMI_READ_DATA_FROM_FLASH_EVENTID, + + /** event to report rx aggregation failure frame information */ + WMI_REPORT_RX_AGGR_FAILURE_EVENTID, + + /* GPIO Event */ + WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), + /** upload H_CV info WMI event + * to indicate uploaded H_CV info to host + */ + WMI_UPLOADH_EVENTID, + + /** capture H info WMI event + * to indicate captured H info to host + */ + WMI_CAPTUREH_EVENTID, + /* hw RFkill */ + WMI_RFKILL_STATE_CHANGE_EVENTID, + + /* TDLS Event */ + WMI_TDLS_PEER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TDLS), + + /* STA SMPS Event */ + /* force SMPS mode */ + WMI_STA_SMPS_FORCE_MODE_COMPLETE_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_STA_SMPS), + + /*location scan event */ + /*report the firmware's capability of batch scan */ + WMI_BATCH_SCAN_ENABLED_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_LOCATION_SCAN), + /*batch scan result */ + WMI_BATCH_SCAN_RESULT_EVENTID, + /* OEM Event */ + WMI_OEM_CAPABILITY_EVENTID = /* DEPRECATED */ + WMI_EVT_GRP_START_ID(WMI_GRP_OEM), + WMI_OEM_MEASUREMENT_REPORT_EVENTID, /* DEPRECATED */ + WMI_OEM_ERROR_REPORT_EVENTID, /* DEPRECATED */ + WMI_OEM_RESPONSE_EVENTID, + + /* NAN Event */ + WMI_NAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_NAN), + WMI_NAN_DISC_IFACE_CREATED_EVENTID, + WMI_NAN_DISC_IFACE_DELETED_EVENTID, + WMI_NAN_STARTED_CLUSTER_EVENTID, + WMI_NAN_JOINED_CLUSTER_EVENTID, + + /* Coex Event */ + WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_COEX), + + /* LPI Event */ + WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI), + WMI_LPI_STATUS_EVENTID, + WMI_LPI_HANDOFF_EVENTID, + + /* ExtScan events */ + WMI_EXTSCAN_START_STOP_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_EXTSCAN), + WMI_EXTSCAN_OPERATION_EVENTID, + WMI_EXTSCAN_TABLE_USAGE_EVENTID, + WMI_EXTSCAN_CACHED_RESULTS_EVENTID, + WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, + WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, + WMI_EXTSCAN_CAPABILITIES_EVENTID, + WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, + + /* mDNS offload events */ + WMI_MDNS_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MDNS_OFL), + + /* SAP Authentication offload events */ + WMI_SAP_OFL_ADD_STA_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SAP_OFL), + WMI_SAP_OFL_DEL_STA_EVENTID, + + /** Out-of-context-of-bss (OCB) events */ + WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_OCB), + WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, + WMI_DCC_GET_STATS_RESP_EVENTID, + WMI_DCC_UPDATE_NDL_RESP_EVENTID, + WMI_DCC_STATS_EVENTID, + /* System-On-Chip events */ + WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SOC), + WMI_SOC_HW_MODE_TRANSITION_EVENTID, + WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, + /** Motion Aided WiFi Connectivity (MAWC) events */ + WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MAWC), + + /** pkt filter (BPF) offload relevant events */ + WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_BPF_OFFLOAD), + WMI_BPF_VDEV_STATS_INFO_EVENTID, + + /* Events in Prototyping phase */ + WMI_NDI_CAP_RSP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PROTOTYPE), + WMI_NDP_INITIATOR_RSP_EVENTID, + WMI_NDP_RESPONDER_RSP_EVENTID, + WMI_NDP_END_RSP_EVENTID, + WMI_NDP_INDICATION_EVENTID, + WMI_NDP_CONFIRM_EVENTID, + WMI_NDP_END_INDICATION_EVENTID, } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -1420,39 +1486,43 @@ typedef enum { #define WMI_OEM_CONFIGURE_LCR 0x09 #define WMI_OEM_CONFIGURE_LCI 0x0A +/* below message subtype is internal to CLD. Target should + * never use internal response type + */ +#define WMI_OEM_INTERNAL_RSP 0xdeadbeef -#define WMI_CHAN_LIST_TAG 0x1 -#define WMI_SSID_LIST_TAG 0x2 -#define WMI_BSSID_LIST_TAG 0x3 -#define WMI_IE_TAG 0x4 +#define WMI_CHAN_LIST_TAG 0x1 +#define WMI_SSID_LIST_TAG 0x2 +#define WMI_BSSID_LIST_TAG 0x3 +#define WMI_IE_TAG 0x4 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel */ - /** primary 20 MHz channel frequency in mhz */ - A_UINT32 mhz; - /** Center frequency 1 in MHz*/ - A_UINT32 band_center_freq1; - /** Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/ - A_UINT32 band_center_freq2; - /** channel info described below */ - A_UINT32 info; - /** contains min power, max power, reg power and reg class id. */ - A_UINT32 reg_info_1; - /** contains antennamax */ - A_UINT32 reg_info_2; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel */ + /** primary 20 MHz channel frequency in mhz */ + A_UINT32 mhz; + /** Center frequency 1 in MHz*/ + A_UINT32 band_center_freq1; + /** Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/ + A_UINT32 band_center_freq2; + /** channel info described below */ + A_UINT32 info; + /** contains min power, max power, reg power and reg class id. */ + A_UINT32 reg_info_1; + /** contains antennamax */ + A_UINT32 reg_info_2; } wmi_channel; typedef enum { - WMI_CHANNEL_CHANGE_CAUSE_NONE = 0, - WMI_CHANNEL_CHANGE_CAUSE_CSA, + WMI_CHANNEL_CHANGE_CAUSE_NONE = 0, + WMI_CHANNEL_CHANGE_CAUSE_CSA, } wmi_channel_change_cause; /** channel info consists of 6 bits of channel mode */ -#define WMI_SET_CHANNEL_MODE(pwmi_channel,val) do { \ - (pwmi_channel)->info &= 0xffffffc0; \ - (pwmi_channel)->info |= (val); \ - } while (0) +#define WMI_SET_CHANNEL_MODE(pwmi_channel, val) do { \ + (pwmi_channel)->info &= 0xffffffc0; \ + (pwmi_channel)->info |= (val); \ +} while (0) #define WMI_GET_CHANNEL_MODE(pwmi_channel) ((pwmi_channel)->info & 0x0000003f) @@ -1461,98 +1531,96 @@ typedef enum { #define WMI_CHAN_ADHOC_ALLOWED 8 #define WMI_CHAN_AP_DISABLED 9 #define WMI_CHAN_FLAG_DFS 10 -#define WMI_CHAN_FLAG_ALLOW_HT 11 /* HT is allowed on this channel */ -#define WMI_CHAN_FLAG_ALLOW_VHT 12 /* VHT is allowed on this channel */ +#define WMI_CHAN_FLAG_ALLOW_HT 11 /* HT is allowed on this channel */ +#define WMI_CHAN_FLAG_ALLOW_VHT 12 /* VHT is allowed on this channel */ #define WMI_CHANNEL_CHANGE_CAUSE_CSA 13 /*Indicate reason for channel switch */ #define WMI_CHAN_FLAG_HALF_RATE 14 /* Indicates half rate channel */ #define WMI_CHAN_FLAG_QUARTER_RATE 15 /* Indicates quarter rate channel */ -#define WMI_CHAN_FLAG_DFS_CFREQ2 16 /* Enable radar event reporting for sec80 in VHT80p80 */ +/* Enable radar event reporting for sec80 in VHT80p80 */ +#define WMI_CHAN_FLAG_DFS_CFREQ2 16 #define WMI_CHAN_FLAG_ALLOW_HE 17 /* HE (11ax) is allowed on this channel */ -#define WMI_SET_CHANNEL_FLAG(pwmi_channel,flag) do { \ - (pwmi_channel)->info |= (1 << flag); \ - } while (0) +#define WMI_SET_CHANNEL_FLAG(pwmi_channel, flag) do { \ + (pwmi_channel)->info |= (1 << flag); \ +} while (0) -#define WMI_GET_CHANNEL_FLAG(pwmi_channel,flag) \ - (((pwmi_channel)->info & (1 << flag)) >> flag) +#define WMI_GET_CHANNEL_FLAG(pwmi_channel, flag) \ + (((pwmi_channel)->info & (1 << flag)) >> flag) -#define WMI_SET_CHANNEL_MIN_POWER(pwmi_channel,val) do { \ - (pwmi_channel)->reg_info_1 &= 0xffffff00; \ - (pwmi_channel)->reg_info_1 |= (val & 0xff); \ - } while (0) +#define WMI_SET_CHANNEL_MIN_POWER(pwmi_channel, val) do { \ + (pwmi_channel)->reg_info_1 &= 0xffffff00; \ + (pwmi_channel)->reg_info_1 |= (val&0xff); \ +} while (0) #define WMI_GET_CHANNEL_MIN_POWER(pwmi_channel) ((pwmi_channel)->reg_info_1 & 0xff) -#define WMI_SET_CHANNEL_MAX_POWER(pwmi_channel,val) do { \ - (pwmi_channel)->reg_info_1 &= 0xffff00ff; \ - (pwmi_channel)->reg_info_1 |= ((val & 0xff) << 8); \ - } while (0) +#define WMI_SET_CHANNEL_MAX_POWER(pwmi_channel, val) do { \ + (pwmi_channel)->reg_info_1 &= 0xffff00ff; \ + (pwmi_channel)->reg_info_1 |= ((val&0xff) << 8); \ +} while (0) #define WMI_GET_CHANNEL_MAX_POWER(pwmi_channel) ((((pwmi_channel)->reg_info_1) >> 8) & 0xff) -#define WMI_SET_CHANNEL_REG_POWER(pwmi_channel,val) do { \ - (pwmi_channel)->reg_info_1 &= 0xff00ffff; \ - (pwmi_channel)->reg_info_1 |= ((val & 0xff) << 16); \ - } while (0) +#define WMI_SET_CHANNEL_REG_POWER(pwmi_channel, val) do { \ + (pwmi_channel)->reg_info_1 &= 0xff00ffff; \ + (pwmi_channel)->reg_info_1 |= ((val&0xff) << 16); \ +} while (0) #define WMI_GET_CHANNEL_REG_POWER(pwmi_channel) ((((pwmi_channel)->reg_info_1) >> 16) & 0xff) -#define WMI_SET_CHANNEL_REG_CLASSID(pwmi_channel,val) do { \ - (pwmi_channel)->reg_info_1 &= 0x00ffffff; \ - (pwmi_channel)->reg_info_1 |= ((val & 0xff) << 24); \ - } while (0) +#define WMI_SET_CHANNEL_REG_CLASSID(pwmi_channel, val) do { \ + (pwmi_channel)->reg_info_1 &= 0x00ffffff; \ + (pwmi_channel)->reg_info_1 |= ((val&0xff) << 24); \ +} while (0) #define WMI_GET_CHANNEL_REG_CLASSID(pwmi_channel) ((((pwmi_channel)->reg_info_1) >> 24) & 0xff) -#define WMI_SET_CHANNEL_ANTENNA_MAX(pwmi_channel,val) do { \ - (pwmi_channel)->reg_info_2 &= 0xffffff00; \ - (pwmi_channel)->reg_info_2 |= (val & 0xff); \ - } while (0) +#define WMI_SET_CHANNEL_ANTENNA_MAX(pwmi_channel, val) do { \ + (pwmi_channel)->reg_info_2 &= 0xffffff00; \ + (pwmi_channel)->reg_info_2 |= (val&0xff); \ +} while (0) #define WMI_GET_CHANNEL_ANTENNA_MAX(pwmi_channel) ((pwmi_channel)->reg_info_2 & 0xff) /* max tx power is in 1 dBm units */ -#define WMI_SET_CHANNEL_MAX_TX_POWER(pwmi_channel,val) do { \ - (pwmi_channel)->reg_info_2 &= 0xffff00ff; \ - (pwmi_channel)->reg_info_2 |= ((val & 0xff) << 8); \ - } while (0) +#define WMI_SET_CHANNEL_MAX_TX_POWER(pwmi_channel, val) do { \ + (pwmi_channel)->reg_info_2 &= 0xffff00ff; \ + (pwmi_channel)->reg_info_2 |= ((val&0xff)<<8); \ +} while (0) #define WMI_GET_CHANNEL_MAX_TX_POWER(pwmi_channel) ((((pwmi_channel)->reg_info_2)>>8) & 0xff) /** HT Capabilities*/ -#define WMI_HT_CAP_ENABLED 0x0001 /* HT Enabled/ disabled */ -#define WMI_HT_CAP_HT20_SGI 0x0002 /* Short Guard Interval with HT20 */ -#define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 /* Dynamic MIMO powersave */ -#define WMI_HT_CAP_TX_STBC 0x0008 /* B3 TX STBC */ +#define WMI_HT_CAP_ENABLED 0x0001 /* HT Enabled/ disabled */ +#define WMI_HT_CAP_HT20_SGI 0x0002 /* Short Guard Interval with HT20 */ +#define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 /* Dynamic MIMO powersave */ +#define WMI_HT_CAP_TX_STBC 0x0008 /* B3 TX STBC */ #define WMI_HT_CAP_TX_STBC_MASK_SHIFT 3 -#define WMI_HT_CAP_RX_STBC 0x0030 /* B4-B5 RX STBC */ +#define WMI_HT_CAP_RX_STBC 0x0030 /* B4-B5 RX STBC */ #define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4 -#define WMI_HT_CAP_LDPC 0x0040 /* LDPC supported */ -#define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 /* L-SIG TXOP Protection */ -#define WMI_HT_CAP_MPDU_DENSITY 0x0700 /* MPDU Density */ +#define WMI_HT_CAP_LDPC 0x0040 /* LDPC supported */ +#define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 /* L-SIG TXOP Protection */ +#define WMI_HT_CAP_MPDU_DENSITY 0x0700 /* MPDU Density */ #define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT 8 #define WMI_HT_CAP_HT40_SGI 0x0800 #define WMI_HT_CAP_RX_LDPC 0x1000 /* LDPC RX support */ #define WMI_HT_CAP_TX_LDPC 0x2000 /* LDPC TX support */ - /* These macros should be used when we wish to advertise STBC support for * only 1SS or 2SS or 3SS. */ -#define WMI_HT_CAP_RX_STBC_1SS 0x0010 /* B4-B5 RX STBC */ -#define WMI_HT_CAP_RX_STBC_2SS 0x0020 /* B4-B5 RX STBC */ -#define WMI_HT_CAP_RX_STBC_3SS 0x0030 /* B4-B5 RX STBC */ - +#define WMI_HT_CAP_RX_STBC_1SS 0x0010 /* B4-B5 RX STBC */ +#define WMI_HT_CAP_RX_STBC_2SS 0x0020 /* B4-B5 RX STBC */ +#define WMI_HT_CAP_RX_STBC_3SS 0x0030 /* B4-B5 RX STBC */ #define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED | \ - WMI_HT_CAP_HT20_SGI | \ - WMI_HT_CAP_HT40_SGI | \ - WMI_HT_CAP_TX_STBC | \ - WMI_HT_CAP_RX_STBC | \ - WMI_HT_CAP_LDPC | \ - WMI_HT_CAP_TX_LDPC | \ - WMI_HT_CAP_RX_LDPC) + WMI_HT_CAP_HT20_SGI | \ + WMI_HT_CAP_HT40_SGI | \ + WMI_HT_CAP_TX_STBC | \ + WMI_HT_CAP_RX_STBC | \ + WMI_HT_CAP_LDPC | \ + WMI_HT_CAP_TX_LDPC | \ + WMI_HT_CAP_RX_LDPC) /* WMI_VHT_CAP_* these maps to ieee 802.11ac vht capability information - field. The fields not defined here are not supported, or reserved. - Do not change these masks and if you have to add new one follow the - bitmask as specified by 802.11ac draft. + field. The fields not defined here are not supported, or reserved. + Do not change these masks and if you have to add new one follow the + bitmask as specified by 802.11ac draft. */ - #define WMI_VHT_CAP_MAX_MPDU_LEN_7935 0x00000001 #define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002 #define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003 @@ -1579,7 +1647,6 @@ typedef enum { #define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000 #define WMI_VHT_CAP_TX_LDPC 0x40000000 - /* TEMPORARY: * Preserve the incorrect old name as an alias for the correct new name * until all references to the old name have been removed from all hosts @@ -1587,7 +1654,6 @@ typedef enum { */ #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIT WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIFT - /* These macros should be used when we wish to advertise STBC support for * only 1SS or 2SS or 3SS. */ #define WMI_VHT_CAP_RX_STBC_1SS 0x00000100 @@ -1601,20 +1667,20 @@ typedef enum { */ #define WMI_vHT_CAP_RX_STBC_3SS WMI_VHT_CAP_RX_STBC_3SS -#define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \ - WMI_VHT_CAP_SGI_80MHZ | \ - WMI_VHT_CAP_TX_STBC | \ - WMI_VHT_CAP_RX_STBC_MASK | \ - WMI_VHT_CAP_RX_LDPC | \ - WMI_VHT_CAP_TX_LDPC | \ - WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \ - WMI_VHT_CAP_RX_FIXED_ANT | \ - WMI_VHT_CAP_TX_FIXED_ANT) +#define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \ + WMI_VHT_CAP_SGI_80MHZ | \ + WMI_VHT_CAP_TX_STBC | \ + WMI_VHT_CAP_RX_STBC_MASK | \ + WMI_VHT_CAP_RX_LDPC | \ + WMI_VHT_CAP_TX_LDPC | \ + WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \ + WMI_VHT_CAP_RX_FIXED_ANT | \ + WMI_VHT_CAP_TX_FIXED_ANT) /* Interested readers refer to Rx/Tx MCS Map definition as defined in - 802.11ac + 802.11ac */ -#define WMI_VHT_MAX_MCS_4_SS_MASK(r,ss) ((3 & (r)) << (((ss) - 1) << 1)) +#define WMI_VHT_MAX_MCS_4_SS_MASK(r, ss) ((3 & (r)) << (((ss) - 1) << 1)) #define WMI_VHT_MAX_SUPP_RATE_MASK 0x1fff0000 #define WMI_VHT_MAX_SUPP_RATE_MASK_SHIFT 16 @@ -1625,17 +1691,27 @@ typedef enum { #define WMI_HE_FRAG_SUPPORT_MASK 0x00000018 #define WMI_HE_FRAG_SUPPORT_SHIFT 3 + /* fragmentation support field value */ enum { - WMI_HE_FRAG_SUPPORT_LEVEL0, /* No Fragmentation support */ - WMI_HE_FRAG_SUPPORT_LEVEL1, /* support for fragments within a VHT single MPDU, no support for fragments within AMPDU */ - WMI_HE_FRAG_SUPPORT_LEVEL2, /* support for up to 1 fragment per MSDU within a single A-MPDU */ - WMI_HE_FRAG_SUPPORT_LEVEL3, /* support for multiple fragments per MSDU within an A-MPDU */ + WMI_HE_FRAG_SUPPORT_LEVEL0, /* No Fragmentation support */ + /* + * support for fragments within a VHT single MPDU, + * no support for fragments within AMPDU + */ + WMI_HE_FRAG_SUPPORT_LEVEL1, + /* support for up to 1 fragment per MSDU within a single A-MPDU */ + WMI_HE_FRAG_SUPPORT_LEVEL2, + /* support for multiple fragments per MSDU within an A-MPDU */ + WMI_HE_FRAG_SUPPORT_LEVEL3, }; -/** NOTE: This defs cannot be changed in the future without breaking WMI compatibility */ -#define WMI_MAX_NUM_SS 8 -#define WMI_MAX_NUM_RU 4 + +/** NOTE: This defs cannot be changed in the future without + * breaking WMI compatibility + */ +#define WMI_MAX_NUM_SS MAX_HE_NSS +#define WMI_MAX_NUM_RU MAX_HE_RU /* * Figure 8 554ae: -PPE Threshold Info field format @@ -1647,7 +1723,7 @@ enum { *31:23| 22:20 | 19:17 | 17:15 | 14:12 | 11:9 | 8:6 | 5:3 | 2:0 | * * ppet16_ppet8_ru3_ru0 array element 1 holds: - * | PPET8 | PPET16 | PPET8 | PPET16 | PPET8 | PPET16 | PPET8 | PPET16 | + * | PPET8 | PPET16 | PPET8 | PPET16 | PPET8 | PPET16 | PPET8 | PPET16 | *rsvd |NSS2,RU4|NSS2,RU4|NSS2,RU3|NSS2,RU3|NSS2,RU2|NSS2,RU2|NSS2,RU1|NSS2,RU1| *31:23| 22:20 | 19:17 | 17:15 | 14:12 | 11:9 | 8:6 | 5:3 | 2:0 | * @@ -1659,27 +1735,28 @@ enum { * nssm1 is zero-based. */ #define WMI_SET_PPET16(ppet16_ppet8_ru3_ru0, ppet, ru, nssm1) \ - do { \ - ppet16_ppet8_ru3_ru0[nssm1] &= ~(7 << (((ru-1) % 4) * 6)); \ - ppet16_ppet8_ru3_ru0[nssm1] |= ((ppet & 7) << (((ru-1) % 4) * 6)); \ - } while (0) + do { \ + ppet16_ppet8_ru3_ru0[nssm1] &= ~(7 << (((ru-1)%4)*6)); \ + ppet16_ppet8_ru3_ru0[nssm1] |= ((ppet&7) << (((ru-1)%4)*6)); \ + } while (0) #define WMI_GET_PPET16(ppet16_ppet8_ru3_ru0, ru, nssm1) \ - ((ppet16_ppet8_ru3_ru0[nssm1] >> (((ru-1) % 4) * 6)) & 7) + ((ppet16_ppet8_ru3_ru0[nssm1] >> (((ru-1)%4)*6))&7) #define WMI_SET_PPET8(ppet16_ppet8_ru3_ru0, ppet, ru, nssm1) \ - do { \ - ppet16_ppet8_ru3_ru0[nssm1] &= ~(7 << (((ru-1) % 4) * 6 + 3)); \ - ppet16_ppet8_ru3_ru0[nssm1] |= ((ppet&7) << (((ru-1) % 4) * 6 + 3)); \ - } while (0) + do { \ + ppet16_ppet8_ru3_ru0[nssm1] &= ~(7 << (((ru-1)%4)*6+3)); \ + ppet16_ppet8_ru3_ru0[nssm1] |= ((ppet&7) << (((ru-1)%4)*6+3)); \ + } while (0) #define WMI_GET_PPET8(ppet16_ppet8_ru3_ru0, ru, nssm1) \ - ((ppet16_ppet8_ru3_ru0[nssm1] >> (((ru-1) % 4) * 6 + 3)) & 7) + ((ppet16_ppet8_ru3_ru0[nssm1] >> (((ru-1)%4)*6+3))&7) typedef struct _wmi_ppe_threshold { - A_UINT32 numss_m1; /** NSS - 1*/ - A_UINT32 ru_count; /** Max RU count */ - A_UINT32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; /** ppet8 and ppet16 for max num ss */ + A_UINT32 numss_m1; /** NSS - 1*/ + A_UINT32 ru_count; /** Max RU count */ + /** ppet8 and ppet16 for max num ss */ + A_UINT32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; } wmi_ppe_threshold; /* WMI_SYS_CAPS_* refer to the capabilities that system support @@ -1772,23 +1849,29 @@ typedef struct _wmi_ppe_threshold { #define WMI_DBS_FW_MODE_CFG_AGILE_DFS_MASK (0x1 << WMI_DBS_FW_MODE_CFG_AGILE_DFS_BITPOS) #define WMI_DBS_FW_MODE_CFG_DBS_SET(fw_mode, value) \ - WMI_SET_BITS(fw_mode, WMI_DBS_FW_MODE_CFG_DBS_BITPOS, 1, value) + WMI_SET_BITS(fw_mode, WMI_DBS_FW_MODE_CFG_DBS_BITPOS, 1, value) #define WMI_DBS_FW_MODE_CFG_AGILE_DFS_SET(fw_mode, value) \ - WMI_SET_BITS(fw_mode, WMI_DBS_FW_MODE_CFG_AGILE_DFS_BITPOS, 1, value) + WMI_SET_BITS(fw_mode, WMI_DBS_FW_MODE_CFG_AGILE_DFS_BITPOS, 1, value) #define WMI_DBS_FW_MODE_CFG_DBS_GET(fw_mode) \ - ((fw_mode & WMI_DBS_FW_MODE_CFG_DBS_MASK) >> WMI_DBS_FW_MODE_CFG_DBS_BITPOS) + ((fw_mode & WMI_DBS_FW_MODE_CFG_DBS_MASK) >> WMI_DBS_FW_MODE_CFG_DBS_BITPOS) #define WMI_DBS_FW_MODE_CFG_AGILE_DFS_GET(fw_mode) \ - ((fw_mode & WMI_DBS_FW_MODE_CFG_AGILE_DFS_MASK) >> WMI_DBS_FW_MODE_CFG_AGILE_DFS_BITPOS) + ((fw_mode & WMI_DBS_FW_MODE_CFG_AGILE_DFS_MASK) >> WMI_DBS_FW_MODE_CFG_AGILE_DFS_BITPOS) /** NOTE: This structure cannot be extended in the future without breaking WMI compatibility */ typedef struct _wmi_abi_version { - A_UINT32 abi_version_0; /** WMI Major and Minor versions */ - A_UINT32 abi_version_1; /** WMI change revision */ - A_UINT32 abi_version_ns_0; /** ABI version namespace first four dwords */ - A_UINT32 abi_version_ns_1; /** ABI version namespace second four dwords */ - A_UINT32 abi_version_ns_2; /** ABI version namespace third four dwords */ - A_UINT32 abi_version_ns_3; /** ABI version namespace fourth four dwords */ + A_UINT32 abi_version_0; + /** WMI Major and Minor versions */ + A_UINT32 abi_version_1; + /** WMI change revision */ + A_UINT32 abi_version_ns_0; + /** ABI version namespace first four dwords */ + A_UINT32 abi_version_ns_1; + /** ABI version namespace second four dwords */ + A_UINT32 abi_version_ns_2; + /** ABI version namespace third four dwords */ + A_UINT32 abi_version_ns_3; + /** ABI version namespace fourth four dwords */ } wmi_abi_version; /* @@ -1817,144 +1900,162 @@ typedef struct _wmi_abi_version { * device capability to the host. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SERVICE_READY_EVENT */ - A_UINT32 fw_build_vers; /* firmware build number */ - wmi_abi_version fw_abi_vers; - A_UINT32 phy_capability; /* WMI_PHY_CAPABILITY */ - A_UINT32 max_frag_entry; /* Maximum number of frag table entries that SW will populate less 1 */ - A_UINT32 num_rf_chains; - /* The following field is only valid for service type WMI_SERVICE_11AC */ - A_UINT32 ht_cap_info; /* WMI HT Capability */ - A_UINT32 vht_cap_info; /* VHT capability info field of 802.11ac */ - A_UINT32 vht_supp_mcs; /* VHT Supported MCS Set field Rx/Tx same */ - A_UINT32 hw_min_tx_power; - A_UINT32 hw_max_tx_power; - A_UINT32 sys_cap_info; - A_UINT32 min_pkt_size_enable; /* Enterprise mode short pkt enable */ - /** Max beacon and Probe Response IE offload size (includes - * optional P2P IEs) */ - A_UINT32 max_bcn_ie_size; - /* - * request to host to allocate a chuck of memory and pss it down to FW via WM_INIT. - * FW uses this as FW extesnsion memory for saving its data structures. Only valid - * for low latency interfaces like PCIE where FW can access this memory directly (or) - * by DMA. - */ - A_UINT32 num_mem_reqs; - /* Max No. scan channels target can support - * If FW is too old and doesn't indicate this number, host side value will default to - * 0, and host will take the original compatible value (62) for future scan channel - * setup. - */ - A_UINT32 max_num_scan_channels; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SERVICE_READY_EVENT */ + A_UINT32 fw_build_vers; /* firmware build number */ + wmi_abi_version fw_abi_vers; + A_UINT32 phy_capability; /* WMI_PHY_CAPABILITY */ + A_UINT32 max_frag_entry; /* Maximum number of frag table entries that SW will populate less 1 */ + A_UINT32 num_rf_chains; + /* The following field is only valid for service type WMI_SERVICE_11AC */ + A_UINT32 ht_cap_info; /* WMI HT Capability */ + A_UINT32 vht_cap_info; /* VHT capability info field of 802.11ac */ + A_UINT32 vht_supp_mcs; /* VHT Supported MCS Set field Rx/Tx same */ + A_UINT32 hw_min_tx_power; + A_UINT32 hw_max_tx_power; + A_UINT32 sys_cap_info; + A_UINT32 min_pkt_size_enable; /* Enterprise mode short pkt enable */ + /** Max beacon and Probe Response IE offload size (includes + * optional P2P IEs) */ + A_UINT32 max_bcn_ie_size; + /* + * request to host to allocate a chuck of memory and pss it down to FW via WM_INIT. + * FW uses this as FW extesnsion memory for saving its data structures. Only valid + * for low latency interfaces like PCIE where FW can access this memory directly (or) + * by DMA. + */ + A_UINT32 num_mem_reqs; + /* Max No. scan channels target can support + * If FW is too old and doesn't indicate this number, host side value will default to + * 0, and host will take the original compatible value (62) for future scan channel + * setup. + */ + A_UINT32 max_num_scan_channels; - /* Hardware board specific ID. Values defined in enum WMI_HWBOARD_ID. - * Default 0 means tha hw_bd_info[] is invalid(legacy board). - */ - A_UINT32 hw_bd_id; - A_UINT32 hw_bd_info[HW_BD_INFO_SIZE]; /* Board specific information. Invalid if hw_hd_id is zero. */ + /* Hardware board specific ID. Values defined in enum WMI_HWBOARD_ID. + * Default 0 means tha hw_bd_info[] is invalid(legacy board). + */ + A_UINT32 hw_bd_id; + A_UINT32 hw_bd_info[HW_BD_INFO_SIZE]; /* Board specific information. Invalid if hw_hd_id is zero. */ - /* - * Number of MACs supported, i.e. a DBS-capable device will return 2 - */ - A_UINT32 max_supported_macs; + /* + * Number of MACs supported, i.e. a DBS-capable device will return 2 + */ + A_UINT32 max_supported_macs; - /* - * FW sub-feature capabilities to be used in concurrence with wmi_service_bitmap - */ - A_UINT32 wmi_fw_sub_feat_caps; /* values from enum WMI_FW_SUB_FEAT_CAPS */ + /* + * FW sub-feature capabilities to be used in concurrence with + * wmi_service_bitmap + * values from enum WMI_FW_SUB_FEAT_CAPS + */ + A_UINT32 wmi_fw_sub_feat_caps; + /* + * Number of Dual Band Simultaneous (DBS) hardware modes + */ + A_UINT32 num_dbs_hw_modes; + /* + * txrx_chainmask + * [7:0] - 2G band tx chain mask + * [15:8] - 2G band rx chain mask + * [23:16] - 5G band tx chain mask + * [31:24] - 5G band rx chain mask + * + */ + A_UINT32 txrx_chainmask; - /* - * Number of Dual Band Simultaneous (DBS) hardware modes - */ - A_UINT32 num_dbs_hw_modes; + /* + * default Dual Band Simultaneous (DBS) hardware mode + */ + A_UINT32 default_dbs_hw_mode_index; - /* - * txrx_chainmask - * [7:0] - 2G band tx chain mask - * [15:8] - 2G band rx chain mask - * [23:16] - 5G band tx chain mask - * [31:24] - 5G band rx chain mask - * - */ - A_UINT32 txrx_chainmask; + /* + * Number of msdu descriptors target would use + */ + A_UINT32 num_msdu_desc; - /* - * default Dual Band Simultaneous (DBS) hardware mode - */ - A_UINT32 default_dbs_hw_mode_index; - - /* - * Number of msdu descriptors target would use - */ - A_UINT32 num_msdu_desc; - -/* The TLVs for hal_reg_capabilities, wmi_service_bitmap and mem_reqs[] will follow this TLV. - * HAL_REG_CAPABILITIES hal_reg_capabilities; - * A_UINT32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE]; - * wlan_host_mem_req mem_reqs[]; - * wlan_dbs_hw_mode_list[]; - */ + /* The TLVs for hal_reg_capabilities, wmi_service_bitmap and mem_reqs[] will follow this TLV. + * HAL_REG_CAPABILITIES hal_reg_capabilities; + * A_UINT32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE]; + * wlan_host_mem_req mem_reqs[]; + * wlan_dbs_hw_mode_list[]; + */ } wmi_service_ready_event_fixed_param; #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x A_UINT32 = 128 bits */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_available_event_fixed_param */ - /* - * The wmi_service_segment offset field specifies the position within the - * logical bitmap of WMI service flags at which the WMI service flags - * specified within this message begin. - * Since the first 128 WMI service flags are specified within the - * wmi_service_bitmap field of the WMI_SERVICE_READY_EVENT message, - * the wmi_service_segment_offset value is expected to be 128 or more. - */ - A_UINT32 wmi_service_segment_offset; - A_UINT32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_service_available_event_fixed_param + */ + A_UINT32 tlv_header; + /** + * The wmi_service_segment offset field specifies the position + * within the logical bitmap of WMI service flags at which the + * WMI service flags specified within this message begin. + * Since the first 128 WMI service flags are specified within + * the wmi_service_bitmap field of the WMI_SERVICE_READY_EVENT + * message, the wmi_service_segment_offset value is expected to + * be 128 or more. + */ + A_UINT32 wmi_service_segment_offset; + A_UINT32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; } wmi_service_available_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SERVICE_EXT_READY_EVENT */ - /* which WMI_DBS_CONC_SCAN_CFG setting the FW is initialized with */ - A_UINT32 default_conc_scan_config_bits; - /* which WMI_DBS_FW_MODE_CFG setting the FW is initialized with */ - A_UINT32 default_fw_config_bits; - wmi_ppe_threshold ppet; - A_UINT32 he_cap_info; /* see section 8.4.2.213 from draft r8 of 802.11ax; see WMI_HE_FRAG_SUPPORT enum */ - /* - * An HT STA shall not allow transmission of more than one MPDU start - * within the time limit described in the MPDU maximum density field. - */ - A_UINT32 mpdu_density; /* units are microseconds */ - /* - * Maximum no of BSSID based RX filters host can program - * Value 0 means FW hasn't given any limit to host. - */ - A_UINT32 max_bssid_rx_filters; + /* TLV tag and len; tag equals + *WMITLV_TAG_STRUC_WMI_SERVICE_EXT_READY_EVENT + */ + A_UINT32 tlv_header; + /* which WMI_DBS_CONC_SCAN_CFG setting the FW is initialized with */ + A_UINT32 default_conc_scan_config_bits; + /* which WMI_DBS_FW_MODE_CFG setting the FW is initialized with */ + A_UINT32 default_fw_config_bits; + wmi_ppe_threshold ppet; + /* + * see section 8.4.2.213 from draft r8 of 802.11ax; + * see WMI_HE_FRAG_SUPPORT enum + */ + A_UINT32 he_cap_info; + /* + * An HT STA shall not allow transmission of more than one MPDU start + * within the time limit described in the MPDU maximum density field. + */ + A_UINT32 mpdu_density; /* units are microseconds */ + /* + * Maximum no of BSSID based RX filters host can program + * Value 0 means FW hasn't given any limit to host. + */ + A_UINT32 max_bssid_rx_filters; + /* + * Extended FW build version information: + * bits 27:0 -> reserved + * bits 31:28 -> CRM sub ID + */ + A_UINT32 fw_build_vers_ext; } wmi_service_ready_ext_event_fixed_param; typedef enum { - WMI_FW_STA_RTT_INITR = 0x00000001, - WMI_FW_STA_RTT_RESPR = 0x00000002, - WMI_FW_P2P_CLI_RTT_INITR = 0x00000004, - WMI_FW_P2P_CLI_RTT_RESPR = 0x00000008, - WMI_FW_P2P_GO_RTT_INITR = 0x00000010, - WMI_FW_P2P_GO_RTT_RESPR = 0x00000020, - WMI_FW_AP_RTT_INITR = 0x00000040, - WMI_FW_AP_RTT_RESPR = 0x00000080, - WMI_FW_NAN_RTT_INITR = 0x00000100, - WMI_FW_NAN_RTT_RESPR = 0x00000200, - /* - * New fw sub feature capabilites before - * WMI_FW_MAX_SUB_FEAT_CAP - */ - WMI_FW_MAX_SUB_FEAT_CAP = 0x80000000, -} WMI_FW_SUB_FEAT_CAPS; + WMI_HWBD_NONE = 0, /* No hw board information is given */ + WMI_HWBD_QCA6174 = 1, /* Rome(AR6320) */ + WMI_HWBD_QCA2582 = 2, /* Killer 1525 */ +} WMI_HWBD_ID; typedef enum { - WMI_HWBD_NONE = 0, /* No hw board information is given */ - WMI_HWBD_QCA6174 = 1, /* Rome(AR6320) */ - WMI_HWBD_QCA2582 = 2, /* Killer 1525*/ -} WMI_HWBD_ID; + WMI_FW_STA_RTT_INITR = 0x00000001, + WMI_FW_STA_RTT_RESPR = 0x00000002, + WMI_FW_P2P_CLI_RTT_INITR = 0x00000004, + WMI_FW_P2P_CLI_RTT_RESPR = 0x00000008, + WMI_FW_P2P_GO_RTT_INITR = 0x00000010, + WMI_FW_P2P_GO_RTT_RESPR = 0x00000020, + WMI_FW_AP_RTT_INITR = 0x00000040, + WMI_FW_AP_RTT_RESPR = 0x00000080, + WMI_FW_NAN_RTT_INITR = 0x00000100, + WMI_FW_NAN_RTT_RESPR = 0x00000200, + /* + * New fw sub feature capabilites before + * WMI_FW_MAX_SUB_FEAT_CAP + */ + WMI_FW_MAX_SUB_FEAT_CAP = 0x80000000, +} WMI_FW_SUB_FEAT_CAPS; #define ATH_BD_DATA_REV_MASK 0x000000FF #define ATH_BD_DATA_REV_SHIFT 0 @@ -1968,42 +2069,41 @@ typedef enum { #define ATH_BD_DATA_REF_DESIGN_ID_MASK 0xFF000000 #define ATH_BD_DATA_REF_DESIGN_ID_SHIFT 24 -#define SET_BD_DATA_REV(bd_data_ver, value) \ - ((bd_data_ver) &= ~ATH_BD_DATA_REV_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_REV_SHIFT)) +#define SET_BD_DATA_REV(bd_data_ver, value) \ + ((bd_data_ver) &= ~ATH_BD_DATA_REV_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_REV_SHIFT)) -#define GET_BD_DATA_REV(bd_data_ver) \ - (((bd_data_ver) & ATH_BD_DATA_REV_MASK) >> ATH_BD_DATA_REV_SHIFT) +#define GET_BD_DATA_REV(bd_data_ver) \ + (((bd_data_ver) & ATH_BD_DATA_REV_MASK) >> ATH_BD_DATA_REV_SHIFT) -#define SET_BD_DATA_PROJ_ID(bd_data_ver, value) \ - ((bd_data_ver) &= ~ATH_BD_DATA_PROJ_ID_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_PROJ_ID_SHIFT)) +#define SET_BD_DATA_PROJ_ID(bd_data_ver, value) \ + ((bd_data_ver) &= ~ATH_BD_DATA_PROJ_ID_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_PROJ_ID_SHIFT)) -#define GET_BD_DATA_PROJ_ID(bd_data_ver) \ - (((bd_data_ver) & ATH_BD_DATA_PROJ_ID_MASK) >> ATH_BD_DATA_PROJ_ID_SHIFT) +#define GET_BD_DATA_PROJ_ID(bd_data_ver) \ + (((bd_data_ver) & ATH_BD_DATA_PROJ_ID_MASK) >> ATH_BD_DATA_PROJ_ID_SHIFT) -#define SET_BD_DATA_CUST_ID(bd_data_ver, value) \ - ((bd_data_ver) &= ~ATH_BD_DATA_CUST_ID_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_CUST_ID_SHIFT)) +#define SET_BD_DATA_CUST_ID(bd_data_ver, value) \ + ((bd_data_ver) &= ~ATH_BD_DATA_CUST_ID_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_CUST_ID_SHIFT)) -#define GET_BD_DATA_CUST_ID(bd_data_ver) \ - (((bd_data_ver) & ATH_BD_DATA_CUST_ID_MASK) >> ATH_BD_DATA_CUST_ID_SHIFT) +#define GET_BD_DATA_CUST_ID(bd_data_ver) \ + (((bd_data_ver) & ATH_BD_DATA_CUST_ID_MASK) >> ATH_BD_DATA_CUST_ID_SHIFT) -#define SET_BD_DATA_REF_DESIGN_ID(bd_data_ver, value) \ - ((bd_data_ver) &= ~ATH_BD_DATA_REF_DESIGN_ID_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_REF_DESIGN_ID_SHIFT)) - -#define GET_BD_DATA_REF_DESIGN_ID(bd_data_ver) \ - (((bd_data_ver) & ATH_BD_DATA_REF_DESIGN_ID_MASK) >> ATH_BD_DATA_REF_DESIGN_ID_SHIFT) +#define SET_BD_DATA_REF_DESIGN_ID(bd_data_ver, value) \ + ((bd_data_ver) &= ~ATH_BD_DATA_REF_DESIGN_ID_MASK, (bd_data_ver) |= ((value) << ATH_BD_DATA_REF_DESIGN_ID_SHIFT)) +#define GET_BD_DATA_REF_DESIGN_ID(bd_data_ver) \ + (((bd_data_ver) & ATH_BD_DATA_REF_DESIGN_ID_MASK) >> ATH_BD_DATA_REF_DESIGN_ID_SHIFT) #ifdef ROME_LTE_COEX_FREQ_AVOID typedef struct { - A_UINT32 start_freq; /* start frequency, not channel center freq */ - A_UINT32 end_freq; /* end frequency */ + A_UINT32 start_freq; /* start frequency, not channel center freq */ + A_UINT32 end_freq; /* end frequency */ } avoid_freq_range_desc; typedef struct { - /* bad channel range count, multi range is allowed, 0 means all channel clear */ - A_UINT32 num_freq_ranges; - /* multi range with num_freq_ranges, LTE advance multi carrier, CDMA,etc */ - avoid_freq_range_desc avd_freq_range[0]; + /* bad channel range count, multi range is allowed, 0 means all channel clear */ + A_UINT32 num_freq_ranges; + /* multi range with num_freq_ranges, LTE advance multi carrier, CDMA,etc */ + avoid_freq_range_desc avd_freq_range[0]; } wmi_wlan_avoid_freq_ranges_event; #endif @@ -2016,446 +2116,457 @@ typedef struct { typedef A_UINT32 WLAN_INIT_STATUS; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ready_event_fixed_param */ - wmi_abi_version fw_abi_vers; - wmi_mac_addr mac_addr; - A_UINT32 status; - A_UINT32 num_dscp_table; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ready_event_fixed_param */ + wmi_abi_version fw_abi_vers; + wmi_mac_addr mac_addr; + A_UINT32 status; + A_UINT32 num_dscp_table; } wmi_ready_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resource_config */ - /** - * @brief num_vdev - number of virtual devices (VAPs) to support - */ - A_UINT32 num_vdevs; - /** - * @brief num_peers - number of peer nodes to support - */ - A_UINT32 num_peers; - /* - * @brief In offload mode target supports features like WOW, chatter and other - * protocol offloads. In order to support them some functionalities like - * reorder buffering, PN checking need to be done in target. This determines - * maximum number of peers suported by target in offload mode - */ - A_UINT32 num_offload_peers; - /* @brief Number of reorder buffers available for doing target based reorder - * Rx reorder buffering - */ - A_UINT32 num_offload_reorder_buffs; - /** - * @brief num_peer_keys - number of keys per peer - */ - A_UINT32 num_peer_keys; - /** - * @brief num_peer_tids - number of TIDs to provide storage for per peer. - */ - A_UINT32 num_tids; - /** - * @brief ast_skid_limit - max skid for resolving hash collisions - * @details - * The address search table is sparse, so that if two MAC addresses - * result in the same hash value, the second of these conflicting - * entries can slide to the next index in the address search table, - * and use it, if it is unoccupied. This ast_skid_limit parameter - * specifies the upper bound on how many subsequent indices to search - * over to find an unoccupied space. - */ - A_UINT32 ast_skid_limit; - /** - * @brief tx_chain_mask - the nominal chain mask for transmit - * @details - * The chain mask may be modified dynamically, e.g. to operate AP tx with - * a reduced number of chains if no clients are associated. - * This configuration parameter specifies the nominal chain-mask that - * should be used when not operating with a reduced set of tx chains. - */ - A_UINT32 tx_chain_mask; - /** - * @brief rx_chain_mask - the nominal chain mask for receive - * @details - * The chain mask may be modified dynamically, e.g. for a client to use - * a reduced number of chains for receive if the traffic to the client - * is low enough that it doesn't require downlink MIMO or antenna - * diversity. - * This configuration parameter specifies the nominal chain-mask that - * should be used when not operating with a reduced set of rx chains. - */ - A_UINT32 rx_chain_mask; - /** - * @brief rx_timeout_pri - what rx reorder timeout (ms) to use for the AC - * @details - * Each WMM access class (voice, video, best-effort, background) will - * have its own timeout value to dictate how long to wait for missing - * rx MPDUs to arrive before flushing subsequent MPDUs that have already - * been received. - * This parameter specifies the timeout in milliseconds for each class . - * NOTE: the number of class (defined as 4) cannot be - * changed in the future without breaking WMI compatibility. - */ - A_UINT32 rx_timeout_pri[4]; - /** - * @brief rx_decap mode - what mode the rx should decap packets to - * @details - * MAC can decap to RAW (no decap), native wifi or Ethernet types - * THis setting also determines the default TX behavior, however TX - * behavior can be modified on a per VAP basis during VAP init - */ - A_UINT32 rx_decap_mode; - /** - * @brief scan_max_pending_req - what is the maximum scan requests than can be queued - */ - A_UINT32 scan_max_pending_req; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resource_config */ +/** + * @brief num_vdev - number of virtual devices (VAPs) to support + */ + A_UINT32 num_vdevs; +/** + * @brief num_peers - number of peer nodes to support + */ + A_UINT32 num_peers; +/* + * @brief In offload mode target supports features like WOW, chatter and other + * protocol offloads. In order to support them some functionalities like + * reorder buffering, PN checking need to be done in target. This determines + * maximum number of peers suported by target in offload mode + */ + A_UINT32 num_offload_peers; +/* @brief Number of reorder buffers available for doing target based reorder + * Rx reorder buffering + */ + A_UINT32 num_offload_reorder_buffs; +/** + * @brief num_peer_keys - number of keys per peer + */ + A_UINT32 num_peer_keys; +/** + * @brief num_peer_tids - number of TIDs to provide storage for per peer. + */ + A_UINT32 num_tids; +/** + * @brief ast_skid_limit - max skid for resolving hash collisions + * @details + * The address search table is sparse, so that if two MAC addresses + * result in the same hash value, the second of these conflicting + * entries can slide to the next index in the address search table, + * and use it, if it is unoccupied. This ast_skid_limit parameter + * specifies the upper bound on how many subsequent indices to search + * over to find an unoccupied space. + */ + A_UINT32 ast_skid_limit; +/** + * @brief tx_chain_mask - the nominal chain mask for transmit + * @details + * The chain mask may be modified dynamically, e.g. to operate AP tx with + * a reduced number of chains if no clients are associated. + * This configuration parameter specifies the nominal chain-mask that + * should be used when not operating with a reduced set of tx chains. + */ + A_UINT32 tx_chain_mask; +/** + * @brief rx_chain_mask - the nominal chain mask for receive + * @details + * The chain mask may be modified dynamically, e.g. for a client to use + * a reduced number of chains for receive if the traffic to the client + * is low enough that it doesn't require downlink MIMO or antenna + * diversity. + * This configuration parameter specifies the nominal chain-mask that + * should be used when not operating with a reduced set of rx chains. + */ + A_UINT32 rx_chain_mask; +/** + * @brief rx_timeout_pri - what rx reorder timeout (ms) to use for the AC + * @details + * Each WMM access class (voice, video, best-effort, background) will + * have its own timeout value to dictate how long to wait for missing + * rx MPDUs to arrive before flushing subsequent MPDUs that have already + * been received. + * This parameter specifies the timeout in milliseconds for each class . + * NOTE: the number of class (defined as 4) cannot be + * changed in the future without breaking WMI compatibility. + */ + A_UINT32 rx_timeout_pri[4]; +/** + * @brief rx_decap mode - what mode the rx should decap packets to + * @details + * MAC can decap to RAW (no decap), native wifi or Ethernet types + * THis setting also determines the default TX behavior, however TX + * behavior can be modified on a per VAP basis during VAP init + */ + A_UINT32 rx_decap_mode; + /** + * @brief scan_max_pending_req - what is the maximum scan requests than can be queued + */ + A_UINT32 scan_max_pending_req; - /** - * @brief maximum VDEV that could use BMISS offload - */ - A_UINT32 bmiss_offload_max_vdev; + /** + * @brief maximum VDEV that could use BMISS offload + */ + A_UINT32 bmiss_offload_max_vdev; - /** - * @brief maximum VDEV that could use offload roaming - */ - A_UINT32 roam_offload_max_vdev; + /** + * @brief maximum VDEV that could use offload roaming + */ + A_UINT32 roam_offload_max_vdev; - /** - * @brief maximum AP profiles that would push to offload roaming - */ - A_UINT32 roam_offload_max_ap_profiles; + /** + * @brief maximum AP profiles that would push to offload roaming + */ + A_UINT32 roam_offload_max_ap_profiles; - /** - * @brief num_mcast_groups - how many groups to use for mcast->ucast conversion - * @details - * The target's WAL maintains a table to hold information regarding which - * peers belong to a given multicast group, so that if multicast->unicast - * conversion is enabled, the target can convert multicast tx frames to a - * series of unicast tx frames, to each peer within the multicast group. - * This num_mcast_groups configuration parameter tells the target how - * many multicast groups to provide storage for within its multicast - * group membership table. - */ - A_UINT32 num_mcast_groups; +/** + * @brief num_mcast_groups - how many groups to use for mcast->ucast conversion + * @details + * The target's WAL maintains a table to hold information regarding which + * peers belong to a given multicast group, so that if multicast->unicast + * conversion is enabled, the target can convert multicast tx frames to a + * series of unicast tx frames, to each peer within the multicast group. + * This num_mcast_groups configuration parameter tells the target how + * many multicast groups to provide storage for within its multicast + * group membership table. + */ + A_UINT32 num_mcast_groups; - /** - * @brief num_mcast_table_elems - size to alloc for the mcast membership table - * @details - * This num_mcast_table_elems configuration parameter tells the target - * how many peer elements it needs to provide storage for in its - * multicast group membership table. - * These multicast group membership table elements are shared by the - * multicast groups stored within the table. - */ - A_UINT32 num_mcast_table_elems; +/** + * @brief num_mcast_table_elems - size to alloc for the mcast membership table + * @details + * This num_mcast_table_elems configuration parameter tells the target + * how many peer elements it needs to provide storage for in its + * multicast group membership table. + * These multicast group membership table elements are shared by the + * multicast groups stored within the table. + */ + A_UINT32 num_mcast_table_elems; - /** - * @brief mcast2ucast_mode - whether/how to do multicast->unicast conversion - * @details - * This configuration parameter specifies whether the target should - * perform multicast --> unicast conversion on transmit, and if so, - * what to do if it finds no entries in its multicast group membership - * table for the multicast IP address in the tx frame. - * Configuration value: - * 0 -> Do not perform multicast to unicast conversion. - * 1 -> Convert multicast frames to unicast, if the IP multicast address - * from the tx frame is found in the multicast group membership - * table. If the IP multicast address is not found, drop the frame. - * 2 -> Convert multicast frames to unicast, if the IP multicast address - * from the tx frame is found in the multicast group membership - * table. If the IP multicast address is not found, transmit the - * frame as multicast. - */ - A_UINT32 mcast2ucast_mode; +/** + * @brief mcast2ucast_mode - whether/how to do multicast->unicast conversion + * @details + * This configuration parameter specifies whether the target should + * perform multicast --> unicast conversion on transmit, and if so, + * what to do if it finds no entries in its multicast group membership + * table for the multicast IP address in the tx frame. + * Configuration value: + * 0 -> Do not perform multicast to unicast conversion. + * 1 -> Convert multicast frames to unicast, if the IP multicast address + * from the tx frame is found in the multicast group membership + * table. If the IP multicast address is not found, drop the frame. + * 2 -> Convert multicast frames to unicast, if the IP multicast address + * from the tx frame is found in the multicast group membership + * table. If the IP multicast address is not found, transmit the + * frame as multicast. + */ + A_UINT32 mcast2ucast_mode; + /** + * @brief tx_dbg_log_size - how much memory to allocate for a tx PPDU dbg log + * @details + * This parameter controls how much memory the target will allocate to + * store a log of tx PPDU meta-information (how large the PPDU was, + * when it was sent, whether it was successful, etc.) + */ + A_UINT32 tx_dbg_log_size; - /** - * @brief tx_dbg_log_size - how much memory to allocate for a tx PPDU dbg log - * @details - * This parameter controls how much memory the target will allocate to - * store a log of tx PPDU meta-information (how large the PPDU was, - * when it was sent, whether it was successful, etc.) - */ - A_UINT32 tx_dbg_log_size; + /** + * @brief num_wds_entries - how many AST entries to be allocated for WDS + */ + A_UINT32 num_wds_entries; - /** - * @brief num_wds_entries - how many AST entries to be allocated for WDS - */ - A_UINT32 num_wds_entries; + /** + * @brief dma_burst_size - MAC DMA burst size, e.g., on Peregrine on PCI + * this limit can be 0 -default, 1 256B + */ + A_UINT32 dma_burst_size; - /** - * @brief dma_burst_size - MAC DMA burst size, e.g., on Peregrine on PCI - * this limit can be 0 -default, 1 256B - */ - A_UINT32 dma_burst_size; + /** + * @brief mac_aggr_delim - Fixed delimiters to be inserted after every MPDU + * to account for interface latency to avoid underrun. + */ + A_UINT32 mac_aggr_delim; + /** + * @brief rx_skip_defrag_timeout_dup_detection_check + * @details + * determine whether target is responsible for detecting duplicate + * non-aggregate MPDU and timing out stale fragments. + * + * A-MPDU reordering is always performed on the target. + * + * 0: target responsible for frag timeout and dup checking + * 1: host responsible for frag timeout and dup checking + */ + A_UINT32 rx_skip_defrag_timeout_dup_detection_check; - /** - * @brief mac_aggr_delim - Fixed delimiters to be inserted after every MPDU - * to account for interface latency to avoid underrun. - */ - A_UINT32 mac_aggr_delim; - /** - * @brief rx_skip_defrag_timeout_dup_detection_check - * @details - * determine whether target is responsible for detecting duplicate - * non-aggregate MPDU and timing out stale fragments. - * - * A-MPDU reordering is always performed on the target. - * - * 0: target responsible for frag timeout and dup checking - * 1: host responsible for frag timeout and dup checking - */ - A_UINT32 rx_skip_defrag_timeout_dup_detection_check; + /** + * @brief vow_config - Configuration for VoW : No of Video Nodes to be supported + * and Max no of descriptors for each Video link (node). + */ + A_UINT32 vow_config; - /** - * @brief vow_config - Configuration for VoW : No of Video Nodes to be supported - * and Max no of descriptors for each Video link (node). - */ - A_UINT32 vow_config; + /** + * @brief maximum VDEV that could use GTK offload + */ + A_UINT32 gtk_offload_max_vdev; - /** - * @brief maximum VDEV that could use GTK offload - */ - A_UINT32 gtk_offload_max_vdev; + /** + * @brief num_msdu_desc - Number of msdu descriptors target should use + */ + A_UINT32 num_msdu_desc; /* Number of msdu desc */ + /** + * @brief max_frag_entry - Max. number of Tx fragments per MSDU + * @details + * This parameter controls the max number of Tx fragments per MSDU. + * This is sent by the target as part of the WMI_SERVICE_READY event + * and is overriden by the OS shim as required. + */ + A_UINT32 max_frag_entries; - /** - * @brief num_msdu_desc - Number of msdu descriptors target should use - */ - A_UINT32 num_msdu_desc; /* Number of msdu desc */ - /** - * @brief max_frag_entry - Max. number of Tx fragments per MSDU - * @details - * This parameter controls the max number of Tx fragments per MSDU. - * This is sent by the target as part of the WMI_SERVICE_READY event - * and is overriden by the OS shim as required. - */ - A_UINT32 max_frag_entries; + /** + * @brief num_tdls_vdevs - Max. number of vdevs that can support TDLS + * @brief num_msdu_desc - Number of vdev that can support beacon offload + */ - /** - * @brief num_tdls_vdevs - Max. number of vdevs that can support TDLS - * @brief num_msdu_desc - Number of vdev that can support beacon offload - */ + A_UINT32 num_tdls_vdevs; /* number of vdevs allowed to do tdls */ - A_UINT32 num_tdls_vdevs; /* number of vdevs allowed to do tdls */ + /** + * @brief num_tdls_conn_table_entries - Number of peers tracked by tdls vdev + * @details + * Each TDLS enabled vdev can track outgoing transmits/rssi/rates to/of + * peers in a connection tracking table for possible TDLS link creation + * or deletion. This controls the number of tracked peers per vdev. + */ + A_UINT32 num_tdls_conn_table_entries; /* number of peers to track per TDLS vdev */ + A_UINT32 beacon_tx_offload_max_vdev; + A_UINT32 num_multicast_filter_entries; + A_UINT32 num_wow_filters; /*host can configure the number of wow filters */ - /** - * @brief num_tdls_conn_table_entries - Number of peers tracked by tdls vdev - * @details - * Each TDLS enabled vdev can track outgoing transmits/rssi/rates to/of - * peers in a connection tracking table for possible TDLS link creation - * or deletion. This controls the number of tracked peers per vdev. - */ - A_UINT32 num_tdls_conn_table_entries; /* number of peers to track per TDLS vdev */ - A_UINT32 beacon_tx_offload_max_vdev; - A_UINT32 num_multicast_filter_entries; - A_UINT32 num_wow_filters; /*host can configure the number of wow filters*/ + /** + * @brief num_keep_alive_pattern - Num of keep alive patterns configured + * from host. + */ + A_UINT32 num_keep_alive_pattern; + /** + * @brief keep_alive_pattern_size - keep alive pattern size. + */ + A_UINT32 keep_alive_pattern_size; - /** - * @brief num_keep_alive_pattern - Num of keep alive patterns configured - * from host. - */ - A_UINT32 num_keep_alive_pattern; - /** - * @brief keep_alive_pattern_size - keep alive pattern size. - */ - A_UINT32 keep_alive_pattern_size; - /** - * @brief max_tdls_concurrent_sleep_sta - Number of tdls sleep sta supported - * @details - * Each TDLS STA can become a sleep STA independently. This parameter - * mentions how many such sleep STAs can be supported concurrently. - */ - A_UINT32 max_tdls_concurrent_sleep_sta; + /** + * @brief max_tdls_concurrent_sleep_sta - Number of tdls sleep sta supported + * @details + * Each TDLS STA can become a sleep STA independently. This parameter + * mentions how many such sleep STAs can be supported concurrently. + */ + A_UINT32 max_tdls_concurrent_sleep_sta; - /** - * @brief max_tdls_concurrent_buffer_sta - Number of tdls buffer sta supported - * @details - * Each TDLS STA can become a buffer STA independently. This parameter - * mentions how many such buffer STAs can be supported concurrently. - */ - A_UINT32 max_tdls_concurrent_buffer_sta; + /** + * @brief max_tdls_concurrent_buffer_sta - Number of tdls buffer sta supported + * @details + * Each TDLS STA can become a buffer STA independently. This parameter + * mentions how many such buffer STAs can be supported concurrently. + */ + A_UINT32 max_tdls_concurrent_buffer_sta; - /** - * @brief wmi_send_separate - host configures fw to send the wmi separately - */ - A_UINT32 wmi_send_separate; + /** + * @brief wmi_send_separate - host configures fw to send the wmi separately + */ + A_UINT32 wmi_send_separate; - /** - * @brief num_ocb_vdevs - Number of vdevs used for OCB support - */ - A_UINT32 num_ocb_vdevs; + /** + * @brief num_ocb_vdevs - Number of vdevs used for OCB support + */ + A_UINT32 num_ocb_vdevs; - /** - * @brief num_ocb_channels - The supported number of simultaneous OCB channels - */ - A_UINT32 num_ocb_channels; + /** + * @brief num_ocb_channels - The supported number of simultaneous OCB channels + */ + A_UINT32 num_ocb_channels; - /** - * @brief num_ocb_schedules - The supported number of OCB schedule segments - */ - A_UINT32 num_ocb_schedules; + /** + * @brief num_ocb_schedules - The supported number of OCB schedule segments + */ + A_UINT32 num_ocb_schedules; + /** + * @brief specific configuration from host, such as per platform configuration + */ + #define WMI_RSRC_CFG_FLAG_WOW_IGN_PCIE_RST_S 0 + #define WMI_RSRC_CFG_FLAG_WOW_IGN_PCIE_RST_M 0x1 - /** - * @brief specific configuration from host, such as per platform configuration - */ - #define WMI_RSRC_CFG_FLAG_WOW_IGN_PCIE_RST_S 0 - #define WMI_RSRC_CFG_FLAG_WOW_IGN_PCIE_RST_M 0x1 + #define WMI_RSRC_CFG_FLAG_LTEU_SUPPORT_S 1 + #define WMI_RSRC_CFG_FLAG_LTEU_SUPPORT_M 0x2 - #define WMI_RSRC_CFG_FLAG_LTEU_SUPPORT_S 1 - #define WMI_RSRC_CFG_FLAG_LTEU_SUPPORT_M 0x2 + #define WMI_RSRC_CFG_FLAG_COEX_GPIO_SUPPORT_S 2 + #define WMI_RSRC_CFG_FLAG_COEX_GPIO_SUPPORT_M 0x4 - #define WMI_RSRC_CFG_FLAG_COEX_GPIO_SUPPORT_S 2 - #define WMI_RSRC_CFG_FLAG_COEX_GPIO_SUPPORT_M 0x4 + #define WMI_RSRC_CFG_FLAG_AUX_RADIO_SPECTRAL_INTF_S 3 + #define WMI_RSRC_CFG_FLAG_AUX_RADIO_SPECTRAL_INTF_M 0x8 - #define WMI_RSRC_CFG_FLAG_AUX_RADIO_SPECTRAL_INTF_S 3 - #define WMI_RSRC_CFG_FLAG_AUX_RADIO_SPECTRAL_INTF_M 0x8 + #define WMI_RSRC_CFG_FLAG_AUX_RADIO_CHAN_LOAD_INTF_S 4 + #define WMI_RSRC_CFG_FLAG_AUX_RADIO_CHAN_LOAD_INTF_M 0x10 - #define WMI_RSRC_CFG_FLAG_AUX_RADIO_CHAN_LOAD_INTF_S 4 - #define WMI_RSRC_CFG_FLAG_AUX_RADIO_CHAN_LOAD_INTF_M 0x10 + #define WMI_RSRC_CFG_FLAG_BSS_CHANNEL_INFO_64_S 5 + #define WMI_RSRC_CFG_FLAG_BSS_CHANNEL_INFO_64_M 0x20 - #define WMI_RSRC_CFG_FLAG_BSS_CHANNEL_INFO_64_S 5 - #define WMI_RSRC_CFG_FLAG_BSS_CHANNEL_INFO_64_M 0x20 + #define WMI_RSRC_CFG_FLAG_ATF_CONFIG_ENABLE_S 6 + #define WMI_RSRC_CFG_FLAG_ATF_CONFIG_ENABLE_M 0x40 - #define WMI_RSRC_CFG_FLAG_ATF_CONFIG_ENABLE_S 6 - #define WMI_RSRC_CFG_FLAG_ATF_CONFIG_ENABLE_M 0x40 + #define WMI_RSRC_CFG_FLAG_IPHR_PAD_CONFIG_ENABLE_S 7 + #define WMI_RSRC_CFG_FLAG_IPHR_PAD_CONFIG_ENABLE_M 0x80 - #define WMI_RSRC_CFG_FLAG_IPHR_PAD_CONFIG_ENABLE_S 7 - #define WMI_RSRC_CFG_FLAG_IPHR_PAD_CONFIG_ENABLE_M 0x80 + #define WMI_RSRC_CFG_FLAG_QWRAP_MODE_ENABLE_S 8 + #define WMI_RSRC_CFG_FLAG_QWRAP_MODE_ENABLE_M 0x100 - #define WMI_RSRC_CFG_FLAG_QWRAP_MODE_ENABLE_S 8 - #define WMI_RSRC_CFG_FLAG_QWRAP_MODE_ENABLE_M 0x100 + #define WMI_RSRC_CFG_FLAG_MGMT_COMP_EVT_BUNDLE_SUPPORT_S 9 + #define WMI_RSRC_CFG_FLAG_MGMT_COMP_EVT_BUNDLE_SUPPORT_M 0x200 - #define WMI_RSRC_CFG_FLAG_MGMT_COMP_EVT_BUNDLE_SUPPORT_S 9 - #define WMI_RSRC_CFG_FLAG_MGMT_COMP_EVT_BUNDLE_SUPPORT_M 0x200 + #define WMI_RSRC_CFG_FLAG_TX_MSDU_ID_NEW_PARTITION_SUPPORT_S 10 + #define WMI_RSRC_CFG_FLAG_TX_MSDU_ID_NEW_PARTITION_SUPPORT_M 0x400 - A_UINT32 flag1; + A_UINT32 flag1; - /** @brief smart_ant_cap - Smart Antenna capabilities information - * @details - * 1 - Smart antenna is enabled. - * 0 - Smart antenna is disabled. - * In future this can contain smart antenna specifc capabilities. - */ - A_UINT32 smart_ant_cap; + /** @brief smart_ant_cap - Smart Antenna capabilities information + * @details + * 1 - Smart antenna is enabled. + * 0 - Smart antenna is disabled. + * In future this can contain smart antenna specifc capabilities. + */ + A_UINT32 smart_ant_cap; - /** - * User can configure the buffers allocated for each AC (BE, BK, VI, VO) - * during init - */ - A_UINT32 BK_Minfree; - A_UINT32 BE_Minfree; - A_UINT32 VI_Minfree; - A_UINT32 VO_Minfree; + /** + * User can configure the buffers allocated for each AC (BE, BK, VI, VO) + * during init + */ + A_UINT32 BK_Minfree; + A_UINT32 BE_Minfree; + A_UINT32 VI_Minfree; + A_UINT32 VO_Minfree; - /** - * @brief alloc_frag_desc_for_data_pkt . Controls data packet fragment - * descriptor memory allocation. - * 1 - Allocate fragment descriptor memory for data packet in firmware. - * If host wants to transmit data packet at its desired rate, - * this field must be set. - * 0 - Don't allocate fragment descriptor for data packet. - */ - A_UINT32 alloc_frag_desc_for_data_pkt; + /** + * @brief alloc_frag_desc_for_data_pkt . Controls data packet fragment + * descriptor memory allocation. + * 1 - Allocate fragment descriptor memory for data packet in firmware. + * If host wants to transmit data packet at its desired rate, + * this field must be set. + * 0 - Don't allocate fragment descriptor for data packet. + */ + A_UINT32 alloc_frag_desc_for_data_pkt; - /** how much space to allocate for NDP NS (neighbor solicitation) specs */ - A_UINT32 num_ns_ext_tuples_cfg; - - /** - * size (in bytes) of the buffer the FW shall allocate to store - * packet filtering instructions - */ - A_UINT32 bpf_instruction_size; - - /** - * Maximum no of BSSID based RX filters host would program - * Value 0 means host doesn't given any limit to FW. - */ - A_UINT32 max_bssid_rx_filters; - /** - * Use PDEV ID instead of MAC ID, added for backward compatibility with older host - * which is using MAC ID. 1 means PDEV ID, 0 means MAC ID. - */ - A_UINT32 use_pdev_id; + /* + * how much space to allocate for NDP NS (neighbor solicitation) + * specs + */ + A_UINT32 num_ns_ext_tuples_cfg; + /** + * size (in bytes) of the buffer the FW shall allocate to store + * packet filtering instructions + */ + A_UINT32 bpf_instruction_size; + /** + * Maximum no of BSSID based RX filters host would program + * Value 0 means host doesn't given any limit to FW. + */ + A_UINT32 max_bssid_rx_filters; + /** + * Use PDEV ID instead of MAC ID, added for backward compatibility with + * older host which is using MAC ID. 1 means PDEV ID, 0 means MAC ID. + */ + A_UINT32 use_pdev_id; } wmi_resource_config; #define WMI_RSRC_CFG_FLAG_SET(word32, flag, value) \ - do { \ - (word32) &= ~WMI_RSRC_CFG_FLAG_ ## flag ## _M; \ - (word32) |= ((value) << WMI_RSRC_CFG_FLAG_ ## flag ## _S) & \ - WMI_RSRC_CFG_FLAG_ ## flag ## _M; \ - } while (0) + do { \ + (word32) &= ~WMI_RSRC_CFG_FLAG_ ## flag ## _M; \ + (word32) |= ((value) << WMI_RSRC_CFG_FLAG_ ## flag ## _S) & \ + WMI_RSRC_CFG_FLAG_ ## flag ## _M; \ + } while (0) #define WMI_RSRC_CFG_FLAG_GET(word32, flag) \ - (((word32) & WMI_RSRC_CFG_FLAG_ ## flag ## _M) >> \ - WMI_RSRC_CFG_FLAG_ ## flag ## _S) + (((word32) & WMI_RSRC_CFG_FLAG_ ## flag ## _M) >> \ + WMI_RSRC_CFG_FLAG_ ## flag ## _S) #define WMI_RSRC_CFG_FLAG_WOW_IGN_PCIE_RST_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), WOW_IGN_PCIE_RST, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), WOW_IGN_PCIE_RST, (value)) #define WMI_RSRC_CFG_FLAG_WOW_IGN_PCIE_RST_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), WOW_IGN_PCIE_RST) + WMI_RSRC_CFG_FLAG_GET((word32), WOW_IGN_PCIE_RST) #define WMI_RSRC_CFG_FLAG_LTEU_SUPPORT_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), LTEU_SUPPORT, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), LTEU_SUPPORT, (value)) #define WMI_RSRC_CFG_FLAG_LTEU_SUPPORT_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), LTEU_SUPPORT) + WMI_RSRC_CFG_FLAG_GET((word32), LTEU_SUPPORT) #define WMI_RSRC_CFG_FLAG_COEX_GPIO_SUPPORT_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), COEX_GPIO_SUPPORT, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), COEX_GPIO_SUPPORT, (value)) #define WMI_RSRC_CFG_FLAG_COEX_GPIO_SUPPORT_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), COEX_GPIO_SUPPORT) + WMI_RSRC_CFG_FLAG_GET((word32), COEX_GPIO_SUPPORT) #define WMI_RSRC_CFG_FLAG_AUX_RADIO_SPECTRAL_INTF_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), AUX_RADIO_SPECTRAL_INTF, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), AUX_RADIO_SPECTRAL_INTF, (value)) #define WMI_RSRC_CFG_FLAG_AUX_RADIO_SPECTRAL_INTF_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), AUX_RADIO_SPECTRAL_INTF) + WMI_RSRC_CFG_FLAG_GET((word32), AUX_RADIO_SPECTRAL_INTF) #define WMI_RSRC_CFG_FLAG_AUX_RADIO_CHAN_LOAD_INTF_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), AUX_RADIO_CHAN_LOAD_INTF, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), AUX_RADIO_CHAN_LOAD_INTF, (value)) #define WMI_RSRC_CFG_FLAG_AUX_RADIO_CHAN_LOAD_INTF_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), AUX_RADIO_CHAN_LOAD_INTF) + WMI_RSRC_CFG_FLAG_GET((word32), AUX_RADIO_CHAN_LOAD_INTF) #define WMI_RSRC_CFG_FLAG_BSS_CHANNEL_INFO_64_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), BSS_CHANNEL_INFO_64, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), BSS_CHANNEL_INFO_64, (value)) #define WMI_RSRC_CFG_FLAG_BSS_CHANNEL_INFO_64_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), BSS_CHANNEL_INFO_64) + WMI_RSRC_CFG_FLAG_GET((word32), BSS_CHANNEL_INFO_64) #define WMI_RSRC_CFG_FLAG_ATF_CONFIG_ENABLE_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), ATF_CONFIG_ENABLE, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), ATF_CONFIG_ENABLE, (value)) #define WMI_RSRC_CFG_FLAG_ATF_CONFIG_ENABLE_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), ATF_CONFIG_ENABLE) + WMI_RSRC_CFG_FLAG_GET((word32), ATF_CONFIG_ENABLE) #define WMI_RSRC_CFG_FLAG_IPHR_PAD_CONFIG_ENABLE_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), IPHR_PAD_CONFIG_ENABLE, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), IPHR_PAD_CONFIG_ENABLE, (value)) #define WMI_RSRC_CFG_FLAG_IPHR_PAD_CONFIG_ENABLE_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), IPHR_PAD_CONFIG_ENABLE) + WMI_RSRC_CFG_FLAG_GET((word32), IPHR_PAD_CONFIG_ENABLE) #define WMI_RSRC_CFG_FLAG_QWRAP_MODE_ENABLE_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), QWRAP_MODE_ENABLE, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), QWRAP_MODE_ENABLE, (value)) #define WMI_RSRC_CFG_FLAG_QWRAP_MODE_ENABLE_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), QWRAP_MODE_ENABLE) + WMI_RSRC_CFG_FLAG_GET((word32), QWRAP_MODE_ENABLE) #define WMI_RSRC_CFG_FLAG_MGMT_COMP_EVT_BUNDLE_SUPPORT_SET(word32, value) \ - WMI_RSRC_CFG_FLAG_SET((word32), MGMT_COMP_EVT_BUNDLE_SUPPORT, (value)) + WMI_RSRC_CFG_FLAG_SET((word32), MGMT_COMP_EVT_BUNDLE_SUPPORT, (value)) #define WMI_RSRC_CFG_FLAG_MGMT_COMP_EVT_BUNDLE_SUPPORT_GET(word32) \ - WMI_RSRC_CFG_FLAG_GET((word32), MGMT_COMP_EVT_BUNDLE_SUPPORT) + WMI_RSRC_CFG_FLAG_GET((word32), MGMT_COMP_EVT_BUNDLE_SUPPORT) + +#define WMI_RSRC_CFG_FLAG_TX_MSDU_ID_NEW_PARTITION_SUPPORT_SET(word32, value) \ + WMI_RSRC_CFG_FLAG_SET((word32), \ + TX_MSDU_ID_NEW_PARTITION_SUPPORT, (value)) +#define WMI_RSRC_CFG_FLAG_TX_MSDU_ID_NEW_PARTITION_SUPPORT_GET(word32) \ + WMI_RSRC_CFG_FLAG_GET((word32), TX_MSDU_ID_NEW_PARTITION_SUPPORT) typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param */ - /** The following indicate the WMI versions to be supported by - * the host driver. Note that the host driver decide to - * "downgrade" its WMI version support and this may not be the - * native version of the host driver. */ - wmi_abi_version host_abi_vers; + /** The following indicate the WMI versions to be supported by + * the host driver. Note that the host driver decide to + * "downgrade" its WMI version support and this may not be the + * native version of the host driver. */ + wmi_abi_version host_abi_vers; - A_UINT32 num_host_mem_chunks; /** size of array host_mem_chunks[] */ -/* The TLVs for resource_config, host_mem_chunks[], and hw_mode_config will follow. - * wmi_resource_config resource_config; - * wlan_host_memory_chunk host_mem_chunks[]; - * wmi_pdev_set_hw_mode_cmd_fixed_param hw_mode_config; - * Note that the hw_mode_config, in spite of its "pdev" name, - * applies to the entire target rather than for a single pdev - * within the target. - * To avoid specifying a HW mode for the target, the host should - * fill hw_mode_config's fields with 0x0. - */ + A_UINT32 num_host_mem_chunks; + /** size of array host_mem_chunks[] */ + /* The TLVs for resource_config, host_mem_chunks[], and + * hw_mode_config will follow. + * wmi_resource_config resource_config; + * wlan_host_memory_chunk host_mem_chunks[]; + * wmi_pdev_set_hw_mode_cmd_fixed_param hw_mode_config; + * Note that the hw_mode_config, in spite of its "pdev" name, + * applies to the entire target rather than for a single pdev + * within the target. + * To avoid specifying a HW mode for the target, the host should + * fill hw_mode_config's fields with 0x0. + */ } wmi_init_cmd_fixed_param; @@ -2463,63 +2574,68 @@ typedef struct { * TLV for channel list */ typedef struct { - /** WMI_CHAN_LIST_TAG */ - A_UINT32 tag; - /** # of channels to scan */ - A_UINT32 num_chan; - /** channels in Mhz */ - A_UINT32 channel_list[1]; + /** WMI_CHAN_LIST_TAG */ + A_UINT32 tag; + /** # of channels to scan */ + A_UINT32 num_chan; + /** channels in Mhz */ + A_UINT32 channel_list[1]; } wmi_chan_list; /** * TLV for bssid list */ typedef struct { - /** WMI_BSSID_LIST_TAG */ - A_UINT32 tag; - /** number of bssids */ - A_UINT32 num_bssid; - /** bssid list */ - wmi_mac_addr bssid_list[1]; + /** WMI_BSSID_LIST_TAG */ + A_UINT32 tag; + /** number of bssids */ + A_UINT32 num_bssid; + /** bssid list */ + wmi_mac_addr bssid_list[1]; } wmi_bssid_list; /** * TLV for ie data. */ typedef struct { - /** WMI_IE_TAG */ - A_UINT32 tag; - /** number of bytes in ie data */ - A_UINT32 ie_len; - /** ie data array (ie_len adjusted to number of words (ie_len + 4)/4) */ - A_UINT32 ie_data[1]; + /** WMI_IE_TAG */ + A_UINT32 tag; + /** number of bytes in ie data */ + A_UINT32 ie_len; + /** ie data array (ie_len adjusted to number of words (ie_len + 4)/4 ) */ + A_UINT32 ie_data[1]; } wmi_ie_data; /** * TLV used for length/buffer */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tlv_buf_len_param */ - A_UINT32 buf_len; /** Length of buf */ - /** - * Following this structure is the TLV byte stream of buf of length buf_len: - * A_UINT8 buf[]; - * - */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_tlv_buf_len_param + */ + A_UINT32 tlv_header; + A_UINT32 buf_len; /** Length of buf */ + /** + * Following this structure is the TLV byte stream of buf + * of length buf_len: + * A_UINT8 buf[]; + * + */ } wmi_tlv_buf_len_param; typedef struct { - /** Len of the SSID */ - A_UINT32 ssid_len; - /** SSID */ - A_UINT32 ssid[8]; + /** Len of the SSID */ + A_UINT32 ssid_len; + /** SSID */ + A_UINT32 ssid[8]; } wmi_ssid; typedef struct { - /** WMI_SSID_LIST_TAG */ - A_UINT32 tag; - A_UINT32 num_ssids; - wmi_ssid ssids[1]; + /** WMI_SSID_LIST_TAG */ + A_UINT32 tag; + A_UINT32 num_ssids; + wmi_ssid ssids[1]; } wmi_ssid_list; /* prefix used by scan requestor ids on the host */ @@ -2533,68 +2649,68 @@ typedef struct { #define WLAN_SCAN_PARAMS_MAX_IE_LEN 512 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */ - /** Scan ID */ - A_UINT32 scan_id; - /** Scan requestor ID */ - A_UINT32 scan_req_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** Scan Priority, input to scan scheduler */ - A_UINT32 scan_priority; - /** Scan events subscription */ - A_UINT32 notify_scan_events; - /** dwell time in msec on active channels */ - A_UINT32 dwell_time_active; - /** dwell time in msec on passive channels */ - A_UINT32 dwell_time_passive; - /** min time in msec on the BSS channel,only valid if atleast one VDEV is active*/ - A_UINT32 min_rest_time; - /** max rest time in msec on the BSS channel,only valid if at least one VDEV is active*/ - /** the scanner will rest on the bss channel at least min_rest_time. after min_rest_time the scanner - * will start checking for tx/rx activity on all VDEVs. if there is no activity the scanner will - * switch to off channel. if there is activity the scanner will let the radio on the bss channel - * until max_rest_time expires.at max_rest_time scanner will switch to off channel - * irrespective of activity. activity is determined by the idle_time parameter. - */ - A_UINT32 max_rest_time; - /** time before sending next set of probe requests. - * The scanner keeps repeating probe requests transmission with period specified by repeat_probe_time. - * The number of probe requests specified depends on the ssid_list and bssid_list - */ - A_UINT32 repeat_probe_time; - /** time in msec between 2 consequetive probe requests with in a set. */ - A_UINT32 probe_spacing_time; - /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity */ - A_UINT32 idle_time; - /** maximum time in msec allowed for scan */ - A_UINT32 max_scan_time; - /** delay in msec before sending first probe request after switching to a channel */ - A_UINT32 probe_delay; - /** Scan control flags */ - A_UINT32 scan_ctrl_flags; - /** Burst duration time in msec*/ - A_UINT32 burst_duration; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */ + /** Scan ID */ + A_UINT32 scan_id; + /** Scan requestor ID */ + A_UINT32 scan_req_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** Scan Priority, input to scan scheduler */ + A_UINT32 scan_priority; + /** Scan events subscription */ + A_UINT32 notify_scan_events; + /** dwell time in msec on active channels */ + A_UINT32 dwell_time_active; + /** dwell time in msec on passive channels */ + A_UINT32 dwell_time_passive; + /** min time in msec on the BSS channel,only valid if atleast one VDEV is active*/ + A_UINT32 min_rest_time; + /** max rest time in msec on the BSS channel,only valid if at least one VDEV is active*/ + /** the scanner will rest on the bss channel at least min_rest_time. after min_rest_time the scanner + * will start checking for tx/rx activity on all VDEVs. if there is no activity the scanner will + * switch to off channel. if there is activity the scanner will let the radio on the bss channel + * until max_rest_time expires.at max_rest_time scanner will switch to off channel + * irrespective of activity. activity is determined by the idle_time parameter. + */ + A_UINT32 max_rest_time; + /** time before sending next set of probe requests. + * The scanner keeps repeating probe requests transmission with period specified by repeat_probe_time. + * The number of probe requests specified depends on the ssid_list and bssid_list + */ + A_UINT32 repeat_probe_time; + /** time in msec between 2 consequetive probe requests with in a set. */ + A_UINT32 probe_spacing_time; + /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity */ + A_UINT32 idle_time; + /** maximum time in msec allowed for scan */ + A_UINT32 max_scan_time; + /** delay in msec before sending first probe request after switching to a channel */ + A_UINT32 probe_delay; + /** Scan control flags */ + A_UINT32 scan_ctrl_flags; + /** Burst duration time in msec*/ + A_UINT32 burst_duration; - /** # if channels to scan. In the TLV channel_list[] */ - A_UINT32 num_chan; - /** number of bssids. In the TLV bssid_list[] */ - A_UINT32 num_bssid; - /** number of ssid. In the TLV ssid_list[] */ - A_UINT32 num_ssids; - /** number of bytes in ie data. In the TLV ie_data[]. Max len is defined by WLAN_SCAN_PARAMS_MAX_IE_LEN */ - A_UINT32 ie_len; - /** Max number of probes to be sent */ - A_UINT32 n_probes; + /** # if channels to scan. In the TLV channel_list[] */ + A_UINT32 num_chan; + /** number of bssids. In the TLV bssid_list[] */ + A_UINT32 num_bssid; + /** number of ssid. In the TLV ssid_list[] */ + A_UINT32 num_ssids; + /** number of bytes in ie data. In the TLV ie_data[]. Max len is defined by WLAN_SCAN_PARAMS_MAX_IE_LEN */ + A_UINT32 ie_len; + /** Max number of probes to be sent */ + A_UINT32 n_probes; -/** - * TLV (tag length value) parameters follow the scan_cmd - * structure. The TLV's are: - * A_UINT32 channel_list[]; - * wmi_ssid ssid_list[]; - * wmi_mac_addr bssid_list[]; - * A_UINT8 ie_data[]; - */ + /** + * TLV (tag length value ) parameters follow the scan_cmd + * structure. The TLV's are: + * A_UINT32 channel_list[]; + * wmi_ssid ssid_list[]; + * wmi_mac_addr bssid_list[]; + * A_UINT8 ie_data[]; + */ } wmi_start_scan_cmd_fixed_param; /** @@ -2618,7 +2734,7 @@ typedef struct { /**When set, certain errors are ignored and scan continues. * Different FW scan engine may use its own logic to decide what errors to ignore*/ #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 -/** Enable promiscous mode for CCXv4 */ +/** Enable promiscous mode for ese */ #define WMI_SCAN_FILTER_PROMISCOUS 0x100 /** allow to send probe req on DFS channel */ #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 @@ -2637,7 +2753,7 @@ typedef struct { /** allow capture ppdu with phy errrors */ #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 /** always do passive scan on passive channels */ -#define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 +#define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x1000 /** set HALF (10MHz) rate support */ #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 /** set Quarter (5MHz) rate support */ @@ -2648,21 +2764,21 @@ typedef struct { #define WMI_SCAN_DWELL_MODE_SHIFT 21 typedef enum { - WMI_SCAN_DWELL_MODE_DEFAULT = 0, - WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, - WMI_SCAN_DWELL_MODE_MODERATE = 2, - WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, - WMI_SCAN_DWELL_MODE_STATIC = 4, + WMI_SCAN_DWELL_MODE_DEFAULT = 0, + WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, + WMI_SCAN_DWELL_MODE_MODERATE = 2, + WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, + WMI_SCAN_DWELL_MODE_STATIC = 4, } WMI_SCAN_DWELL_MODE; #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \ - do { \ - (flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ - WMI_SCAN_DWELL_MODE_MASK); \ - } while (0) + do { \ + (flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ + WMI_SCAN_DWELL_MODE_MASK); \ + } while (0) #define WMI_SCAN_GET_DWELL_MODE(flag) \ - (((flag) & WMI_SCAN_DWELL_MODE_MASK) >> WMI_SCAN_DWELL_MODE_SHIFT) + (((flag) & WMI_SCAN_DWELL_MODE_MASK) >> WMI_SCAN_DWELL_MODE_SHIFT) /** WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK */ #define WMI_SCAN_CLASS_MASK 0xFF000000 @@ -2679,36 +2795,36 @@ typedef enum { #define WMI_SCAN_STOP_ALL 0x04000000 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */ - /** requestor requesting cancel */ - A_UINT32 requestor; - /** Scan ID */ - A_UINT32 scan_id; - /** - * Req Type - * req_type should be WMI_SCAN_STOP_ONE, WMI_SCN_STOP_VAP_ALL or WMI_SCAN_STOP_ALL - * WMI_SCAN_STOP_ONE indicates to stop a specific scan with scan_id - * WMI_SCN_STOP_VAP_ALL indicates to stop all scan requests on a specific vDev with vdev_id - * WMI_SCAN_STOP_ALL indicates to stop all scan requests in both Scheduler's queue and Scan Engine - */ - A_UINT32 req_type; - /** - * vDev ID - * used when req_type equals to WMI_SCN_STOP_VAP_ALL, it indexed the vDev on which to stop the scan - */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */ + /** requestor requesting cancel */ + A_UINT32 requestor; + /** Scan ID */ + A_UINT32 scan_id; + /** + * Req Type + * req_type should be WMI_SCAN_STOP_ONE, WMI_SCN_STOP_VAP_ALL or WMI_SCAN_STOP_ALL + * WMI_SCAN_STOP_ONE indicates to stop a specific scan with scan_id + * WMI_SCN_STOP_VAP_ALL indicates to stop all scan requests on a specific vDev with vdev_id + * WMI_SCAN_STOP_ALL indicates to stop all scan requests in both Scheduler's queue and Scan Engine + */ + A_UINT32 req_type; + /** + * vDev ID + * used when req_type equals to WMI_SCN_STOP_VAP_ALL, it indexed the vDev on which to stop the scan + */ + A_UINT32 vdev_id; } wmi_stop_scan_cmd_fixed_param; - -#define MAX_NUM_CHAN_PER_WMI_CMD 58 /* each WMI cmd can hold 58 channel entries at most */ +#define MAX_NUM_CHAN_PER_WMI_CMD 58 /* each WMI cmd can hold 58 channel entries at most */ #define APPEND_TO_EXISTING_CHAN_LIST 1 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param */ - A_UINT32 num_scan_chans; /** no of elements in chan_info[] */ - A_UINT32 flags; /* Flags used to control the behavior of channel list update on target side */ -/** Followed by the variable length TLV chan_info: - * wmi_channel chan_info[] */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param */ + A_UINT32 num_scan_chans; + /** no of elements in chan_info[] */ + A_UINT32 flags; /* Flags used to control the behavior of channel list update on target side */ + /** Followed by the variable length TLV chan_info: + * wmi_channel chan_info[] */ } wmi_scan_chan_list_cmd_fixed_param; /* @@ -2716,13 +2832,13 @@ typedef struct { */ /* NOTE: WLAN SCAN_PRIORITY_COUNT can't be changed without breaking the compatibility */ typedef enum { - WMI_SCAN_PRIORITY_VERY_LOW = 0, - WMI_SCAN_PRIORITY_LOW, - WMI_SCAN_PRIORITY_MEDIUM, - WMI_SCAN_PRIORITY_HIGH, - WMI_SCAN_PRIORITY_VERY_HIGH, + WMI_SCAN_PRIORITY_VERY_LOW = 0, + WMI_SCAN_PRIORITY_LOW, + WMI_SCAN_PRIORITY_MEDIUM, + WMI_SCAN_PRIORITY_HIGH, + WMI_SCAN_PRIORITY_VERY_HIGH, - WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ + WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ } wmi_scan_priority; /* Five Levels for Requested Priority */ @@ -2735,19 +2851,19 @@ typedef A_UINT32 WLAN_PRIORITY_MAPPING[WMI_SCAN_PRIORITY_COUNT]; * we will generate the new WLAN_M_STA table with modified P2P Client Entry but keep STA entry intact */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_sch_priority_table_cmd_fixed_param */ - /** - * used as an index to find the proper table for a specific vdev type in default_scan_priority_mapping_table - * vdev_type should be one of enum in WLAN_OPMODE which inculdes WLAN_M_IBSS, WLAN_M_STA, WLAN_M_AP and WLAN_M_MONITOR currently - */ - A_UINT32 vdev_type; - /** - * number of rows in mapping_table for a specific vdev - * for WLAN_M_STA type, there are 3 entries in the table (refer to default_scan_priority_mapping_table definition) - */ - A_UINT32 number_rows; -/** mapping_table for a specific vdev follows this TLV - * WLAN_PRIORITY_MAPPING mapping_table[]; */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_sch_priority_table_cmd_fixed_param */ + /** + * used as an index to find the proper table for a specific vdev type in default_scan_priority_mapping_table + * vdev_type should be one of enum in WLAN_OPMODE which inculdes WLAN_M_IBSS, WLAN_M_STA, WLAN_M_AP and WLAN_M_MONITOR currently + */ + A_UINT32 vdev_type; + /** + * number of rows in mapping_table for a specific vdev + * for WLAN_M_STA type, there are 3 entries in the table (refer to default_scan_priority_mapping_table definition) + */ + A_UINT32 number_rows; + /** mapping_table for a specific vdev follows this TLV + * WLAN_PRIORITY_MAPPING mapping_table[]; */ } wmi_scan_sch_priority_table_cmd_fixed_param; /** update flags */ @@ -2756,98 +2872,98 @@ typedef struct { #define WMI_SCAN_UPDATE_SCAN_MAX_REST_TIME 0x4 typedef struct { - A_UINT32 tlv_header; - /** requestor requesting update scan request */ - A_UINT32 requestor; - /** Scan ID of the scan request that need to be update */ - A_UINT32 scan_id; - /** update flags, indicating which of the following fields are valid and need to be updated*/ - A_UINT32 scan_update_flags; - /** scan priority. Only valid if WMI_SCAN_UPDATE_SCAN_PRIORITY flag is set in scan_update_flag */ - A_UINT32 scan_priority; - /** min rest time. Only valid if WMI_SCAN_UPDATE_MIN_REST_TIME flag is set in scan_update_flag */ - A_UINT32 min_rest_time; - /** min rest time. Only valid if WMI_SCAN_UPDATE_MAX_REST_TIME flag is set in scan_update_flag */ - A_UINT32 max_rest_time; + A_UINT32 tlv_header; + /** requestor requesting update scan request */ + A_UINT32 requestor; + /** Scan ID of the scan request that need to be update */ + A_UINT32 scan_id; + /** update flags, indicating which of the following fields are valid and need to be updated*/ + A_UINT32 scan_update_flags; + /** scan priority. Only valid if WMI_SCAN_UPDATE_SCAN_PRIORITY flag is set in scan_update_flag */ + A_UINT32 scan_priority; + /** min rest time. Only valid if WMI_SCAN_UPDATE_MIN_REST_TIME flag is set in scan_update_flag */ + A_UINT32 min_rest_time; + /** min rest time. Only valid if WMI_SCAN_UPDATE_MAX_REST_TIME flag is set in scan_update_flag */ + A_UINT32 max_rest_time; } wmi_scan_update_request_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; - /** oui to be used in probe request frame when random mac addresss is - * requested part of scan parameters. this is applied to both FW internal scans and - * host initated scans. host can request for random mac address with - * WMI_SCAN_ADD_SPOOFED_MAC_IN_PROBE_REQ flag. */ - A_UINT32 prob_req_oui; + A_UINT32 tlv_header; + /** oui to be used in probe request frame when random mac addresss is + * requested part of scan parameters. this is applied to both FW internal scans and + * host initated scans. host can request for random mac address with + * WMI_SCAN_ADD_SPOOFED_MAC_IN_PROBE_REQ flag. */ + A_UINT32 prob_req_oui; } wmi_scan_prob_req_oui_cmd_fixed_param; enum wmi_scan_event_type { - WMI_SCAN_EVENT_STARTED = 0x1, - WMI_SCAN_EVENT_COMPLETED = 0x2, - WMI_SCAN_EVENT_BSS_CHANNEL = 0x4, - WMI_SCAN_EVENT_FOREIGN_CHANNEL = 0x8, - WMI_SCAN_EVENT_DEQUEUED = 0x10, /* scan request got dequeued */ - WMI_SCAN_EVENT_PREEMPTED = 0x20, /* preempted by other high priority scan */ - WMI_SCAN_EVENT_START_FAILED = 0x40, /* scan start failed */ - WMI_SCAN_EVENT_RESTARTED = 0x80, /* scan restarted */ - WMI_SCAN_EVENT_FOREIGN_CHANNEL_EXIT = 0x100, - WMI_SCAN_EVENT_SUSPENDED = 0x200, /* scan request is suspended */ - WMI_SCAN_EVENT_RESUMED = 0x400, /* scan request is resumed */ - WMI_SCAN_EVENT_MAX = 0x8000 + WMI_SCAN_EVENT_STARTED = 0x1, + WMI_SCAN_EVENT_COMPLETED = 0x2, + WMI_SCAN_EVENT_BSS_CHANNEL = 0x4, + WMI_SCAN_EVENT_FOREIGN_CHANNEL = 0x8, + WMI_SCAN_EVENT_DEQUEUED = 0x10, /* scan request got dequeued */ + WMI_SCAN_EVENT_PREEMPTED = 0x20, /* preempted by other high priority scan */ + WMI_SCAN_EVENT_START_FAILED = 0x40, /* scan start failed */ + WMI_SCAN_EVENT_RESTARTED = 0x80, /* scan restarted */ + WMI_SCAN_EVENT_FOREIGN_CHANNEL_EXIT = 0x100, + WMI_SCAN_EVENT_SUSPENDED = 0x200, /* scan request is suspended */ + WMI_SCAN_EVENT_RESUMED = 0x400, /* scan request is resumed */ + WMI_SCAN_EVENT_MAX = 0x8000 }; enum wmi_scan_completion_reason { - /** scan related events */ - WMI_SCAN_REASON_NONE = 0xFF, - WMI_SCAN_REASON_COMPLETED = 0, - WMI_SCAN_REASON_CANCELLED = 1, - WMI_SCAN_REASON_PREEMPTED = 2, - WMI_SCAN_REASON_TIMEDOUT = 3, - WMI_SCAN_REASON_INTERNAL_FAILURE = 4, /* This reason indication failures when performaing scan */ - WMI_SCAN_REASON_SUSPENDED = 5, - WMI_SCAN_REASON_MAX, + /** scan related events */ + WMI_SCAN_REASON_NONE = 0xFF, + WMI_SCAN_REASON_COMPLETED = 0, + WMI_SCAN_REASON_CANCELLED = 1, + WMI_SCAN_REASON_PREEMPTED = 2, + WMI_SCAN_REASON_TIMEDOUT = 3, + WMI_SCAN_REASON_INTERNAL_FAILURE = 4, /* This reason indication failures when performaing scan */ + WMI_SCAN_REASON_SUSPENDED = 5, + WMI_SCAN_REASON_MAX, }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_event_fixed_param */ - /** scan event (wmi_scan_event_type) */ - A_UINT32 event; - /** status of the scan completion event */ - A_UINT32 reason; - /** channel freq , only valid for FOREIGN channel event*/ - A_UINT32 channel_freq; - /**id of the requestor whose scan is in progress */ - A_UINT32 requestor; - /**id of the scan that is in progress */ - A_UINT32 scan_id; - /**id of VDEV that requested the scan */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_event_fixed_param */ + /** scan event (wmi_scan_event_type) */ + A_UINT32 event; + /** status of the scan completion event */ + A_UINT32 reason; + /** channel freq , only valid for FOREIGN channel event*/ + A_UINT32 channel_freq; + /**id of the requestor whose scan is in progress */ + A_UINT32 requestor; + /**id of the scan that is in progress */ + A_UINT32 scan_id; + /**id of VDEV that requested the scan */ + A_UINT32 vdev_id; } wmi_scan_event_fixed_param; /* WMI Diag event */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag is WMITLV_TAG_STRUC_wmi_diag_event_fixed_param */ - A_UINT32 time_stamp; /* Reference timestamp. diag frame contains diff value */ - A_UINT32 count; /* Number of diag frames added to current event */ - A_UINT32 dropped; - /* followed by WMITLV_TAG_ARRAY_BYTE */ + A_UINT32 tlv_header; /* TLV tag and len; tag is WMITLV_TAG_STRUC_wmi_diag_event_fixed_param */ + A_UINT32 time_stamp; /* Reference timestamp. diag frame contains diff value */ + A_UINT32 count; /* Number of diag frames added to current event */ + A_UINT32 dropped; + /* followed by WMITLV_TAG_ARRAY_BYTE */ } wmi_diag_event_fixed_param; /* -* If FW has multiple active channels due to MCC(multi channel concurrency), -* then these stats are combined stats for all the active channels. -*/ + * If FW has multiple active channels due to MCC(multi channel concurrency), + * then these stats are combined stats for all the active channels. + */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_update_whal_mib_stats_event_fixed_param */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_update_whal_mib_stats_event_fixed_param */ /** ack count, it is an incremental number, not accumulated number */ A_UINT32 ackRcvBad; /** bad rts count, it is an incremental number, not accumulated number */ - A_UINT32 rtsBad; + A_UINT32 rtsBad; /** good rts, it is an incremental number, not accumulated number */ - A_UINT32 rtsGood; + A_UINT32 rtsGood; /** fcs count, it is an incremental number, not accumulated number */ - A_UINT32 fcsBad; + A_UINT32 fcsBad; /** beacon count, it is an incremental number, not accumulated number */ - A_UINT32 noBeacons; + A_UINT32 noBeacons; } wmi_update_whal_mib_stats_event_fixed_param; /* @@ -2858,7 +2974,7 @@ typedef struct { * * This is in bytes. */ -#define WMI_MGMT_RX_HDR_HEADROOM (sizeof(wmi_comb_phyerr_rx_hdr) + WMI_TLV_HDR_SIZE + sizeof(wmi_single_phyerr_rx_hdr)) +#define WMI_MGMT_RX_HDR_HEADROOM sizeof(wmi_comb_phyerr_rx_hdr) + WMI_TLV_HDR_SIZE + sizeof(wmi_single_phyerr_rx_hdr) /** This event will be used for sending scan results * as well as rx mgmt frames to the host. The rx buffer @@ -2867,117 +2983,122 @@ typedef struct { * descriptor up to the host. */ /* ATH_MAX_ANTENNA value (4) can't be changed without breaking the compatibility */ -#define ATH_MAX_ANTENNA 4 /* To support beelinear, which is up to 4 chains */ +#define ATH_MAX_ANTENNA 4 /* To support beelinear, which is up to 4 chains */ /** flag indicating that the the mgmt frame (probe req/beacon) is received in the context of extscan performed by FW */ #define WMI_MGMT_RX_HDR_EXTSCAN 0x01 -/** flag indicating that the the mgmt frame (probe req/beacon) is received in the context of matched network by FW ENLO */ -#define WMI_MGMT_RX_HDR_ENLO 0x02 +/** + * flag indicating that the the mgmt frame (probe req/beacon) is received in + * the context of matched network by FW ENLO + */ +#define WMI_MGMT_RX_HDR_ENLO 0x02 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr */ - /** channel on which this frame is received. */ - A_UINT32 channel; - /** snr information used to cal rssi */ - A_UINT32 snr; - /** Rate kbps */ - A_UINT32 rate; - /** rx phy mode WLAN_PHY_MODE */ - A_UINT32 phy_mode; - /** length of the frame */ - A_UINT32 buf_len; - /** rx status */ - A_UINT32 status; - /** RSSI of PRI 20MHz for each chain. */ - A_UINT32 rssi_ctl[ATH_MAX_ANTENNA]; - /** information about the management frame e.g. can give a scan source for a scan result mgmt frame */ - A_UINT32 flags; - /** combined RSSI, i.e. the sum of the snr + noise floor (dBm units) */ - A_INT32 rssi; - /** delta between local TSF(TSF timestamp when frame was RXd) - * and remote TSF(TSF timestamp in the IE for mgmt frame - - * beacon,proberesp for e.g). If remote TSF is not available, - * delta set to 0. - * Although tsf_delta is stored as A_UINT32, it can be negative, - * and thus would need to be sign-extended if added to a value - * larger than 32 bits. - */ - A_UINT32 tsf_delta; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr */ + /** channel on which this frame is received. */ + A_UINT32 channel; + /** snr information used to cal rssi */ + A_UINT32 snr; + /** Rate kbps */ + A_UINT32 rate; + /** rx phy mode WLAN_PHY_MODE */ + A_UINT32 phy_mode; + /** length of the frame */ + A_UINT32 buf_len; + /** rx status */ + A_UINT32 status; + /** RSSI of PRI 20MHz for each chain. */ + A_UINT32 rssi_ctl[ATH_MAX_ANTENNA]; + /** information about the management frame e.g. can give a scan source for a scan result mgmt frame */ + A_UINT32 flags; + /** combined RSSI, i.e. the sum of the snr + noise floor (dBm units) */ + A_INT32 rssi; - /* The lower 32 bits of the TSF (rx_tsf_l32) is copied by FW from - * TSF timestamp in the RX MAC descriptor provided by HW. - */ - A_UINT32 rx_tsf_l32; + /** delta between local TSF(TSF timestamp when frame was RXd) + * and remote TSF(TSF timestamp in the IE for mgmt frame + * beacon,proberesp for e.g). If remote TSF is not available, + * delta set to 0. + * Although tsf_delta is stored as A_UINT32, it can be negative, + * and thus would need to be sign-extended if added to a value + * larger than 32 bits. + */ + A_UINT32 tsf_delta; + /* + * The lower 32 bits of the TSF (rx_tsf_l32) is copied by FW from + * TSF timestamp in the RX MAC descriptor provided by HW. + */ + A_UINT32 rx_tsf_l32; - /* The Upper 32 bits (rx_tsf_u32) is filled by reading the TSF register - * after the packet is received. - */ - A_UINT32 rx_tsf_u32; - -/* This TLV is followed by array of bytes: - * A_UINT8 bufp[]; <-- management frame buffer - */ + /* + *The Upper 32 bits (rx_tsf_u32) is filled by reading the TSF register + * after the packet is received. + */ + A_UINT32 rx_tsf_u32; + /* This TLV is followed by array of bytes: + * // management frame buffer + * A_UINT8 bufp[]; + */ } wmi_mgmt_rx_hdr; typedef struct { - /** TSF timestamp */ - A_UINT32 tsf_timestamp; + /** TSF timestamp */ + A_UINT32 tsf_timestamp; - /** - * Current freq1, freq2 - * - * [7:0]: freq1[lo] - * [15:8] : freq1[hi] - * [23:16]: freq2[lo] - * [31:24]: freq2[hi] - */ - A_UINT32 freq_info_1; + /** + * Current freq1, freq2 + * + * [7:0]: freq1[lo] + * [15:8] : freq1[hi] + * [23:16]: freq2[lo] + * [31:24]: freq2[hi] + */ + A_UINT32 freq_info_1; - /** - * Combined RSSI over all chains and channel width for this PHY error - * - * [7:0]: RSSI combined - * [15:8]: Channel width (MHz) - * [23:16]: PHY error code - * [24:16]: reserved (future use) - */ - A_UINT32 freq_info_2; + /** + * Combined RSSI over all chains and channel width for this PHY error + * + * [7:0]: RSSI combined + * [15:8]: Channel width (MHz) + * [23:16]: PHY error code + * [24:16]: reserved (future use) + */ + A_UINT32 freq_info_2; - /** - * RSSI on chain 0 through 3 - * - * This is formatted the same as the PPDU_START RX descriptor - * field: - * - * [7:0]: pri20 - * [15:8]: sec20 - * [23:16]: sec40 - * [31:24]: sec80 - */ - A_UINT32 rssi_chain0; - A_UINT32 rssi_chain1; - A_UINT32 rssi_chain2; - A_UINT32 rssi_chain3; + /** + * RSSI on chain 0 through 3 + * + * This is formatted the same as the PPDU_START RX descriptor + * field: + * + * [7:0]: pri20 + * [15:8]: sec20 + * [23:16]: sec40 + * [31:24]: sec80 + */ + A_UINT32 rssi_chain0; + A_UINT32 rssi_chain1; + A_UINT32 rssi_chain2; + A_UINT32 rssi_chain3; - /** - * Last calibrated NF value for chain 0 through 3 - * - * nf_list_1: - * - * + [15:0] - chain 0 - * + [31:16] - chain 1 - * - * nf_list_2: - * - * + [15:0] - chain 2 - * + [31:16] - chain 3 - */ - A_UINT32 nf_list_1; - A_UINT32 nf_list_2; + /** + * Last calibrated NF value for chain 0 through 3 + * + * nf_list_1: + * + * + [15:0] - chain 0 + * + [31:16] - chain 1 + * + * nf_list_2: + * + * + [15:0] - chain 2 + * + [31:16] - chain 3 + */ + A_UINT32 nf_list_1; + A_UINT32 nf_list_2; - /** Length of the frame */ - A_UINT32 buf_len; + /** Length of the frame */ + A_UINT32 buf_len; } wmi_single_phyerr_rx_hdr; #define WMI_UNIFIED_FREQINFO_1_LO 0x000000ff @@ -2993,19 +3114,19 @@ typedef struct { * Please keep in mind that these _SET macros break macro side effect * assumptions; don't be clever with them. */ -#define WMI_UNIFIED_FREQ_INFO_GET(hdr, f) \ - (WMI_F_MS((hdr)->freq_info_1, \ - WMI_UNIFIED_FREQINFO_##f##_LO) \ - | (WMI_F_MS((hdr)->freq_info_1, \ - WMI_UNIFIED_FREQINFO_##f##_HI) << 8)) +#define WMI_UNIFIED_FREQ_INFO_GET(hdr, f) \ + (WMI_F_MS((hdr)->freq_info_1, \ + WMI_UNIFIED_FREQINFO_ ## f ## _LO) \ + | (WMI_F_MS((hdr)->freq_info_1, \ + WMI_UNIFIED_FREQINFO_ ## f ## _HI) << 8)) -#define WMI_UNIFIED_FREQ_INFO_SET(hdr, f, v) \ - do { \ - WMI_F_RMW((hdr)->freq_info_1, (v) & 0xff, \ - WMI_UNIFIED_FREQINFO_##f##_LO); \ - WMI_F_RMW((hdr)->freq_info_1, ((v) >> 8) & 0xff, \ - WMI_UNIFIED_FREQINFO_##f##_HI); \ - } while (0) +#define WMI_UNIFIED_FREQ_INFO_SET(hdr, f, v) \ + do { \ + WMI_F_RMW((hdr)->freq_info_1, (v) & 0xff, \ + WMI_UNIFIED_FREQINFO_ ## f ## _LO); \ + WMI_F_RMW((hdr)->freq_info_1, ((v) >> 8) & 0xff, \ + WMI_UNIFIED_FREQINFO_ ## f ## _HI); \ + } while (0) #define WMI_UNIFIED_FREQINFO_2_RSSI_COMB 0x000000ff #define WMI_UNIFIED_FREQINFO_2_RSSI_COMB_S 0 @@ -3014,27 +3135,27 @@ typedef struct { #define WMI_UNIFIED_FREQINFO_2_PHYERRCODE 0x00ff0000 #define WMI_UNIFIED_FREQINFO_2_PHYERRCODE_S 16 -#define WMI_UNIFIED_RSSI_COMB_GET(hdr) \ - ((int8_t) (WMI_F_MS((hdr)->freq_info_2, \ - WMI_UNIFIED_FREQINFO_2_RSSI_COMB))) +#define WMI_UNIFIED_RSSI_COMB_GET(hdr) \ + ((int8_t) (WMI_F_MS((hdr)->freq_info_2, \ + WMI_UNIFIED_FREQINFO_2_RSSI_COMB))) -#define WMI_UNIFIED_RSSI_COMB_SET(hdr, v) \ - WMI_F_RMW((hdr)->freq_info_2, (v) & 0xff, \ - WMI_UNIFIED_FREQINFO_2_RSSI_COMB); +#define WMI_UNIFIED_RSSI_COMB_SET(hdr, v) \ + WMI_F_RMW((hdr)->freq_info_2, (v) & 0xff, \ + WMI_UNIFIED_FREQINFO_2_RSSI_COMB); -#define WMI_UNIFIED_CHWIDTH_GET(hdr) \ - WMI_F_MS((hdr)->freq_info_2, WMI_UNIFIED_FREQINFO_2_CHWIDTH) +#define WMI_UNIFIED_CHWIDTH_GET(hdr) \ + WMI_F_MS((hdr)->freq_info_2, WMI_UNIFIED_FREQINFO_2_CHWIDTH) -#define WMI_UNIFIED_CHWIDTH_SET(hdr, v) \ - WMI_F_RMW((hdr)->freq_info_2, (v) & 0xff, \ - WMI_UNIFIED_FREQINFO_2_CHWIDTH); +#define WMI_UNIFIED_CHWIDTH_SET(hdr, v) \ + WMI_F_RMW((hdr)->freq_info_2, (v) & 0xff, \ + WMI_UNIFIED_FREQINFO_2_CHWIDTH); -#define WMI_UNIFIED_PHYERRCODE_GET(hdr) \ - WMI_F_MS((hdr)->freq_info_2, WMI_UNIFIED_FREQINFO_2_PHYERRCODE) +#define WMI_UNIFIED_PHYERRCODE_GET(hdr) \ + WMI_F_MS((hdr)->freq_info_2, WMI_UNIFIED_FREQINFO_2_PHYERRCODE) -#define WMI_UNIFIED_PHYERRCODE_SET(hdr, v) \ - WMI_F_RMW((hdr)->freq_info_2, (v) & 0xff, \ - WMI_UNIFIED_FREQINFO_2_PHYERRCODE); +#define WMI_UNIFIED_PHYERRCODE_SET(hdr, v) \ + WMI_F_RMW((hdr)->freq_info_2, (v) & 0xff, \ + WMI_UNIFIED_FREQINFO_2_PHYERRCODE); #define WMI_UNIFIED_CHAIN_0 0x0000ffff #define WMI_UNIFIED_CHAIN_0_S 0 @@ -3050,13 +3171,13 @@ typedef struct { #define WMI_UNIFIED_CHAIN_2_FIELD nf_list_2 #define WMI_UNIFIED_CHAIN_3_FIELD nf_list_2 -#define WMI_UNIFIED_NF_CHAIN_GET(hdr, c) \ - ((int16_t) (WMI_F_MS((hdr)->WMI_UNIFIED_CHAIN_##c##_FIELD, \ - WMI_UNIFIED_CHAIN_##c))) +#define WMI_UNIFIED_NF_CHAIN_GET(hdr, c) \ + ((int16_t) (WMI_F_MS((hdr)->WMI_UNIFIED_CHAIN_ ## c ## _FIELD, \ + WMI_UNIFIED_CHAIN_ ## c))) -#define WMI_UNIFIED_NF_CHAIN_SET(hdr, c, nf) \ - WMI_F_RMW((hdr)->WMI_UNIFIED_CHAIN_##c##_FIELD, (nf) & 0xffff, \ - WMI_UNIFIED_CHAIN_##c); +#define WMI_UNIFIED_NF_CHAIN_SET(hdr, c, nf) \ + WMI_F_RMW((hdr)->WMI_UNIFIED_CHAIN_ ## c ## _FIELD, (nf) & 0xffff, \ + WMI_UNIFIED_CHAIN_ ## c); /* * For now, this matches what the underlying hardware is doing. @@ -3074,202 +3195,256 @@ typedef struct { #define WMI_UNIFIED_RSSI_CHAN_SEC80 0xff000000 #define WMI_UNIFIED_RSSI_CHAN_SEC80_S 24 -#define WMI_UNIFIED_RSSI_CHAN_SET(hdr, c, ch, rssi) \ - WMI_F_RMW((hdr)->rssi_chain##c, (rssi) & 0xff, \ - WMI_UNIFIED_RSSI_CHAN_##ch); +#define WMI_UNIFIED_RSSI_CHAN_SET(hdr, c, ch, rssi) \ + WMI_F_RMW((hdr)->rssi_chain ## c, (rssi) & 0xff, \ + WMI_UNIFIED_RSSI_CHAN_ ## ch); -#define WMI_UNIFIED_RSSI_CHAN_GET(hdr, c, ch) \ - ((int8_t) (WMI_F_MS((hdr)->rssi_chain##c, \ - WMI_UNIFIED_RSSI_CHAN_##ch))) +#define WMI_UNIFIED_RSSI_CHAN_GET(hdr, c, ch) \ + ((int8_t) (WMI_F_MS((hdr)->rssi_chain ## c, \ + WMI_UNIFIED_RSSI_CHAN_ ## ch))) typedef struct { - /** Phy error event header */ - wmi_single_phyerr_rx_hdr hdr; - /** frame buffer */ - A_UINT8 bufp[1]; + /** Phy error event header */ + wmi_single_phyerr_rx_hdr hdr; + /** frame buffer */ + A_UINT8 bufp[1]; } wmi_single_phyerr_rx_event; /* PHY ERROR MASK 0 */ /* bits 1:0 defined but not published */ -#define WMI_PHY_ERROR_MASK0_RADAR (1 << 2) +#define WMI_PHY_ERROR_MASK0_RADAR (1<<2) /* bits 23:3 defined but not published */ -#define WMI_PHY_ERROR_MASK0_FALSE_RADAR_EXT (1 << 24) +#define WMI_PHY_ERROR_MASK0_FALSE_RADAR_EXT (1<<24) /* bits 25:24 defined but not published */ -#define WMI_PHY_ERROR_MASK0_SPECTRAL_SCAN (1 << 26) +#define WMI_PHY_ERROR_MASK0_SPECTRAL_SCAN (1<<26) /* bits 31:27 defined but not published */ -/* PHY ERROR MASK 1 */ -/* bits 13:0 defined but not published */ -/* bits 31:14 reserved */ +/* PHY ERROR MASK 1 + * bits 13:0 defined but not published + * bits 31:14 reserved + */ -/* PHY ERROR MASK 2 */ -/* bits 31:0 reserved */ +/* PHY ERROR MASK 2 + * bits 31:0 reserved + */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr */ - /** Phy error phy error count */ - A_UINT32 num_phyerr_events; - A_UINT32 tsf_l32; - A_UINT32 tsf_u32; - A_UINT32 buf_len; - union { - A_UINT32 pmac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 rsPhyErrMask0; /* see WMI_PHY_ERROR_MASK0 */ - A_UINT32 rsPhyErrMask1; /* see WMI_PHY_ERROR_MASK1 */ - A_UINT32 rsPhyErrMask2; /* see WMI_PHY_ERROR_MASK2 */ -/* This TLV is followed by array of bytes: - * frame buffer - contains multiple payloads in the order: - * header - payload, header - payload... - * (The header is of type: wmi_single_phyerr_rx_hdr) - * A_UINT8 bufp[]; - */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_comb_phyerr_rx_hdr + */ + A_UINT32 tlv_header; + /** Phy error phy error count */ + A_UINT32 num_phyerr_events; + A_UINT32 tsf_l32; + A_UINT32 tsf_u32; + A_UINT32 buf_len; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 pmac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + A_UINT32 rsPhyErrMask0; /* see WMI_PHY_ERROR_MASK0 */ + A_UINT32 rsPhyErrMask1; /* see WMI_PHY_ERROR_MASK1 */ + A_UINT32 rsPhyErrMask2; /* see WMI_PHY_ERROR_MASK2 */ + + /* This TLV is followed by array of bytes: + * // frame buffer - contains multiple payloads in the order: + * // header - payload, header - payload... + * (The header is of type: wmi_single_phyerr_rx_hdr) + * A_UINT8 bufp[]; + */ } wmi_comb_phyerr_rx_hdr; /* WMI MGMT TX */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_tx_hdr */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** xmit rate */ - A_UINT32 tx_rate; - /** xmit power */ - A_UINT32 tx_power; - /** Buffer length in bytes */ - A_UINT32 buf_len; -/* This TLV is followed by array of bytes: - * A_UINT8 bufp[]; <-- management frame buffer - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_tx_hdr */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** xmit rate */ + A_UINT32 tx_rate; + /** xmit power */ + A_UINT32 tx_power; + /** Buffer length in bytes */ + A_UINT32 buf_len; + /* This TLV is followed by array of bytes: + * // management frame buffer + * A_UINT8 bufp[]; + */ } wmi_mgmt_tx_hdr; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 desc_id; /* echoed in tx_compl_event */ - A_UINT32 chanfreq; /* MHz units */ - A_UINT32 paddr_lo; - A_UINT32 paddr_hi; - A_UINT32 frame_len; - A_UINT32 buf_len; /** Buffer length in bytes */ -/* This TLV is followed by array of bytes: First 64 bytes of management frame - * A_UINT8 bufp[]; - */ + /* + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_mgmt_tx_send_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* echoed in tx_compl_event */ + A_UINT32 desc_id; + /* MHz units */ + A_UINT32 chanfreq; + A_UINT32 paddr_lo; + A_UINT32 paddr_hi; + A_UINT32 frame_len; + /* Buffer length in bytes */ + A_UINT32 buf_len; + /* + * This TLV is followed by array of bytes: + * First 64 bytes of management frame + * A_UINT8 bufp[]; + */ } wmi_mgmt_tx_send_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_echo_event_fixed_param */ - A_UINT32 value; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_echo_event_fixed_param */ + A_UINT32 value; } wmi_echo_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_echo_cmd_fixed_param */ - A_UINT32 value; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_echo_cmd_fixed_param */ + A_UINT32 value; } wmi_echo_cmd_fixed_param; - typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param */ - - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /** reg domain code */ - A_UINT32 reg_domain; - A_UINT32 reg_domain_2G; - A_UINT32 reg_domain_5G; - A_UINT32 conformance_test_limit_2G; - A_UINT32 conformance_test_limit_5G; - A_UINT32 dfs_domain; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /** reg domain code */ + A_UINT32 reg_domain; + A_UINT32 reg_domain_2G; + A_UINT32 reg_domain_5G; + A_UINT32 conformance_test_limit_2G; + A_UINT32 conformance_test_limit_5G; + A_UINT32 dfs_domain; } wmi_pdev_set_regdomain_cmd_fixed_param; typedef struct { - /** TRUE for scan start and flase for scan end */ - A_UINT32 scan_start; + /** true for scan start and flase for scan end */ + A_UINT32 scan_start; } wmi_pdev_scan_cmd; /* WMI support for setting ratemask in target */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_config_ratemask_fixed_param */ - A_UINT32 vdev_id; - /* 0 - cck/ofdm - * 1 - HT - * 2 - VHT */ - A_UINT32 type; + A_UINT32 tlv_header; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_config_ratemask_fixed_param + */ + A_UINT32 vdev_id; + /* + * 0 - cck/ofdm + * 1 - HT + * 2 - VHT */ + A_UINT32 type; - A_UINT32 mask_lower32; - A_UINT32 mask_higher32; + A_UINT32 mask_lower32; + A_UINT32 mask_higher32; } wmi_vdev_config_ratemask_cmd_fixed_param; /* nrp action - Filter Neighbor Rx Packets - add/remove filter */ enum { - WMI_FILTER_NRP_ACTION_ADD = 0x1, - WMI_FILTER_NRP_ACTION_REMOVE = 0x2, - WMI_FILTER_NRP_ACTION_GET_LIST = 0x3, + WMI_FILTER_NRP_ACTION_ADD = 0x1, + WMI_FILTER_NRP_ACTION_REMOVE = 0x2, + WMI_FILTER_NRP_ACTION_GET_LIST = 0x3, }; /* nrp - Neighbor Rx Packets */ /* nrp type - Filter Neighbor Rx Packets - ap/client addr */ enum { - WMI_FILTER_NRP_TYPE_AP_BSSID = 0x1, - WMI_FILTER_NRP_TYPE_STA_MACADDR = 0x2, + WMI_FILTER_NRP_TYPE_AP_BSSID = 0x1, + WMI_FILTER_NRP_TYPE_STA_MACADDR = 0x2, }; /* nrp flag - Filter Neighbor Rx Packets * (capture flag, 2 & 3 not initially supported) */ enum { - WMI_FILTER_NRP_CAPTURE_ONLY_RX_PACKETS = 0x1, - WMI_FILTER_NRP_CAPTURE_ONLY_TX_PACKETS = 0x2, - WMI_FILTER_NRP_CAPTURE_BOTH_TXRX_PACKETS = 0x3, + WMI_FILTER_NRP_CAPTURE_ONLY_RX_PACKETS = 0x1, + WMI_FILTER_NRP_CAPTURE_ONLY_TX_PACKETS = 0x2, + WMI_FILTER_NRP_CAPTURE_BOTH_TXRX_PACKETS = 0x3, }; +/* Filter for Neighbor Rx Packets */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param */ - A_UINT32 vdev_id; - /* AP Bssid or Client Mac-addr */ - wmi_mac_addr addr; - /* Add/Remove NRF Filter */ - A_UINT32 action; /* WMI_FILTER_NRP_ACTION enum */ - /* client/ap filter */ - A_UINT32 type; /* WMI_FILTER_NRP_TYPE enum */ - /* optional - tx/rx capture */ - A_UINT32 flag; /* WMI_FILTER_NRP_CAPTURE enum */ - /* BSSID index - index of the BSSID register */ - A_UINT32 bssid_idx; -} wmi_vdev_filter_nrp_config_cmd_fixed_param; /* Filter for Neighbor Rx Packets */ - + A_UINT32 tlv_header; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_filter_nrp_config_cmd_fixed_param + */ + A_UINT32 vdev_id; + /* AP Bssid or Client Mac-addr */ + wmi_mac_addr addr; + /* Add/Remove NRF Filter */ + A_UINT32 action; /* WMI_FILTER_NRP_ACTION enum */ + /* client/ap filter */ + A_UINT32 type; /* WMI_FILTER_NRP_TYPE enum */ + /* optional - tx/rx capture */ + A_UINT32 flag; /* WMI_FILTER_NRP_CAPTURE enum */ + /* BSSID index - index of the BSSID register */ + A_UINT32 bssid_idx; +} wmi_vdev_filter_nrp_config_cmd_fixed_param; /*Command to set/unset chip in quiet mode*/ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_quiet_cmd_fixed_param */ - A_UINT32 pdev_id; /** pdev_id for identifying the MAC, See macros starting with WMI_PDEV_ID_ for values. */ - A_UINT32 period; /*period in TUs*/ - A_UINT32 duration; /*duration in TUs*/ - A_UINT32 next_start; /*offset in TUs*/ - A_UINT32 enabled; /*enable/disable*/ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_quiet_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* + * pdev_id for identifying the MAC, See macros + * starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + A_UINT32 period; /*period in TUs */ + A_UINT32 duration; /*duration in TUs */ + A_UINT32 next_start; /*offset in TUs */ + A_UINT32 enabled; /*enable/disable */ } wmi_pdev_set_quiet_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_quiet_cmd_fixed_param */ - A_UINT32 vdev_id; /* Virtual interface ID */ - A_UINT32 period; /* period in TUs */ - A_UINT32 duration; /* duration in TUs */ - A_UINT32 next_start; /* offset in TUs */ - A_UINT32 enabled; /* enable/disable */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_set_quiet_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; /* Virtual interface ID */ + A_UINT32 period; /* period in TUs */ + A_UINT32 duration; /* duration in TUs */ + A_UINT32 next_start; /* offset in TUs */ + A_UINT32 enabled; /* enable/disable */ } wmi_vdev_set_quiet_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param */ - A_UINT32 vdev_id; /* vdev id indicating to which the vdev custom aggregation size will be applied. */ - A_UINT32 tx_aggr_size; /* Size for tx aggregation (max MPDUs per A-MPDU) for the vdev mentioned in vdev id */ - A_UINT32 rx_aggr_size; /* Size for rx aggregation (block ack window size limit) for the vdev mentioned in vdev id*/ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* + * vdev id indicating to which the vdev custom aggregation size + * will be applied. + */ + A_UINT32 vdev_id; + /* + * Size for tx aggregation (max MPDUs per A-MPDU) for the vdev + * mentioned in vdev id + */ + A_UINT32 tx_aggr_size; + /* + * Size for rx aggregation (block ack window size limit) for + * the vdev mentioned in vdev id + */ + A_UINT32 rx_aggr_size; } wmi_vdev_set_custom_aggr_size_cmd_fixed_param; /* @@ -3280,48 +3455,57 @@ typedef struct { * chains. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_green_ap_ps_enable_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - A_UINT32 enable; /*1:enable, 0:disable*/ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_green_ap_ps_enable_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + A_UINT32 enable; /*1:enable, 0:disable */ } wmi_pdev_green_ap_ps_enable_cmd_fixed_param; - #define MAX_HT_IE_LEN 32 /* DEPRECATED */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_ht_ie_cmd_fixed_param */ - A_UINT32 reserved0; /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ - A_UINT32 ie_len; /*length of the ht ie in the TLV ie_data[] */ - A_UINT32 tx_streams; /* Tx streams supported for this HT IE */ - A_UINT32 rx_streams; /* Rx streams supported for this HT IE */ -/** The TLV for the HT IE follows: - * A_UINT32 ie_data[]; - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_ht_ie_cmd_fixed_param */ + A_UINT32 reserved0; + /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ + A_UINT32 ie_len; /*length of the ht ie in the TLV ie_data[] */ + A_UINT32 tx_streams; /* Tx streams supported for this HT IE */ + A_UINT32 rx_streams; /* Rx streams supported for this HT IE */ + /** The TLV for the HT IE follows: + * A_UINT32 ie_data[]; + */ } wmi_pdev_set_ht_ie_cmd_fixed_param; #define MAX_VHT_IE_LEN 32 /* DEPRECATED */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_vht_ie_cmd_fixed_param */ - A_UINT32 reserved0; /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ - A_UINT32 ie_len; /*length of the vht ie in the TLV ie_data[] */ - A_UINT32 tx_streams; /* Tx streams supported for this HT IE */ - A_UINT32 rx_streams; /* Rx streams supported for this HT IE */ -/** The TLV for the VHT IE follows: - * A_UINT32 ie_data[]; - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_vht_ie_cmd_fixed_param */ + A_UINT32 reserved0; + /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ + A_UINT32 ie_len; /*length of the vht ie in the TLV ie_data[] */ + A_UINT32 tx_streams; /* Tx streams supported for this HT IE */ + A_UINT32 rx_streams; /* Rx streams supported for this HT IE */ + /** The TLV for the VHT IE follows: + * A_UINT32 ie_data[]; + */ } wmi_pdev_set_vht_ie_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - wmi_mac_addr base_macaddr; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + wmi_mac_addr base_macaddr; } wmi_pdev_set_base_macaddr_cmd_fixed_param; /* @@ -3330,26 +3514,26 @@ typedef struct { * by the firmware. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_spectral_configure_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 spectral_scan_count; - A_UINT32 spectral_scan_period; - A_UINT32 spectral_scan_priority; - A_UINT32 spectral_scan_fft_size; - A_UINT32 spectral_scan_gc_ena; - A_UINT32 spectral_scan_restart_ena; - A_UINT32 spectral_scan_noise_floor_ref; - A_UINT32 spectral_scan_init_delay; - A_UINT32 spectral_scan_nb_tone_thr; - A_UINT32 spectral_scan_str_bin_thr; - A_UINT32 spectral_scan_wb_rpt_mode; - A_UINT32 spectral_scan_rssi_rpt_mode; - A_UINT32 spectral_scan_rssi_thr; - A_UINT32 spectral_scan_pwr_format; - A_UINT32 spectral_scan_rpt_mode; - A_UINT32 spectral_scan_bin_scale; - A_UINT32 spectral_scan_dBm_adj; - A_UINT32 spectral_scan_chn_mask; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_spectral_configure_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 spectral_scan_count; + A_UINT32 spectral_scan_period; + A_UINT32 spectral_scan_priority; + A_UINT32 spectral_scan_fft_size; + A_UINT32 spectral_scan_gc_ena; + A_UINT32 spectral_scan_restart_ena; + A_UINT32 spectral_scan_noise_floor_ref; + A_UINT32 spectral_scan_init_delay; + A_UINT32 spectral_scan_nb_tone_thr; + A_UINT32 spectral_scan_str_bin_thr; + A_UINT32 spectral_scan_wb_rpt_mode; + A_UINT32 spectral_scan_rssi_rpt_mode; + A_UINT32 spectral_scan_rssi_thr; + A_UINT32 spectral_scan_pwr_format; + A_UINT32 spectral_scan_rpt_mode; + A_UINT32 spectral_scan_bin_scale; + A_UINT32 spectral_scan_dBm_adj; + A_UINT32 spectral_scan_chn_mask; } wmi_vdev_spectral_configure_cmd_fixed_param; /* @@ -3359,506 +3543,631 @@ typedef struct { * and multiple STA (eg p2p, tdls, multi-band STA) is possible. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_spectral_enable_cmd_fixed_param */ - A_UINT32 vdev_id; - /* 0 - ignore; 1 - trigger, 2 - clear trigger */ - A_UINT32 trigger_cmd; - /* 0 - ignore; 1 - enable, 2 - disable */ - A_UINT32 enable_cmd; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_spectral_enable_cmd_fixed_param */ + A_UINT32 vdev_id; + /* 0 - ignore; 1 - trigger, 2 - clear trigger */ + A_UINT32 trigger_cmd; + /* 0 - ignore; 1 - enable, 2 - disable */ + A_UINT32 enable_cmd; } wmi_vdev_spectral_enable_cmd_fixed_param; +/* information sub element id for QSBW, expected value is 0x02 */ +#define WMI_CSA_EVENT_QSBW_ISE_ID_MASK 0x000000FF +/* length of QSBW ISE data, expected value is 0x02 */ +#define WMI_CSA_EVENT_QSBW_ISE_LEN_MASK 0x0000FF00 +/* capabilities, 0x01 for 5MHz, 0x02 for 10MHz, 0x01|0x2 for both + * (see WMI_CSA_EVENT_QSBW_ISE bitmask defs) + */ +#define WMI_CSA_EVENT_QSBW_ISE_CAP_MASK 0x00FF0000 +/* notification from AP, 0x01 for 5MHz, 0x02 for 10MHz + * (see WMI_CSA_EVENT_QSBW_ISE bitmask defs) + */ +#define WMI_CSA_EVENT_QSBW_ISE_NOTIF_MASK 0xFF000000 + +#define WMI_CSA_EVENT_QSBW_ISE_ID 0x02 +#define WMI_CSA_EVENT_QSBW_ISE_LEN 0x02 + +#define WMI_CSA_EVENT_QSBW_ISE_5M_BITMASK 0x01 +#define WMI_CSA_EVENT_QSBW_ISE_10M_BITMASK 0x02 + +#define WMI_CSA_EVENT_QSBW_ISE_CAP_5M(qsbw_ise) \ + (((qsbw_ise) >> 16) & WMI_CSA_EVENT_QSBW_ISE_5M_BITMASK) +#define WMI_CSA_EVENT_QSBW_ISE_CAP_10M(qsbw_ise) \ + (((qsbw_ise) >> 16) & WMI_CSA_EVENT_QSBW_ISE_10M_BITMASK) +#define WMI_CSA_EVENT_QSBW_ISE_NOTIF_5M(qsbw_ise) \ + (((qsbw_ise) >> 24) & WMI_CSA_EVENT_QSBW_ISE_5M_BITMASK) +#define WMI_CSA_EVENT_QSBW_ISE_NOTIF_10M(qsbw_ise) \ + (((qsbw_ise) >> 24) & WMI_CSA_EVENT_QSBW_ISE_10M_BITMASK) + typedef enum { - WMI_CSA_IE_PRESENT = 0x00000001, - WMI_XCSA_IE_PRESENT = 0x00000002, - WMI_WBW_IE_PRESENT = 0x00000004, - WMI_CSWARP_IE_PRESENT = 0x00000008, + WMI_CSA_IE_PRESENT = 0x00000001, + WMI_XCSA_IE_PRESENT = 0x00000002, + WMI_WBW_IE_PRESENT = 0x00000004, + WMI_CSWARP_IE_PRESENT = 0x00000008, + WMI_QSBW_ISE_PRESENT = 0x00000010, } WMI_CSA_EVENT_IES_PRESENT_FLAG; /* wmi CSA receive event from beacon frame */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csa_event_fixed_param */ - A_UINT32 i_fc_dur; /* Bit 0-15: FC, Bit 16-31: DUR */ - wmi_mac_addr i_addr1; - wmi_mac_addr i_addr2; - /* NOTE: size of array of csa_ie[], xcsa_ie[], and wb_ie[] cannot be - * changed in the future without breaking WMI compatibility */ - A_UINT32 csa_ie[2]; - A_UINT32 xcsa_ie[2]; - A_UINT32 wb_ie[2]; - A_UINT32 cswarp_ie; - A_UINT32 ies_present_flag; /* WMI_CSA_EVENT_IES_PRESENT_FLAG */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csa_event_fixed_param */ + A_UINT32 i_fc_dur; +/* Bit 0-15: FC */ +/* Bit 16-31: DUR */ + wmi_mac_addr i_addr1; + wmi_mac_addr i_addr2; + /* NOTE: size of array of csa_ie[], xcsa_ie[], and wb_ie[] cannot be + * changed in the future without breaking WMI compatibility */ + A_UINT32 csa_ie[2]; + A_UINT32 xcsa_ie[2]; + A_UINT32 wb_ie[2]; + A_UINT32 cswarp_ie; + A_UINT32 ies_present_flag; /* WMI_CSA_EVENT_IES_PRESENT_FLAG */ + A_UINT32 qsbw_ise; } wmi_csa_event_fixed_param; typedef enum { - WAL_PEER_MCAST2UCAST_DISABLED = 0, - WAL_PEER_MCAST2UCAST_DROP_EMPTY = 1, /* Drop the frames if match is not found */ - WAL_PEER_MCAST2UCAST_MCAST_EMPTY = 2, /* Send as mcast if match is not found */ + WAL_PEER_MCAST2UCAST_DISABLED = 0, + /* Drop the frames if match is not found */ + WAL_PEER_MCAST2UCAST_DROP_EMPTY = 1, + /* Send as mcast if match is not found */ + WAL_PEER_MCAST2UCAST_MCAST_EMPTY = 2, } WMI_PEER_MCAST2UCAST_MODE; typedef enum { - /** TX chain mask */ - WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, - /** RX chain mask */ - WMI_PDEV_PARAM_RX_CHAIN_MASK, - /** TX power limit for 2G Radio */ - WMI_PDEV_PARAM_TXPOWER_LIMIT2G, - /** TX power limit for 5G Radio */ - WMI_PDEV_PARAM_TXPOWER_LIMIT5G, - /** TX power scale */ - WMI_PDEV_PARAM_TXPOWER_SCALE, - /** Beacon generation mode . 0: host, 1: target */ - WMI_PDEV_PARAM_BEACON_GEN_MODE, - /** Beacon generation mode . 0: staggered 1: bursted */ - WMI_PDEV_PARAM_BEACON_TX_MODE, - /** Resource manager off chan mode . - * 0: turn off off chan mode. 1: turn on offchan mode - */ - WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, - /** Protection mode 0: no protection 1:use CTS-to-self 2: use RTS/CTS */ - WMI_PDEV_PARAM_PROTECTION_MODE, - /** Dynamic bandwidth 0: disable 1: enable */ - WMI_PDEV_PARAM_DYNAMIC_BW, - /** Non aggregrate/ 11g sw retry threshold.0-disable */ - WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, - /** aggregrate sw retry threshold. 0-disable*/ - WMI_PDEV_PARAM_AGG_SW_RETRY_TH, - /** Station kickout threshold (non of consecutive failures).0-disable */ - WMI_PDEV_PARAM_STA_KICKOUT_TH, - /** Aggerate size scaling configuration per AC */ - WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, - /** LTR enable */ - WMI_PDEV_PARAM_LTR_ENABLE, - /** LTR latency for BE, in us */ - WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, - /** LTR latency for BK, in us */ - WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, - /** LTR latency for VI, in us */ - WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, - /** LTR latency for VO, in us */ - WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, - /** LTR AC latency timeout, in ms */ - WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, - /** LTR platform latency override, in us */ - WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, - /** LTR-M override, in us */ - WMI_PDEV_PARAM_LTR_RX_OVERRIDE, - /** Tx activity timeout for LTR, in us */ - WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, - /** L1SS state machine enable */ - WMI_PDEV_PARAM_L1SS_ENABLE, - /** Deep sleep state machine enable */ - WMI_PDEV_PARAM_DSLEEP_ENABLE, - /** RX buffering flush enable */ - WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, - /** RX buffering matermark */ - WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, - /** RX buffering timeout enable */ - WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, - /** RX buffering timeout value */ - WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, - /** pdev level stats update period in ms */ - WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, - /** vdev level stats update period in ms */ - WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, - /** peer level stats update period in ms */ - WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, - /** beacon filter status update period */ - WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, - /** QOS Mgmt frame protection MFP/PMF 0: disable, 1: enable */ - WMI_PDEV_PARAM_PMF_QOS, - /** Access category on which ARP frames are sent */ - WMI_PDEV_PARAM_ARP_AC_OVERRIDE, - /** DCS configuration */ - WMI_PDEV_PARAM_DCS, - /** Enable/Disable ANI on target */ - WMI_PDEV_PARAM_ANI_ENABLE, - /** configure the ANI polling period */ - WMI_PDEV_PARAM_ANI_POLL_PERIOD, - /** configure the ANI listening period */ - WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, - /** configure OFDM immunity level */ - WMI_PDEV_PARAM_ANI_OFDM_LEVEL, - /** configure CCK immunity level */ - WMI_PDEV_PARAM_ANI_CCK_LEVEL, - /** Enable/Disable CDD for 1x1 STAs in rate control module */ - WMI_PDEV_PARAM_DYNTXCHAIN, - /** Enable/Disable proxy STA */ - WMI_PDEV_PARAM_PROXY_STA, - /** Enable/Disable low power state when all VDEVs are inactive/idle. */ - WMI_PDEV_PARAM_IDLE_PS_CONFIG, - /** Enable/Disable power gating sleep */ - WMI_PDEV_PARAM_POWER_GATING_SLEEP, - /** Enable/Disable Rfkill */ - WMI_PDEV_PARAM_RFKILL_ENABLE, - /** Set Bursting DUR */ - WMI_PDEV_PARAM_BURST_DUR, - /** Set Bursting ENABLE */ - WMI_PDEV_PARAM_BURST_ENABLE, - /** HW rfkill config */ - WMI_PDEV_PARAM_HW_RFKILL_CONFIG, - /** Enable radio low power features */ - WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, - /** L1SS entry and residency time track */ - WMI_PDEV_PARAM_L1SS_TRACK, - /** set hyst at runtime, requirement from SS */ - WMI_PDEV_PARAM_HYST_EN, - /** Enable/ Disable POWER COLLAPSE */ - WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, - /** configure LED system state */ - WMI_PDEV_PARAM_LED_SYS_STATE, - /** Enable/Disable LED */ - WMI_PDEV_PARAM_LED_ENABLE, - /** set DIRECT AUDIO time latency */ - WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, /* DEPRECATED */ - /** set DIRECT AUDIO Feature ENABLE */ - WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, /* DEPRECATED */ - /** pdev level whal mib stats update enable */ - WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, - /** ht/vht info based on vdev */ - WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, - /** Set CTS channel BW for dynamic BW adjustment feature */ - WMI_PDEV_PARAM_CTS_CBW, - /** Set GPIO pin info used by WNTS */ - WMI_PDEV_PARAM_WNTS_CONFIG, - /** Enable/Disable hardware adaptive early rx feature */ - WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, - /** The minimum early rx duration, to ensure early rx duration is non-zero */ - WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, - /** Increasing/decreasing step used by hardware */ - WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, - /** The fixed early rx duration when adaptive early rx is disabled */ - WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, - /** Enable/Disable bmiss based adaptive beacon timeout feature */ - WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, - /** The minimum beacon timeout duration, to ensure beacon timeout duration is non-zero */ - WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, - /** Increasing/decreasing step used by hardware */ - WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, - /** The fixed beacon timeout duration when bmiss based adaptive beacon timeout is disabled */ - WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, - /** Enable/Disable Congestion Estimator based adaptive beacon timeout feature */ - WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, - /** combo value of ce_id, ce_threshold, ce_time, refer to WMI_CE_BTO_CE_ID_MASK */ - WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, - /** 2G TX chain mask */ - WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, - /** 2G RX chain mask */ - WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, - /** 5G TX chain mask */ - WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, - /** 5G RX chain mask */ - WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, - /* Set tx chain mask for CCK rates */ - WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, - /* Set tx chain mask for 1SS stream */ - WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, - /* Enable/Disable CTS2Self for P2P GO when Non-P2P Client is connected */ - WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, - /** TX power backoff in dB: tx power -= param value - * Host passes values(DB) to Halphy, Halphy reduces the power table by - * the values. Safety check will happen in Halphy - */ - WMI_PDEV_PARAM_TXPOWER_DECR_DB, - /** enable and disable aggregate burst along with duration */ - WMI_PDEV_PARAM_AGGR_BURST, - /** Set the global RX decap mode */ - WMI_PDEV_PARAM_RX_DECAP_MODE, - /** Enable/Disable Fast channel reset */ - WMI_PDEV_PARAM_FAST_CHANNEL_RESET, - /** Default antenna for Smart antenna */ - WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, - /** Set the user-specified antenna gain */ - WMI_PDEV_PARAM_ANTENNA_GAIN, - /** Set the user-specified RX filter */ - WMI_PDEV_PARAM_RX_FILTER, - /** configure the user-specified MCAST tid for managed mcast feature - * 0-15 is the valid range. 0xff will clear the tid setting */ - WMI_PDEV_SET_MCAST_TO_UCAST_TID, - /** Enable/Disable Proxy sta mode */ - WMI_PDEV_PARAM_PROXY_STA_MODE, - /** configure the mcast2ucast mode for the pdev->peer_mcast. - * See WMI_PEER_MCAST2UCAST_MODE for possible values */ - WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, - /** Sets the Mcast buffers for cloning, to support Mcast enhancement */ - WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, - /** Remove the Mcast buffers added by host */ - WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, - /** En/disable station power save state indication */ - WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, - /** Access category on which ARP frames are sent */ - WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, - /** allow or disallow interbss frame forwarding */ - WMI_PDEV_PARAM_BLOCK_INTERBSS, - /** Enable/Disable reset */ - WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, - /** Enable/Disable/Set MSDU_TTL in milliseconds. */ - WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, - /** Set global PPDU duration limit (usec). */ - WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, - /** set txbf sounding period of vap in milliseconds */ - WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, - /** Set promiscuous mode */ - WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, - /** Set burst mode */ - WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, - /** enable enhanced stats */ - WMI_PDEV_PARAM_EN_STATS, - /** Set mu-grouping policy */ - WMI_PDEV_PARAM_MU_GROUP_POLICY, - /** Channel Hopping Enable */ - WMI_PDEV_PARAM_NOISE_DETECTION, - /** Set Channel Hopping NF threshold in dBm */ - WMI_PDEV_PARAM_NOISE_THRESHOLD, - /** Set PAPRD policy */ - WMI_PDEV_PARAM_DPD_ENABLE, - /** Enable/disable mcast/bcast echo, used by ProxySTA */ - WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, - /** ATF enable/disable strict schedule */ - WMI_PDEV_PARAM_ATF_STRICT_SCH, - /** ATF set access category duration, B0-B29 duration, B30-B31: AC */ - WMI_PDEV_PARAM_ATF_SCHED_DURATION, - /** Default antenna polarization */ - WMI_PDEV_PARAM_ANT_PLZN, - /** Set mgmt retry limit */ - WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, - /** Set CCA sensitivity level in dBm */ - WMI_PDEV_PARAM_SENSITIVITY_LEVEL, - /** Set 2G positive and negative Tx power in 0.5dBm units */ - WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, - /** Set 5G positive and negative Tx power in 0.5dBm - * units */ - WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, - /** Enable/disble AMSDU for tids */ - WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, - /** Enable/disable AMPDU for tids */ - WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, - /** Set CCA threshold in dBm */ - WMI_PDEV_PARAM_CCA_THRESHOLD, - /** RTS Fixed rate setting */ - WMI_PDEV_PARAM_RTS_FIXED_RATE, - /** Pdev reset */ - WMI_PDEV_PARAM_PDEV_RESET, - /** wapi mbssid offset **/ - WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, - /** ARP DEBUG source address*/ - WMI_PDEV_PARAM_ARP_DBG_SRCADDR, - /** ARP DEBUG destination address*/ - WMI_PDEV_PARAM_ARP_DBG_DSTADDR, - /** ATF enable/disable obss noise scheduling */ - WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, - /** ATF obss noise scaling factor */ - WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, - /** - * TX power reduction scaling exponent - final tx power is the - * nominal tx power (A_MIN(reg_pow,ctl,etc..)) divided by - * 2^(scale exponent). For example: - * If this scale exponent is 0, the power is unchanged (divided by 2^0) - * If this factor is 1, the power is scaled down by 2^1, i.e. 3 dB - * If this factor is 2, the power is scaled down by 2^2, i.e. 6 dB - * If this factor is 3, the power is scaled down by 2^3, i.e. 9 dB - */ - WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, - /** ATF enabe/disabe dynamically */ - WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, - /** Set tx retry limit for control frames. 0 = disable, 31 = max */ - WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, - /** Set propagation delay for 2G / 5G band. - * The propagation delay is fundamentally a per-peer property, but - * the target may not support per-peer settings for ack timeouts. - * This pdev parameter allows the MAC-level ack timeout to be set to - * a value suitable for the worst-case propagation delay of any peer - * within that pdev. - * Units are microseconds. - */ - WMI_PDEV_PARAM_PROPAGATION_DELAY, - /** - * Host can enable/disable ANT DIV feature - * if it's been enabled in BDF - */ - WMI_PDEV_PARAM_ENA_ANT_DIV, - /** Host can force one chain to select a specific ANT */ - WMI_PDEV_PARAM_FORCE_CHAIN_ANT, - /** - * Start a cycle ANT self test periodically. - * In the test, the FW would select each ANT pair - * one by one, the cycle time could be configured - * via WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL - */ - WMI_PDEV_PARAM_ANT_DIV_SELFTEST, - /** - * Configure the cycle time of ANT self test, - * the unit is micro second. Per the timer - * limitation, too small value could be not so - * accurate. - */ - WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, - /** - * wlan stats observation period, the unit is millisecond. - * The value of 0 is used to turn off periodic stats report. - */ - WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, - /** - * Set tx_msdu_delay[] bin size to specify how many - * milliseconds each bin of the wmi_tx_stats.tx_msdu_delay[] - * histogram represents. - */ - WMI_PDEV_PARAM_TX_DELAY_BIN_SIZE_MS, - /** set wmi_tx_stats.tx_msdu_delay[] array size */ - WMI_PDEV_PARAM_TX_DELAY_ARRAY_SIZE, - /** set wmi_tx_stats.tx_mpdu_aggr[] array size */ - WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_SIZE, - /** set wmi_rx_stats.rx_mpdu_aggr[] array size */ - WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_SIZE, - + /** TX chain mask */ + WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, + /** RX chain mask */ + WMI_PDEV_PARAM_RX_CHAIN_MASK, + /** TX power limit for 2G Radio */ + WMI_PDEV_PARAM_TXPOWER_LIMIT2G, + /** TX power limit for 5G Radio */ + WMI_PDEV_PARAM_TXPOWER_LIMIT5G, + /** TX power scale */ + WMI_PDEV_PARAM_TXPOWER_SCALE, + /** Beacon generation mode . 0: host, 1: target */ + WMI_PDEV_PARAM_BEACON_GEN_MODE, + /** Beacon generation mode . 0: staggered 1: bursted */ + WMI_PDEV_PARAM_BEACON_TX_MODE, + /** Resource manager off chan mode . + * 0: turn off off chan mode. 1: turn on offchan mode + */ + WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, + /** Protection mode 0: no protection 1:use CTS-to-self 2: use RTS/CTS */ + WMI_PDEV_PARAM_PROTECTION_MODE, + /** Dynamic bandwidth 0: disable 1: enable */ + WMI_PDEV_PARAM_DYNAMIC_BW, + /** Non aggregrate/ 11g sw retry threshold.0-disable */ + WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, + /** aggregrate sw retry threshold. 0-disable*/ + WMI_PDEV_PARAM_AGG_SW_RETRY_TH, + /** Station kickout threshold (non of consecutive failures).0-disable */ + WMI_PDEV_PARAM_STA_KICKOUT_TH, + /** Aggerate size scaling configuration per AC */ + WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, + /** LTR enable */ + WMI_PDEV_PARAM_LTR_ENABLE, + /** LTR latency for BE, in us */ + WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, + /** LTR latency for BK, in us */ + WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, + /** LTR latency for VI, in us */ + WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, + /** LTR latency for VO, in us */ + WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, + /** LTR AC latency timeout, in ms */ + WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, + /** LTR platform latency override, in us */ + WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, + /** LTR-M override, in us */ + WMI_PDEV_PARAM_LTR_RX_OVERRIDE, + /** Tx activity timeout for LTR, in us */ + WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, + /** L1SS state machine enable */ + WMI_PDEV_PARAM_L1SS_ENABLE, + /** Deep sleep state machine enable */ + WMI_PDEV_PARAM_DSLEEP_ENABLE, + /** RX buffering flush enable */ + WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, + /** RX buffering matermark */ + WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, + /** RX buffering timeout enable */ + WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, + /** RX buffering timeout value */ + WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, + /** pdev level stats update period in ms */ + WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, + /** vdev level stats update period in ms */ + WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, + /** peer level stats update period in ms */ + WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, + /** beacon filter status update period */ + WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, + /** QOS Mgmt frame protection MFP/PMF 0: disable, 1: enable */ + WMI_PDEV_PARAM_PMF_QOS, + /** Access category on which ARP frames are sent */ + WMI_PDEV_PARAM_ARP_AC_OVERRIDE, + /** DCS configuration */ + WMI_PDEV_PARAM_DCS, + /** Enable/Disable ANI on target */ + WMI_PDEV_PARAM_ANI_ENABLE, + /** configure the ANI polling period */ + WMI_PDEV_PARAM_ANI_POLL_PERIOD, + /** configure the ANI listening period */ + WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, + /** configure OFDM immunity level */ + WMI_PDEV_PARAM_ANI_OFDM_LEVEL, + /** configure CCK immunity level */ + WMI_PDEV_PARAM_ANI_CCK_LEVEL, + /** Enable/Disable CDD for 1x1 STAs in rate control module */ + WMI_PDEV_PARAM_DYNTXCHAIN, + /** Enable/Disable proxy STA */ + WMI_PDEV_PARAM_PROXY_STA, + /** Enable/Disable low power state when all VDEVs are inactive/idle. */ + WMI_PDEV_PARAM_IDLE_PS_CONFIG, + /** Enable/Disable power gating sleep */ + WMI_PDEV_PARAM_POWER_GATING_SLEEP, + /** Enable/Disable Rfkill */ + WMI_PDEV_PARAM_RFKILL_ENABLE, + /** Set Bursting DUR */ + WMI_PDEV_PARAM_BURST_DUR, + /** Set Bursting ENABLE */ + WMI_PDEV_PARAM_BURST_ENABLE, + /** HW rfkill config */ + WMI_PDEV_PARAM_HW_RFKILL_CONFIG, + /** Enable radio low power features */ + WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, + /** L1SS entry and residency time track */ + WMI_PDEV_PARAM_L1SS_TRACK, + /** set hyst at runtime, requirement from SS */ + WMI_PDEV_PARAM_HYST_EN, + /** Enable/ Disable POWER COLLAPSE */ + WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, + /** configure LED system state */ + WMI_PDEV_PARAM_LED_SYS_STATE, + /** Enable/Disable LED */ + WMI_PDEV_PARAM_LED_ENABLE, + /** set DIRECT AUDIO time latency */ + WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, /* DEPRECATED */ + /** set DIRECT AUDIO Feature ENABLE */ + WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, /* DEPRECATED */ + /** pdev level whal mib stats update enable */ + WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, + /** ht/vht info based on vdev */ + WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, + /** Set CTS channel BW for dynamic BW adjustment feature */ + WMI_PDEV_PARAM_CTS_CBW, + /** Set GPIO pin info used by WNTS */ + WMI_PDEV_PARAM_WNTS_CONFIG, + /** Enable/Disable hardware adaptive early rx feature */ + WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, + /** The minimum early rx duration, to ensure early rx duration is non-zero */ + WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, + /** Increasing/decreasing step used by hardware */ + WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, + /** The fixed early rx duration when adaptive early rx is disabled */ + WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, + /** Enable/Disable bmiss based adaptive beacon timeout feature */ + WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, + /* + * The minimum beacon timeout duration, to ensure beacon timeout + * duration is non-zero + */ + WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, + /** Increasing/decreasing step used by hardware */ + WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, + /* + * The fixed beacon timeout duration when bmiss based adaptive beacon + * timeout is disabled + */ + WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, + /* + * Enable/Disable Congestion Estimator based adaptive beacon + * timeout feature */ + WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, + /* + * combo value of ce_id, ce_threshold, ce_time, refer + * to WMI_CE_BTO_CE_ID_MASK + */ + WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, + /** 2G TX chain mask */ + WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, + /** 2G RX chain mask */ + WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, + /** 5G TX chain mask */ + WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, + /** 5G RX chain mask */ + WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, + /* Set tx chain mask for CCK rates */ + WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, + /* Set tx chain mask for 1SS stream */ + WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, + /* Enable/Disable CTS2Self for P2P GO when Non-P2P Client is connected*/ + WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, + /* TX power backoff in dB: tx power -= param value + * Host passes values(DB) to Halphy, Halphy reduces the power table by + * the values. Safety check will happen in Halphy + */ + WMI_PDEV_PARAM_TXPOWER_DECR_DB, + /** enable and disable aggregate burst along with duration */ + WMI_PDEV_PARAM_AGGR_BURST, + /** Set the global RX decap mode */ + WMI_PDEV_PARAM_RX_DECAP_MODE, + /** Enable/Disable Fast channel reset */ + WMI_PDEV_PARAM_FAST_CHANNEL_RESET, + /** Default antenna for Smart antenna */ + WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, + /** Set the user-specified antenna gain */ + WMI_PDEV_PARAM_ANTENNA_GAIN, + /** Set the user-specified RX filter */ + WMI_PDEV_PARAM_RX_FILTER, + /* + * configure the user-specified MCAST tid for managed mcast feature + * 0-15 is the valid range. 0xff will clear the tid setting + */ + WMI_PDEV_SET_MCAST_TO_UCAST_TID, + /** Enable/Disable Proxy sta mode */ + WMI_PDEV_PARAM_PROXY_STA_MODE, + /* + * configure the mcast2ucast mode for the pdev->peer_mcast. + * See WMI_PEER_MCAST2UCAST_MODE for possible values + */ + WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, + /** Sets the Mcast buffers for cloning, to support Mcast enhancement */ + WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, + /** Remove the Mcast buffers added by host */ + WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, + /** En/disable station power save state indication */ + WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, + /** Access category on which ARP frames are sent */ + WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, + /** allow or disallow interbss frame forwarding */ + WMI_PDEV_PARAM_BLOCK_INTERBSS, + /** Enable/Disable reset */ + WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, + /** Enable/Disable/Set MSDU_TTL in milliseconds. */ + WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, + /** Set global PPDU duration limit (usec). */ + WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, + /** set txbf sounding period of vap in milliseconds */ + WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, + /** Set promiscuous mode */ + WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, + /** Set burst mode */ + WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, + /** enable enhanced stats */ + WMI_PDEV_PARAM_EN_STATS, + /** Set mu-grouping policy */ + WMI_PDEV_PARAM_MU_GROUP_POLICY, + /** Channel Hopping Enable */ + WMI_PDEV_PARAM_NOISE_DETECTION, + /** Set Channel Hopping NF threshold in dBm */ + WMI_PDEV_PARAM_NOISE_THRESHOLD, + /** Set PAPRD policy */ + WMI_PDEV_PARAM_DPD_ENABLE, + /** Enable/disable mcast/bcast echo, used by ProxySTA */ + WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, + /** ATF enable/disable strict schedule */ + WMI_PDEV_PARAM_ATF_STRICT_SCH, + /** ATF set access category duration, B0-B29 duration, B30-B31: AC */ + WMI_PDEV_PARAM_ATF_SCHED_DURATION, + /** Default antenna polarization */ + WMI_PDEV_PARAM_ANT_PLZN, + /** Set mgmt retry limit */ + WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, + /** Set CCA sensitivity level in dBm */ + WMI_PDEV_PARAM_SENSITIVITY_LEVEL, + /** Set 2G positive and negative Tx power in 0.5dBm units */ + WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, + /** Set 5G positive and negative Tx power in 0.5dBm units */ + WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, + /** Enable/disble AMSDU for tids */ + WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, + /** Enable/disable AMPDU for tids */ + WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, + /** Set CCA threshold in dBm */ + WMI_PDEV_PARAM_CCA_THRESHOLD, + /** RTS Fixed rate setting */ + WMI_PDEV_PARAM_RTS_FIXED_RATE, + /** Pdev reset */ + WMI_PDEV_PARAM_PDEV_RESET, + /** wapi mbssid offset **/ + WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, + /** ARP DEBUG source address*/ + WMI_PDEV_PARAM_ARP_DBG_SRCADDR, + /** ARP DEBUG destination address*/ + WMI_PDEV_PARAM_ARP_DBG_DSTADDR, + /** ATF enable/disable obss noise scheduling */ + WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, + /** ATF obss noise scaling factor */ + WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, + /** + * TX power reduction scaling exponent - final tx power is the + * nominal tx power (A_MIN(reg_pow,ctl,etc..)) divided by + * 2^(scale exponent). For example: + * If this scale exponent is 0, the power is unchanged (divided by 2^0) + * If this factor is 1, the power is scaled down by 2^1, i.e. 3 dB + * If this factor is 2, the power is scaled down by 2^2, i.e. 6 dB + * If this factor is 3, the power is scaled down by 2^3, i.e. 9 dB + */ + WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, + /** ATF enabe/disabe dynamically */ + WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, + /** Set tx retry limit for control frames. 0 = disable, 31 = max */ + WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, + /** Set propagation delay for 2G / 5G band. + * The propagation delay is fundamentally a per-peer property, but + * the target may not support per-peer settings for ack timeouts. + * This pdev parameter allows the MAC-level ack timeout to be set to + * a value suitable for the worst-case propagation delay of any peer + * within that pdev. + * Units are microseconds. + */ + WMI_PDEV_PARAM_PROPAGATION_DELAY, + /** + * Host can enable/disable ANT DIV feature + * if it's been enabled in BDF + */ + WMI_PDEV_PARAM_ENA_ANT_DIV, + /** Host can force one chain to select a specific ANT */ + WMI_PDEV_PARAM_FORCE_CHAIN_ANT, + /** + * Start a cycle ANT self test periodically. + * In the test, the FW would select each ANT pair + * one by one, the cycle time could be configured + * via WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL + */ + WMI_PDEV_PARAM_ANT_DIV_SELFTEST, + /** + * Configure the cycle time of ANT self test, + * the unit is micro second. Per the timer + * limitation, too small value could be not so + * accurate. + */ + WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, + /** + * wlan stats observation period, the unit is millisecond. + * The value of 0 is used to turn off periodic stats report. + */ + WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, + /** + * Set tx_ppdu_delay[] bin size to specify how many + * milliseconds each bin of the wmi_tx_stats.tx_ppdu_delay[] + * histogram represents. + */ + WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, + /** set wmi_tx_stats.tx_ppdu_delay[] array length */ + WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, + /** set wmi_tx_stats.tx_mpdu_aggr[] array length */ + WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, + /** set wmi_rx_stats.rx_mpdu_aggr[] array length */ + WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, + /** Set TX delay value in TX sch module, unit is microseconds */ + WMI_PDEV_PARAM_TX_SCH_DELAY, } WMI_PDEV_PARAM; -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /** parameter id */ - A_UINT32 param_id; - /** parametr value */ - A_UINT32 param_value; -} wmi_pdev_set_param_cmd_fixed_param; +typedef enum { + /** Set the loglevel */ + WMI_DBGLOG_LOG_LEVEL = 0x1, + /** Enable VAP level debug */ + WMI_DBGLOG_VAP_ENABLE, + /** Disable VAP level debug */ + WMI_DBGLOG_VAP_DISABLE, + /** Enable MODULE level debug */ + WMI_DBGLOG_MODULE_ENABLE, + /** Disable MODULE level debug */ + WMI_DBGLOG_MODULE_DISABLE, + /** Enable MODULE level debug */ + WMI_DBGLOG_MOD_LOG_LEVEL, + /** set type of the debug output */ + WMI_DBGLOG_TYPE, + /** Enable Disable debug */ + WMI_DBGLOG_REPORT_ENABLE +} WMI_DBG_PARAM; /* param_value for param_id WMI_PDEV_PARAM_CTS_CBW */ typedef enum { - WMI_CTS_CBW_INVALID = 0, - WMI_CTS_CBW_20, - WMI_CTS_CBW_40, - WMI_CTS_CBW_80, - WMI_CTS_CBW_80_80, - WMI_CTS_CBW_160, + WMI_CTS_CBW_INVALID = 0, + WMI_CTS_CBW_20, + WMI_CTS_CBW_40, + WMI_CTS_CBW_80, + WMI_CTS_CBW_80_80, + WMI_CTS_CBW_160, } WMI_CTS_CBW; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_tpc_config_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /** parameter */ - A_UINT32 param; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /** parameter id */ + A_UINT32 param_id; + /** parametr value */ + A_UINT32 param_value; +} wmi_pdev_set_param_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_get_tpc_config_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /** parameter */ + A_UINT32 param; } wmi_pdev_get_tpc_config_cmd_fixed_param; #define WMI_FAST_DIVERSITY_BIT_OFFSET 0 #define WMI_SLOW_DIVERSITY_BIT_OFFSET 1 #define WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT 2 -#define WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK (0xf << WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT) +#define WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK \ + (0xf << WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT) #define WMI_SLOW_DIVERSITY_CH0_WEIGHT_GET_BITS(word32) \ - (((word32) & WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK) >> WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT) + (((word32) & WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK) >> \ + WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT) #define WMI_SLOW_DIVERSITY_CH0_WEIGHT_SET_BITS(word32, value) \ - do { \ - (word32) &= ~WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK; \ - (word32) |= ((value) << WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT) & \ - WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK; \ - } while (0) + do { \ + (word32) &= ~WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK; \ + (word32) |= ((value) << WMI_SLOW_DIVERSITY_CH0_WEIGHT_SHIFT) & \ + WMI_SLOW_DIVERSITY_CH0_WEIGHT_MASK; \ + } while (0) #define WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT 6 -#define WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK (0xf << WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT) +#define WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK \ + (0xf << WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT) #define WMI_SLOW_DIVERSITY_CH1_WEIGHT_GET_BITS(word32) \ - (((word32) & WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK) >> WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT) + (((word32) & WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK) >> \ + WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT) #define WMI_SLOW_DIVERSITY_CH1_WEIGHT_SET_BITS(word32, value) \ - do { \ - (word32) &= ~WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK; \ - (word32) |= ((value) << WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT) & \ - WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK; \ - } while (0) + do { \ + (word32) &= ~WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK; \ + (word32) |= ((value) << WMI_SLOW_DIVERSITY_CH1_WEIGHT_SHIFT) & \ + WMI_SLOW_DIVERSITY_CH1_WEIGHT_MASK; \ + } while (0) typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_antenna_diversity_cmd_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - /** - * The following "value" field is divided into bit fields as follows: - * bits | purpose - * -----+--------------------------------------- - * 0 | enable/disable FAST diversity - * 1 | enable/disable SLOW diversity - * 5:2 | chain0 slow-diversity weighting factor - * 9:6 | chain1 slow-diversity weighting factor - * 31:10| currenty unused (set to 0x0) - * Refer to the above WMI_[FAST/SLOW]_DIVERSITY constants. - */ - A_UINT32 value; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_antenna_diversity_cmd_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + /* + * The following "value" field is divided into bit fields as follows: + * bits | purpose + * -----+--------------------------------------- + * 0 | enable/disable FAST diversity + * 1 | enable/disable SLOW diversity + * 5:2 | chain0 slow-diversity weighting factor + * 9:6 | chain1 slow-diversity weighting factor + * 31:10| currenty unused (set to 0x0) + * Refer to the above WMI_[FAST/SLOW]_DIVERSITY constants. + */ + A_UINT32 value; } wmi_pdev_set_antenna_diversity_cmd_fixed_param; #define WMI_MAX_RSSI_THRESHOLD_SUPPORTED 3 typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_breach_monitor_config_cmd_fixed_param */ - A_UINT32 vdev_id; /* vdev_id, where RSSI monitoring will take place */ - A_UINT32 request_id; /* host will configure request_id and firmware echo this id in RSSI_BREACH_EVENT */ - A_UINT32 enabled_bitmap; /* bit [0-2] = low_rssi_breach_enabled[0-2] enabled, bit [3-5] = hi_rssi_breach_enabled[0-2] */ - A_UINT32 low_rssi_breach_threshold[WMI_MAX_RSSI_THRESHOLD_SUPPORTED]; /* unit dBm. host driver to make sure [0] > [1] > [2] */ - A_UINT32 hi_rssi_breach_threshold[WMI_MAX_RSSI_THRESHOLD_SUPPORTED]; /* unit dBm. host driver to make sure [0] < [1] < [2] */ - A_UINT32 lo_rssi_reenable_hysteresis; /* unit dBm. once low rssi[] breached, same event bitmap will be generated only after signal gets better than this level. This value is adopted for all low_rssi_breach_threshold[3] */ - A_UINT32 hi_rssi_reenable_histeresis;/* unit dBm. once hi rssi[] breached, same event bitmap will be generated only after signal gets worse than this level. This value is adopted for all hi_rssi_breach_threshold[3] */ - A_UINT32 min_report_interval; /* After last event is generated, we wait until this interval to generate next event */ - A_UINT32 max_num_report; /* this is to suppress number of event to be generated */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_rssi_breach_monitor_config_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* vdev_id, where RSSI monitoring will take place */ + A_UINT32 vdev_id; + /* + * host will configure request_id and firmware echo + * this id in RSSI_BREACH_EVENT + */ + A_UINT32 request_id; + /* + * bit [0-2] = low_rssi_breach_enabled[0-2] + * enabled, bit [3-5] = hi_rssi_breach_enabled[0-2] + */ + A_UINT32 enabled_bitmap; + /* unit dBm. host driver to make sure [0] > [1] > [2] */ + A_UINT32 low_rssi_breach_threshold[WMI_MAX_RSSI_THRESHOLD_SUPPORTED]; + /* unit dBm. host driver to make sure [0] < [1] < [2] */ + A_UINT32 hi_rssi_breach_threshold[WMI_MAX_RSSI_THRESHOLD_SUPPORTED]; + /* + * unit dBm. once low rssi[] breached, same event + * bitmap will be generated only after signal gets better + * than this level. This value is adopted for all low_rssi_breach_threshold[3] + */ + A_UINT32 lo_rssi_reenable_hysteresis; + /* + * unit dBm. once hi rssi[] breached, same event bitmap + * will be generated only after signal gets worse than this + * level. This value is adopted for all hi_rssi_breach_threshold[3] + */ + A_UINT32 hi_rssi_reenable_histeresis; + /* + * After last event is generated, we wait + * until this interval to generate next event + */ + A_UINT32 min_report_interval; + /* this is to suppress number of event to be generated */ + A_UINT32 max_num_report; } wmi_rssi_breach_monitor_config_fixed_param; typedef struct { - /** parameter */ - A_UINT32 param; + /** parameter */ + A_UINT32 param; } wmi_pdev_dump_cmd; typedef enum { - PAUSE_TYPE_CHOP = 0x1, /** for MCC (switch channel), only vdev_map is valid */ - PAUSE_TYPE_PS = 0x2, /** for peer station sleep in sap mode, only peer_id is valid */ - PAUSE_TYPE_UAPSD = 0x3, /** for uapsd, only peer_id and tid_map are valid. */ - PAUSE_TYPE_P2P_CLIENT_NOA = 0x4, /** only vdev_map is valid, actually only one vdev id is set at one time */ - PAUSE_TYPE_P2P_GO_PS = 0x5, /** only vdev_map is valid, actually only one vdev id is set at one time */ - PAUSE_TYPE_STA_ADD_BA = 0x6, /** only peer_id and tid_map are valid, actually only one tid is set at one time */ - PAUSE_TYPE_AP_PS = 0x7, /** for pausing AP vdev when all the connected clients are in PS. only vdev_map is valid */ - PAUSE_TYPE_IBSS_PS = 0x8, /** for pausing IBSS vdev when all the peers are in PS. only vdev_map is valid */ - PAUSE_TYPE_CHOP_TDLS_OFFCHAN = 0x9, /** for TDLS offchannel MCC (switch channel), only vdev_map is valid, TDLS connection tracker needs to be notified */ + PAUSE_TYPE_CHOP = 0x1, + /** for MCC (switch channel), only vdev_map is valid */ + PAUSE_TYPE_PS = 0x2, /** for peer station sleep in sap mode, only peer_id is valid */ + PAUSE_TYPE_UAPSD = 0x3, + /** for uapsd, only peer_id and tid_map are valid. */ + PAUSE_TYPE_P2P_CLIENT_NOA = 0x4, + /** only vdev_map is valid, actually only one vdev id is set at one time */ + PAUSE_TYPE_P2P_GO_PS = 0x5, + /** only vdev_map is valid, actually only one vdev id is set at one time */ + PAUSE_TYPE_STA_ADD_BA = 0x6, + /** only peer_id and tid_map are valid, actually only one tid is set at one time */ + PAUSE_TYPE_AP_PS = 0x7, + /** for pausing AP vdev when all the connected clients are in PS. only vdev_map is valid */ + PAUSE_TYPE_IBSS_PS = 0x8, + /** for pausing IBSS vdev when all the peers are in PS. only vdev_map is valid */ + PAUSE_TYPE_CHOP_TDLS_OFFCHAN = 0x9, + /* + * for TDLS offchannel MCC (switch channel), only vdev_map is valid, + * TDLS connection tracker needs to be notified + */ + PAUSE_TYPE_HOST = 0x15, + /** host is requesting vdev pause */ } wmi_tx_pause_type; typedef enum { - ACTION_PAUSE = 0x0, - ACTION_UNPAUSE = 0x1, + ACTION_PAUSE = 0x0, + ACTION_UNPAUSE = 0x1, } wmi_tx_pause_action; typedef struct { - A_UINT32 tlv_header; - A_UINT32 pause_type; - A_UINT32 action; - A_UINT32 vdev_map; - A_UINT32 peer_id; - A_UINT32 tid_map; + A_UINT32 tlv_header; + A_UINT32 pause_type; + A_UINT32 action; + A_UINT32 vdev_map; + A_UINT32 peer_id; + A_UINT32 tid_map; } wmi_tx_pause_event_fixed_param; typedef enum { - WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK = 0, - WMI_MGMT_TX_COMP_TYPE_DISCARD, - WMI_MGMT_TX_COMP_TYPE_INSPECT, - WMI_MGMT_TX_COMP_TYPE_COMPLETE_NO_ACK, - WMI_MGMT_TX_COMP_TYPE_MAX, + WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK = 0, + WMI_MGMT_TX_COMP_TYPE_DISCARD, + WMI_MGMT_TX_COMP_TYPE_INSPECT, + WMI_MGMT_TX_COMP_TYPE_COMPLETE_NO_ACK, + WMI_MGMT_TX_COMP_TYPE_MAX, } WMI_MGMT_TX_COMP_STATUS_TYPE; typedef struct { - A_UINT32 tlv_header; - A_UINT32 desc_id; /* from tx_send_cmd */ - A_UINT32 status; /* WMI_MGMT_TX_COMP_STATUS_TYPE */ + A_UINT32 tlv_header; + A_UINT32 desc_id; /* from tx_send_cmd */ + A_UINT32 status; /* WMI_MGMT_TX_COMP_STATUS_TYPE */ } wmi_mgmt_tx_compl_event_fixed_param; typedef struct { - A_UINT32 tlv_header; - A_UINT32 num_reports; - /* tlv for completion - * A_UINT32 desc_ids[num_reports]; <- from tx_send_cmd - * A_UINT32 status[num_reports]; <- WMI_MGMT_TX_COMP_STATUS_TYPE - */ + A_UINT32 tlv_header; + A_UINT32 num_reports; + /* tlv for completion + * A_UINT32 desc_ids[num_reports]; <- from tx_send_cmd + * A_UINT32 status[num_reports]; <- WMI_MGMT_TX_COMP_STATUS_TYPE + */ } wmi_mgmt_tx_compl_bundle_event_fixed_param; #define WMI_TPC_RATE_MAX 160 @@ -3866,137 +4175,163 @@ typedef struct { #define WMI_TPC_TX_NUM_CHAIN 4 typedef enum { - WMI_TPC_CONFIG_EVENT_FLAG_TABLE_CDD = 0x1, - WMI_TPC_CONFIG_EVENT_FLAG_TABLE_STBC = 0x2, - WMI_TPC_CONFIG_EVENT_FLAG_TABLE_TXBF = 0x4, + WMI_TPC_CONFIG_EVENT_FLAG_TABLE_CDD = 0x1, + WMI_TPC_CONFIG_EVENT_FLAG_TABLE_STBC = 0x2, + WMI_TPC_CONFIG_EVENT_FLAG_TABLE_TXBF = 0x4, } WMI_TPC_CONFIG_EVENT_FLAG; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param */ - A_UINT32 regDomain; - A_UINT32 chanFreq; - A_UINT32 phyMode; - A_UINT32 twiceAntennaReduction; - A_UINT32 twiceMaxRDPower; - A_INT32 twiceAntennaGain; - A_UINT32 powerLimit; - A_UINT32 rateMax; - A_UINT32 numTxChain; - A_UINT32 ctl; - A_UINT32 flags; - /* WMI_TPC_TX_NUM_CHAIN macro can't be changed without breaking the WMI compatibility */ - A_INT8 maxRegAllowedPower[WMI_TPC_TX_NUM_CHAIN]; - A_INT8 maxRegAllowedPowerAGCDD[WMI_TPC_TX_NUM_CHAIN][WMI_TPC_TX_NUM_CHAIN]; - A_INT8 maxRegAllowedPowerAGSTBC[WMI_TPC_TX_NUM_CHAIN][WMI_TPC_TX_NUM_CHAIN]; - A_INT8 maxRegAllowedPowerAGTXBF[WMI_TPC_TX_NUM_CHAIN][WMI_TPC_TX_NUM_CHAIN]; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; -/* This TLV is followed by a byte array: - * A_UINT8 ratesArray[]; - */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 regDomain; + A_UINT32 chanFreq; + A_UINT32 phyMode; + A_UINT32 twiceAntennaReduction; + A_UINT32 twiceMaxRDPower; + A_INT32 twiceAntennaGain; + A_UINT32 powerLimit; + A_UINT32 rateMax; + A_UINT32 numTxChain; + A_UINT32 ctl; + A_UINT32 flags; + /* WMI_TPC_TX_NUM_CHAIN macro can't be changed without + * breaking the WMI compatibility + */ + A_INT8 maxRegAllowedPower[WMI_TPC_TX_NUM_CHAIN]; + A_INT8 + maxRegAllowedPowerAGCDD[WMI_TPC_TX_NUM_CHAIN] + [WMI_TPC_TX_NUM_CHAIN]; + A_INT8 + maxRegAllowedPowerAGSTBC[WMI_TPC_TX_NUM_CHAIN] + [WMI_TPC_TX_NUM_CHAIN]; + A_INT8 + maxRegAllowedPowerAGTXBF[WMI_TPC_TX_NUM_CHAIN] + [WMI_TPC_TX_NUM_CHAIN]; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* This TLV is followed by a byte array: + * A_UINT8 ratesArray[]; + */ } wmi_pdev_tpc_config_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_l1ss_track_event_fixed_param */ - A_UINT32 periodCnt; - A_UINT32 L1Cnt; - A_UINT32 L11Cnt; - A_UINT32 L12Cnt; - A_UINT32 L1Entry; - A_UINT32 L11Entry; - A_UINT32 L12Entry; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_l1ss_track_event_fixed_param */ + A_UINT32 periodCnt; + A_UINT32 L1Cnt; + A_UINT32 L11Cnt; + A_UINT32 L12Cnt; + A_UINT32 L1Entry; + A_UINT32 L11Entry; + A_UINT32 L12Entry; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_l1ss_track_event_fixed_param; typedef struct { - A_UINT32 len; - A_UINT32 msgref; - A_UINT32 segmentInfo; + A_UINT32 len; + A_UINT32 msgref; + A_UINT32 segmentInfo; } wmi_pdev_seg_hdr_info; - /* * Transmit power scale factor. * */ typedef enum { - WMI_TP_SCALE_MAX = 0, /* no scaling (default) */ - WMI_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ - WMI_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ - WMI_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ - WMI_TP_SCALE_MIN = 4, /* min, but still on */ - WMI_TP_SCALE_SIZE = 5, /* max num of enum */ + WMI_TP_SCALE_MAX = 0, /* no scaling (default) */ + WMI_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ + WMI_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ + WMI_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ + WMI_TP_SCALE_MIN = 4, /* min, but still on */ + WMI_TP_SCALE_SIZE = 5, /* max num of enum */ } WMI_TP_SCALE; #define WMI_MAX_DEBUG_MESG (sizeof(A_UINT32) * 32) typedef struct { - /** message buffer, NULL terminated */ - char bufp[WMI_MAX_DEBUG_MESG]; + /** message buffer, NULL terminated */ + char bufp[WMI_MAX_DEBUG_MESG]; } wmi_debug_mesg_event; enum { - /** P2P device */ - VDEV_SUBTYPE_P2PDEV = 0, - /** P2P client */ - VDEV_SUBTYPE_P2PCLI, - /** P2P GO */ - VDEV_SUBTYPE_P2PGO, - /** BT3.0 HS */ - VDEV_SUBTYPE_BT, + /** P2P device */ + VDEV_SUBTYPE_P2PDEV = 0, + /** P2P client */ + VDEV_SUBTYPE_P2PCLI, + /** P2P GO */ + VDEV_SUBTYPE_P2PGO, + /** BT3.0 HS */ + VDEV_SUBTYPE_BT, }; typedef struct { - /** idnore power , only use flags , mode and freq */ - wmi_channel chan; + /** idnore power , only use flags , mode and freq */ + wmi_channel chan; } wmi_pdev_set_channel_cmd; typedef enum { - WMI_PKTLOG_EVENT_RX = 0x1, - WMI_PKTLOG_EVENT_TX = 0x2, - WMI_PKTLOG_EVENT_RCF = 0x4, /* Rate Control Find */ - WMI_PKTLOG_EVENT_RCU = 0x8, /* Rate Control Update */ - /* 0x10 used by deprecated DBG_PRINT */ - WMI_PKTLOG_EVENT_SMART_ANTENNA = 0x20, /* To support Smart Antenna */ - WMI_PKTLOG_EVENT_SW = 0x40, /* To support SW defined events */ + WMI_PKTLOG_EVENT_RX = 0x1, + WMI_PKTLOG_EVENT_TX = 0x2, + WMI_PKTLOG_EVENT_RCF = 0x4, /* Rate Control Find */ + WMI_PKTLOG_EVENT_RCU = 0x8, /* Rate Control Update */ + /* 0x10 used by deprecated DBG_PRINT */ + WMI_PKTLOG_EVENT_SMART_ANTENNA = 0x20, /* To support Smart Antenna */ + WMI_PKTLOG_EVENT_SW = 0x40, /* To support SW defined events */ } WMI_PKTLOG_EVENT; typedef enum { - WMI_PKTLOG_ENABLE_AUTO = 0, /* (default) FW will decide under what conditions to enable pktlog */ - WMI_PKTLOG_ENABLE_FORCE = 1, /* pktlog unconditionally enabled */ + /* (default) FW will decide under what conditions to enable pktlog */ + WMI_PKTLOG_ENABLE_AUTO = 0, + WMI_PKTLOG_ENABLE_FORCE = 1, /* pktlog unconditionally enabled */ } WMI_PKTLOG_ENABLE; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - A_UINT32 evlist; /* WMI_PKTLOG_EVENT */ - A_UINT32 enable; /* WMI_PKTLOG_ENABLE */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + A_UINT32 evlist; /* WMI_PKTLOG_EVENT */ + A_UINT32 enable; /* WMI_PKTLOG_ENABLE */ } wmi_pdev_pktlog_enable_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_pktlog_disable_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_pktlog_disable_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_pktlog_disable_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - A_UINT32 enable_Mib; /** enable for mib stats collection. Stats are delivered to host in wmi_mib_stats structure. - * If enable_Mib=1, stats collection is enabled. If enable_Mib=0, stats collection does not happen */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* + * enable for mib stats collection. + * Stats are delivered to host in wmi_mib_stats structure. + * If enable_Mib=1, stats collection is enabled. + * If enable_Mib=0, stats collection does not happen + */ + A_UINT32 enable_Mib; } wmi_mib_stats_enable_cmd_fixed_param; /** Customize the DSCP (bit) to TID (0-7) mapping for QOS. @@ -4018,19 +4353,19 @@ typedef struct { * Implementation details of the API to send the map to the target are as described- * * 1. The function will have 2 arguments- struct ieee80211com, DSCP-to-TID map. - * DSCP-to-TID map is a one dimensional u_int32_t array of length 64 to accomodate + * DSCP-to-TID map is a one dimensional uint32_t array of length 64 to accomodate * 64 TID values for 2^6 (64) DSCP ids. * Example: * A_UINT32 dscp_tid_map[WMI_DSCP_MAP_MAX] = { - * 0, 0, 0, 0, 0, 0, 0, 0, - * 1, 1, 1, 1, 1, 1, 1, 1, - * 2, 2, 2, 2, 2, 2, 2, 2, - * 3, 3, 3, 3, 3, 3, 3, 3, - * 4, 4, 4, 4, 4, 4, 4, 4, - * 5, 5, 5, 5, 5, 5, 5, 5, - * 6, 6, 6, 6, 6, 6, 6, 6, - * 7, 7, 7, 7, 7, 7, 7, 7, - * }; + * 0, 0, 0, 0, 0, 0, 0, 0, + * 1, 1, 1, 1, 1, 1, 1, 1, + * 2, 2, 2, 2, 2, 2, 2, 2, + * 3, 3, 3, 3, 3, 3, 3, 3, + * 4, 4, 4, 4, 4, 4, 4, 4, + * 5, 5, 5, 5, 5, 5, 5, 5, + * 6, 6, 6, 6, 6, 6, 6, 6, + * 7, 7, 7, 7, 7, 7, 7, 7, + * }; * * 2. Request for the WMI buffer of size equal to the size of the DSCP-to-TID map. * @@ -4042,40 +4377,55 @@ typedef struct { * the WMI_PDEV_SET_DSCP_TID_MAP_CMDID id. * */ + /* DEPRECATED - use VDEV level command instead * (wmi_vdev_set_dscp_tid_map_cmd_fixed_param) */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param */ - A_UINT32 reserved0; /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ - /* map indicating DSCP to TID conversion */ - A_UINT32 dscp_to_tid_map[WMI_DSCP_MAP_MAX]; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param */ + A_UINT32 reserved0; + /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ + /* map indicating DSCP to TID conversion */ + A_UINT32 dscp_to_tid_map[WMI_DSCP_MAP_MAX]; } wmi_pdev_set_dscp_tid_map_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_dscp_tid_map_cmd_fixed_param */ - A_UINT32 vdev_id; - /** map indicating DSCP to TID conversion */ - A_UINT32 dscp_to_tid_map[WMI_DSCP_MAP_MAX]; - A_UINT32 enable_override; + A_UINT32 tlv_header; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_set_dscp_tid_map_cmd_fixed_param + */ + A_UINT32 vdev_id; + /** map indicating DSCP to TID conversion */ + A_UINT32 dscp_to_tid_map[WMI_DSCP_MAP_MAX]; + A_UINT32 enable_override; } wmi_vdev_set_dscp_tid_map_cmd_fixed_param; enum WMI_WAKE_GPIO_TYPE { - WMI_WAKE_GPIO_LOW = 1, - WMI_WAKE_GPIO_HIGH = 2, - WMI_WAKE_GPIO_RISING_EDGE = 3, - WMI_WAKE_GPIO_FALLING_EDGE = 4, + WMI_WAKE_GPIO_LOW = 1, + WMI_WAKE_GPIO_HIGH = 2, + WMI_WAKE_GPIO_RISING_EDGE = 3, + WMI_WAKE_GPIO_FALLING_EDGE = 4, }; /** * Set GPIO numbers used to wakeup host and wakeup target. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param */ - A_UINT32 host_wakeup_gpio; /* gpio num used to wakeup host, 0xff disable wakeup gpio */ - A_UINT32 host_wakeup_type; /* refer to WMI_WAKE_GPIO_TYPE */ - A_UINT32 target_wakeup_gpio; /* gpio num used to wakeup target, 0xff disable wakeup gpio */ - A_UINT32 target_wakeup_type; /* refer to WMI_WAKE_GPIO_TYPE */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param + */ + A_UINT32 tlv_header; + /* gpio num used to wakeup host, 0xff disable wakeup gpio */ + A_UINT32 host_wakeup_gpio; + /* refer to WMI_WAKE_GPIO_TYPE */ + A_UINT32 host_wakeup_type; + /* gpio num used to wakeup target, 0xff disable wakeup gpio */ + A_UINT32 target_wakeup_gpio; + /* refer to WMI_WAKE_GPIO_TYPE */ + A_UINT32 target_wakeup_type; } WMI_PDEV_SET_WAKEUP_CONFIG_CMDID_fixed_param; /** Fixed rate (rate-code) for broadcast/ multicast data frames */ @@ -4127,60 +4477,63 @@ typedef struct { * rate value. */ typedef enum { - WMI_SET_MCAST_RATE, - WMI_SET_BCAST_RATE + WMI_SET_MCAST_RATE, + WMI_SET_BCAST_RATE } MCAST_BCAST_RATE_ID; typedef struct { - MCAST_BCAST_RATE_ID rate_id; - A_UINT32 rate; + MCAST_BCAST_RATE_ID rate_id; + A_UINT32 rate; } mcast_bcast_rate; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wmm_params */ - A_UINT32 cwmin; - A_UINT32 cwmax; - A_UINT32 aifs; - A_UINT32 txoplimit; - A_UINT32 acm; - A_UINT32 no_ack; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wmm_params */ + A_UINT32 cwmin; + A_UINT32 cwmax; + A_UINT32 aifs; + A_UINT32 txoplimit; + A_UINT32 acm; + A_UINT32 no_ack; } wmi_wmm_params; /* DEPRECATED - use VDEV level command instead * (wmi_vdev_set_wmm_params_cmd_fixed_param) */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_wmm_params_cmd_fixed_param */ - A_UINT32 reserved0; /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ - A_UINT32 dg_type; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_wmm_params_cmd_fixed_param */ + A_UINT32 reserved0; + /** placeholder for pdev_id of future multiple MAC products. Init. to 0. */ + A_UINT32 dg_type; -/* The TLVs for the 4 AC follows: - * wmi_wmm_params wmm_params_ac_be; - * wmi_wmm_params wmm_params_ac_bk; - * wmi_wmm_params wmm_params_ac_vi; - * wmi_wmm_params wmm_params_ac_vo; - */ + /* The TLVs for the 4 AC follows: + * wmi_wmm_params wmm_params_ac_be; + * wmi_wmm_params wmm_params_ac_bk; + * wmi_wmm_params wmm_params_ac_vi; + * wmi_wmm_params wmm_params_ac_vo; + */ } wmi_pdev_set_wmm_params_cmd_fixed_param; typedef enum { - WMI_REQUEST_PEER_STAT = 0x01, - WMI_REQUEST_AP_STAT = 0x02, - WMI_REQUEST_PDEV_STAT = 0x04, - WMI_REQUEST_VDEV_STAT = 0x08, - WMI_REQUEST_BCNFLT_STAT = 0x10, - WMI_REQUEST_VDEV_RATE_STAT = 0x20, - WMI_REQUEST_INST_STAT = 0x40, - WMI_REQUEST_MIB_STAT = 0x80, - WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x100, + WMI_REQUEST_PEER_STAT = 0x01, + WMI_REQUEST_AP_STAT = 0x02, + WMI_REQUEST_PDEV_STAT = 0x04, + WMI_REQUEST_VDEV_STAT = 0x08, + WMI_REQUEST_BCNFLT_STAT = 0x10, + WMI_REQUEST_VDEV_RATE_STAT = 0x20, + WMI_REQUEST_INST_STAT = 0x40, + WMI_REQUEST_MIB_STAT = 0x80, + WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x100, } wmi_stats_id; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param */ - wmi_stats_id stats_id; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param */ + wmi_stats_id stats_id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_request_stats_cmd_fixed_param; /* stats type bitmap */ @@ -4189,7 +4542,6 @@ typedef struct { #define WMI_LINK_STATS_ALL_PEER 0x00000004 #define WMI_LINK_STATS_PER_PEER 0x00000008 - /* wifi clear statistics bitmap */ #define WIFI_STATS_RADIO 0x00000001 /** all radio statistics */ #define WIFI_STATS_RADIO_CCA 0x00000002 /** cca_busy_time (within radio statistics) */ @@ -4213,8 +4565,8 @@ typedef struct { #define WMI_DIAG_ID_ENABLED_DISABLED_SET(diag_events_logs, value) WMI_SET_BITS(diag_events_logs, 17, 1, value) typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_diag_event_log_config_fixed_param */ - A_UINT32 num_of_diag_events_logs; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_diag_event_log_config_fixed_param */ + A_UINT32 num_of_diag_events_logs; /* The TLVs will follow. * A_UINT32 diag_events_logs_list[]; 0-15 Bits Diag EVENT/LOG ID, * Bit 16 - DIAG type EVENT/LOG, 0 - Event, 1 - LOG @@ -4228,8 +4580,8 @@ typedef struct { #define WMI_DIAG_EXT_FEATURE_SET(diag_events_logs, value) WMI_SET_BITS(diag_events_logs, 18, 1, value) typedef struct { - A_UINT32 tlv_header; - A_UINT32 num_of_diag_events_logs; + A_UINT32 tlv_header; + A_UINT32 num_of_diag_events_logs; /* The TLVs will follow. * A_UINT32 diag_events_logs_list[]; 0-15 Bits Diag EVENT/LOG ID, * Bit 16 - DIAG type EVENT/LOG, 0 - Event, 1 - LOG @@ -4239,150 +4591,179 @@ typedef struct { } wmi_diag_event_log_supported_event_fixed_params; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_debug_mesg_flush_fixed_param*/ - A_UINT32 reserved0; /** placeholder for future */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_debug_mesg_flush_fixed_param + */ + A_UINT32 tlv_header; + /** placeholder for future */ + A_UINT32 reserved0; } wmi_debug_mesg_flush_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param*/ - A_UINT32 reserved0; /** placeholder for future */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_debug_mesg_flush_complete_fixed_param + */ + A_UINT32 tlv_header; + /** placeholder for future */ + A_UINT32 reserved0; } wmi_debug_mesg_flush_complete_fixed_param; -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_breach_fixed_param */ - /* vdev_id, where RSSI breach event occurred */ - A_UINT32 vdev_id; - /* request id */ - A_UINT32 request_id; - /* bitmap[0-2] is corresponding to low_rssi[0-2]. bitmap[3-5] is corresponding to hi_rssi[0-2]*/ - A_UINT32 event_bitmap; - /* rssi at the time of RSSI breach. Unit dBm */ - A_UINT32 rssi; - /* bssid of the monitored AP's */ - wmi_mac_addr bssid; -} wmi_rssi_breach_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_fw_mem_dump */ - /** unique id identifying the segment */ - A_UINT32 seg_id; - /** Start address of the segment to be read */ - A_UINT32 seg_start_addr_lo; - A_UINT32 seg_start_addr_hi; - /** Length of the segment to be read */ - A_UINT32 seg_length; - /** Host bufeer address to which the segment will be read and dumped */ - A_UINT32 dest_addr_lo; - A_UINT32 dest_addr_hi; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_rssi_breach_fixed_param + * vdev_id, where RSSI breach event occurred + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* request id */ + A_UINT32 request_id; + /* + * bitmap[0-2] is corresponding to low_rssi[0-2]. bitmap[3-5] is + * corresponding to hi_rssi[0-2] + */ + A_UINT32 event_bitmap; + /* rssi at the time of RSSI breach. Unit dBm */ + A_UINT32 rssi; + /* bssid of the monitored AP's */ + wmi_mac_addr bssid; +} wmi_rssi_breach_event_fixed_param; + + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_fw_mem_dump */ + A_UINT32 tlv_header; + /** unique id identifying the segment */ + A_UINT32 seg_id; + /** Start address of the segment to be read */ + A_UINT32 seg_start_addr_lo; + A_UINT32 seg_start_addr_hi; + /** Length of the segment to be read */ + A_UINT32 seg_length; + /** Host bufeer address to which the segment will be read and dumped */ + A_UINT32 dest_addr_lo; + A_UINT32 dest_addr_hi; } wmi_fw_mem_dump; /* Command to get firmware memory dump*/ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param */ - /** unique id identifying the request */ - A_UINT32 request_id; - /** number of memory dump segments */ - A_UINT32 num_fw_mem_dump_segs; -/** - * This TLV is followed by another TLV - * wmi_fw_mem_dump fw_mem_dump[]; - */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the request */ + A_UINT32 request_id; + /** number of memory dump segments */ + A_UINT32 num_fw_mem_dump_segs; + /** + * This TLV is followed by another TLV + * wmi_fw_mem_dump fw_mem_dump[]; + */ } wmi_get_fw_mem_dump_fixed_param; /** Event to indicate the completion of fw mem dump */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_update_fw_mem_dump_fixed_param */ - /** unique id identifying the request, given in the request stats command */ - A_UINT32 request_id; - /*In case of Firmware memory dump */ - A_UINT32 fw_mem_dump_complete; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_update_fw_mem_dump_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the request, given + * in the request stats command */ + A_UINT32 request_id; + /*In case of Firmware memory dump */ + A_UINT32 fw_mem_dump_complete; } wmi_update_fw_mem_dump_fixed_param; - typedef enum { - WMI_ROAMING_IDLE = 0, - WMI_ROAMING_ACTIVE = 1, + WMI_ROAMING_IDLE = 0, + WMI_ROAMING_ACTIVE = 1, } wmi_roam_state; /* access categories */ typedef enum { - WMI_AC_VO = 0, - WMI_AC_VI = 1, - WMI_AC_BE = 2, - WMI_AC_BK = 3, - WMI_AC_MAX = 4, + WMI_AC_VO = 0, + WMI_AC_VI = 1, + WMI_AC_BE = 2, + WMI_AC_BK = 3, + WMI_AC_MAX = 4, } wmi_traffic_ac; typedef enum { - WMI_STA_STATS = 0, - WMI_SOFTAP_STATS = 1, - WMI_IBSS_STATS = 2, - WMI_P2P_CLIENT_STATS = 3, - WMI_P2P_GO_STATS = 4, - WMI_NAN_STATS = 5, - WMI_MESH_STATS = 6, - } wmi_link_iface_type; + WMI_STA_STATS = 0, + WMI_SOFTAP_STATS = 1, + WMI_IBSS_STATS = 2, + WMI_P2P_CLIENT_STATS = 3, + WMI_P2P_GO_STATS = 4, + WMI_NAN_STATS = 5, + WMI_MESH_STATS = 6, +} wmi_link_iface_type; /* channel operating width */ typedef enum { - WMI_CHAN_WIDTH_20 = 0, - WMI_CHAN_WIDTH_40 = 1, - WMI_CHAN_WIDTH_80 = 2, - WMI_CHAN_WIDTH_160 = 3, - WMI_CHAN_WIDTH_80P80 = 4, - WMI_CHAN_WIDTH_5 = 5, - WMI_CHAN_WIDTH_10 = 6, + WMI_CHAN_WIDTH_20 = 0, + WMI_CHAN_WIDTH_40 = 1, + WMI_CHAN_WIDTH_80 = 2, + WMI_CHAN_WIDTH_160 = 3, + WMI_CHAN_WIDTH_80P80 = 4, + WMI_CHAN_WIDTH_5 = 5, + WMI_CHAN_WIDTH_10 = 6, } wmi_channel_width; /*Clear stats*/ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** stop_stats_collection_req = 1 will imply stop the statistics collection */ - A_UINT32 stop_stats_collection_req; - /** identifies what stats to be cleared */ - A_UINT32 stats_clear_req_mask; - /** identifies which peer stats to be cleared. Valid only while clearing PER_REER */ - wmi_mac_addr peer_macaddr; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** stop_stats_collection_req = 1 will imply stop the statistics collection */ + A_UINT32 stop_stats_collection_req; + /** identifies what stats to be cleared */ + A_UINT32 stats_clear_req_mask; + /** identifies which peer stats to be cleared. Valid only while clearing PER_REER */ + wmi_mac_addr peer_macaddr; } wmi_clear_link_stats_cmd_fixed_param; /* Link Stats configuration params. Trigger the link layer statistics collection*/ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_link_stats_cmd_fixed_param */ - /** threshold to classify the pkts as short or long */ - A_UINT32 mpdu_size_threshold; - /** set for field debug mode. Driver should collect all statistics regardless of performance impact.*/ - A_UINT32 aggressive_statistics_gathering; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_link_stats_cmd_fixed_param */ + /** threshold to classify the pkts as short or long */ + A_UINT32 mpdu_size_threshold; + /** set for field debug mode. Driver should collect all statistics regardless of performance impact.*/ + A_UINT32 aggressive_statistics_gathering; } wmi_start_link_stats_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_link_stats_cmd_fixed_param */ - /** Type of stats required. This is a bitmask WMI_LINK_STATS_RADIO, WMI_LINK_STATS_IFACE */ - A_UINT32 stats_type; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** unique id identifying the request, generated by the caller */ - A_UINT32 request_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_link_stats_cmd_fixed_param */ + /** Type of stats required. This is a bitmask WMI_LINK_STATS_RADIO, WMI_LINK_STATS_IFACE */ + A_UINT32 stats_type; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** unique id identifying the request, generated by the caller */ + A_UINT32 request_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_request_link_stats_cmd_fixed_param; /* channel statistics */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_stats */ - /** Channel width (20, 40, 80, 80+80, 160) enum wmi_channel_width*/ - A_UINT32 channel_width; - /** Primary 20 MHz channel */ - A_UINT32 center_freq; - /** center frequency (MHz) first segment */ - A_UINT32 center_freq0; - /** center frequency (MHz) second segment */ - A_UINT32 center_freq1; - /** msecs the radio is awake (32 bits number accruing over time) */ - A_UINT32 radio_awake_time; - /** msecs the CCA register is busy (32 bits number accruing over time) */ - A_UINT32 cca_busy_time; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_stats */ + /** Channel width (20, 40, 80, 80+80, 160) enum wmi_channel_width*/ + A_UINT32 channel_width; + /** Primary 20 MHz channel */ + A_UINT32 center_freq; + /** center frequency (MHz) first segment */ + A_UINT32 center_freq0; + /** center frequency (MHz) second segment */ + A_UINT32 center_freq1; + /** msecs the radio is awake (32 bits number accruing over time) */ + A_UINT32 radio_awake_time; + /** msecs the CCA register is busy (32 bits number accruing over time) */ + A_UINT32 cca_busy_time; } wmi_channel_stats; /* @@ -4393,75 +4774,85 @@ typedef struct { /* radio statistics */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_radio_link_stats */ - /** Wifi radio (if multiple radio supported) */ - A_UINT32 radio_id; - /** msecs the radio is awake (32 bits number accruing over time) */ - A_UINT32 on_time; - /** msecs the radio is transmitting (32 bits number accruing over time) */ - A_UINT32 tx_time; - /** msecs the radio is in active receive (32 bits number accruing over time) */ - A_UINT32 rx_time; - /** msecs the radio is awake due to all scan (32 bits number accruing over time) */ - A_UINT32 on_time_scan; - /** msecs the radio is awake due to NAN (32 bits number accruing over time) */ - A_UINT32 on_time_nbd; - /** msecs the radio is awake due to G?scan (32 bits number accruing over time) */ - A_UINT32 on_time_gscan; - /** msecs the radio is awake due to roam?scan (32 bits number accruing over time) */ - A_UINT32 on_time_roam_scan; - /** msecs the radio is awake due to PNO scan (32 bits number accruing over time) */ - A_UINT32 on_time_pno_scan; - /** msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time) */ - A_UINT32 on_time_hs20; - /** number of channels */ - A_UINT32 num_channels; - /** tx time per TPC level - DEPRECATED - * This field is deprecated. - * It is superseded by the WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID message. - */ - A_UINT32 tx_time_per_tpc[MAX_TPC_LEVELS]; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_radio_link_stats */ + /** Wifi radio (if multiple radio supported) */ + A_UINT32 radio_id; + /** msecs the radio is awake (32 bits number accruing over time) */ + A_UINT32 on_time; + /** msecs the radio is transmitting (32 bits number accruing over time) */ + A_UINT32 tx_time; + /** msecs the radio is in active receive (32 bits number accruing over time) */ + A_UINT32 rx_time; + /** msecs the radio is awake due to all scan (32 bits number accruing over time) */ + A_UINT32 on_time_scan; + /** msecs the radio is awake due to NAN (32 bits number accruing over time) */ + A_UINT32 on_time_nbd; + /** msecs the radio is awake due to G?scan (32 bits number accruing over time) */ + A_UINT32 on_time_gscan; + /** msecs the radio is awake due to roam?scan (32 bits number accruing over time) */ + A_UINT32 on_time_roam_scan; + /** msecs the radio is awake due to PNO scan (32 bits number accruing over time) */ + A_UINT32 on_time_pno_scan; + /** msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time) */ + A_UINT32 on_time_hs20; + /** number of channels */ + A_UINT32 num_channels; + /* + * tx time per TPC level - DEPRECATED + * This field is deprecated. + * It is superseded by the WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID + * message. + */ + A_UINT32 tx_time_per_tpc[MAX_TPC_LEVELS]; } wmi_radio_link_stats; /** tx time per power level statistics */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_power_level_stats_evt_fixed_param */ - /** total number of tx power levels */ - A_UINT32 total_num_tx_power_levels; - /** number of tx power levels that are carried in this event */ - A_UINT32 num_tx_power_levels; - /** offset of current stats - * If ((num_tx_power_levels + power_level_offset)) == - * total_num_tx_power_levels) - * this message completes the report of tx time per power levels. - * Otherwise, additional WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID messages - * will be sent by the target to deliver the remainder of the tx time - * per power level stats. - */ - A_UINT32 power_level_offset; -/* - * This TLV will be followed by a TLV containing a variable-length array of - * A_UINT32 with tx time per power level data - * A_UINT32 tx_time_per_power_level[num_tx_power_levels] - * The tx time is in units of milliseconds. - * The power levels are board-specific values; a board-specific translation - * has to be applied to determine what actual power corresponds to each - * power level. - * Just as the host has a BDF file available, the host should also have - * a data file available that provides the power level to power translations. - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_tx_power_level_stats_evt_fixed_param + */ + A_UINT32 tlv_header; + /* total number of tx power levels */ + A_UINT32 total_num_tx_power_levels; + /* number of tx power levels that are carried in this event */ + A_UINT32 num_tx_power_levels; + /* + * offset of current stats + * If ((num_tx_power_levels + power_level_offset)) == + * total_num_tx_power_levels) + * this message completes the report of tx time per power levels. + * Otherwise, additional WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID + * messages will be sent by the target to deliver the remainder of the + * tx time per power level stats. + */ + A_UINT32 power_level_offset; + /* radio id for this tx time per power level statistics (if multiple radio supported) */ + A_UINT32 radio_id; + /* + * This TLV will be followed by a TLV containing a variable-length + * array of A_UINT32 with tx time per power level data + * A_UINT32 tx_time_per_power_level[num_tx_power_levels] + * The tx time is in units of milliseconds. + * The power levels are board-specific values; a board-specific + * translation has to be applied to determine what actual power + * corresponds to each power level. + * Just as the host has a BDF file available, the host should also have + * a data file available that provides the power level to power + * translations. + */ } wmi_tx_power_level_stats_evt_fixed_param; - /** Radio statistics (once started) do not stop or get reset unless wifi_clear_link_stats is invoked */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ - /** unique id identifying the request, given in the request stats command */ - A_UINT32 request_id; - /** Number of radios*/ - A_UINT32 num_radio; - /** more_data will be set depending on the number of radios */ - A_UINT32 more_radio_events; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ + /** unique id identifying the request, given in the request stats command */ + A_UINT32 request_id; + /** Number of radios*/ + A_UINT32 num_radio; + /** more_data will be set depending on the number of radios */ + A_UINT32 more_radio_events; /* * This TLV is followed by another TLV of array of bytes * size of(struct wmi_radio_link_stats); @@ -4474,65 +4865,65 @@ typedef struct { /* per rate statistics */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rate_stats */ - /** rate information - * The rate-code is a 1-byte field in which:for given rate, nss and preamble - * b'7-b-6 indicate the preamble (0 OFDM, 1 CCK, 2, HT, 3 VHT) - * b'5-b'4 indicate the NSS (0 - 1x1, 1 - 2x2, 2 - 3x3) - * b'3-b'0 indicate the rate, which is indicated as follows: - * OFDM : 0: OFDM 48 Mbps - * 1: OFDM 24 Mbps - * 2: OFDM 12 Mbps - * 3: OFDM 6 Mbps - * 4: OFDM 54 Mbps - * 5: OFDM 36 Mbps - * 6: OFDM 18 Mbps - * 7: OFDM 9 Mbps - * CCK (pream == 1) - * 0: CCK 11 Mbps Long - * 1: CCK 5.5 Mbps Long - * 2: CCK 2 Mbps Long - * 3: CCK 1 Mbps Long - * 4: CCK 11 Mbps Short - * 5: CCK 5.5 Mbps Short - * 6: CCK 2 Mbps Short - * HT/VHT (pream == 2/3) - * 0..7: MCS0..MCS7 (HT) - * 0..9: MCS0..MCS9 (VHT) - */ - A_UINT32 rate; - /** units of 100 Kbps */ - A_UINT32 bitrate; - /** number of successfully transmitted data pkts (ACK rcvd) */ - A_UINT32 tx_mpdu; - /** number of received data pkts */ - A_UINT32 rx_mpdu; - /** number of data packet losses (no ACK) */ - A_UINT32 mpdu_lost; - /** total number of data pkt retries */ - A_UINT32 retries; - /** number of short data pkt retries */ - A_UINT32 retries_short; - /** number of long data pkt retries */ - A_UINT32 retries_long; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rate_stats */ + /** rate information + * The rate-code is a 1-byte field in which:for given rate, nss and preamble + * b'7-b-6 indicate the preamble (0 OFDM, 1 CCK, 2, HT, 3 VHT) + * b'5-b'4 indicate the NSS (0 - 1x1, 1 - 2x2, 2 - 3x3) + * b'3-b'0 indicate the rate, which is indicated as follows: + * OFDM : 0: OFDM 48 Mbps + * 1: OFDM 24 Mbps + * 2: OFDM 12 Mbps + * 3: OFDM 6 Mbps + * 4: OFDM 54 Mbps + * 5: OFDM 36 Mbps + * 6: OFDM 18 Mbps + * 7: OFDM 9 Mbps + * CCK (pream == 1) + * 0: CCK 11 Mbps Long + * 1: CCK 5.5 Mbps Long + * 2: CCK 2 Mbps Long + * 3: CCK 1 Mbps Long + * 4: CCK 11 Mbps Short + * 5: CCK 5.5 Mbps Short + * 6: CCK 2 Mbps Short + * HT/VHT (pream == 2/3) + * 0..7: MCS0..MCS7 (HT) + * 0..9: MCS0..MCS9 (VHT) + */ + A_UINT32 rate; + /** units of 100 Kbps */ + A_UINT32 bitrate; + /** number of successfully transmitted data pkts (ACK rcvd) */ + A_UINT32 tx_mpdu; + /** number of received data pkts */ + A_UINT32 rx_mpdu; + /** number of data packet losses (no ACK) */ + A_UINT32 mpdu_lost; + /** total number of data pkt retries */ + A_UINT32 retries; + /** number of short data pkt retries */ + A_UINT32 retries_short; + /** number of long data pkt retries */ + A_UINT32 retries_long; } wmi_rate_stats; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_link_stats */ - /** peer type (AP, TDLS, GO etc.) enum wmi_peer_type*/ - A_UINT32 peer_type; - /** mac address */ - wmi_mac_addr peer_mac_address; - /** peer wmi_CAPABILITY_XXX */ - A_UINT32 capabilities; - /** number of rates */ - A_UINT32 num_rates; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_link_stats */ + /** peer type (AP, TDLS, GO etc.) enum wmi_peer_type*/ + A_UINT32 peer_type; + /** mac address */ + wmi_mac_addr peer_mac_address; + /** peer wmi_CAPABILITY_XXX */ + A_UINT32 capabilities; + /** number of rates */ + A_UINT32 num_rates; } wmi_peer_link_stats; /** PEER statistics (once started) reset and start afresh after each connection */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_stats_event_fixed_param */ - /** unique id identifying the request, given in the request stats command */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_stats_event_fixed_param */ + /** unique id identifying the request, given in the request stats command */ A_UINT32 request_id; /** number of peers accomidated in this particular event */ A_UINT32 num_peers; @@ -4550,87 +4941,91 @@ typedef struct { /* per access category statistics */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wmm_ac_stats */ - /** access category (VI, VO, BE, BK) enum wmi_traffic_ac*/ - A_UINT32 ac_type; - /** number of successfully transmitted unicast data pkts (ACK rcvd) */ - A_UINT32 tx_mpdu; - /** number of received unicast mpdus */ - A_UINT32 rx_mpdu; - /** number of succesfully transmitted multicast data packets */ - /** STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent */ - A_UINT32 tx_mcast; - /** number of received multicast data packets */ - A_UINT32 rx_mcast; - /** number of received unicast a-mpdus */ - A_UINT32 rx_ampdu; - /** number of transmitted unicast a-mpdus */ - A_UINT32 tx_ampdu; - /** number of data pkt losses (no ACK) */ - A_UINT32 mpdu_lost; - /** total number of data pkt retries */ - A_UINT32 retries; - /** number of short data pkt retries */ - A_UINT32 retries_short; - /** number of long data pkt retries */ - A_UINT32 retries_long; - /** data pkt min contention time (usecs) */ - A_UINT32 contention_time_min; - /** data pkt max contention time (usecs) */ - A_UINT32 contention_time_max; - /** data pkt avg contention time (usecs) */ - A_UINT32 contention_time_avg; - /** num of data pkts used for contention statistics */ - A_UINT32 contention_num_samples; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wmm_ac_stats */ + /** access category (VI, VO, BE, BK) enum wmi_traffic_ac*/ + A_UINT32 ac_type; + /** number of successfully transmitted unicast data pkts (ACK rcvd) */ + A_UINT32 tx_mpdu; + /** number of received unicast mpdus */ + A_UINT32 rx_mpdu; + /** number of succesfully transmitted multicast data packets */ + /** STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent */ + A_UINT32 tx_mcast; + /** number of received multicast data packets */ + A_UINT32 rx_mcast; + /** number of received unicast a-mpdus */ + A_UINT32 rx_ampdu; + /** number of transmitted unicast a-mpdus */ + A_UINT32 tx_ampdu; + /** number of data pkt losses (no ACK) */ + A_UINT32 mpdu_lost; + /** total number of data pkt retries */ + A_UINT32 retries; + /** number of short data pkt retries */ + A_UINT32 retries_short; + /** number of long data pkt retries */ + A_UINT32 retries_long; + /** data pkt min contention time (usecs) */ + A_UINT32 contention_time_min; + /** data pkt max contention time (usecs) */ + A_UINT32 contention_time_max; + /** data pkt avg contention time (usecs) */ + A_UINT32 contention_time_avg; + /** num of data pkts used for contention statistics */ + A_UINT32 contention_num_samples; } wmi_wmm_ac_stats; /* interface statistics */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_link_stats */ - /** access point beacon received count from connected AP */ - A_UINT32 beacon_rx; - /** access point mgmt frames received count from connected AP (including Beacon) */ - A_UINT32 mgmt_rx; - /** action frames received count */ - A_UINT32 mgmt_action_rx; - /** action frames transmit count */ - A_UINT32 mgmt_action_tx; - /** access Point Beacon and Management frames RSSI (averaged) */ - A_UINT32 rssi_mgmt; - /** access Point Data Frames RSSI (averaged) from connected AP */ - A_UINT32 rssi_data; - /** access Point ACK RSSI (averaged) from connected AP */ - A_UINT32 rssi_ack; - /** number of peers */ - A_UINT32 num_peers; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_link_stats */ + /** access point beacon received count from connected AP */ + A_UINT32 beacon_rx; + /** access point mgmt frames received count from connected AP (including Beacon) */ + A_UINT32 mgmt_rx; + /** action frames received count */ + A_UINT32 mgmt_action_rx; + /** action frames transmit count */ + A_UINT32 mgmt_action_tx; + /** access Point Beacon and Management frames RSSI (averaged) */ + A_UINT32 rssi_mgmt; + /** access Point Data Frames RSSI (averaged) from connected AP */ + A_UINT32 rssi_data; + /** access Point ACK RSSI (averaged) from connected AP */ + A_UINT32 rssi_ack; + /** number of peers */ + A_UINT32 num_peers; /** Indicates how many peer_stats events will be sent depending on the num_peers. */ - A_UINT32 num_peer_events; - /** number of ac */ - A_UINT32 num_ac; - /** Roaming Stat */ - A_UINT32 roam_state; - /** Average Beacon spread offset is the averaged time delay between TBTT and beacon TSF */ - /** Upper 32 bits of averaged 64 bit beacon spread offset */ - A_UINT32 avg_bcn_spread_offset_high; - /** Lower 32 bits of averaged 64 bit beacon spread offset */ - A_UINT32 avg_bcn_spread_offset_low; - /** Takes value of 1 if AP leaks packets after sending an ACK for PM=1 otherwise 0 */ - A_UINT32 is_leaky_ap; - /** Average number of frames received from AP after receiving the ACK for a frame with PM=1 */ - A_UINT32 avg_rx_frms_leaked; - /** Rx leak watch window currently in force to minimize data loss because of leaky AP. Rx leak window is the - time driver waits before shutting down the radio or switching the channel and after receiving an ACK for - a data frame with PM bit set) */ - A_UINT32 rx_leak_window; + A_UINT32 num_peer_events; + /** number of ac */ + A_UINT32 num_ac; + /** Roaming Stat */ + A_UINT32 roam_state; + /** + * Average Beacon spread offset is the averaged time delay between TBTT + * and beacon TSF */ + /** Upper 32 bits of averaged 64 bit beacon spread offset */ + A_UINT32 avg_bcn_spread_offset_high; + /** Lower 32 bits of averaged 64 bit beacon spread offset */ + A_UINT32 avg_bcn_spread_offset_low; + /** Takes value of 1 if AP leaks packets after sending an ACK for PM=1 otherwise 0 */ + A_UINT32 is_leaky_ap; + /** Average number of frames received from AP after receiving the ACK for a frame with PM=1 */ + A_UINT32 avg_rx_frms_leaked; + /** Rx leak watch window currently in force to minimize data loss + * because of leaky AP. Rx leak window is the + * time driver waits before shutting down the radio or switching the + * channel and after receiving an ACK for + * a data frame with PM bit set) */ + A_UINT32 rx_leak_window; } wmi_iface_link_stats; /** Interface statistics (once started) reset and start afresh after each connection */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param */ - /** unique id identifying the request, given in the request stats command */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param */ + /** unique id identifying the request, given in the request stats command */ A_UINT32 request_id; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; /* * This TLV is followed by another TLV * wmi_iface_link_stats iface_link_stats; @@ -4640,440 +5035,507 @@ typedef struct { /** Suspend option */ enum { - WMI_PDEV_SUSPEND, /* suspend */ - WMI_PDEV_SUSPEND_AND_DISABLE_INTR, /* suspend and disable all interrupts */ + WMI_PDEV_SUSPEND, /* suspend */ + WMI_PDEV_SUSPEND_AND_DISABLE_INTR, /* suspend and disable all interrupts */ }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param */ - /* suspend option sent to target */ - A_UINT32 pdev_id; /** pdev_id for identifying the MAC, See macros starting with WMI_PDEV_ID_ for values. */ - A_UINT32 suspend_opt; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param */ + /* suspend option sent to target */ + /* + * pdev_id for identifying the MAC, See macros + * starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + A_UINT32 suspend_opt; } wmi_pdev_suspend_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_resume_cmd_fixed_param */ - A_UINT32 pdev_id; /** pdev_id for identifying the MAC, See macros starting with WMI_PDEV_ID_ for values. */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_resume_cmd_fixed_param */ + /* + * pdev_id for identifying the MAC, See macros + * starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_resume_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, */ - A_UINT32 num_vdev_stats; /* number of vdevs */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, */ + A_UINT32 num_vdev_stats; /* number of vdevs */ } wmi_vdev_rate_stats_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len, tag equals WMITLV_TAG_STRUC_wmi_vdev_rate_ht_info*/ - A_UINT32 vdevid; /* Id of the wlan vdev*/ - A_UINT32 tx_nss; /* Bit 28 of tx_rate_kbps has this info - based on last data packet transmitted*/ - A_UINT32 rx_nss; /* Bit 24 of rx_rate_kbps - same as above*/ - A_UINT32 tx_preamble; /* Bits 30-29 from tx_rate_kbps */ - A_UINT32 rx_preamble; /* Bits 26-25 from rx_rate_kbps */ + A_UINT32 tlv_header; /* TLV tag and len, tag equals WMITLV_TAG_STRUC_wmi_vdev_rate_ht_info */ + A_UINT32 vdevid; /* Id of the wlan vdev */ + A_UINT32 tx_nss; /* Bit 28 of tx_rate_kbps has this info - based on last data packet transmitted */ + A_UINT32 rx_nss; /* Bit 24 of rx_rate_kbps - same as above */ + A_UINT32 tx_preamble; /* Bits 30-29 from tx_rate_kbps */ + A_UINT32 rx_preamble; /* Bits 26-25 from rx_rate_kbps */ } wmi_vdev_rate_ht_info; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ - wmi_stats_id stats_id; - /** number of pdev stats event structures (wmi_pdev_stats) 0 or 1 */ - A_UINT32 num_pdev_stats; - /** number of vdev stats event structures (wmi_vdev_stats) 0 or max vdevs */ - A_UINT32 num_vdev_stats; - /** number of peer stats event structures (wmi_peer_stats) 0 or max peers */ - A_UINT32 num_peer_stats; - A_UINT32 num_bcnflt_stats; - /** number of chan stats event structures (wmi_chan_stats) 0 to MAX MCC CHANS */ - A_UINT32 num_chan_stats; - /** number of MIB stats event structures (wmi_mib_stats) */ - A_UINT32 num_mib_stats; -/* This TLV is followed by another TLV of array of bytes - * A_UINT8 data[]; - * This data array contains - * num_pdev_stats * size of(struct wmi_pdev_stats) - * num_vdev_stats * size of(struct wmi_vdev_stats) - * num_peer_stats * size of(struct wmi_peer_stats) - * num_bcnflt_stats * size_of() - * num_chan_stats * size of(struct wmi_chan_stats) - * num_mib_stats * size of(struct wmi_mib_stats) - * - */ + /** + * TLV tag and len, tag equals + * WMITLV_TAG_STRUC_wmi_rx_aggr_failure_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 num_failure_info; /* How many holes on rx aggregation */ +} wmi_rx_aggr_failure_event_fixed_param; + +typedef struct { + /** + * TLV tag and len, tag equals + * WMITLV_wmi_rx_aggr_failure_info + */ + A_UINT32 tlv_header; + A_UINT32 start_seq; /* start sequence number of the hole */ + A_UINT32 end_seq; /* end sequence number of the hole */ +} wmi_rx_aggr_failure_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ + wmi_stats_id stats_id; + /** number of pdev stats event structures (wmi_pdev_stats) 0 or 1 */ + A_UINT32 num_pdev_stats; + /** number of vdev stats event structures (wmi_vdev_stats) 0 or max vdevs */ + A_UINT32 num_vdev_stats; + /** number of peer stats event structures (wmi_peer_stats) 0 or max peers */ + A_UINT32 num_peer_stats; + A_UINT32 num_bcnflt_stats; + /** number of chan stats event structures (wmi_chan_stats) 0 to MAX MCC CHANS */ + A_UINT32 num_chan_stats; + /** number of MIB stats event structures (wmi_mib_stats) */ + A_UINT32 num_mib_stats; + /* This TLV is followed by another TLV of array of bytes + * A_UINT8 data[]; + * This data array contains + * num_pdev_stats * size of(struct wmi_pdev_stats) + * num_vdev_stats * size of(struct wmi_vdev_stats) + * num_peer_stats * size of(struct wmi_peer_stats) + * num_bcnflt_stats * size_of() + * num_chan_stats * size of(struct wmi_chan_stats) + * num_mib_stats * size of(struct wmi_mib_stats) + * + */ } wmi_stats_event_fixed_param; /* WLAN channel CCA stats bitmap */ -#define WLAN_STATS_IDLE_TIME_SHIFT 0 -#define WLAN_STATS_IDLE_TIME_TIME 0x00000001 +#define WLAN_STATS_IDLE_TIME_SHIFT 0 +#define WLAN_STATS_IDLE_TIME_TIME 0x00000001 -#define WLAN_STATS_TX_TIME_SHIFT 1 -#define WLAN_STATS_TX_TIME_MASK 0x00000002 +#define WLAN_STATS_TX_TIME_SHIFT 1 +#define WLAN_STATS_TX_TIME_MASK 0x00000002 -#define WLAN_STATS_RX_IN_BSS_TIME_SHIFT 2 -#define WLAN_STATS_RX_IN_BSS_TIME_MASK 0x00000004 +#define WLAN_STATS_RX_IN_BSS_TIME_SHIFT 2 +#define WLAN_STATS_RX_IN_BSS_TIME_MASK 0x00000004 -#define WLAN_STATS_RX_OUT_BSS_TIME_SHIFT 3 -#define WLAN_STATS_RX_OUT_BSS_TIME_MASK 0x00000008 +#define WLAN_STATS_RX_OUT_BSS_TIME_SHIFT 3 +#define WLAN_STATS_RX_OUT_BSS_TIME_MASK 0x00000008 -#define WLAN_STATS_RX_BUSY_TIME_SHIFT 4 -#define WLAN_STATS_RX_BUSY_TIME_MASK 0x00000010 +#define WLAN_STATS_RX_BUSY_TIME_SHIFT 4 +#define WLAN_STATS_RX_BUSY_TIME_MASK 0x00000010 -#define WLAN_STATS_RX_IN_BAD_COND_TIME_SHIFT 5 -#define WLAN_STATS_RX_IN_BAD_COND_TIME_MASK 0x00000020 +#define WLAN_STATS_RX_IN_BAD_COND_TIME_SHIFT 5 +#define WLAN_STATS_RX_IN_BAD_COND_TIME_MASK 0x00000020 -#define WLAN_STATS_TX_IN_BAD_COND_TIME_SHIFT 6 -#define WLAN_STATS_TX_IN_BAD_COND_TIME_MASK 0x00000040 +#define WLAN_STATS_TX_IN_BAD_COND_TIME_SHIFT 6 +#define WLAN_STATS_TX_IN_BAD_COND_TIME_MASK 0x00000040 -#define WLAN_STATS_WLAN_NOT_AVAIL_TIME_SHIFT 7 -#define WLAN_STATS_WLAN_NOT_AVAIL_TIME_MASK 0x00000080 +#define WLAN_STATS_WLAN_NOT_AVAIL_TIME_SHIFT 7 +#define WLAN_STATS_WLAN_NOT_AVAIL_TIME_MASK 0x00000080 /* WLAN peer signal stats bitmap */ -#define WLAN_STATS_PER_ANT_SNR_SHIFT 0 -#define WLAN_STATS_PER_ANT_SNR_MASK 0x00000001 +#define WLAN_STATS_PER_CHAIN_SNR_SHIFT 0 +#define WLAN_STATS_PER_CHAIN_SNR_MASK 0x00000001 -#define WLAN_STATS_NF_SHIFT 1 -#define WLAN_STATS_NF_MASK 0x00000002 +#define WLAN_STATS_PER_CHAIN_NF_SHIFT 1 +#define WLAN_STATS_PER_CHAIN_NF_MASK 0x00000002 /* WLAN TX stats bitmap */ -#define WLAN_STATS_TX_MSDUS_SHIFT 0 -#define WLAN_STATS_TX_MSDUS_MASK 0x00000001 +#define WLAN_STATS_TX_MSDU_CNT_SHIFT 0 +#define WLAN_STATS_TX_MSDU_CNT_MASK 0x00000001 -#define WLAN_STATS_TX_BYTES_SHIFT 1 -#define WLAN_STATS_TX_BYTES_MASK 0x00000002 +#define WLAN_STATS_TX_MPDU_CNT_SHIFT 1 +#define WLAN_STATS_TX_MPDU_CNT_MASK 0x00000002 -#define WLAN_STATS_TX_MSDU_DROPS_SHIFT 2 -#define WLAN_STATS_TX_MSDU_DROPS_MASK 0x00000004 +#define WLAN_STATS_TX_PPDU_CNT_SHIFT 2 +#define WLAN_STATS_TX_PPDU_CNT_MASK 0x00000004 -#define WLAN_STATS_TX_DROP_BYTES_SHIFT 3 -#define WLAN_STATS_TX_DROP_BYTES_MASK 0x00000008 +#define WLAN_STATS_TX_BYTES_SHIFT 3 +#define WLAN_STATS_TX_BYTES_MASK 0x00000008 -#define WLAN_STATS_TX_MPDU_RETRIES_SHIFT 4 -#define WLAN_STATS_TX_MPDU_RETRIES_MASK 0x00000010 +#define WLAN_STATS_TX_MSDU_DROP_CNT_SHIFT 4 +#define WLAN_STATS_TX_MSDU_DROP_CNT_MASK 0x00000010 -#define WLAN_STATS_TX_MSDU_FAILED_SHIFT 5 -#define WLAN_STATS_TX_MSDU_FAILED_MASK 0x00000020 +#define WLAN_STATS_TX_DROP_BYTES_SHIFT 5 +#define WLAN_STATS_TX_DROP_BYTES_MASK 0x00000020 -#define WLAN_STATS_TX_MPDU_AGGR_SHIFT 6 -#define WLAN_STATS_TX_MPDU_AGGR_MASK 0x00000040 +#define WLAN_STATS_TX_MPDU_RETRY_CNT_SHIFT 6 +#define WLAN_STATS_TX_MPDU_RETRY_CNT_MASK 0x00000040 -#define WLAN_STATS_TX_MSDU_ACKED_MCS_SHIFT 7 -#define WLAN_STATS_TX_MSDU_ACKED_MCS_MASK 0x00000080 +#define WLAN_STATS_TX_MPDU_FAIL_CNT_SHIFT 7 +#define WLAN_STATS_TX_MPDU_FAIL_CNT_MASK 0x00000080 -#define WLAN_STATS_TX_MSDU_FAILED_MCS_SHIFT 8 -#define WLAN_STATS_TX_MSDU_FAILED_MCS_MASK 0x00000100 +#define WLAN_STATS_TX_PPDU_FAIL_CNT_SHIFT 8 +#define WLAN_STATS_TX_PPDU_FAIL_CNT_MASK 0x00000100 -#define WLAN_STATS_TX_MSDU_DELAY_SHIFT 9 -#define WLAN_STATS_TX_MSDU_DELAY_MASK 0x00000200 +#define WLAN_STATS_TX_MPDU_AGGR_SHIFT 9 +#define WLAN_STATS_TX_MPDU_AGGR_MASK 0x00000200 + +#define WLAN_STATS_TX_SUCC_MCS_SHIFT 10 +#define WLAN_STATS_TX_SUCC_MCS_MASK 0x00000400 + +#define WLAN_STATS_TX_FAIL_MCS_SHIFT 11 +#define WLAN_STATS_TX_FAIL_MCS_MASK 0x00000800 + +#define WLAN_STATS_TX_PPDU_DELAY_SHIFT 12 +#define WLAN_STATS_TX_PPDU_DELAY_MASK 0x00001000 /* WLAN RX stats bitmap */ -#define WLAN_STATS_MAC_RX_MSDUS_SHIFT 0 -#define WLAN_STATS_MAC_RX_MSDUS_MASK 0x00000001 +#define WLAN_STATS_MAC_RX_MPDU_CNT_SHIFT 0 +#define WLAN_STATS_MAC_RX_MPDU_CNT_MASK 0x00000001 -#define WLAN_STATS_MAC_RX_BYTES_SHIFT 1 -#define WLAN_STATS_MAC_RX_BYTES_MASK 0x00000002 +#define WLAN_STATS_MAC_RX_BYTES_SHIFT 1 +#define WLAN_STATS_MAC_RX_BYTES_MASK 0x00000002 -#define WLAN_STATS_PHY_RX_MSDUS_SHIFT 2 -#define WLAN_STATS_PHY_RX_MSDUS_MASK 0x00000004 +#define WLAN_STATS_PHY_RX_PPDU_CNT_SHIFT 2 +#define WLAN_STATS_PHY_RX_PPDU_CNT_MASK 0x00000004 -#define WLAN_STATS_PHY_RX_BYTES_SHIFT 3 -#define WLAN_STATS_PHY_RX_BYTES_MASK 0x00000008 +#define WLAN_STATS_PHY_RX_BYTES_SHIFT 3 +#define WLAN_STATS_PHY_RX_BYTES_MASK 0x00000008 -#define WLAN_STATS_SEQ_DCONT_NUM_SHIFT 4 -#define WLAN_STATS_SEQ_DCONT_NUM_MASK 0x00000010 +#define WLAN_STATS_RX_DISORDER_CNT_SHIFT 4 +#define WLAN_STATS_RX_DISORDER_CNT_MASK 0x00000010 -#define WLAN_STATS_RX_MSDU_RETRY_SHIFT 5 -#define WLAN_STATS_RX_MSDU_RETRY_MASK 0x00000020 +#define WLAN_STATS_RX_RETRY_CNT_SHIFT 5 +#define WLAN_STATS_RX_RETRY_CNT_MASK 0x00000020 -#define WLAN_STATS_RX_MSDU_DUP_SHIFT 6 -#define WLAN_STATS_RX_MSDU_DUP_MASK 0x00000040 +#define WLAN_STATS_RX_DUP_CNT_SHIFT 6 +#define WLAN_STATS_RX_DUP_CNT_MASK 0x00000040 -#define WLAN_STATS_RX_MSDU_DISCARD_SHIFT 7 -#define WLAN_STATS_RX_MSDU_DISCARD_MASK 0x00000080 +#define WLAN_STATS_RX_DISCARD_CNT_SHIFT 7 +#define WLAN_STATS_RX_DISCARD_CNT_MASK 0x00000080 -#define WLAN_STATS_STA_PS_INDS_SHIFT 8 -#define WLAN_STATS_STA_PS_INDS_MASK 0x00000100 +#define WLAN_STATS_RX_MPDU_AGGR_SHIFT 8 +#define WLAN_STATS_RX_MPDU_AGGR_MASK 0x00000100 -#define WLAN_STATS_STA_PS_DURS_SHIFT 9 -#define WLAN_STATS_STA_PS_DURS_MASK 0x00000200 +#define WLAN_STATS_RX_MCS_SHIFT 9 +#define WLAN_STATS_RX_MCS_MASK 0x00000200 -#define WLAN_STATS_RX_PROBE_REQS_SHIFT 10 -#define WLAN_STATS_RX_PROBE_REQS_MASK 0x00000400 +#define WLAN_STATS_STA_PS_INDS_SHIFT 10 +#define WLAN_STATS_STA_PS_INDS_MASK 0x00000400 -#define WLAN_STATS_RX_OTH_MGMTS_SHIFT 11 -#define WLAN_STATS_RX_OTH_MGMTS_MASK 0x00000800 +#define WLAN_STATS_STA_PS_DURS_SHIFT 11 +#define WLAN_STATS_STA_PS_DURS_MASK 0x00000800 -#define WLAN_STATS_RX_MPDU_AGGR_SHIFT 12 -#define WLAN_STATS_RX_MPDU_AGGR_MASK 0x00001000 +#define WLAN_STATS_RX_PROBE_REQS_SHIFT 12 +#define WLAN_STATS_RX_PROBE_REQS_MASK 0x00001000 -#define WLAN_STATS_RX_MSDU_MCS_SHIFT 13 -#define WLAN_STATS_RX_MSDU_MCS_MASK 0x00002000 +#define WLAN_STATS_RX_OTH_MGMTS_SHIFT 13 +#define WLAN_STATS_RX_OTH_MGMTS_MASK 0x00002000 -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_cca_stats */ - A_UINT32 vdev_id; - /** Percentage of idle time, no TX, no RX, no interference */ - A_UINT32 idle_time; - /** Percentage of time transmitting packets */ - A_UINT32 tx_time; - /** Percentage of time receiving packets in current BSSs */ - A_UINT32 rx_in_bss_time; - /** Percentage of time receiving packets not in current BSSs */ - A_UINT32 rx_out_bss_time; - /** Percentage of time interference detected. */ - A_UINT32 rx_busy_time; - /** Percentage of time receiving packets with errors - * or packets flagged as retransmission or seqnum discontinued. */ - A_UINT32 rx_in_bad_cond_time; - /** Percentage of time the device transmitted packets that haven't been ACKed. */ - A_UINT32 tx_in_bad_cond_time; - /** Percentage of time the chip is unable to work in normal conditions. */ - A_UINT32 wlan_not_avail_time; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_cca_stats */ + A_UINT32 vdev_id; + /** Percentage of idle time, no TX, no RX, no interference */ + A_UINT32 idle_time; + /** Percentage of time transmitting packets */ + A_UINT32 tx_time; + /** Percentage of time receiving packets in current BSSs */ + A_UINT32 rx_in_bss_time; + /** Percentage of time receiving packets not in current BSSs */ + A_UINT32 rx_out_bss_time; + /** Percentage of time interference detected. */ + A_UINT32 rx_busy_time; + /** Percentage of time receiving packets with errors + * or packets flagged as retransmission or seqnum discontinued. */ + A_UINT32 rx_in_bad_cond_time; + /** Percentage of time the device transmitted packets that haven't been ACKed. */ + A_UINT32 tx_in_bad_cond_time; + /** Percentage of time the chip is unable to work in normal conditions. */ + A_UINT32 wlan_not_avail_time; } wmi_chan_cca_stats; /** Thresholds of cca stats, stands for percentages of stats variation. * Check wmi_chan_cca_stats for each stats's meaning. */ -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_cca_stats_thresh */ - A_UINT32 idle_time; /* units = percent */ - A_UINT32 tx_time; /* units = percent */ - A_UINT32 rx_in_bss_time; /* units = percent */ - A_UINT32 rx_out_bss_time; /* units = percent */ - A_UINT32 rx_busy_time; /* units = percent */ - A_UINT32 rx_in_bad_cond_time; /* units = percent */ - A_UINT32 tx_in_bad_cond_time; /* units = percent */ - A_UINT32 wlan_not_avail_time; /* units = percent */ +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_cca_stats_thresh */ + A_UINT32 idle_time; /* units = percent */ + A_UINT32 tx_time; /* units = percent */ + A_UINT32 rx_in_bss_time; /* units = percent */ + A_UINT32 rx_out_bss_time; /* units = percent */ + A_UINT32 rx_busy_time; /* units = percent */ + A_UINT32 rx_in_bad_cond_time; /* units = percent */ + A_UINT32 tx_in_bad_cond_time; /* units = percent */ + A_UINT32 wlan_not_avail_time; /* units = percent */ } wmi_chan_cca_stats_thresh; -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_signal_stats */ - A_UINT32 vdev_id; - A_UINT32 peer_id; - /** per antenna SNR in current bss, units are dB */ - A_INT32 per_ant_snr[WMI_MAX_CHAINS]; - /** Background noise, units are dBm */ - A_INT32 nf; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_signal_stats */ + A_UINT32 vdev_id; + A_UINT32 peer_id; + /** per chain SNR in current bss, units are dB */ + A_INT32 per_chain_snr[WMI_MAX_CHAINS]; + /** per chain background noise, units are dBm */ + A_INT32 per_chain_nf[WMI_MAX_CHAINS]; } wmi_peer_signal_stats; /** Thresholds of signal stats, stand for percentage of stats variation. * Check wmi_peer_signal_stats for each stats's meaning. */ -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_signal_stats_thresh */ - A_UINT32 per_ant_snr; /* units = dB */ - A_UINT32 nf; /* units = dBm */ +typedef struct { + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_signal_stats_thresh + */ + A_UINT32 tlv_header; + A_UINT32 per_chain_snr; /* units = dB */ + A_UINT32 per_chain_nf; /* units = dBm */ } wmi_peer_signal_stats_thresh; -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_stats */ - /** Number of total TX packets on MAC layer in the period */ - A_UINT32 tx_msdus; - /** Bytes of tx data on MAC layer in the period */ - A_UINT32 tx_bytes; - /** Number of TX packets cancelled due to any reason in the period, - * such as WMM limitation/bandwidth limitation/radio congestion */ - A_UINT32 tx_msdu_drops; - /** Bytes of dropped TX packets in the period */ - A_UINT32 tx_drop_bytes; - /** Number of unacked transmissions of MPDUs */ - A_UINT32 tx_mpdu_retries; - /** Number of packets have not been ACKed despite retried */ - A_UINT32 tx_msdu_failed; - /* This TLV is followed by TLVs below: : - * A_UINT32 tx_mpdu_aggr[tx_mpdu_aggr_array_size]; - * A_UINT32 tx_msdu_acked_mcs[tx_msdu_acked_mcs_array_size]; - * A_UINT32 tx_msdu_failed_mcs[tx_msdu_failed_mcs_array_size]; - * A_UINT32 tx_msdu_delay[tx_msdu_delay_array_size]; - */ +typedef struct { + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_tx_stats + */ + A_UINT32 tlv_header; + /** Number of total TX MSDUs on MAC layer in the period */ + A_UINT32 tx_msdu_cnt; + /** Number of total TX MPDUs on MAC layer in the period */ + A_UINT32 tx_mpdu_cnt; + /** Number of total TX PPDUs on MAC layer in the period */ + A_UINT32 tx_ppdu_cnt; + /** Bytes of tx data on MAC layer in the period */ + A_UINT32 tx_bytes; + /** + * Number of TX MSDUs cancelled due to any reason in the period, + * such as WMM limitation/bandwidth limitation/radio congestion + */ + A_UINT32 tx_msdu_drop_cnt; + /** Bytes of dropped TX packets in the period */ + A_UINT32 tx_drop_bytes; + /** Number of unacked transmissions of MPDUs */ + A_UINT32 tx_mpdu_retry_cnt; + /** Number of MPDUs have not been ACKed despite retried */ + A_UINT32 tx_mpdu_fail_cnt; + /** Number of PPDUs which received no block ack */ + A_UINT32 tx_ppdu_fail_cnt; + /** + * This TLV is followed by TLVs below: : + * A_UINT32 tx_mpdu_aggr[tx_mpdu_aggr_array_len]; + * A_UINT32 tx_succ_mcs[tx_succ_mcs_array_len]; + * A_UINT32 tx_fail_mcs[tx_fail_mcs_array_len]; + * A_UINT32 tx_delay[tx_ppdu_delay_array_len]; + */ } wmi_tx_stats; /** Thresholds of tx stats, stand for percentage of stats variation. * Check wmi_tx_stats for each stats's meaning. */ -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_stats_thresh */ - A_UINT32 tx_msdus; - A_UINT32 tx_bytes; - A_UINT32 tx_msdu_drops; - A_UINT32 tx_drop_bytes; - A_UINT32 tx_mpdu_retries; - A_UINT32 tx_msdu_failed; - A_UINT32 tx_mpdu_aggr; - A_UINT32 tx_msdu_acked_mcs; - A_UINT32 tx_msdu_failed_mcs; - A_UINT32 tx_msdu_delay; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_stats_thresh */ + A_UINT32 tx_msdu_cnt; + A_UINT32 tx_mpdu_cnt; + A_UINT32 tx_ppdu_cnt; + A_UINT32 tx_bytes; + A_UINT32 tx_msdu_drop_cnt; + A_UINT32 tx_drop_bytes; + A_UINT32 tx_mpdu_retry_cnt; + A_UINT32 tx_mpdu_fail_cnt; + A_UINT32 tx_ppdu_fail_cnt; + A_UINT32 tx_mpdu_aggr; + A_UINT32 tx_succ_mcs; + A_UINT32 tx_fail_mcs; + A_UINT32 tx_ppdu_delay; } wmi_tx_stats_thresh; -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_ac_tx_stats */ - A_UINT32 vdev_id; - A_UINT32 peer_id; - /* The TLVs for the 4 AC follows: - * wmi_tx_stats tx_stats[]; wmi_tx_stats for BE/BK/VI/VO - */ +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_ac_tx_stats */ + A_UINT32 vdev_id; + A_UINT32 peer_id; + /* The TLVs for the 4 AC follows: + * wmi_tx_stats tx_stats[]; wmi_tx_stats for BE/BK/VI/VO + */ } wmi_peer_ac_tx_stats; -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rx_stats */ - /** Number of RX packets on MAC layer */ - A_UINT32 mac_rx_msdus; - /** Bytes of RX packets on MAC layer */ - A_UINT32 mac_rx_bytes; - /** Number of RX packets on PHY layer */ - A_UINT32 phy_rx_msdus; - /** Bytes of RX packets on PHY layer */ - A_UINT32 phy_rx_bytes; - /** Number of discontinuity in seqnum */ - A_UINT32 seq_dcont_num; - /** Number of RX packets flagged as retransmissions */ - A_UINT32 rx_msdu_retry; - /** Number of RX packets identified as duplicates */ - A_UINT32 rx_msdu_dup; - /** Number of RX packets discarded */ - A_UINT32 rx_msdu_discard; - /** How many times STAs go to sleep */ - A_UINT32 sta_ps_inds; - /** Total sleep time of STAs, milliseconds units */ - A_UINT32 sta_ps_durs; - /** Number of probe requests received */ - A_UINT32 rx_probe_reqs; - /** Number of other management frames received, not including probe requests */ - A_UINT32 rx_oth_mgmts; - /* This TLV is followed by TLVs below: - * A_UINT32 rx_mpdu_aggr[rx_mpdu_aggr_array_size]; - * A_UINT32 rx_msdu_mcs[rx_msdu_mcs_array_size]; - */ +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rx_stats */ + A_UINT32 tlv_header; + /** Number of RX MPDUs on MAC layer */ + A_UINT32 mac_rx_mpdu_cnt; + /** Bytes of RX packets on MAC layer */ + A_UINT32 mac_rx_bytes; + /** Number of RX PPDU on PHY layer */ + A_UINT32 phy_rx_ppdu_cnt; + /** Bytes of RX packets on PHY layer */ + A_UINT32 phy_rx_bytes; + /** Number of discontinuity in seqnum */ + A_UINT32 rx_disorder_cnt; + /** Number of RX MPDUs flagged as retransmissions */ + A_UINT32 rx_mpdu_retry_cnt; + /** Number of RX MPDUs identified as duplicates */ + A_UINT32 rx_mpdu_dup_cnt; + /** Number of RX MPDUs discarded */ + A_UINT32 rx_mpdu_discard_cnt; + /** + * This TLV is followed by TLVs below: + * A_UINT32 rx_mpdu_aggr[rx_mpdu_aggr_array_len]; + * A_UINT32 rx_mcs[rx_mcs_array_len]; + */ } wmi_rx_stats; /** Thresholds of rx stats, stands for percentage of stats variation. * Check wmi_rx_stats for each stats's meaning. */ -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rx_stats_thresh */ - A_UINT32 mac_rx_msdus; - A_UINT32 mac_rx_bytes; - A_UINT32 phy_rx_msdus; - A_UINT32 phy_rx_bytes; - A_UINT32 seq_dcont_num; - A_UINT32 rx_msdu_retry; - A_UINT32 rx_msdu_dup; - A_UINT32 rx_msdu_discard; - A_UINT32 sta_ps_inds; - A_UINT32 sta_ps_durs; - A_UINT32 rx_probe_reqs; - A_UINT32 rx_oth_mgmts; - A_UINT32 rx_mpdu_aggr; - A_UINT32 rx_msdu_mcs; +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rx_stats_thresh */ + A_UINT32 tlv_header; + A_UINT32 mac_rx_mpdu_cnt; + A_UINT32 mac_rx_bytes; + A_UINT32 phy_rx_ppdu_cnt; + A_UINT32 phy_rx_bytes; + A_UINT32 rx_disorder_cnt; + A_UINT32 rx_mpdu_retry_cnt; + A_UINT32 rx_mpdu_dup_cnt; + A_UINT32 rx_mpdu_discard_cnt; + A_UINT32 rx_mpdu_aggr; + A_UINT32 rx_mcs; + A_UINT32 sta_ps_inds; + A_UINT32 sta_ps_durs; + A_UINT32 rx_probe_reqs; + A_UINT32 rx_oth_mgmts; } wmi_rx_stats_thresh; -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_ac_rx_stats */ - A_UINT32 vdev_id; - A_UINT32 peer_id; - /* The TLVs for the 4 AC follows: - * wmi_rx_stats rx_stats[]; wmi_rx_stats for BE/BK/VI/VO - */ +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_ac_rx_stats */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 peer_id; + /** How many times STAs go to sleep */ + A_UINT32 sta_ps_inds; + /** Total sleep time of STAs, milliseconds units */ + A_UINT32 sta_ps_durs; + /** Number of probe requests received */ + A_UINT32 rx_probe_reqs; + /** + * Number of other management frames received, not including probe + * requests + */ + A_UINT32 rx_oth_mgmts; + /** + * The TLVs for the 4 AC follows: + * wmi_rx_stats rx_stats[]; wmi_rx_stats for BE/BK/VI/VO + */ } wmi_peer_ac_rx_stats; typedef enum { - /** Periodic timer timed out, based on the period specified - * by WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD - */ - TRIGGER_COND_ID_TIMER_TIMED_OUT = 0x1, - /** Any of the (enabled) stats thresholds specified - * in the WMI_PDEV_SET_STATS_THRESHOLD_CMD message is exceeded - * within the current stats period. - */ - TRIGGER_COND_ID_THRESH_EXCEEDED = 0x2, - /** In Response to the one-time wlan stats request of - * WMI_REQUEST_WLAN_STATS_CMDID from host. - */ - TRIGGER_COND_ID_ONE_TIME_REQUEST = 0x3, + /** Periodic timer timed out, based on the period specified + * by WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD + */ + TRIGGER_COND_ID_TIMER_TIMED_OUT = 0x1, + /** Any of the (enabled) stats thresholds specified + * in the WMI_PDEV_SET_STATS_THRESHOLD_CMD message is exceeded + * within the current stats period. + */ + TRIGGER_COND_ID_THRESH_EXCEEDED = 0x2, + /** In Response to the one-time wlan stats request of + * WMI_REQUEST_WLAN_STATS_CMDID from host. + */ + TRIGGER_COND_ID_ONE_TIME_REQUEST = 0x3, } wmi_report_stats_event_trigger_cond_id; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param */ - /** Indicate what triggered this event, check wmi_report_stats_event_trigger_cond_id for details */ - A_UINT32 trigger_cond_id; - /** Bitmap to indicate changed channel CCA stats which exceeded the thresholds */ - A_UINT32 cca_chgd_bitmap; - /** Bitmap to indicate changed peer signal stats which exceeded the thresholds */ - A_UINT32 sig_chgd_bitmap; - /** Bitmap to indicate changed TX counters which exceeded the thresholds */ - A_UINT32 tx_chgd_bitmap; - /** Bitmap to indicate changed RX counters which exceeded the thresholds */ - A_UINT32 rx_chgd_bitmap; - /** number of per channel CCA stats structures (wmi_chan_cca_stats), 0 to max vdevs*/ - A_UINT32 num_chan_cca_stats; - /** number of per peer signal stats structures (wmi_peer_signal_stats), 0 to max peers*/ - A_UINT32 num_peer_signal_stats; - /** number of per peer ac TX stats structures (wmi_peer_ac_tx_stats), 0 to max peers*/ - A_UINT32 num_peer_ac_tx_stats; - /** Array size of tx_mpdu_aggr[] which is histogram of MPDU aggregation size(1 to 7 and 8+). - * The array indicates number of MPDUs sent on specified aggregation size - * (per number of MPDUs per AMPDUs / 1 to 7 and 8+). - * Array size can be set per WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_SIZE */ - A_UINT32 tx_mpdu_aggr_array_size; - /** Array size of tx_msdu_acked_mcs[] which is histogram of encoding rate. - * The array indicates number of acked packets sent at a specific rate */ - A_UINT32 tx_msdu_acked_mcs_array_size; - /** Array size of tx_msdu_failed_mcs[] which is histogram of encoding rate. - * The array indicates number of failed packets sent at a specific rate */ - A_UINT32 tx_msdu_failed_mcs_array_size; - /** tx_msdu_delay[]is a histogram of delays on MAC layer. - * The array stands for numbers of packets on different TX time delays. - * TX delay here means time interval between the time the packet has been received - * at the MAC layer and the time lower layers returns a tx status (<10ms to >100ms) - * - * The bin size tx_delay_bin_size_ms specifies how many milliseconds - * each bin of the tx_delay histogram represents. - * By default the bin size is 10ms. - * tx_msdu_delay[0] -> delays between 0-9 ms - * tx_msdu_delay[1] -> delays between 10-19 ms - * ... - * tx_msdu_delay[9] -> delays between 90-99 ms - * tx_msdu_delay[10] -> delays >= 100 ms - * Bin size can be set per WMI_PDEV_PARAM_TX_DELAY_BIN_SIZE_MS. - */ - A_UINT32 tx_msdu_delay_bin_size_ms; - /** Array size of tx_msdu_delay[]. It can be set per WMI_PDEV_PARAM_TX_DELAY_ARRAY_SIZE */ - A_UINT32 tx_msdu_delay_array_size; - /** number of per peer ac RX stats structures (wmi_peer_ac_rx_stats), 0 to max peers*/ - A_UINT32 num_peer_ac_rx_stats; - /** Array size of rx_mpdu_aggr[] which is histogram of MPDU aggregation size(1 to 7 and 8+). - * It can be set per WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_SIZE */ - A_UINT32 rx_mpdu_aggr_array_size; - /** Array size of rx_msdu_mcs[] which is histogram of encoding rate. - * The array indicates number of packets received at a specific rate */ - A_UINT32 rx_msdu_mcs_array_size; - - /** - * This TLV is followed by TLVs below: - * wmi_chan_cca_stats chan_cca_stats[]; Array size is specified by num_chan_cca_stats - * wmi_peer_signal_stats peer_signal_stats[]; Array size is specified by num_peer_signal_stats - * wmi_peer_ac_tx_stats peer_ac_tx_stats[]; Array size is specified by num_peer_ac_tx_stats - * wmi_tx_stats tx_stats[][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) - * A_UINT32 tx_mpdu_aggr[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_mpdu_aggr_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_mpdu_aggr_array_size + A-MPDU aggregation index - * A_UINT32 tx_msdu_acked_mcs[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_msdu_acked_mcs_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_msdu_acked_mcs_array_size + MCS index - * A_UINT32 tx_msdu_failed_mcs[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_msdu_failed_mcs_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_msdu_failed_mcs_array_size + MCS index - * A_UINT32 tx_msdu_delay[][][]; Array size is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_msdu_delay_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_msdu_delay_array_size + tx delay index - * wmi_peer_ac_rx_stats peer_ac_rx_stats[]; Array size is specified by num_peer_ac_rx_stats - * wmi_rx_stats rx_stats[][]; Array size is num_peer_ac_rx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) - * A_UINT32 rx_mpdu_aggr[][][]; Array size is num_peer_ac_rx_stats * WLAN_MAX_AC * rx_mpdu_aggr_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mpdu_aggr_array_size + A-MPDU aggregation index - * A_UINT32 rx_msdu_mcs[][][]; Array size is (num_peer_ac_rx_stats * WLAN_MAX_AC) * rx_msdu_mcs_array_size, - * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_msdu_mcs_array_size + MCS index - **/ -} wmi_report_stats_event_fixed_param; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param */ + /** Indicate what triggered this event, check wmi_report_stats_event_trigger_cond_id for details */ + A_UINT32 trigger_cond_id; + /** Bitmap to indicate changed channel CCA stats which exceeded the thresholds */ + A_UINT32 cca_chgd_bitmap; + /** Bitmap to indicate changed peer signal stats which exceeded the thresholds */ + A_UINT32 sig_chgd_bitmap; + /** Bitmap to indicate changed TX counters which exceeded the thresholds */ + A_UINT32 tx_chgd_bitmap; + /** Bitmap to indicate changed RX counters which exceeded the thresholds */ + A_UINT32 rx_chgd_bitmap; + /** number of per channel CCA stats structures (wmi_chan_cca_stats), 0 to max vdevs*/ + A_UINT32 num_chan_cca_stats; + /** number of per peer signal stats structures (wmi_peer_signal_stats), 0 to max peers*/ + A_UINT32 num_peer_signal_stats; + /** number of per peer ac TX stats structures (wmi_peer_ac_tx_stats), 0 to max peers*/ + A_UINT32 num_peer_ac_tx_stats; + /** + * Array length of tx_mpdu_aggr[] which is histogram of MPDU aggregation size(1 to 7 and 8+). + * The array indicates number of MPDUs sent on specified aggregation size + * (per number of MPDUs per AMPDUs / 1 to 7 and 8+). + * Array length can be set per WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN + */ + A_UINT32 tx_mpdu_aggr_array_len; + /** + * Array length of tx_succ_mcs[] which is histogram of encoding rate. + * The array indicates number of acked PPDUs sent at a specific rate + */ + A_UINT32 tx_succ_mcs_array_len; + /** + * Array length of tx_fail_mcs[] which is histogram of encoding rate. + * The array indicates number of unacked PPDUs sent at a specific rate + */ + A_UINT32 tx_fail_mcs_array_len; + /** + * tx_ppdu_delay[]is a histogram of delays on MAC layer. + * The array counts numbers of PPDUs encountering different TX time delays. + * TX delay here means time interval between the time a PPDU is queued + * to the MAC HW for transmission and the time the lower layers of + * tx FW return a tx status. + * + * The bin size tx_ppdu_delay_bin_size_ms specifies how many + * milliseconds. Each bin of the tx_ppdu_delay histogram represents. + * By default the bin size is 10ms. + * tx_ppdu_delay[0] -> delays between 0-9 ms + * tx_ppdu_delay[1] -> delays between 10-19 ms + * ... + * tx_ppdu_delay[9] -> delays between 90-99 ms + * tx_ppdu_delay[10] -> delays >= 100 ms + * Bin size can be set per WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS. + */ + A_UINT32 tx_ppdu_delay_bin_size_ms; + /** Array length of tx_ppdu_delay[]. It can be set per WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN */ + A_UINT32 tx_ppdu_delay_array_len; + /** number of per peer ac RX stats structures (wmi_peer_ac_rx_stats), 0 to max peers*/ + A_UINT32 num_peer_ac_rx_stats; + /** + * Array length of rx_mpdu_aggr[] which is histogram of MPDU aggregation size(1 to 7 and 8+). + * It can be set per WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN + */ + A_UINT32 rx_mpdu_aggr_array_len; + /** + * Array size of rx_mcs[] which is histogram of encoding rate. + * The array indicates number of PPDUs received at a specific rate + */ + A_UINT32 rx_mcs_array_len; + + /** + * This TLV is followed by TLVs below: + * wmi_chan_cca_stats chan_cca_stats[]; Array length is specified by num_chan_cca_stats + * wmi_peer_signal_stats peer_signal_stats[]; Array length is specified by num_peer_signal_stats + * wmi_peer_ac_tx_stats peer_ac_tx_stats[]; Array length is specified by num_peer_ac_tx_stats + * wmi_tx_stats tx_stats[][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) + * A_UINT32 tx_mpdu_aggr[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_mpdu_aggr_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_mpdu_aggr_array_len + A-MPDU aggregation index + * A_UINT32 tx_succ_mcs[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_succ_mcs_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_succ_mcs_array_len + MCS index + * A_UINT32 tx_fail_mcs[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_fail_mcs_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_fail_mcs_array_len + MCS index + * A_UINT32 tx_ppdu_delay[][][]; Array length is num_peer_ac_tx_stats * WLAN_MAX_AC * tx_ppdu_delay_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * tx_ppdu_delay_array_len + tx delay index + * wmi_peer_ac_rx_stats peer_ac_rx_stats[]; Array length is specified by num_peer_ac_rx_stats + * wmi_rx_stats rx_stats[][]; Array length is num_peer_ac_rx_stats * WLAN_MAX_AC, array index is (peer_index * WLAN_MAX_AC + ac_index) + * A_UINT32 rx_mpdu_aggr[][][]; Array length is num_peer_ac_rx_stats * WLAN_MAX_AC * rx_mpdu_aggr_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mpdu_aggr_array_len + A-MPDU aggregation index + * A_UINT32 rx_mcs[][][]; Array length is (num_peer_ac_rx_stats * WLAN_MAX_AC) * rx_mcs_array_len, + * array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mcs_array_len + MCS index + */ +} wmi_report_stats_event_fixed_param; + /** * PDEV statistics @@ -5081,22 +5543,22 @@ typedef struct { * add all PDEV stats here */ typedef struct { - /** Channel noise floor */ - A_INT32 chan_nf; - /** TX frame count */ - A_UINT32 tx_frame_count; - /** RX frame count */ - A_UINT32 rx_frame_count; - /** rx clear count */ - A_UINT32 rx_clear_count; - /** cycle count */ - A_UINT32 cycle_count; - /** Phy error count */ - A_UINT32 phy_err_count; - /** Channel Tx Power */ - A_UINT32 chan_tx_pwr; - /** WAL dbg stats */ - struct wlan_dbg_stats pdev_stats; + /** Channel noise floor */ + A_INT32 chan_nf; + /** TX frame count */ + A_UINT32 tx_frame_count; + /** RX frame count */ + A_UINT32 rx_frame_count; + /** rx clear count */ + A_UINT32 rx_clear_count; + /** cycle count */ + A_UINT32 cycle_count; + /** Phy error count */ + A_UINT32 phy_err_count; + /** Channel Tx Power */ + A_UINT32 chan_tx_pwr; + /** WAL dbg stats */ + struct wlan_dbg_stats pdev_stats; } wmi_pdev_stats; @@ -5107,26 +5569,26 @@ typedef struct { */ typedef struct { - A_INT32 bcn_snr; - A_INT32 dat_snr; + A_INT32 bcn_snr; + A_INT32 dat_snr; } wmi_snr_info; typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - wmi_snr_info vdev_snr; - A_UINT32 tx_frm_cnt[WLAN_MAX_AC];/* Total number of packets(per AC) that were successfully transmitted(with and without retries, including multi-cast, broadcast) */ - A_UINT32 rx_frm_cnt;/* Total number of packets that were successfully received (after appropriate filter rules including multi-cast, broadcast)*/ - A_UINT32 multiple_retry_cnt[WLAN_MAX_AC];/*The number of MSDU packets and MMPDU frames per AC - that the 802.11 station successfully transmitted after more than one retransmission attempt*/ - A_UINT32 fail_cnt[WLAN_MAX_AC]; /*Total number packets(per AC) failed to transmit */ - A_UINT32 rts_fail_cnt;/*Total number of RTS/CTS sequence failures for transmission of a packet*/ - A_UINT32 rts_succ_cnt;/*Total number of RTS/CTS sequence success for transmission of a packet*/ - A_UINT32 rx_err_cnt;/*The receive error count. HAL will provide the RxP FCS error global */ - A_UINT32 rx_discard_cnt;/* The sum of the receive error count and dropped-receive-buffer error count. (FCS error)*/ - A_UINT32 ack_fail_cnt;/*Total number packets failed transmit because of no ACK from the remote entity*/ - A_UINT32 tx_rate_history[MAX_TX_RATE_VALUES];/*History of last ten transmit rate, in units of 500 kbit/sec*/ - A_UINT32 bcn_rssi_history[MAX_RSSI_VALUES];/*History of last ten Beacon rssi of the connected Bss*/ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + wmi_snr_info vdev_snr; + A_UINT32 tx_frm_cnt[WLAN_MAX_AC]; /* Total number of packets(per AC) that were successfully transmitted(with and without retries, including multi-cast, broadcast) */ + A_UINT32 rx_frm_cnt; /* Total number of packets that were successfully received (after appropriate filter rules including multi-cast, broadcast) */ + A_UINT32 multiple_retry_cnt[WLAN_MAX_AC]; /*The number of MSDU packets and MMPDU frames per AC + that the 802.11 station successfully transmitted after more than one retransmission attempt */ + A_UINT32 fail_cnt[WLAN_MAX_AC]; /*Total number packets(per AC) failed to transmit */ + A_UINT32 rts_fail_cnt; /*Total number of RTS/CTS sequence failures for transmission of a packet */ + A_UINT32 rts_succ_cnt; /*Total number of RTS/CTS sequence success for transmission of a packet */ + A_UINT32 rx_err_cnt; /*The receive error count. HAL will provide the RxP FCS error global */ + A_UINT32 rx_discard_cnt; /* The sum of the receive error count and dropped-receive-buffer error count. (FCS error) */ + A_UINT32 ack_fail_cnt; /*Total number packets failed transmit because of no ACK from the remote entity */ + A_UINT32 tx_rate_history[MAX_TX_RATE_VALUES]; /*History of last ten transmit rate, in units of 500 kbit/sec */ + A_UINT32 bcn_rssi_history[MAX_RSSI_VALUES]; /*History of last ten Beacon rssi of the connected Bss */ } wmi_vdev_stats; /** @@ -5137,136 +5599,158 @@ typedef struct { * */ typedef struct { - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** rssi */ - A_UINT32 peer_rssi; - /** last tx data rate used for peer */ - A_UINT32 peer_tx_rate; - /** last rx data rate used for peer */ - A_UINT32 peer_rx_rate; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** rssi */ + A_UINT32 peer_rssi; + /** last tx data rate used for peer */ + A_UINT32 peer_tx_rate; + /** last rx data rate used for peer */ + A_UINT32 peer_rx_rate; } wmi_peer_stats; typedef struct { - /** Primary channel freq of the channel for which stats are sent */ - A_UINT32 chan_mhz; - /** Time spent on the channel */ - A_UINT32 sampling_period_us; - /** Aggregate duration over a sampling period for which channel activity was observed */ - A_UINT32 rx_clear_count; - /** Accumalation of the TX PPDU duration over a sampling period */ - A_UINT32 tx_duration_us; - /** Accumalation of the RX PPDU duration over a sampling period */ - A_UINT32 rx_duration_us; + /** Primary channel freq of the channel for which stats are sent */ + A_UINT32 chan_mhz; + /** Time spent on the channel */ + A_UINT32 sampling_period_us; + /** Aggregate duration over a sampling period for which channel activity was observed */ + A_UINT32 rx_clear_count; + /** Accumalation of the TX PPDU duration over a sampling period */ + A_UINT32 tx_duration_us; + /** Accumalation of the RX PPDU duration over a sampling period */ + A_UINT32 rx_duration_us; } wmi_chan_stats; typedef struct { - A_UINT32 tx_mpdu_grp_frag_cnt; /*dot11TransmittedFragmentCount */ - A_UINT32 tx_msdu_grp_frm_cnt; /*dot11GroupTransmittedFrameCount */ - A_UINT32 tx_msdu_fail_cnt; /*dot11FailedCount*/ - A_UINT32 rx_mpdu_frag_cnt; /*dot11ReceivedFragmentCount*/ - A_UINT32 rx_msdu_grp_frm_cnt; /*dot11GroupReceivedFrameCount*/ - A_UINT32 rx_mpdu_fcs_err; /*dot11FCSErrorCount*/ - A_UINT32 tx_msdu_frm_cnt; /*dot11TransmittedFrameCount*/ - A_UINT32 tx_msdu_retry_cnt; /*dot11RetryCount*/ - A_UINT32 rx_frm_dup_cnt; /*dot11FrameDuplicateCount */ - A_UINT32 tx_rts_success_cnt; /*dot11RTSSuccessCount*/ - A_UINT32 tx_rts_fail_cnt; /*dot11RTSFailureCount*/ - A_UINT32 tx_Qos_mpdu_grp_frag_cnt; /*dot11QosTransmittedFragmentCount */ - A_UINT32 tx_Qos_msdu_fail_UP; /*dot11QosFailedCount */ - A_UINT32 tx_Qos_msdu_retry_UP; /*dot11QosRetryCount */ - A_UINT32 rx_Qos_frm_dup_cnt_UP; /*dot11QosFrameDuplicateCount*/ - A_UINT32 tx_Qos_rts_success_cnt_UP; /*dot11QosRTSSuccessCount*/ - A_UINT32 tx_Qos_rts_fail_cnt_UP; /*dot11QosRTSFailureCount*/ - A_UINT32 rx_Qos_mpdu_frag_cnt_UP; /*dot11QosReceivedFragmentCount*/ - A_UINT32 tx_Qos_msdu_frm_cnt_UP; /*dot11QosTransmittedFrameCount*/ - A_UINT32 rx_Qos_msdu_discard_cnt_UP; /*dot11QosDiscardedFrameCount*/ - A_UINT32 rx_Qos_mpdu_cnt; /*dot11QosMPDUsReceivedCount*/ - A_UINT32 rx_Qos_mpdu_retryBit_cnt; /*dot11QosRetriesReceivedCount*/ - A_UINT32 rsna_Mgmt_discard_CCMP_replay_err_cnt; /*dot11RSNAStatsRobustMgmtCCMPReplays*/ - A_UINT32 rsna_TKIP_icv_err_cnt; /*dot11RSNAStatsTKIPICVErrors*/ - A_UINT32 rsna_TKIP_replay_err_cnt; /*dot11RSNAStatsTKIPReplays*/ - A_UINT32 rsna_CCMP_decrypt_err_cnt; /*dot11RSNAStatsCCMPDecryptErrors*/ - A_UINT32 rsna_CCMP_replay_err_cnt; /*dot11RSNAStatsCCMPReplays*/ - A_UINT32 tx_ampdu_cnt; /*dot11TransmittedAMPDUCount*/ - A_UINT32 tx_mpdu_cnt_in_ampdu; /*dot11TransmittedMPDUsInAMPDUCount*/ - union { - A_UINT64 counter; /* for use by target only */ - struct { - A_UINT32 low; - A_UINT32 high; - } upload; /* for use by host */ - } tx_octets_in_ampdu; /*dot11TransmittedOctetsInAMPDUCount*/ - A_UINT32 rx_ampdu_cnt; /*dot11AMPDUReceivedCount*/ - A_UINT32 rx_mpdu_cnt_in_ampdu; /*dot11MPDUInReceivedAMPDUCount*/ - union { - A_UINT64 counter; /* for use by target only */ - struct { - A_UINT32 rx_octets_in_ampdu_low; - A_UINT32 rx_octets_in_ampdu_high; - } upload; /* for use by host */ - } rx_octets_in_ampdu; /*dot11ReceivedOctetsInAMPDUCount*/ - A_UINT32 reserved_1; - A_UINT32 reserved_2; - A_UINT32 reserved_3; - A_UINT32 reserved_4; + A_UINT32 tx_mpdu_grp_frag_cnt; /*dot11TransmittedFragmentCount */ + A_UINT32 tx_msdu_grp_frm_cnt; /*dot11GroupTransmittedFrameCount */ + A_UINT32 tx_msdu_fail_cnt; /*dot11FailedCount*/ + A_UINT32 rx_mpdu_frag_cnt; /*dot11ReceivedFragmentCount*/ + A_UINT32 rx_msdu_grp_frm_cnt; /*dot11GroupReceivedFrameCount*/ + A_UINT32 rx_mpdu_fcs_err; /*dot11FCSErrorCount*/ + A_UINT32 tx_msdu_frm_cnt; /*dot11TransmittedFrameCount*/ + A_UINT32 tx_msdu_retry_cnt; /*dot11RetryCount*/ + A_UINT32 rx_frm_dup_cnt; /*dot11FrameDuplicateCount */ + A_UINT32 tx_rts_success_cnt; /*dot11RTSSuccessCount*/ + A_UINT32 tx_rts_fail_cnt; /*dot11RTSFailureCount*/ + /*dot11QosTransmittedFragmentCount */ + A_UINT32 tx_Qos_mpdu_grp_frag_cnt; + A_UINT32 tx_Qos_msdu_fail_UP; /*dot11QosFailedCount */ + A_UINT32 tx_Qos_msdu_retry_UP; /*dot11QosRetryCount */ + A_UINT32 rx_Qos_frm_dup_cnt_UP; /*dot11QosFrameDuplicateCount*/ + A_UINT32 tx_Qos_rts_success_cnt_UP; /*dot11QosRTSSuccessCount*/ + A_UINT32 tx_Qos_rts_fail_cnt_UP; /*dot11QosRTSFailureCount*/ + A_UINT32 rx_Qos_mpdu_frag_cnt_UP; /*dot11QosReceivedFragmentCount*/ + A_UINT32 tx_Qos_msdu_frm_cnt_UP; /*dot11QosTransmittedFrameCount*/ + A_UINT32 rx_Qos_msdu_discard_cnt_UP; /*dot11QosDiscardedFrameCount*/ + A_UINT32 rx_Qos_mpdu_cnt; /*dot11QosMPDUsReceivedCount*/ + A_UINT32 rx_Qos_mpdu_retryBit_cnt; /*dot11QosRetriesReceivedCount*/ + /*dot11RSNAStatsRobustMgmtCCMPReplays */ + A_UINT32 rsna_Mgmt_discard_CCMP_replay_err_cnt; + A_UINT32 rsna_TKIP_icv_err_cnt; /*dot11RSNAStatsTKIPICVErrors*/ + A_UINT32 rsna_TKIP_replay_err_cnt; /*dot11RSNAStatsTKIPReplays*/ + /*dot11RSNAStatsCCMPDecryptErrors */ + A_UINT32 rsna_CCMP_decrypt_err_cnt; + A_UINT32 rsna_CCMP_replay_err_cnt; /*dot11RSNAStatsCCMPReplays*/ + A_UINT32 tx_ampdu_cnt; /*dot11TransmittedAMPDUCount*/ + /*dot11TransmittedMPDUsInAMPDUCount*/ + A_UINT32 tx_mpdu_cnt_in_ampdu; + /*dot11TransmittedOctetsInAMPDUCount*/ + union { + A_UINT64 counter; /* for use by target only */ + struct { + A_UINT32 low; + A_UINT32 high; + } upload; /* for use by host */ + } tx_octets_in_ampdu; + A_UINT32 rx_ampdu_cnt; /*dot11AMPDUReceivedCount*/ + A_UINT32 rx_mpdu_cnt_in_ampdu; /*dot11MPDUInReceivedAMPDUCount*/ + union { + A_UINT64 counter; /* for use by target only */ + struct { + A_UINT32 rx_octets_in_ampdu_low; + A_UINT32 rx_octets_in_ampdu_high; + } upload; /* for use by host */ + } rx_octets_in_ampdu; /*dot11ReceivedOctetsInAMPDUCount*/ + A_UINT32 reserved_1; + A_UINT32 reserved_2; + A_UINT32 reserved_3; + A_UINT32 reserved_4; } wmi_mib_stats; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_stats */ - A_UINT32 vdev_id; - A_INT32 rssi_avg_beacon[WMI_MAX_CHAINS]; - A_INT32 rssi_avg_data[WMI_MAX_CHAINS]; - wmi_mac_addr peer_macaddr; + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_stats */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_INT32 rssi_avg_beacon[WMI_MAX_CHAINS]; + A_INT32 rssi_avg_data[WMI_MAX_CHAINS]; + wmi_mac_addr peer_macaddr; } wmi_rssi_stats; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats */ - A_UINT32 num_per_chain_rssi_stats; -/* This TLV is followed by another TLV of array of structs: - * wmi_rssi_stats rssi_stats[num_per_chain_rssi_stats]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats + */ + A_UINT32 tlv_header; + A_UINT32 num_per_chain_rssi_stats; + /* + * This TLV is followed by another TLV of array of structs: + * wmi_rssi_stats rssi_stats[num_per_chain_rssi_stats]; + */ } wmi_per_chain_rssi_stats; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** VDEV type (AP,STA,IBSS,MONITOR) */ - A_UINT32 vdev_type; - /** VDEV subtype (P2PDEV, P2PCLI, P2PGO, BT3.0)*/ - A_UINT32 vdev_subtype; - /** VDEV MAC address */ - wmi_mac_addr vdev_macaddr; - /** Number of configured txrx streams */ - A_UINT32 num_cfg_txrx_streams; - /** - * pdev_id for identifying the MAC, - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; -/* This TLV is followed by another TLV of array of structures - * wmi_vdev_txrx_streams cfg_txrx_streams[]; - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** VDEV type (AP,STA,IBSS,MONITOR) */ + A_UINT32 vdev_type; + /** VDEV subtype (P2PDEV, P2PCLI, P2PGO, BT3.0)*/ + A_UINT32 vdev_subtype; + /** VDEV MAC address */ + wmi_mac_addr vdev_macaddr; + /** Number of configured txrx streams */ + A_UINT32 num_cfg_txrx_streams; + /* + * pdev_id for identifying the MAC, + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* + * This TLV is followed by another TLV of array of structures + * wmi_vdev_txrx_streams cfg_txrx_streams[]; + */ } wmi_vdev_create_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_txrx_streams */ - /* band - Should take values from wmi_channel_band_mask */ - A_UINT32 band; - /* max supported tx streams per given band for this vdev */ - A_UINT32 supported_tx_streams; - /* max supported rx streams per given band for this vdev */ - A_UINT32 supported_rx_streams; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_txrx_streams + */ + A_UINT32 tlv_header; + /* band - Should take values from wmi_channel_band_mask */ + A_UINT32 band; + /* max supported tx streams per given band for this vdev */ + A_UINT32 supported_tx_streams; + /* max supported rx streams per given band for this vdev */ + A_UINT32 supported_rx_streams; } wmi_vdev_txrx_streams; /* wmi_p2p_noa_descriptor structure can't be modified without breaking the compatibility for WMI_HOST_SWBA_EVENTID */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_noa_descriptor */ - A_UINT32 type_count; /** 255: continuous schedule, 0: reserved */ - A_UINT32 duration; /** Absent period duration in micro seconds */ - A_UINT32 interval; /** Absent period interval in micro seconds */ - A_UINT32 start_time; /** 32 bit tsf time when in starts */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_noa_descriptor */ + A_UINT32 type_count; + /** 255: continuous schedule, 0: reserved */ + A_UINT32 duration; + /** Absent period duration in micro seconds */ + A_UINT32 interval; + /** Absent period interval in micro seconds */ + A_UINT32 start_time; + /** 32 bit tsf time when in starts */ } wmi_p2p_noa_descriptor; /** values for vdev_type */ @@ -5276,12 +5760,12 @@ typedef struct { #define WMI_VDEV_TYPE_MONITOR 0x4 /** VDEV type is for social wifi interface.This VDEV is Currently mainly needed -* by FW to execute the NAN specific WMI commands and also implement NAN specific -* operations like Network discovery, service provisioning and service -* subscription ..etc. If FW needs NAN VDEV then Host should issue VDEV create -* WMI command to create this VDEV once during initialization and host is not -* expected to use any VDEV specific WMI commands on this VDEV. -**/ + * by FW to execute the NAN specific WMI commands and also implement NAN specific + * operations like Network discovery, service provisioning and service + * subscription ..etc. If FW needs NAN VDEV then Host should issue VDEV create + * WMI command to create this VDEV once during initialization and host is not + * expected to use any VDEV specific WMI commands on this VDEV. + **/ #define WMI_VDEV_TYPE_NAN 0x5 #define WMI_VDEV_TYPE_OCB 0x6 @@ -5295,7 +5779,8 @@ typedef struct { #define WMI_UNIFIED_VDEV_SUBTYPE_P2P_GO 0x3 #define WMI_UNIFIED_VDEV_SUBTYPE_PROXY_STA 0x4 #define WMI_UNIFIED_VDEV_SUBTYPE_MESH 0x5 -/* new subtype for 11S mesh is required as 11S functionality differs +/* + * new subtype for 11S mesh is required as 11S functionality differs * in many ways from proprietary mesh * 11S uses 6-addr frame format and supports peering between mesh * stations and dynamic best path selection between mesh stations. @@ -5320,99 +5805,258 @@ typedef struct { */ #define WMI_UNIFIED_VDEV_START_BCN_TX_RATE_PRESENT (1<<2) +#define WMI_HEOPS_COLOR_GET(he_ops) WMI_GET_BITS(he_ops, 0, 6) +#define WMI_HEOPS_COLOR_SET(he_ops, value) WMI_SET_BITS(he_ops, 0, 6, value) + +#define WMI_HEOPS_DEFPE_GET(he_ops) WMI_GET_BITS(he_ops, 6, 3) +#define WMI_HEOPS_DEFPE_SET(he_ops, value) WMI_SET_BITS(he_ops, 6, 3, value) + +#define WMI_HEOPS_TWT_GET(he_ops) WMI_GET_BITS(he_ops, 9, 1) +#define WMI_HEOPS_TWT_SET(he_ops, value) WMI_SET_BITS(he_ops, 9, 1, value) + +#define WMI_HEOPS_RTSTHLD_GET(he_ops) WMI_GET_BITS(he_ops, 10, 7) +#define WMI_HEOPS_RTSTHLD_SET(he_ops, value) WMI_SET_BITS(he_ops, 10, 7, value) + +#define WMI_HEOPS_PDMIN_GET(he_ops) WMI_GET_BITS(he_ops, 17, 5) +#define WMI_HEOPS_PDMIN_SET(he_ops, value) WMI_SET_BITS(he_ops, 17, 5, value) + +#define WMI_HEOPS_PDMAX_GET(he_ops) WMI_GET_BITS(he_ops, 22, 5) +#define WMI_HEOPS_PDMAX_SET(he_ops, value) WMI_SET_BITS(he_ops, 22, 5, value) + +#define WMI_MAX_HECAP_PHY_SIZE (3) +#define WMI_HECAP_PHY_COD_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 0, 1) +#define WMI_HECAP_PHY_COD_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 0, 1, value) + +#define WMI_HECAP_PHY_TXLDPC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 1) +#define WMI_HECAP_PHY_TXLDPC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 1, value) + +#define WMI_HECAP_PHY_RXLDPC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 2, 1) +#define WMI_HECAP_PHY_RXLDPC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 2, 1, value) + +#define WMI_HECAP_PHY_DCM_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 3, 3) +#define WMI_HECAP_PHY_DCM_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 3, 3, value) + +#define WMI_HECAP_PHY_OLTF_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 6, 1) +#define WMI_HECAP_PHY_OLTF_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 6, 1, value) + +#define WMI_HECAP_PHY_CBW_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 7, 3) +#define WMI_HECAP_PHY_CBW_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 7, 3, value) + +#define WMI_HECAP_PHY_TXSTBC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 10, 1) +#define WMI_HECAP_PHY_TXSTBC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 10, 1, value) + +#define WMI_HECAP_PHY_RXSTBC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 11, 1) +#define WMI_HECAP_PHY_RXSTBC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 11, 1, value) + +#define WMI_HECAP_PHY_DLOFMAMUMIMO_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1) +#define WMI_HECAP_PHY_DLOFDMAMUMIO_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value) + +#define WMI_HECAP_PHY_UL_MU_MIMO_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1) +#define WMI_HECAP_PHY_UL_MU_MIMO_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value) + +#define WMI_HECAP_PHY_ULOFDMA_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1) +#define WMI_HECAP_PHY_ULOFDMA_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value) + +#define WMI_HECAP_PHY_TXDOPPLER_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 1) +#define WMI_HECAP_PHY_TXDOPPLER_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 1, value) + +#define WMI_HECAP_PHY_RXDOPPLER_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 16, 1) +#define WMI_HECAP_PHY_RXDOPPLER_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 16, 1, value) + +#define WMI_HECAP_PHY_CBMODE_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 8) +#define WMI_HECAP_PHY_CBMODE_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 8, value) + +#define WMI_HECAP_PHY_PADDING_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 25, 2) +#define WMI_HECAP_PHY_PADDING_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 25, 2, value) + +#define WMI_HECAP_PHY_32GI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 26) +#define WMI_HECAP_PHY_32GI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 26, value) + +#define WMI_HECAP_PHY_SUBFMR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1) +#define WMI_HECAP_PHY_SUBFMR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value) + +#define WMI_HECAP_PHY_SUBFME_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 1) +#define WMI_HECAP_PHY_SUBFME_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 1, value) + +#define WMI_HECAP_PHY_SUBFMESTS_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 28, 3) +#define WMI_HECAP_PHY_SUBFMESTS_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 28, 3, value) + +#define WMI_HECAP_PHY_NOSUNDIMENS_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 3) +#define WMI_HECAP_PHY_NOSUNDIMENS_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 3, value) + +#define WMI_HECAP_PHY_MUBFMR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1) +#define WMI_HECAP_PHY_MUBFMR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value) + +#define WMI_HECAP_PHY_40MHZNSS_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 18) +#define WMI_HECAP_PHY_40MHZNSS_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 18, value) + +#define WMI_HECAP_MAC_MTID_GET(he_cap) WMI_GET_BITS(he_cap, 0, 3) +#define WMI_HECAP_MAC_MTID_SET(he_cap, value) WMI_SET_BITS(he_cap, 0, 3, value) + +#define WMI_HECAP_MAC_AACK_GET(he_cap) WMI_GET_BITS(he_cap, 3, 1) +#define WMI_HECAP_MAC_AACK_SET(he_cap, value) WMI_SET_BITS(he_cap, 3, 1, value) + +#define WMI_HECAP_MAC_MINFRAGSZ_GET(he_cap) WMI_GET_BITS(he_cap, 4, 2) +#define WMI_HECAP_MAC_MINFRAGSZ_SET(he_cap, value) WMI_SET_BITS(he_cap, 4, 2, value) + +#define WMI_HECAP_MAC_HEFRAG_GET(he_cap) WMI_GET_BITS(he_cap, 6, 2) +#define WMI_HECAP_MAC_HEFRAG_SET(he_cap, value) WMI_SET_BITS(he_cap, 6, 2, value) + +#define WMI_HECAP_MAC_MURTS_GET(he_cap) WMI_GET_BITS(he_cap, 8, 1) +#define WMI_HECAP_MAC_MURTS_SET(he_cap, value) WMI_SET_BITS(he_cap, 8, 1, value) + +#define WMI_HECAP_MAC_OMI_GET(he_cap) WMI_GET_BITS(he_cap, 9, 1) +#define WMI_HECAP_MAC_OMI_SET(he_cap, value) WMI_SET_BITS(he_cap, 9, 1, value) + +#define WMI_HECAP_MAC_HECTRL_GET(he_cap) WMI_GET_BITS(he_cap, 10, 1) +#define WMI_HECAP_MAC_HECTRL_SET(he_cap, value) WMI_SET_BITS(he_cap, 10, 1, value) + +#define WMI_HECAP_MAC_MBAHECTRL_GET(he_cap) WMI_GET_BITS(he_cap, 11, 1) +#define WMI_HECAP_MAC_MBAHECTRL_SET(he_cap, value) WMI_SET_BITS(he_cap, 11, 1, value) + +#define WMI_HECAP_MAC_ULMURSP_GET(he_cap) WMI_GET_BITS(he_cap, 12, 1) +#define WMI_HECAP_MAC_ULMURSP_SET(he_cap, value) WMI_SET_BITS(he_cap, 12, 1, value) + +#define WMI_HECAP_MAC_HELKAD_GET(he_cap) WMI_GET_BITS(he_cap, 13, 2) +#define WMI_HECAP_MAC_HELKAD_SET(he_cap, value) WMI_SET_BITS(he_cap, 13, 2, value) + +#define WMI_HECAP_MAC_BSR_GET(he_cap) WMI_GET_BITS(he_cap, 15, 1) +#define WMI_HECAP_MAC_BSR_SET(he_cap, value) WMI_SET_BITS(he_cap, 15, 1, value) + +#define WMI_HECAP_MAC_TWTREQ_GET(he_cap) WMI_GET_BITS(he_cap, 16, 1) +#define WMI_HECAP_MAC_TWTREQ_SET(he_cap, value) WMI_SET_BITS(he_cap, 16, 1, value) + +#define WMI_HECAP_MAC_TWTRSP_GET(he_cap) WMI_GET_BITS(he_cap, 17, 1) +#define WMI_HECAP_MAC_TWTRSP_SET(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value) + +#define WMI_HECAP_MAC_BCSTTWT_GET(he_cap) WMI_GET_BITS(he_cap, 18, 1) +#define WMI_HECAP_MAC_BCSTTWT_SET(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value) + +#define WMI_HECAP_MAC_MBSS_GET(he_cap) WMI_GET_BITS(he_cap, 19, 1) +#define WMI_HECAP_MAC_MBSS_SET(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value) + +#define WMI_HECAP_MAC_TRIGPADDUR_GET(he_cap) WMI_GET_BITS(he_cap, 20, 2) +#define WMI_HECAP_MAC_TRIGPADDUR_SET(he_cap, value) WMI_SET_BITS(he_cap, 20, 2, value) + +#define WMI_HECAP_MAC_MAXFRAGMSDU_GET(he_cap) WMI_GET_BITS(he_cap, 22, 3) +#define WMI_HECAP_MAC_MAXFRAGMSDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 22, 3, value) + +#define WMI_HECAP_MAC_32BITBA_GET(he_cap) WMI_GET_BITS(he_cap, 25, 1) +#define WMI_HECAP_MAC_32BITBA_SET(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value) + +#define WMI_HECAP_MAC_MUCASCADE_GET(he_cap) WMI_GET_BITS(he_cap, 26, 1) +#define WMI_HECAP_MAC_MUCASCADE_SET(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value) + +#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET(he_cap) WMI_GET_BITS(he_cap, 27, 1) +#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 27, 1, value) + +#define WMI_HECAP_MAC_GROUPMSTABA_GET(he_cap) WMI_GET_BITS(he_cap, 28, 1) +#define WMI_HECAP_MAC_GROUPMSTABA_SET(he_cap, value) WMI_SET_BITS(he_cap, 28, 1, value) + +#define WMI_HECAP_MAC_OFDMARA_GET(he_cap) WMI_GET_BITS(he_cap, 29, 1) +#define WMI_HECAP_MAC_OFDMARA_SET(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value) + typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** requestor id identifying the caller module */ - A_UINT32 requestor_id; - /** beacon interval from received beacon */ - A_UINT32 beacon_interval; - /** DTIM Period from the received beacon */ - A_UINT32 dtim_period; - /** Flags */ - A_UINT32 flags; - /** ssid field. Only valid for AP/GO/IBSS/BTAmp VDEV type. */ - wmi_ssid ssid; - /** beacon/probe reponse xmit rate. Applicable for SoftAP. */ - /** This field will be invalid and ignored unless the */ - /** flags field has the WMI_UNIFIED_VDEV_START_BCN_TX_RATE_PRESENT bit. */ - /** When valid, this field contains the fixed tx rate for the beacon */ - /** and probe response frames send by the GO or SoftAP */ - A_UINT32 bcn_tx_rate; - /** beacon/probe reponse xmit power. Applicable for SoftAP. */ - A_UINT32 bcn_txPower; - /** number of p2p NOA descriptor(s) from scan entry */ - A_UINT32 num_noa_descriptors; - /** Disable H/W ack. This used by WMI_VDEV_RESTART_REQUEST_CMDID. - During CAC, Our HW shouldn't ack ditected frames */ - A_UINT32 disable_hw_ack; - /** This field will be invalid unless the Dual Band Simultaneous (DBS) feature is enabled. */ - /** The DBS policy manager indicates the preferred number of transmit streams. */ - A_UINT32 preferred_tx_streams; - /** This field will be invalid unless the Dual Band Simultaneous (DBS) feature is enabled. */ - /** the DBS policy manager indicates the preferred number of receive streams. */ - A_UINT32 preferred_rx_streams; -/* The TLVs follows this structure: - * wmi_channel chan; <-- WMI channel - * wmi_p2p_noa_descriptor noa_descriptors[]; <-- actual p2p NOA descriptor from scan entry - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** requestor id identifying the caller module */ + A_UINT32 requestor_id; + /** beacon interval from received beacon */ + A_UINT32 beacon_interval; + /** DTIM Period from the received beacon */ + A_UINT32 dtim_period; + /** Flags */ + A_UINT32 flags; + /** ssid field. Only valid for AP/GO/IBSS/BTAmp VDEV type. */ + wmi_ssid ssid; + /** beacon/probe reponse xmit rate. Applicable for SoftAP. */ + /** This field will be invalid and ignored unless the */ + /** flags field has the WMI_UNIFIED_VDEV_START_BCN_TX_RATE_PRESENT bit. */ + /** When valid, this field contains the fixed tx rate for the beacon */ + /** and probe response frames send by the GO or SoftAP */ + A_UINT32 bcn_tx_rate; + /** beacon/probe reponse xmit power. Applicable for SoftAP. */ + A_UINT32 bcn_txPower; + /** number of p2p NOA descriptor(s) from scan entry */ + A_UINT32 num_noa_descriptors; + /** Disable H/W ack. This used by WMI_VDEV_RESTART_REQUEST_CMDID. + During CAC, Our HW shouldn't ack ditected frames */ + A_UINT32 disable_hw_ack; + /** This field will be invalid unless the Dual Band Simultaneous (DBS) feature is enabled. */ + /** The DBS policy manager indicates the preferred number of transmit streams. */ + A_UINT32 preferred_tx_streams; + /** This field will be invalid unless the Dual Band Simultaneous (DBS) feature is enabled. */ + /** the DBS policy manager indicates the preferred number of receive streams. */ + A_UINT32 preferred_rx_streams; + A_UINT32 he_ops; /* refer to WMI_HEOPS_xxx macros */ + A_UINT32 cac_duration_ms; /* in milliseconds */ + A_UINT32 regdomain; + /* The TLVs follows this structure: + * wmi_channel chan; //WMI channel + * wmi_p2p_noa_descriptor noa_descriptors[]; //actual p2p NOA descriptor from scan entry + */ } wmi_vdev_start_request_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_delete_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_delete_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_delete_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_up_cmdid_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** aid (assoc id) received in association response for STA VDEV */ - A_UINT32 vdev_assoc_id; - /** bssid of the BSS the VDEV is joining */ - wmi_mac_addr vdev_bssid; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_up_cmdid_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** aid (assoc id) received in association response for STA VDEV */ + A_UINT32 vdev_assoc_id; + /** bssid of the BSS the VDEV is joining */ + wmi_mac_addr vdev_bssid; } wmi_vdev_up_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_stop_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_down_cmd_fixed_param; typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_standby_response_cmd; typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_resume_response_cmd; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_param_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** parameter id */ - A_UINT32 param_id; - /** parameter value */ - A_UINT32 param_value; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_param_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** parameter id */ + A_UINT32 param_id; + /** parameter value */ + A_UINT32 param_value; } wmi_vdev_set_param_cmd_fixed_param; typedef struct { - A_UINT32 key_seq_counter_l; - A_UINT32 key_seq_counter_h; + A_UINT32 key_seq_counter_l; + A_UINT32 key_seq_counter_h; } wmi_key_seq_counter; -#define WMI_CIPHER_NONE 0x0 /* clear key */ +#define WMI_CIPHER_NONE 0x0 /* clear key */ #define WMI_CIPHER_WEP 0x1 #define WMI_CIPHER_TKIP 0x2 #define WMI_CIPHER_AES_OCB 0x3 @@ -5425,45 +6069,47 @@ typedef struct { #define WMI_CIPHER_AES_GMAC 0xa typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** MAC address used for installing */ - wmi_mac_addr peer_macaddr; - /** key index */ - A_UINT32 key_ix; - /** key flags */ - A_UINT32 key_flags; - /** key cipher, defined above */ - A_UINT32 key_cipher; - /** key rsc counter */ - wmi_key_seq_counter key_rsc_counter; - /** global key rsc counter */ - wmi_key_seq_counter key_global_rsc_counter; - /** global key tsc counter */ - wmi_key_seq_counter key_tsc_counter; - /** WAPI key rsc counter */ - A_UINT8 wpi_key_rsc_counter[16]; - /** WAPI key tsc counter */ - A_UINT8 wpi_key_tsc_counter[16]; - /** key length */ - A_UINT32 key_len; - /** key tx mic length */ - A_UINT32 key_txmic_len; - /** key rx mic length */ - A_UINT32 key_rxmic_len; -/* - * Following this struct are this TLV. - * A_UINT8 key_data[]; <-- actual key data; contains key followed by tx mic followed by rx mic - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** MAC address used for installing */ + wmi_mac_addr peer_macaddr; + /** key index */ + A_UINT32 key_ix; + /** key flags */ + A_UINT32 key_flags; + /** key cipher, defined above */ + A_UINT32 key_cipher; + /** key rsc counter */ + wmi_key_seq_counter key_rsc_counter; + /** global key rsc counter */ + wmi_key_seq_counter key_global_rsc_counter; + /** global key tsc counter */ + wmi_key_seq_counter key_tsc_counter; + /** WAPI key rsc counter */ + A_UINT8 wpi_key_rsc_counter[16]; + /** WAPI key tsc counter */ + A_UINT8 wpi_key_tsc_counter[16]; + /** key length */ + A_UINT32 key_len; + /** key tx mic length */ + A_UINT32 key_txmic_len; + /** key rx mic length */ + A_UINT32 key_rxmic_len; + /* + * Following this struct are this TLV. + * // actual key data + * A_UINT8 key_data[]; // contains key followed by tx mic followed by rx mic + */ } wmi_vdev_install_key_cmd_fixed_param; /** Preamble types to be used with VDEV fixed rate configuration */ typedef enum { - WMI_RATE_PREAMBLE_OFDM, - WMI_RATE_PREAMBLE_CCK, - WMI_RATE_PREAMBLE_HT, - WMI_RATE_PREAMBLE_VHT, + WMI_RATE_PREAMBLE_OFDM, + WMI_RATE_PREAMBLE_CCK, + WMI_RATE_PREAMBLE_HT, + WMI_RATE_PREAMBLE_VHT, } WMI_RATE_PREAMBLE; /** Value to disable fixed rate setting */ @@ -5471,408 +6117,406 @@ typedef enum { /** the definition of different VDEV parameters */ typedef enum { - /** RTS Threshold */ - WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, - /** Fragmentation threshold */ - WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, - /** beacon interval in TUs */ - WMI_VDEV_PARAM_BEACON_INTERVAL, - /** Listen interval in TUs */ - WMI_VDEV_PARAM_LISTEN_INTERVAL, - /** muticast rate in Mbps */ - WMI_VDEV_PARAM_MULTICAST_RATE, - /** management frame rate in Mbps */ - WMI_VDEV_PARAM_MGMT_TX_RATE, - /** slot time (long vs short) */ - WMI_VDEV_PARAM_SLOT_TIME, - /** preamble (long vs short) */ - WMI_VDEV_PARAM_PREAMBLE, - /** SWBA time (time before tbtt in msec) */ - WMI_VDEV_PARAM_SWBA_TIME, - /** time period for updating VDEV stats */ - WMI_VDEV_STATS_UPDATE_PERIOD, - /** age out time in msec for frames queued for station in power save*/ - WMI_VDEV_PWRSAVE_AGEOUT_TIME, - /** Host SWBA interval (time in msec before tbtt for SWBA event generation) */ - WMI_VDEV_HOST_SWBA_INTERVAL, - /** DTIM period (specified in units of num beacon intervals) */ - WMI_VDEV_PARAM_DTIM_PERIOD, - /** scheduler air time limit for this VDEV. used by off chan scheduler */ - WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, - /** enable/dsiable WDS for this VDEV */ - WMI_VDEV_PARAM_WDS, - /** ATIM Window */ - WMI_VDEV_PARAM_ATIM_WINDOW, - /** BMISS max */ - WMI_VDEV_PARAM_BMISS_COUNT_MAX, - /** BMISS first time */ - WMI_VDEV_PARAM_BMISS_FIRST_BCNT, - /** BMISS final time */ - WMI_VDEV_PARAM_BMISS_FINAL_BCNT, - /** WMM enables/disabled */ - WMI_VDEV_PARAM_FEATURE_WMM, - /** Channel width */ - WMI_VDEV_PARAM_CHWIDTH, - /** Channel Offset */ - WMI_VDEV_PARAM_CHEXTOFFSET, - /** Disable HT Protection */ - WMI_VDEV_PARAM_DISABLE_HTPROTECTION, - /** Quick STA Kickout */ - WMI_VDEV_PARAM_STA_QUICKKICKOUT, - /** Rate to be used with Management frames */ - WMI_VDEV_PARAM_MGMT_RATE, - /** Protection Mode */ - WMI_VDEV_PARAM_PROTECTION_MODE, - /** Fixed rate setting */ - WMI_VDEV_PARAM_FIXED_RATE, - /** Short GI Enable/Disable */ - WMI_VDEV_PARAM_SGI, - /** Enable LDPC */ - WMI_VDEV_PARAM_LDPC, - /** Enable Tx STBC */ - WMI_VDEV_PARAM_TX_STBC, - /** Enable Rx STBC */ - WMI_VDEV_PARAM_RX_STBC, - /** Intra BSS forwarding */ - WMI_VDEV_PARAM_INTRA_BSS_FWD, - /** Setting Default xmit key for Vdev */ - WMI_VDEV_PARAM_DEF_KEYID, - /** NSS width */ - WMI_VDEV_PARAM_NSS, - /** Set the custom rate for the broadcast data frames */ - WMI_VDEV_PARAM_BCAST_DATA_RATE, - /** Set the custom rate (rate-code) for multicast data frames */ - WMI_VDEV_PARAM_MCAST_DATA_RATE, - /** Tx multicast packet indicate Enable/Disable */ - WMI_VDEV_PARAM_MCAST_INDICATE, - /** Tx DHCP packet indicate Enable/Disable */ - WMI_VDEV_PARAM_DHCP_INDICATE, - /** Enable host inspection of Tx unicast packet to unknown destination */ - WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, - - /* The minimum amount of time AP begins to consider STA inactive */ - WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, - - /* An associated STA is considered inactive when there is no recent TX/RX - * activity and no downlink frames are buffered for it. Once a STA exceeds - * the maximum idle inactive time, the AP will send an 802.11 data-null as - * a keep alive to verify the STA is still associated. If the STA does ACK - * the data-null, or if the data-null is buffered and the STA does not - * retrieve it, the STA will be considered unresponsive (see - * WMI_VDEV_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS). */ - WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, - - /* An associated STA is considered unresponsive if there is no recent - * TX/RX activity and downlink frames are buffered for it. Once a STA - * exceeds the maximum unresponsive time, the AP will send a - * WMI_STA_KICKOUT event to the host so the STA can be deleted. */ - WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, - - /* Enable NAWDS : MCAST INSPECT Enable, NAWDS Flag set */ - WMI_VDEV_PARAM_AP_ENABLE_NAWDS, - /** Enable/Disable RTS-CTS */ - WMI_VDEV_PARAM_ENABLE_RTSCTS, - /* Enable TXBFee/er */ - WMI_VDEV_PARAM_TXBF, - - /**Set packet power save */ - WMI_VDEV_PARAM_PACKET_POWERSAVE, - - /**Drops un-encrypted packets if any received in an encryted connection - * otherwise forwards to host - */ - WMI_VDEV_PARAM_DROP_UNENCRY, - - /* - * Set TX encap type. - * - * enum wmi_pkt_type is to be used as the parameter - * specifying the encap type. - */ - WMI_VDEV_PARAM_TX_ENCAP_TYPE, - - /* - * Try to detect stations that woke-up and exited power save but did not - * successfully transmit data-null with PM=0 to AP. When this happens, - * STA and AP power save state are out-of-sync. Use buffered but - * undelivered MSDU to the STA as a hint that the STA is really awake - * and expecting normal ASAP delivery, rather than retrieving BU with - * PS-Poll, U-APSD trigger, etc. - * - * 0 disables out-of-sync detection. Maximum time is 255 seconds. - */ - WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, - - /* Enable/Disable early rx dynamic adjust feature. - * Early-rx dynamic adjust is a advance power save feature. - * Early-rx is a wakeup duration before exact TBTT,which is deemed necessary to provide a cushion for various - * timing discrepancies in the system. - * In current code branch, the duration is set to a very conservative fix value to make sure the drift impact is minimum. - * The fix early-tx will result in the unnessary power consume, so a dynamic early-rx adjust algorithm can be designed - * properly to minimum the power consume.*/ - WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, - - /* set target bmiss number per sample cycle if bmiss adjust was chosen. - * In this adjust policy,early-rx is adjusted by comparing the current bmiss rate to target bmiss rate - * which can be set by user through WMI command. - */ - WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, - - /* set sample cycle(in the unit of beacon interval) if bmiss adjust was chosen */ - WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, - - /* set slop_step */ - WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, - - /* set init slop */ - WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, - - /* pause adjust enable/disable */ - WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, - - - /* Set channel pwr limit value of the vdev the minimal value of all - * vdevs operating on this channel will be set as channel tx power - * limit, which is used to configure ratearray - */ - WMI_VDEV_PARAM_TX_PWRLIMIT, - - /* set the count of snr value for calculation in snr monitor */ - WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, - - /** Roaming offload */ - WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, - - /** Enable Leader request RX functionality for RMC */ - WMI_VDEV_PARAM_ENABLE_RMC, - - /* IBSS does not have deauth/disassoc, vdev has to detect peer gone event - * by himself. If the beacon lost time exceed this threshold, the peer is - * thought to be gone. */ - WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, - - /** max rate in kpbs, transmit rate can't go beyond it */ - WMI_VDEV_PARAM_MAX_RATE, - - /* enable/disable drift sample. 0: disable; 1: clk_drift; 2: ap_drift; 3 both clk and ap drift*/ - WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, - - /* set Tx failure count threshold for the vdev */ - WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, - - /* set ebt resync timeout value, in the unit of TU */ - WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, - - /* Enable Aggregation State Trigger Event */ - WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, - - /* This parameter indicates whether IBSS station can enter into power save - * mode by sending Null frame (with PM=1). When not allowed, IBSS station has to stay - * awake all the time and should never set PM=1 in its transmitted frames. - * This parameter is meaningful/valid only when WMI_VDEV_PARAM_ATIM_WINDOW_LENGTH - * is non-zero. */ - WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, - - /* This parameter indicates if this station can enter into power collapse - * for the remaining beacon interval after the ATIM window. - * This parameter is meaningful/valid only when WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED - * is set to TRUE. */ - WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, - - /* This parameter indicates whether IBSS station exit power save mode and - * enter power active state (by sending Null frame with PM=0 in the immediate ATIM Window) - * whenever there is a TX/RX activity. */ - WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, - - /* If Awake on TX/RX activity is enabled, this parameter indicates - * the data inactivity time in number of beacon intervals after which - * IBSS station reenters power save by sending Null frame with PM=1. */ - WMI_VDEV_PARAM_INACTIVITY_CNT, - - /* Inactivity time in msec after which TX Service Period (SP) is - * terminated by sending a Qos Null frame with EOSP. - * If value is 0, TX SP is terminated with the last buffered packet itself - * instead of waiting for the inactivity timeout. */ - WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, - - /** DTIM policy */ - WMI_VDEV_PARAM_DTIM_POLICY, - - /* When IBSS network is initialized, PS-supporting device - * does not enter protocol sleep state during first - * WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS seconds. */ - WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, - - /* Enable/Disable 1 RX chain usage during the ATIM window */ - WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, - - /* RX Leak window is the time driver waits before shutting down - * the radio or switching the channel and after receiving an ACK - * for a data frame with PM bit set) */ - WMI_VDEV_PARAM_RX_LEAK_WINDOW, - - /** Averaging factor(16 bit value) is used in the calculations to - * perform averaging of different link level statistics like average - * beacon spread or average number of frames leaked */ - WMI_VDEV_PARAM_STATS_AVG_FACTOR, - - /** disconnect threshold, once the consecutive error for specific peer - * exceed this threhold, FW will send kickout event to host */ - WMI_VDEV_PARAM_DISCONNECT_TH, - - /** The rate_code of RTS_CTS changed by host. Now FW can support - * more non-HT rates rather than 1Mbps or 6Mbps */ - WMI_VDEV_PARAM_RTSCTS_RATE, - - /** This parameter indicates whether using a long duration RTS-CTS - * protection when a SAP goes off channel in MCC mode */ - WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, - - /** This parameter indicates whether using a broadcast probe response - * to increase the detectability of SAP in MCC mode */ - WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, - - /** This parameter indicates the power backoff in percentage - * currently supports 100%, 50%, 25%, 12.5%, and minimum - * Host passes 0, 1, 2, 3, 4 to Firmware - * 0 --> 100% --> no changes, 1 --> 50% --> -3dB, - * 2 --> 25% --> -6dB, 3 --> 12.5% --> -9dB, 4 --> minimum --> -32dB - */ - WMI_VDEV_PARAM_TXPOWER_SCALE, - - /** TX power backoff in dB: tx power -= param value - * Host passes values(DB) to Halphy, Halphy reduces the power table - * by the values. Safety check will happen in Halphy. - */ - WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, - - /** Multicast to Unicast conversion setting */ - WMI_VDEV_PARAM_MCAST2UCAST_SET, - - /** Total number of HW retries */ - WMI_VDEV_PARAM_RC_NUM_RETRIES, - - /** Max tx percentage for cabq */ - WMI_VDEV_PARAM_CABQ_MAXDUR, - - /** MFPTEST settings */ - WMI_VDEV_PARAM_MFPTEST_SET, - - /** RTS Fixed rate setting */ - WMI_VDEV_PARAM_RTS_FIXED_RATE, - - /** VHT SGI MASK */ - WMI_VDEV_PARAM_VHT_SGIMASK, - - /** VHT80 Auto Rate MASK */ - WMI_VDEV_PARAM_VHT80_RATEMASK, - - /** set Proxy STA features for this vap */ - WMI_VDEV_PARAM_PROXY_STA, - - /** set virtual cell mode - enable/disable */ - WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, - - /** Set receive packet type */ - WMI_VDEV_PARAM_RX_DECAP_TYPE, - - /** Set ratemask with specific Bandwidth and NSS */ - WMI_VDEV_PARAM_BW_NSS_RATEMASK, - - /** Set SENSOR Support */ - WMI_VDEV_PARAM_SENSOR_AP, - - /** Set beacon rate */ - WMI_VDEV_PARAM_BEACON_RATE, - - /** Enable CTS to self for DTIM beacon */ - WMI_VDEV_PARAM_DTIM_ENABLE_CTS, - - /** Disable station kickout at Vap level */ - WMI_VDEV_PARAM_STA_KICKOUT, - - /* VDEV capabilities */ - WMI_VDEV_PARAM_CAPABILITIES, /* see capabilities defs below */ - - /** - * Increment TSF in micro seconds to avoid beacon collision on mesh VAP. - * The host must ensure that either no other vdevs share the TSF with - * this vdev, or else that it is acceptable to apply this TSF adjustment - * to all vdevs sharing the TSF. - */ - WMI_VDEV_PARAM_TSF_INCREMENT, - - /** Disable/Enable AMPDU of vdev per AC: - * bit | AC - * -------- - * 0 | VO - * 1 | VI - * 2 | BE - * 3 | BK - * A value of 0 in a given bit disables A-MPDU aggregation for - * that AC; a value of 1 enables A-MPDU aggregation - */ - WMI_VDEV_PARAM_AMPDU_PER_AC, - - /** - * Vdev level rx filter of from-ds / to-ds / no-ds / ta / ra frames. - * Used mainly for mesh-vap. - * The parameter value delivered with the RX_FILTER vdev param contains - * a bit-or mask of wmi_vdev_param_filter enum values. - */ - WMI_VDEV_PARAM_RX_FILTER, - - /** vdev-specific mgmt tx power in dBm units (signed integer value) */ - WMI_VDEV_PARAM_MGMT_TX_POWER, - - /** Vdev level non aggregration/11g sw retry threshold. 0-disable, min:0, max:31, default:15 */ - WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, - /** Vdev level aggregration sw retry threshold. 0-disable, min:0, max:31, default:15 */ - WMI_VDEV_PARAM_AGG_SW_RETRY_TH, - - /** disable dynamic bw RTS **/ - WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, - - /** per ssid (vdev) based ATF strict/fair scheduling policy - * param values are WMI_ATF_SSID_FAIR_SCHED or WMI_ATF_SSID_STRICT_SCHED - */ - WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, - - - /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === - * The below vdev param types are used for prototyping, and are - * prone to change. - */ - WMI_VDEV_PARAM_PROTOTYPE = 0x8000, - /* 11AX SPECIFIC defines */ - WMI_VDEV_PARAM_BSS_COLOR, - /* In case of AP this will enable / disable MU-MIMO mode */ - WMI_VDEV_PARAM_SET_UL_MU_MIMO, - /* set fragmentation level of the vdev's peers. - * Values can be WMI_HE_FRAG_SUPPORT_LEVEL0..WMI_HE_FRAG_SUPPORT_LEVEL3 - */ - WMI_VDEV_PARAM_SET_FRAG_LEVEL, - /* control different features of HEControl: - * Bit 0:- 1/0-> Enable/Disable transmssion of UL scheduling. - * Bit 1:- 1/0-> Enable / disable honoring of ROMI from a peer. - * Applicable in AP mode only. - */ - WMI_VDEV_PARAM_SET_HECONTROL, - /* enable / disable trigger access for a AP vdev's peers. - * For a STA mode vdev this will enable/disable triggered access - * and enable/disable Multi User mode of operation. - */ - WMI_VDEV_PARAM_SET_HEMU_MODE, - /* For Tx OFDMA this will set values of CP length or guard interval - * to be - * 0: Auto - * 1: 0.8 us - * 2: 1.6 us - * 3: 3.2 us - * Similar to Guard Interval - */ - WMI_VDEV_PARAM_TX_OFDMA_CPLEN, - /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ + /** RTS Threshold */ + WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, + /** Fragmentation threshold */ + WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, + /** beacon interval in TUs */ + WMI_VDEV_PARAM_BEACON_INTERVAL, + /** Listen interval in TUs */ + WMI_VDEV_PARAM_LISTEN_INTERVAL, + /** muticast rate in Mbps */ + WMI_VDEV_PARAM_MULTICAST_RATE, + /** management frame rate in Mbps */ + WMI_VDEV_PARAM_MGMT_TX_RATE, + /** slot time (long vs short) */ + WMI_VDEV_PARAM_SLOT_TIME, + /** preamble (long vs short) */ + WMI_VDEV_PARAM_PREAMBLE, + /** SWBA time (time before tbtt in msec) */ + WMI_VDEV_PARAM_SWBA_TIME, + /** time period for updating VDEV stats */ + WMI_VDEV_STATS_UPDATE_PERIOD, + /** age out time in msec for frames queued for station in power save*/ + WMI_VDEV_PWRSAVE_AGEOUT_TIME, + /** Host SWBA interval (time in msec before tbtt for SWBA event generation) */ + WMI_VDEV_HOST_SWBA_INTERVAL, + /** DTIM period (specified in units of num beacon intervals) */ + WMI_VDEV_PARAM_DTIM_PERIOD, + /** scheduler air time limit for this VDEV. used by off chan scheduler */ + WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, + /** enable/dsiable WDS for this VDEV */ + WMI_VDEV_PARAM_WDS, + /** ATIM Window */ + WMI_VDEV_PARAM_ATIM_WINDOW, + /** BMISS max */ + WMI_VDEV_PARAM_BMISS_COUNT_MAX, + /** BMISS first time */ + WMI_VDEV_PARAM_BMISS_FIRST_BCNT, + /** BMISS final time */ + WMI_VDEV_PARAM_BMISS_FINAL_BCNT, + /** WMM enables/disabled */ + WMI_VDEV_PARAM_FEATURE_WMM, + /** Channel width */ + WMI_VDEV_PARAM_CHWIDTH, + /** Channel Offset */ + WMI_VDEV_PARAM_CHEXTOFFSET, + /** Disable HT Protection */ + WMI_VDEV_PARAM_DISABLE_HTPROTECTION, + /** Quick STA Kickout */ + WMI_VDEV_PARAM_STA_QUICKKICKOUT, + /** Rate to be used with Management frames */ + WMI_VDEV_PARAM_MGMT_RATE, + /** Protection Mode */ + WMI_VDEV_PARAM_PROTECTION_MODE, + /** Fixed rate setting */ + WMI_VDEV_PARAM_FIXED_RATE, + /** Short GI Enable/Disable */ + WMI_VDEV_PARAM_SGI, + /** Enable LDPC */ + WMI_VDEV_PARAM_LDPC, + /** Enable Tx STBC */ + WMI_VDEV_PARAM_TX_STBC, + /** Enable Rx STBC */ + WMI_VDEV_PARAM_RX_STBC, + /** Intra BSS forwarding */ + WMI_VDEV_PARAM_INTRA_BSS_FWD, + /** Setting Default xmit key for Vdev */ + WMI_VDEV_PARAM_DEF_KEYID, + /** NSS width */ + WMI_VDEV_PARAM_NSS, + /** Set the custom rate for the broadcast data frames */ + WMI_VDEV_PARAM_BCAST_DATA_RATE, + /** Set the custom rate (rate-code) for multicast data frames */ + WMI_VDEV_PARAM_MCAST_DATA_RATE, + /** Tx multicast packet indicate Enable/Disable */ + WMI_VDEV_PARAM_MCAST_INDICATE, + /** Tx DHCP packet indicate Enable/Disable */ + WMI_VDEV_PARAM_DHCP_INDICATE, + /** Enable host inspection of Tx unicast packet to unknown destination */ + WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, + + /* The minimum amount of time AP begins to consider STA inactive */ + WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, + + /* An associated STA is considered inactive when there is no recent TX/RX + * activity and no downlink frames are buffered for it. Once a STA exceeds + * the maximum idle inactive time, the AP will send an 802.11 data-null as + * a keep alive to verify the STA is still associated. If the STA does ACK + * the data-null, or if the data-null is buffered and the STA does not + * retrieve it, the STA will be considered unresponsive (see + * WMI_VDEV_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS). */ + WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, + + /* An associated STA is considered unresponsive if there is no recent + * TX/RX activity and downlink frames are buffered for it. Once a STA + * exceeds the maximum unresponsive time, the AP will send a + * WMI_STA_KICKOUT event to the host so the STA can be deleted. */ + WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, + + /* Enable NAWDS : MCAST INSPECT Enable, NAWDS Flag set */ + WMI_VDEV_PARAM_AP_ENABLE_NAWDS, + /** Enable/Disable RTS-CTS */ + WMI_VDEV_PARAM_ENABLE_RTSCTS, + /* Enable TXBFee/er */ + WMI_VDEV_PARAM_TXBF, + + /**Set packet power save */ + WMI_VDEV_PARAM_PACKET_POWERSAVE, + + /**Drops un-encrypted packets if any received in an encryted connection + * otherwise forwards to host + */ + WMI_VDEV_PARAM_DROP_UNENCRY, + + /* + * Set TX encap type. + * + * enum wmi_pkt_type is to be used as the parameter + * specifying the encap type. + */ + WMI_VDEV_PARAM_TX_ENCAP_TYPE, + + /* + * Try to detect stations that woke-up and exited power save but did not + * successfully transmit data-null with PM=0 to AP. When this happens, + * STA and AP power save state are out-of-sync. Use buffered but + * undelivered MSDU to the STA as a hint that the STA is really awake + * and expecting normal ASAP delivery, rather than retrieving BU with + * PS-Poll, U-APSD trigger, etc. + * + * 0 disables out-of-sync detection. Maximum time is 255 seconds. + */ + WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, + + /* Enable/Disable early rx dynamic adjust feature. + * Early-rx dynamic adjust is a advance power save feature. + * Early-rx is a wakeup duration before exact TBTT,which is deemed necessary to provide a cushion for various + * timing discrepancies in the system. + * In current code branch, the duration is set to a very conservative fix value to make sure the drift impact is minimum. + * The fix early-tx will result in the unnessary power consume, so a dynamic early-rx adjust algorithm can be designed + * properly to minimum the power consume.*/ + WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, + + /* set target bmiss number per sample cycle if bmiss adjust was chosen. + * In this adjust policy,early-rx is adjusted by comparing the current bmiss rate to target bmiss rate + * which can be set by user through WMI command. + */ + WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, + + /* set sample cycle(in the unit of beacon interval) if bmiss adjust was chosen */ + WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, + + /* set slop_step */ + WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, + + /* set init slop */ + WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, + + /* pause adjust enable/disable */ + WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, + + /* Set channel pwr limit value of the vdev the minimal value of all + * vdevs operating on this channel will be set as channel tx power + * limit, which is used to configure ratearray + */ + WMI_VDEV_PARAM_TX_PWRLIMIT, + + /* set the count of snr value for calculation in snr monitor */ + WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, + + /** Roaming offload */ + WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, + + /** Enable Leader request RX functionality for RMC */ + WMI_VDEV_PARAM_ENABLE_RMC, + + /* IBSS does not have deauth/disassoc, vdev has to detect peer gone event + * by himself. If the beacon lost time exceed this threshold, the peer is + * thought to be gone. */ + WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, + + /** max rate in kpbs, transmit rate can't go beyond it */ + WMI_VDEV_PARAM_MAX_RATE, + + /* enable/disable drift sample. 0: disable; 1: clk_drift; 2: ap_drift; 3 both clk and ap drift */ + WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, + /* set Tx failure count threshold for the vdev */ + WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, + + /* set ebt resync timeout value, in the unit of TU */ + WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, + + /* Enable Aggregation State Trigger Event */ + WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, + + /* This parameter indicates whether IBSS station can enter into power save + * mode by sending Null frame (with PM=1). When not allowed, IBSS station has to stay + * awake all the time and should never set PM=1 in its transmitted frames. + * This parameter is meaningful/valid only when WMI_VDEV_PARAM_ATIM_WINDOW_LENGTH + * is non-zero. */ + WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, + + /* This parameter indicates if this station can enter into power collapse + * for the remaining beacon interval after the ATIM window. + * This parameter is meaningful/valid only when WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED + * is set to true. */ + WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, + + /* This parameter indicates whether IBSS station exit power save mode and + * enter power active state (by sending Null frame with PM=0 in the immediate ATIM Window) + * whenever there is a TX/RX activity. */ + WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, + + /* If Awake on TX/RX activity is enabled, this parameter indicates + * the data inactivity time in number of beacon intervals after which + * IBSS station reenters power save by sending Null frame with PM=1. */ + WMI_VDEV_PARAM_INACTIVITY_CNT, + + /* Inactivity time in msec after which TX Service Period (SP) is + * terminated by sending a Qos Null frame with EOSP. + * If value is 0, TX SP is terminated with the last buffered packet itself + * instead of waiting for the inactivity timeout. */ + WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, + + /** DTIM policy */ + WMI_VDEV_PARAM_DTIM_POLICY, + + /* When IBSS network is initialized, PS-supporting device + * does not enter protocol sleep state during first + * WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS seconds. */ + WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, + + /* Enable/Disable 1 RX chain usage during the ATIM window */ + WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, + /** + * RX Leak window is the time driver waits before shutting down + * the radio or switching the channel and after receiving an ACK + * for a data frame with PM bit set) + */ + WMI_VDEV_PARAM_RX_LEAK_WINDOW, + + /** + * Averaging factor(16 bit value) is used in the calculations to + * perform averaging of different link level statistics like average + * beacon spread or average number of frames leaked + */ + WMI_VDEV_PARAM_STATS_AVG_FACTOR, + /* + * disconnect threshold, once the consecutive error for specific peer + * exceed this threhold, FW will send kickout event to host + */ + WMI_VDEV_PARAM_DISCONNECT_TH, + /* + * The rate_code of RTS_CTS changed by host. Now FW can support + * more non-HT rates rather than 1Mbps or 6Mbps */ + WMI_VDEV_PARAM_RTSCTS_RATE, + + /** This parameter indicates whether using a long duration RTS-CTS + * protection when a SAP goes off channel in MCC mode */ + WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, + + /* + * This parameter indicates whether using a broadcast probe response + * to increase the detectability of SAP in MCC mode + */ + WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, + + /* This parameter indicates the power backoff in percentage + * currently supports 100%, 50%, 25%, 12.5%, and minimum + * Host passes 0, 1, 2, 3, 4 to Firmware + * 0 --> 100% --> no changes, 1 --> 50% --> -3dB, + * 2 --> 25% --> -6dB, 3 --> 12.5% --> -9dB, 4 --> minimum --> -32dB + */ + WMI_VDEV_PARAM_TXPOWER_SCALE, + + /* TX power backoff in dB: tx power -= param value + * Host passes values(DB) to Halphy, Halphy reduces the power table + * by the values. Safety check will happen in Halphy. + */ + WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, + /** Multicast to Unicast conversion setting */ + WMI_VDEV_PARAM_MCAST2UCAST_SET, + + /** Total number of HW retries */ + WMI_VDEV_PARAM_RC_NUM_RETRIES, + + /** Max tx percentage for cabq */ + WMI_VDEV_PARAM_CABQ_MAXDUR, + + /** MFPTEST settings */ + WMI_VDEV_PARAM_MFPTEST_SET, + + /** RTS Fixed rate setting */ + WMI_VDEV_PARAM_RTS_FIXED_RATE, + + /** VHT SGI MASK */ + WMI_VDEV_PARAM_VHT_SGIMASK, + + /** VHT80 Auto Rate MASK */ + WMI_VDEV_PARAM_VHT80_RATEMASK, + + /** set Proxy STA features for this vap */ + WMI_VDEV_PARAM_PROXY_STA, + + /** set virtual cell mode - enable/disable */ + WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, + + /** Set receive packet type */ + WMI_VDEV_PARAM_RX_DECAP_TYPE, + + /** Set ratemask with specific Bandwidth and NSS */ + WMI_VDEV_PARAM_BW_NSS_RATEMASK, + + /** Set SENSOR Support */ + WMI_VDEV_PARAM_SENSOR_AP, + + /** Set beacon rate */ + WMI_VDEV_PARAM_BEACON_RATE, + + /** Enable CTS to self for DTIM beacon */ + WMI_VDEV_PARAM_DTIM_ENABLE_CTS, + + /** Disable station kickout at Vap level */ + WMI_VDEV_PARAM_STA_KICKOUT, + + /* VDEV capabilities */ + WMI_VDEV_PARAM_CAPABILITIES, /* see capabilities defs below */ + /* + * Increment TSF in micro seconds to avoid beacon collision on mesh VAP + * The host must ensure that either no other vdevs share the TSF with + * this vdev, or else that it is acceptable to apply this TSF adjustment + * to all vdevs sharing the TSF + */ + WMI_VDEV_PARAM_TSF_INCREMENT, + WMI_VDEV_PARAM_PLACE_HOLDER_1, + + /* + * Vdev level rx filter of from-ds / to-ds / no-ds / ta / ra frames. + * Used mainly for mesh-vap. + * The parameter value delivered with the RX_FILTER vdev param contains + * a bit-or mask of wmi_vdev_param_filter enum values. + */ + WMI_VDEV_PARAM_RX_FILTER, + /* vdev-specific mgmt tx power in dBm units (signed integer value) */ + WMI_VDEV_PARAM_MGMT_TX_POWER, + + /* + * Vdev level non aggregration/11g sw retry threshold. + * 0-disable, min:0, max:31, default:15 + */ + WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, + /* + * Vdev level aggregration sw retry threshold. + * 0-disable, min:0, max:31, default:15 + */ + WMI_VDEV_PARAM_AGG_SW_RETRY_TH, + + /** disable dynamic bw RTS **/ + WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, + + /* + * Per ssid (vdev) based ATF strict/fair scheduling policy + * Param values are WMI_ATF_SSID_FAIR_SCHED or + * WMI_ATF_SSID_STRICT_SCHED + */ + WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, + + /* + * === ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === + * The below vdev param types are used for prototyping, and are + * prone to change. + */ + WMI_VDEV_PARAM_PROTOTYPE = 0x8000, + /* 11AX SPECIFIC defines */ + WMI_VDEV_PARAM_BSS_COLOR, + /* + * Enable / disable trigger access for a AP vdev's peers. + * For a STA mode vdev this will enable/disable triggered access + * and enable/disable Multi User mode of operation. + * 0 - Disable MU OFDMA and MU MIMO + * 1 - Disable DL OFDMA + * 2 - Disable DL MUMIMO + * 3 - Disable UL OFDMA + * 4 - Disable UL MUMIMO + * 5 - Enable MU OFDMA and MU MIMO + * 6 - Enable DL OFDMA + * 7 - Enable DL MUMIMO + * 8 - Enable UL OFDMA + * 9 - Enable UL MUMIMO + */ + WMI_VDEV_PARAM_SET_HEMU_MODE, + /* + * For Tx OFDMA this will set values of CP length or guard interval + * to be + * 0: Auto + * 1: 0.8 us + * 2: 1.6 us + * 3: 3.2 us + * Similar to Guard Interval + */ + WMI_VDEV_PARAM_TX_OFDMA_CPLEN, + /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; /* vdev capabilities bit mask */ @@ -5887,85 +6531,106 @@ typedef enum { /* TXBF capabilities masks */ #define WMI_TXBF_CONF_SU_TX_BFEE_S 0 #define WMI_TXBF_CONF_SU_TX_BFEE_M 0x1 -#define WMI_TXBF_CONF_SU_TX_BFEE (WMI_TXBF_CONF_SU_TX_BFEE_M << WMI_TXBF_CONF_SU_TX_BFEE_S) -#define WMI_TXBF_CONF_SU_TX_BFEE_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_SU_TX_BFEE) -#define WMI_TXBF_CONF_SU_TX_BFEE_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_SU_TX_BFEE) +#define WMI_TXBF_CONF_SU_TX_BFEE (WMI_TXBF_CONF_SU_TX_BFEE_M << \ + WMI_TXBF_CONF_SU_TX_BFEE_S) +#define WMI_TXBF_CONF_SU_TX_BFEE_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_SU_TX_BFEE) +#define WMI_TXBF_CONF_SU_TX_BFEE_SET(x, z) WMI_F_RMW(x, z,\ + WMI_TXBF_CONF_SU_TX_BFEE) #define WMI_TXBF_CONF_MU_TX_BFEE_S 1 #define WMI_TXBF_CONF_MU_TX_BFEE_M 0x1 -#define WMI_TXBF_CONF_MU_TX_BFEE (WMI_TXBF_CONF_MU_TX_BFEE_M << WMI_TXBF_CONF_MU_TX_BFEE_S) -#define WMI_TXBF_CONF_MU_TX_BFEE_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_MU_TX_BFEE) -#define WMI_TXBF_CONF_MU_TX_BFEE_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_MU_TX_BFEE) +#define WMI_TXBF_CONF_MU_TX_BFEE (WMI_TXBF_CONF_MU_TX_BFEE_M << \ + WMI_TXBF_CONF_MU_TX_BFEE_S) +#define WMI_TXBF_CONF_MU_TX_BFEE_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_MU_TX_BFEE) +#define WMI_TXBF_CONF_MU_TX_BFEE_SET(x, z) WMI_F_RMW(x, z, \ + WMI_TXBF_CONF_MU_TX_BFEE) #define WMI_TXBF_CONF_SU_TX_BFER_S 2 #define WMI_TXBF_CONF_SU_TX_BFER_M 0x1 -#define WMI_TXBF_CONF_SU_TX_BFER (WMI_TXBF_CONF_SU_TX_BFER_M << WMI_TXBF_CONF_SU_TX_BFER_S) -#define WMI_TXBF_CONF_SU_TX_BFER_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_SU_TX_BFER) -#define WMI_TXBF_CONF_SU_TX_BFER_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_SU_TX_BFER) +#define WMI_TXBF_CONF_SU_TX_BFER (WMI_TXBF_CONF_SU_TX_BFER_M << \ + WMI_TXBF_CONF_SU_TX_BFER_S) +#define WMI_TXBF_CONF_SU_TX_BFER_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_SU_TX_BFER) +#define WMI_TXBF_CONF_SU_TX_BFER_SET(x, z) WMI_F_RMW(x, z, \ + WMI_TXBF_CONF_SU_TX_BFER) #define WMI_TXBF_CONF_MU_TX_BFER_S 3 #define WMI_TXBF_CONF_MU_TX_BFER_M 0x1 -#define WMI_TXBF_CONF_MU_TX_BFER (WMI_TXBF_CONF_MU_TX_BFER_M << WMI_TXBF_CONF_MU_TX_BFER_S) -#define WMI_TXBF_CONF_MU_TX_BFER_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_MU_TX_BFER) -#define WMI_TXBF_CONF_MU_TX_BFER_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_MU_TX_BFER) +#define WMI_TXBF_CONF_MU_TX_BFER (WMI_TXBF_CONF_MU_TX_BFER_M << \ + WMI_TXBF_CONF_MU_TX_BFER_S) +#define WMI_TXBF_CONF_MU_TX_BFER_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_MU_TX_BFER) +#define WMI_TXBF_CONF_MU_TX_BFER_SET(x, z) WMI_F_RMW(x, z, \ + WMI_TXBF_CONF_MU_TX_BFER) #define WMI_TXBF_CONF_STS_CAP_S 4 #define WMI_TXBF_CONF_STS_CAP_M 0x7 -#define WMI_TXBF_CONF_STS_CAP (WMI_TXBF_CONF_STS_CAP_M << WMI_TXBF_CONF_STS_CAP_S) -#define WMI_TXBF_CONF_STS_CAP_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_STS_CAP); -#define WMI_TXBF_CONF_STS_CAP_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_STS_CAP) +#define WMI_TXBF_CONF_STS_CAP (WMI_TXBF_CONF_STS_CAP_M << \ + WMI_TXBF_CONF_STS_CAP_S) +#define WMI_TXBF_CONF_STS_CAP_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_STS_CAP); +#define WMI_TXBF_CONF_STS_CAP_SET(x, z) WMI_F_RMW(x, z, \ + WMI_TXBF_CONF_STS_CAP) #define WMI_TXBF_CONF_IMPLICIT_BF_S 7 #define WMI_TXBF_CONF_IMPLICIT_BF_M 0x1 -#define WMI_TXBF_CONF_IMPLICIT_BF (WMI_TXBF_CONF_IMPLICIT_BF_M << WMI_TXBF_CONF_IMPLICIT_BF_S) -#define WMI_TXBF_CONF_IMPLICIT_BF_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_IMPLICIT_BF) -#define WMI_TXBF_CONF_IMPLICIT_BF_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_IMPLICIT_BF) +#define WMI_TXBF_CONF_IMPLICIT_BF (WMI_TXBF_CONF_IMPLICIT_BF_M << \ + WMI_TXBF_CONF_IMPLICIT_BF_S) +#define WMI_TXBF_CONF_IMPLICIT_BF_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_IMPLICIT_BF) +#define WMI_TXBF_CONF_IMPLICIT_BF_SET(x, z) WMI_F_RMW(x, z, \ + WMI_TXBF_CONF_IMPLICIT_BF) #define WMI_TXBF_CONF_BF_SND_DIM_S 8 #define WMI_TXBF_CONF_BF_SND_DIM_M 0x7 -#define WMI_TXBF_CONF_BF_SND_DIM (WMI_TXBF_CONF_BF_SND_DIM_M << WMI_TXBF_CONF_BF_SND_DIM_S) -#define WMI_TXBF_CONF_BF_SND_DIM_GET(x) WMI_F_MS(x,WMI_TXBF_CONF_BF_SND_DIM) -#define WMI_TXBF_CONF_BF_SND_DIM_SET(x,z) WMI_F_RMW(x,z,WMI_TXBF_CONF_BF_SND_DIM) +#define WMI_TXBF_CONF_BF_SND_DIM (WMI_TXBF_CONF_BF_SND_DIM_M << \ + WMI_TXBF_CONF_BF_SND_DIM_S) +#define WMI_TXBF_CONF_BF_SND_DIM_GET(x) WMI_F_MS(x, WMI_TXBF_CONF_BF_SND_DIM) +#define WMI_TXBF_CONF_BF_SND_DIM_SET(x, z) WMI_F_RMW(x, z, \ + WMI_TXBF_CONF_BF_SND_DIM) /* TXBF capabilities */ typedef struct { - A_UINT32 txbf_cap; + A_UINT32 txbf_cap; } wmi_vdev_txbf_cap; /* vdev rx filters (for mesh) */ typedef enum { - WMI_VDEV_RX_ALLOW_ALL_FRAMES = 0x0, /* Don't drop any frames - Default */ - WMI_VDEV_RX_FILTER_OUT_FROMDS = 0x1, /* Drop FromDS frames */ - WMI_VDEV_RX_FILTER_OUT_TODS = 0x2, /* Drop ToDS frames */ - WMI_VDEV_RX_FILTER_OUT_NODS = 0x4, /* Drop NODS frames */ - WMI_VDEV_RX_FILTER_OUT_RA = 0x8, /* Drop RA frames */ - WMI_VDEV_RX_FILTER_OUT_TA = 0x10, /* Drop TA frames */ + /* Don't drop any frames - Default */ + WMI_VDEV_RX_ALLOW_ALL_FRAMES = 0x0, + /* Drop FromDS frames */ + WMI_VDEV_RX_FILTER_OUT_FROMDS = 0x1, + /* Drop ToDS frames */ + WMI_VDEV_RX_FILTER_OUT_TODS = 0x2, + /* Drop NODS frames */ + WMI_VDEV_RX_FILTER_OUT_NODS = 0x4, + /* Drop RA frames */ + WMI_VDEV_RX_FILTER_OUT_RA = 0x8, + /* Drop TA frames */ + WMI_VDEV_RX_FILTER_OUT_TA = 0x10, } wmi_vdev_param_filter; /* Length of ATIM Window in TU */ #define WMI_VDEV_PARAM_ATIM_WINDOW_LENGTH WMI_VDEV_PARAM_ATIM_WINDOW enum wmi_pkt_type { - WMI_PKT_TYPE_RAW = 0, - WMI_PKT_TYPE_NATIVE_WIFI = 1, - WMI_PKT_TYPE_ETHERNET = 2, + WMI_PKT_TYPE_RAW = 0, + WMI_PKT_TYPE_NATIVE_WIFI = 1, + WMI_PKT_TYPE_ETHERNET = 2, }; /******************************************************************* * wmi_vdev_txbf_en is DEPRECATED in favor of wmi_vdev_txbf_cap * Do not use it! *******************************************************************/ + typedef struct { - A_UINT8 sutxbfee : 1, - mutxbfee : 1, - sutxbfer : 1, - mutxbfer : 1, - txb_sts_cap : 3, - implicit_bf : 1; + A_UINT8 sutxbfee:1, mutxbfee:1, sutxbfer:1, mutxbfer:1, +#if defined(AR900B) + txb_sts_cap:3, implicit_bf:1; +#else + reserved:4; +#endif } wmi_vdev_txbf_en; /** Upto 8 bits are available for Roaming module to be sent along with -WMI_VDEV_PARAM_ROAM_FW_OFFLOAD WMI_VDEV_PARAM **/ + WMI_VDEV_PARAM_ROAM_FW_OFFLOAD WMI_VDEV_PARAM **/ /* Enable Roaming FW offload LFR1.5/LFR2.0 implementation */ #define WMI_ROAM_FW_OFFLOAD_ENABLE_FLAG 0x1 /* Enable Roaming module in FW to do scan based on Final BMISS */ @@ -5982,191 +6647,191 @@ WMI_VDEV_PARAM_ROAM_FW_OFFLOAD WMI_VDEV_PARAM **/ /** the definition of different START/RESTART Event response */ typedef enum { - /* Event respose of START CMD */ - WMI_VDEV_START_RESP_EVENT = 0, - /* Event respose of RESTART CMD */ - WMI_VDEV_RESTART_RESP_EVENT, + /* Event respose of START CMD */ + WMI_VDEV_START_RESP_EVENT = 0, + /* Event respose of RESTART CMD */ + WMI_VDEV_RESTART_RESP_EVENT, } WMI_START_EVENT_PARAM; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** requestor id that requested the VDEV start request */ - A_UINT32 requestor_id; - /* Respose of Event type START/RESTART */ - WMI_START_EVENT_PARAM resp_type; - /** status of the response */ - A_UINT32 status; - /** Vdev chain mask */ - A_UINT32 chain_mask; - /** Vdev mimo power save mode */ - A_UINT32 smps_mode; - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - /** Configured Transmit Streams **/ - A_UINT32 cfgd_tx_streams; - /** Configured Receive Streams **/ - A_UINT32 cfgd_rx_streams; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** requestor id that requested the VDEV start request */ + A_UINT32 requestor_id; + /* Respose of Event type START/RESTART */ + WMI_START_EVENT_PARAM resp_type; + /** status of the response */ + A_UINT32 status; + /** Vdev chain mask */ + A_UINT32 chain_mask; + /** Vdev mimo power save mode */ + A_UINT32 smps_mode; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + /** Configured Transmit Streams **/ + A_UINT32 cfgd_tx_streams; + /** Configured Receive Streams **/ + A_UINT32 cfgd_rx_streams; } wmi_vdev_start_response_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_stopped_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_delete_resp_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_delete_resp_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_delete_resp_event_fixed_param; /** common structure used for simple events (stopped, resume_req, standby response) */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag would be equivalent to actual event */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag would be equivalent to actual event */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_vdev_simple_event_fixed_param; - /** VDEV start response status codes */ -#define WMI_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0 /** VDEV succesfully started */ -#define WMI_VDEV_START_RESPONSE_INVALID_VDEVID 0x1 /** requested VDEV not found */ -#define WMI_VDEV_START_RESPONSE_NOT_SUPPORTED 0x2 /** unsupported VDEV combination */ +#define WMI_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0 /** VDEV succesfully started */ +#define WMI_VDEV_START_RESPONSE_INVALID_VDEVID 0x1 /** requested VDEV not found */ +#define WMI_VDEV_START_RESPONSE_NOT_SUPPORTED 0x2 /** unsupported VDEV combination */ /** Beacon processing related command and event structures */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tx_hdr */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** xmit rate */ - A_UINT32 tx_rate; - /** xmit power */ - A_UINT32 txPower; - /** beacon buffer length in bytes */ - A_UINT32 buf_len; -/* This TLV is followed by array of bytes: - * A_UINT8 bufp[]; <-- beacon frame buffer - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tx_hdr */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** xmit rate */ + A_UINT32 tx_rate; + /** xmit power */ + A_UINT32 txPower; + /** beacon buffer length in bytes */ + A_UINT32 buf_len; + /* This TLV is followed by array of bytes: + * // beacon frame buffer + * A_UINT8 bufp[]; + */ } wmi_bcn_tx_hdr; /* Beacon filter */ -#define WMI_BCN_FILTER_ALL 0 /* Filter all beacons */ -#define WMI_BCN_FILTER_NONE 1 /* Pass all beacons */ -#define WMI_BCN_FILTER_RSSI 2 /* Pass Beacons RSSI >= RSSI threshold */ -#define WMI_BCN_FILTER_BSSID 3 /* Pass Beacons with matching BSSID */ -#define WMI_BCN_FILTER_SSID 4 /* Pass Beacons with matching SSID */ +#define WMI_BCN_FILTER_ALL 0 /* Filter all beacons */ +#define WMI_BCN_FILTER_NONE 1 /* Pass all beacons */ +#define WMI_BCN_FILTER_RSSI 2 /* Pass Beacons RSSI >= RSSI threshold */ +#define WMI_BCN_FILTER_BSSID 3 /* Pass Beacons with matching BSSID */ +#define WMI_BCN_FILTER_SSID 4 /* Pass Beacons with matching SSID */ typedef struct { - /** Filter ID */ - A_UINT32 bcn_filter_id; - /** Filter type - wmi_bcn_filter */ - A_UINT32 bcn_filter; - /** Buffer len */ - A_UINT32 bcn_filter_len; - /** Filter info (threshold, BSSID, RSSI) */ - A_UINT8 *bcn_filter_buf; + /** Filter ID */ + A_UINT32 bcn_filter_id; + /** Filter type - wmi_bcn_filter */ + A_UINT32 bcn_filter; + /** Buffer len */ + A_UINT32 bcn_filter_len; + /** Filter info (threshold, BSSID, RSSI) */ + A_UINT8 *bcn_filter_buf; } wmi_bcn_filter_rx_cmd; /** Capabilities and IEs to be passed to firmware */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_prb_info */ - /** Capabilities */ - A_UINT32 caps; - /** ERP info */ - A_UINT32 erp; -/** Advanced capabilities */ -/** HT capabilities */ -/** HT Info */ -/** ibss_dfs */ -/** wpa Info */ -/** rsn Info */ -/** rrm info */ -/** ath_ext */ -/** app IE */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_prb_info */ + /** Capabilities */ + A_UINT32 caps; + /** ERP info */ + A_UINT32 erp; + /** Advanced capabilities */ + /** HT capabilities */ + /** HT Info */ + /** ibss_dfs */ + /** wpa Info */ + /** rsn Info */ + /** rrm info */ + /** ath_ext */ + /** app IE */ } wmi_bcn_prb_info; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tmpl_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** TIM IE offset from the beginning of the template. */ - A_UINT32 tim_ie_offset; - /** beacon buffer length. data is in TLV data[] */ - A_UINT32 buf_len; - -/* - * The TLVs follows: - * wmi_bcn_prb_info bcn_prb_info; <-- beacon probe capabilities and IEs - * A_UINT8 data[]; <-- Variable length data - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tmpl_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** TIM IE offset from the beginning of the template. */ + A_UINT32 tim_ie_offset; + /** beacon buffer length. data is in TLV data[] */ + A_UINT32 buf_len; + /* + * The TLVs follows: + * wmi_bcn_prb_info bcn_prb_info; //beacon probe capabilities and IEs + * A_UINT8 data[]; //Variable length data + */ } wmi_bcn_tmpl_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** beacon buffer length. data is in TLV data[] */ - A_UINT32 buf_len; -/* - * The TLVs follows: - * wmi_bcn_prb_info bcn_prb_info; <-- beacon probe capabilities and IEs - * A_UINT8 data[]; <-- Variable length data - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** beacon buffer length. data is in TLV data[] */ + A_UINT32 buf_len; + /* + * The TLVs follows: + * wmi_bcn_prb_info bcn_prb_info; //beacon probe capabilities and IEs + * A_UINT8 data[]; //Variable length data + */ } wmi_prb_tmpl_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_offload_bcn_tx_status_event_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** bcn tx status, values defined in enum WMI_FRAME_TX_STATUS */ - A_UINT32 tx_status; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_offload_bcn_tx_status_event_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** bcn tx status, values defined in enum WMI_FRAME_TX_STATUS */ + A_UINT32 tx_status; } wmi_offload_bcn_tx_status_event_fixed_param; enum wmi_sta_ps_mode { - /** enable power save for the given STA VDEV */ - WMI_STA_PS_MODE_DISABLED = 0, - /** disable power save for a given STA VDEV */ - WMI_STA_PS_MODE_ENABLED = 1, + /** enable power save for the given STA VDEV */ + WMI_STA_PS_MODE_DISABLED = 0, + /** disable power save for a given STA VDEV */ + WMI_STA_PS_MODE_ENABLED = 1, }; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_powersave_mode_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_powersave_mode_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; - /** Power save mode - * - * (see enum wmi_sta_ps_mode) - */ - A_UINT32 sta_ps_mode; + /** Power save mode + * + * (see enum wmi_sta_ps_mode) + */ + A_UINT32 sta_ps_mode; } wmi_sta_powersave_mode_cmd_fixed_param; enum wmi_csa_offload_en { - WMI_CSA_OFFLOAD_DISABLE = 0, - WMI_CSA_OFFLOAD_ENABLE = 1, + WMI_CSA_OFFLOAD_DISABLE = 0, + WMI_CSA_OFFLOAD_ENABLE = 1, }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csa_offload_enable_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 csa_offload_enable; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csa_offload_enable_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 csa_offload_enable; } wmi_csa_offload_enable_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csa_offload_chanswitch_cmd_fixed_param */ - A_UINT32 vdev_id; -/* - * The TLVs follows: - * wmi_channel chan; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csa_offload_chanswitch_cmd_fixed_param */ + A_UINT32 vdev_id; + /* + * The TLVs follows: + * wmi_channel chan; + */ } wmi_csa_offload_chanswitch_cmd_fixed_param; /** * This parameter controls the policy for retrieving frames from AP while the @@ -6175,20 +6840,20 @@ typedef struct { * Only takes affect if the sta_ps_mode is enabled */ enum wmi_sta_ps_param_rx_wake_policy { - /* Wake up when ever there is an RX activity on the VDEV. In this mode - * the Power save SM(state machine) will come out of sleep by either - * sending null frame (or) a data frame (with PS==0) in response to TIM - * bit set in the received beacon frame from AP. - */ - WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, + /* Wake up when ever there is an RX activity on the VDEV. In this mode + * the Power save SM(state machine) will come out of sleep by either + * sending null frame (or) a data frame (with PS==0) in response to TIM + * bit set in the received beacon frame from AP. + */ + WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, - /* Here the power save state machine will not wakeup in response to TIM - * bit, instead it will send a PSPOLL (or) UASPD trigger based on UAPSD - * configuration setup by WMISET_PS_SET_UAPSD WMI command. When all - * access categories are delivery-enabled, the station will send a UAPSD - * trigger frame, otherwise it will send a PS-Poll. - */ - WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, + /* Here the power save state machine will not wakeup in response to TIM + * bit, instead it will send a PSPOLL (or) UASPD trigger based on UAPSD + * configuration setup by WMISET_PS_SET_UAPSD WMI command. When all + * access categories are delivery-enabled, the station will send a UAPSD + * trigger frame, otherwise it will send a PS-Poll. + */ + WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, }; /** Number of tx frames/beacon that cause the power save SM to wake up. @@ -6199,12 +6864,12 @@ enum wmi_sta_ps_param_rx_wake_policy { * can change this parameter any time. It will affect at the next tx frame. */ enum wmi_sta_ps_param_tx_wake_threshold { - WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, - WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, + WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, + WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, -/* Values greater than one indicate that many TX attempts per beacon - * interval before the STA will wake up - */ + /* Values greater than one indicate that many TX attempts per beacon + * interval before the STA will wake up + */ }; /** @@ -6217,10 +6882,10 @@ enum wmi_sta_ps_param_tx_wake_threshold { * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. */ enum wmi_sta_ps_param_pspoll_count { - WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, -/* Values greater than 0 indicate the maximum numer of PS-Poll frames FW - * will send before waking up. - */ + WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, + /* Values greater than 0 indicate the maximum numer of PS-Poll frames FW + * will send before waking up. + */ }; /* @@ -6232,95 +6897,95 @@ enum wmi_sta_ps_param_pspoll_count { #define WMI_UAPSD_AC_TYPE_DELI 0 #define WMI_UAPSD_AC_TYPE_TRIG 1 -#define WMI_UAPSD_AC_BIT_MASK(ac,type) \ - ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ - (1 << (ac<<1)) : \ - (1 << ((ac<<1)+1))) +#define WMI_UAPSD_AC_BIT_MASK(ac, type) \ + do { \ + (type == WMI_UAPSD_AC_TYPE_DELI) ? (1<<(ac<<1)) : \ + (1<<((ac<<1)+1)) \ + } while (0) enum wmi_sta_ps_param_uapsd { - WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), - WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), - WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), - WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), - WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), - WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), - WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), - WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), + WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), + WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), + WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), + WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), + WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), + WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), + WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), + WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), }; enum wmi_sta_powersave_param { -/** - * Controls how frames are retrievd from AP while STA is sleeping - * - * (see enum wmi_sta_ps_param_rx_wake_policy) - */ -WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, + /** + * Controls how frames are retrievd from AP while STA is sleeping + * + * (see enum wmi_sta_ps_param_rx_wake_policy) + */ + WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, -/** - * The STA will go active after this many TX - * - * (see enum wmi_sta_ps_param_tx_wake_threshold) - */ -WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, + /** + * The STA will go active after this many TX + * + * (see enum wmi_sta_ps_param_tx_wake_threshold) + */ + WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, -/** - * Number of PS-Poll to send before STA wakes up - * - * (see enum wmi_sta_ps_param_pspoll_count) - * - */ -WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, + /** + * Number of PS-Poll to send before STA wakes up + * + * (see enum wmi_sta_ps_param_pspoll_count) + * + */ + WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, -/** - * TX/RX inactivity time in msec before going to sleep. - * - * The power save SM will monitor tx/rx activity on the VDEV, if no - * activity for the specified msec of the parameter the Power save SM will - * go to sleep. - */ -WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, + /** + * TX/RX inactivity time in msec before going to sleep. + * + * The power save SM will monitor tx/rx activity on the VDEV, if no + * activity for the specified msec of the parameter the Power save SM will + * go to sleep. + */ + WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, -/** - * Set uapsd configuration. - * - * (see enum wmi_sta_ps_param_uapsd) - */ -WMI_STA_PS_PARAM_UAPSD = 4, + /** + * Set uapsd configuration. + * + * (see enum wmi_sta_ps_param_uapsd) + */ + WMI_STA_PS_PARAM_UAPSD = 4, + /** + * Number of PS-Poll to send before STA wakes up in QPower Mode + */ + WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, -/** - * Number of PS-Poll to send before STA wakes up in QPower Mode - */ -WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, + /** + * Enable QPower + */ + WMI_STA_PS_ENABLE_QPOWER = 6, -/** - * Enable QPower - */ -WMI_STA_PS_ENABLE_QPOWER = 6, + /** + * Number of TX frames before the entering the Active state + */ + WMI_STA_PS_PARAM_QPOWER_MAX_TX_BEFORE_WAKE = 7, -/** - * Number of TX frames before the entering the Active state - */ -WMI_STA_PS_PARAM_QPOWER_MAX_TX_BEFORE_WAKE = 7, + /** + * QPower SPEC PSPOLL interval + */ + WMI_STA_PS_PARAM_QPOWER_SPEC_PSPOLL_WAKE_INTERVAL = 8, -/** - * QPower SPEC PSPOLL interval - */ -WMI_STA_PS_PARAM_QPOWER_SPEC_PSPOLL_WAKE_INTERVAL = 8, - -/** - * Max SPEC PSPOLL to be sent when the PSPOLL response has - * no-data bit set - */ -WMI_STA_PS_PARAM_QPOWER_SPEC_MAX_SPEC_NODATA_PSPOLL = 9, + /** + * Max SPEC PSPOLL to be sent when the PSPOLL response has + * no-data bit set + */ + WMI_STA_PS_PARAM_QPOWER_SPEC_MAX_SPEC_NODATA_PSPOLL = 9, }; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_powersave_param_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** station power save parameter (see enum wmi_sta_powersave_param) */ - A_UINT32 param; - A_UINT32 value; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_powersave_param_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** station power save parameter (see enum wmi_sta_powersave_param) */ + A_UINT32 param; + A_UINT32 value; } wmi_sta_powersave_param_cmd_fixed_param; /** No MIMO power save */ @@ -6331,43 +6996,42 @@ typedef struct { #define WMI_STA_MIMO_PS_MODE_DYNAMI typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** mimo powersave mode as defined above */ - A_UINT32 mimo_pwrsave_mode; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** mimo powersave mode as defined above */ + A_UINT32 mimo_pwrsave_mode; } wmi_sta_mimo_ps_mode_cmd; - /** U-APSD configuration of peer station from (re)assoc request and TSPECs */ enum wmi_ap_ps_param_uapsd { - WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), - WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), - WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), - WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), - WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), - WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), - WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), - WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), + WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), + WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), + WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), + WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), + WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), + WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), + WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), + WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), }; /** U-APSD maximum service period of peer station */ enum wmi_ap_ps_peer_param_max_sp { - WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, - WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, - WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, - WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, + WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, + WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, + WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, + WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, - /* keep last! */ - MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, + /* keep last! */ + MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, }; /** param values for WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE */ enum wmi_ap_ps_param_sifs_resp_frmtype { - WMI_SIFS_RESP_PSPOLL = (1 << 0), - WMI_SIFS_RESP_UAPSD = (1 << 1), - WMI_SIFS_RESP_QBST_EXP = (1 << 2), - WMI_SIFS_RESP_QBST_DATA = (1 << 3), - WMI_SIFS_RESP_QBST_BAR = (1 << 4), + WMI_SIFS_RESP_PSPOLL = (1 << 0), + WMI_SIFS_RESP_UAPSD = (1 << 1), + WMI_SIFS_RESP_QBST_EXP = (1 << 2), + WMI_SIFS_RESP_QBST_DATA = (1 << 3), + WMI_SIFS_RESP_QBST_BAR = (1 << 4), }; /** @@ -6375,54 +7039,56 @@ enum wmi_ap_ps_param_sifs_resp_frmtype { * Set a power save specific parameter for a peer station */ enum wmi_ap_ps_peer_param { - /** Set uapsd configuration for a given peer. - * - * This will include the delivery and trigger enabled state for every AC. - * The host MLME needs to set this based on AP capability and stations - * request Set in the association request received from the station. - * - * Lower 8 bits of the value specify the UAPSD configuration. - * - * (see enum wmi_ap_ps_param_uapsd) - * The default value is 0. - */ - WMI_AP_PS_PEER_PARAM_UAPSD = 0, + /** Set uapsd configuration for a given peer. + * + * This will include the delivery and trigger enabled state for every AC. + * The host MLME needs to set this based on AP capability and stations + * request Set in the association request received from the station. + * + * Lower 8 bits of the value specify the UAPSD configuration. + * + * (see enum wmi_ap_ps_param_uapsd) + * The default value is 0. + */ + WMI_AP_PS_PEER_PARAM_UAPSD = 0, - /** - * Set the service period for a UAPSD capable station - * - * The service period from wme ie in the (re)assoc request frame. - * - * (see enum wmi_ap_ps_peer_param_max_sp) - */ - WMI_AP_PS_PEER_PARAM_MAX_SP = 1, + /** + * Set the service period for a UAPSD capable station + * + * The service period from wme ie in the (re)assoc request frame. + * + * (see enum wmi_ap_ps_peer_param_max_sp) + */ + WMI_AP_PS_PEER_PARAM_MAX_SP = 1, - /** Time in seconds for aging out buffered frames for STA in power save */ - WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, + /** Time in seconds for aging out buffered frames for STA in power save */ + WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, + /** + * Specify frame types that are considered SIFS RESP trigger frame + * (see enum wmi_ap_ps_param_sifs_resp_frmtype) + */ + WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, - /** - * Specify frame types that are considered SIFS RESP trigger frame - * (see enum wmi_ap_ps_param_sifs_resp_frmtype) - */ - WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, + /* + * Specifies the trigger state of TID. + * Valid only for UAPSD frame type + */ + WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, - /** Specifies the trigger state of TID. Valid only for UAPSD frame type */ - WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, - - /** Specifies the WNM sleep state of a STA */ - WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, + /** Specifies the WNM sleep state of a STA */ + WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ap_ps_peer_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** AP powersave param (see enum wmi_ap_ps_peer_param) */ - A_UINT32 param; - /** AP powersave param value (see defines) */ - A_UINT32 value; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ap_ps_peer_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** AP powersave param (see enum wmi_ap_ps_peer_param) */ + A_UINT32 param; + /** AP powersave param value (see defines) */ + A_UINT32 value; } wmi_ap_ps_peer_cmd_fixed_param; /** Configure peer station 11v U-APSD coexistance @@ -6456,225 +7122,270 @@ typedef struct { * calculation: End of transmission period = T + Duration */ typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Enable U-APSD coexistence support for this peer - * - * 0 -> disabled (default) - * 1 -> enabled - */ - A_UINT32 enabled; - /** Duration/Interval as defined by 11v U-ASPD coexistance */ - A_UINT32 duration_interval; - /** Upper 32 bits of 64-bit TSF offset */ - A_UINT32 tsf_offset_high; - /** Lower 32 bits of 64-bit TSF offset */ - A_UINT32 tsf_offset_low; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Enable U-APSD coexistence support for this peer + * + * 0 -> disabled (default) + * 1 -> enabled + */ + A_UINT32 enabled; + /** Duration/Interval as defined by 11v U-ASPD coexistance */ + A_UINT32 duration_interval; + /** Upper 32 bits of 64-bit TSF offset */ + A_UINT32 tsf_offset_high; + /** Lower 32 bits of 64-bit TSF offset */ + A_UINT32 tsf_offset_low; } wmi_ap_powersave_peer_uapsd_coex_cmd; typedef enum { - WMI_AP_PS_EGAP_F_ENABLE_PHYERR_DETECTION = 0x0001, - WMI_AP_PS_EGAP_F_ENABLE_PWRSAVE_BY_PS_STATE = 0x0002, - WMI_AP_PS_EGAP_F_ENABLE_PWRSAVE_BY_INACTIVITY = 0x0004, + WMI_AP_PS_EGAP_F_ENABLE_PHYERR_DETECTION = 0x0001, + WMI_AP_PS_EGAP_F_ENABLE_PWRSAVE_BY_PS_STATE = 0x0002, + WMI_AP_PS_EGAP_F_ENABLE_PWRSAVE_BY_INACTIVITY = 0x0004, - WMI_AP_PS_EGAP_FLAG_MAX = 0x8000 + WMI_AP_PS_EGAP_FLAG_MAX = 0x8000 } wmi_ap_ps_egap_flag_type; /** * configure ehanced green ap parameters */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_ap_powersave_egap_param_cmd_fixed_param */ - /** Enable enhanced green ap - * 0 -> disabled - * 1 -> enabled - */ - A_UINT32 enable; - /** The param indicates a duration that all STAs connected - * to S-AP have no traffic. - */ - A_UINT32 inactivity_time; /* in unit of milliseconds */ - /** The param indicates a duration that all STAs connected - * to S-AP have no traffic, after all STAs have entered powersave. - */ - A_UINT32 wait_time; /* in unit of milliseconds */ - /** The param is used to turn on/off some functions within E-GAP. - */ - A_UINT32 flags; /* wmi_ap_ps_egap_flag_type bitmap */ + /* + * TLV tag and len; tag equals + * wmi_ap_powersave_egap_param_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** Enable enhanced green ap + * 0 -> disabled + * 1 -> enabled + */ + A_UINT32 enable; + /** The param indicates a duration that all STAs connected + * to S-AP have no traffic. + */ + A_UINT32 inactivity_time; /* in unit of milliseconds */ + /** The param indicates a duration that all STAs connected + * to S-AP have no traffic, after all STAs have entered powersave. + */ + A_UINT32 wait_time; /* in unit of milliseconds */ + /** The param is used to turn on/off some functions within E-GAP. + */ + A_UINT32 flags; /* wmi_ap_ps_egap_flag_type bitmap */ } wmi_ap_ps_egap_param_cmd_fixed_param; typedef enum { - WMI_AP_PS_EGAP_STATUS_IDLE = 1, - WMI_AP_PS_EGAP_STATUS_PWRSAVE_OFF = 2, - WMI_AP_PS_EGAP_STATUS_PWRSAVE_ON = 3, + WMI_AP_PS_EGAP_STATUS_IDLE = 1, + WMI_AP_PS_EGAP_STATUS_PWRSAVE_OFF = 2, + WMI_AP_PS_EGAP_STATUS_PWRSAVE_ON = 3, - WMI_AP_PS_EGAP_STATUS_MAX = 15 + WMI_AP_PS_EGAP_STATUS_MAX = 15 } wmi_ap_ps_egap_status_type; /** * send ehanced green ap status to host */ -typedef struct -{ - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_chainmask_list */ - A_UINT32 tlv_header; - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - /** The param indicates the current tx chainmask with the mac id. */ - A_UINT32 tx_chainmask; - /** The param indicates the current rx chainmask with the mac id. */ - A_UINT32 rx_chainmask; +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ap_ps_egap_info_chainmask_list + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + /** The param indicates the current tx chainmask with the mac id. */ + A_UINT32 tx_chainmask; + /** The param indicates the current rx chainmask with the mac id. */ + A_UINT32 rx_chainmask; } wmi_ap_ps_egap_info_chainmask_list; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_ap_powersave_egap_param_cmd_fixed_param */ - /** Enhanced green ap status (WMI_AP_PS_EGAP_STATUS). */ - A_UINT32 status; -/* This TLV is followed by - * wmi_ap_ps_egap_info_chainmask_list chainmask_list[]; - */ + /* + * TLV tag and len; tag equals + * wmi_ap_powersave_egap_param_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** Enhanced green ap status (WMI_AP_PS_EGAP_STATUS). */ + A_UINT32 status; + /* This TLV is followed by + * wmi_ap_ps_egap_info_chainmask_list chainmask_list[]; + */ } wmi_ap_ps_egap_info_event_fixed_param; + /* 128 clients = 4 words */ /* WMI_TIM_BITMAP_ARRAY_SIZE can't be modified without breaking the compatibility */ #define WMI_TIM_BITMAP_ARRAY_SIZE 4 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tim_info */ - /** TIM bitmap len (in bytes)*/ - A_UINT32 tim_len; - /** TIM Partial Virtual Bitmap */ - A_UINT32 tim_mcast; - A_UINT32 tim_bitmap[WMI_TIM_BITMAP_ARRAY_SIZE]; - A_UINT32 tim_changed; - A_UINT32 tim_num_ps_pending; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tim_info */ + /** TIM bitmap len (in bytes) */ + A_UINT32 tim_len; + /** TIM Partial Virtual Bitmap */ + A_UINT32 tim_mcast; + A_UINT32 tim_bitmap[WMI_TIM_BITMAP_ARRAY_SIZE]; + A_UINT32 tim_changed; + A_UINT32 tim_num_ps_pending; + /** Use the vdev_id only if vdev_id_valid is set */ + A_UINT32 vdev_id_valid; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; } wmi_tim_info; typedef struct { - /** Flag to enable quiet period IE support */ - A_UINT32 is_enabled; - /** Quiet start */ - A_UINT32 tbttcount; - /** Beacon intervals between quiets*/ - A_UINT32 period; - /** TUs of each quiet*/ - A_UINT32 duration; - /** TUs of from TBTT of quiet start*/ - A_UINT32 offset; + /** Flag to enable quiet period IE support */ + A_UINT32 is_enabled; + /** Quiet start */ + A_UINT32 tbttcount; + /** Beacon intervals between quiets*/ + A_UINT32 period; + /** TUs of each quiet*/ + A_UINT32 duration; + /** TUs of from TBTT of quiet start*/ + A_UINT32 offset; } wmi_quiet_info; /* WMI_P2P_MAX_NOA_DESCRIPTORS can't be modified without breaking the compatibility */ #define WMI_P2P_MAX_NOA_DESCRIPTORS 4 /* Maximum number of NOA Descriptors supported */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_noa_info */ - /** Bit 0: Flag to indicate an update in NOA schedule - * Bits 7-1: Reserved - * Bits 15-8: Index (identifies the instance of NOA sub element) - * Bit 16: Opp PS state of the AP - * Bits 23-17: Ctwindow in TUs - * Bits 31-24: Number of NOA descriptors - */ - A_UINT32 noa_attributes; - wmi_p2p_noa_descriptor noa_descriptors[WMI_P2P_MAX_NOA_DESCRIPTORS]; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_noa_info */ + /** Bit 0: Flag to indicate an update in NOA schedule + * Bits 7-1: Reserved + * Bits 15-8: Index (identifies the instance of NOA sub element) + * Bit 16: Opp PS state of the AP + * Bits 23-17: Ctwindow in TUs + * Bits 31-24: Number of NOA descriptors + */ + A_UINT32 noa_attributes; + wmi_p2p_noa_descriptor + noa_descriptors[WMI_P2P_MAX_NOA_DESCRIPTORS]; + /** Use the vdev_id only if vdev_id_valid is set */ + A_UINT32 vdev_id_valid; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; } wmi_p2p_noa_info; -#define WMI_UNIFIED_NOA_ATTR_MODIFIED 0x1 -#define WMI_UNIFIED_NOA_ATTR_MODIFIED_S 0 +#define WMI_UNIFIED_NOA_ATTR_MODIFIED 0x1 +#define WMI_UNIFIED_NOA_ATTR_MODIFIED_S 0 -#define WMI_UNIFIED_NOA_ATTR_IS_MODIFIED(hdr) \ - WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_MODIFIED) +#define WMI_UNIFIED_NOA_ATTR_IS_MODIFIED(hdr) \ + WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_MODIFIED) -#define WMI_UNIFIED_NOA_ATTR_MODIFIED_SET(hdr) \ - WMI_F_RMW((hdr)->noa_attributes, 0x1, \ - WMI_UNIFIED_NOA_ATTR_MODIFIED); +#define WMI_UNIFIED_NOA_ATTR_MODIFIED_SET(hdr) \ + WMI_F_RMW((hdr)->noa_attributes, 0x1, \ + WMI_UNIFIED_NOA_ATTR_MODIFIED); -#define WMI_UNIFIED_NOA_ATTR_INDEX 0xff00 -#define WMI_UNIFIED_NOA_ATTR_INDEX_S 8 +#define WMI_UNIFIED_NOA_ATTR_INDEX 0xff00 +#define WMI_UNIFIED_NOA_ATTR_INDEX_S 8 -#define WMI_UNIFIED_NOA_ATTR_INDEX_GET(hdr) \ - WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_INDEX) +#define WMI_UNIFIED_NOA_ATTR_INDEX_GET(hdr) \ + WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_INDEX) -#define WMI_UNIFIED_NOA_ATTR_INDEX_SET(hdr, v) \ - WMI_F_RMW((hdr)->noa_attributes, (v) & 0xff, \ - WMI_UNIFIED_NOA_ATTR_INDEX); +#define WMI_UNIFIED_NOA_ATTR_INDEX_SET(hdr, v) \ + WMI_F_RMW((hdr)->noa_attributes, (v) & 0xff, \ + WMI_UNIFIED_NOA_ATTR_INDEX); -#define WMI_UNIFIED_NOA_ATTR_OPP_PS 0x10000 -#define WMI_UNIFIED_NOA_ATTR_OPP_PS_S 16 +#define WMI_UNIFIED_NOA_ATTR_OPP_PS 0x10000 +#define WMI_UNIFIED_NOA_ATTR_OPP_PS_S 16 -#define WMI_UNIFIED_NOA_ATTR_OPP_PS_GET(hdr) \ - WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_OPP_PS) +#define WMI_UNIFIED_NOA_ATTR_OPP_PS_GET(hdr) \ + WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_OPP_PS) -#define WMI_UNIFIED_NOA_ATTR_OPP_PS_SET(hdr) \ - WMI_F_RMW((hdr)->noa_attributes, 0x1, \ - WMI_UNIFIED_NOA_ATTR_OPP_PS); +#define WMI_UNIFIED_NOA_ATTR_OPP_PS_SET(hdr) \ + WMI_F_RMW((hdr)->noa_attributes, 0x1, \ + WMI_UNIFIED_NOA_ATTR_OPP_PS); -#define WMI_UNIFIED_NOA_ATTR_CTWIN 0xfe0000 -#define WMI_UNIFIED_NOA_ATTR_CTWIN_S 17 +#define WMI_UNIFIED_NOA_ATTR_CTWIN 0xfe0000 +#define WMI_UNIFIED_NOA_ATTR_CTWIN_S 17 -#define WMI_UNIFIED_NOA_ATTR_CTWIN_GET(hdr) \ - WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_CTWIN) +#define WMI_UNIFIED_NOA_ATTR_CTWIN_GET(hdr) \ + WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_CTWIN) -#define WMI_UNIFIED_NOA_ATTR_CTWIN_SET(hdr, v) \ - WMI_F_RMW((hdr)->noa_attributes, (v) & 0x7f, \ - WMI_UNIFIED_NOA_ATTR_CTWIN); +#define WMI_UNIFIED_NOA_ATTR_CTWIN_SET(hdr, v) \ + WMI_F_RMW((hdr)->noa_attributes, (v) & 0x7f, \ + WMI_UNIFIED_NOA_ATTR_CTWIN); -#define WMI_UNIFIED_NOA_ATTR_NUM_DESC 0xff000000 -#define WMI_UNIFIED_NOA_ATTR_NUM_DESC_S 24 +#define WMI_UNIFIED_NOA_ATTR_NUM_DESC 0xff000000 +#define WMI_UNIFIED_NOA_ATTR_NUM_DESC_S 24 -#define WMI_UNIFIED_NOA_ATTR_NUM_DESC_GET(hdr) \ - WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_NUM_DESC) +#define WMI_UNIFIED_NOA_ATTR_NUM_DESC_GET(hdr) \ + WMI_F_MS((hdr)->noa_attributes, WMI_UNIFIED_NOA_ATTR_NUM_DESC) -#define WMI_UNIFIED_NOA_ATTR_NUM_DESC_SET(hdr, v) \ - WMI_F_RMW((hdr)->noa_attributes, (v) & 0xff, \ - WMI_UNIFIED_NOA_ATTR_NUM_DESC); +#define WMI_UNIFIED_NOA_ATTR_NUM_DESC_SET(hdr, v) \ + WMI_F_RMW((hdr)->noa_attributes, (v) & 0xff, \ + WMI_UNIFIED_NOA_ATTR_NUM_DESC); typedef struct { - /** TIM info */ - wmi_tim_info tim_info; - /** P2P NOA info */ - wmi_p2p_noa_info p2p_noa_info; -/* TBD: More info elements to be added later */ + /** TIM info */ + wmi_tim_info tim_info; + /** P2P NOA info */ + wmi_p2p_noa_info p2p_noa_info; + /* TBD: More info elements to be added later */ } wmi_bcn_info; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param */ - /** bitmap identifying the VDEVs, generated by the caller */ - A_UINT32 vdev_map; -/* This TLV is followed by tim_info and p2p_noa_info for each vdev in vdevmap : - * wmi_tim_info tim_info[]; - * wmi_p2p_noa_info p2p_noa_info[]; - * - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param */ + /** bitmap identifying the VDEVs, generated by the caller */ + A_UINT32 vdev_map; + /** how many vdev's info is included in this message + * If this field is zero, then the number of vdevs is specified by + * the number of bits set in the vdev_map bitmap. + */ + A_UINT32 num_vdevs; + /* This TLV is followed by tim_info and p2p_noa_info for each vdev: + * wmi_tim_info tim_info[]; + * wmi_p2p_noa_info p2p_noa_info[]; + * + */ } wmi_host_swba_event_fixed_param; #define WMI_MAX_AP_VDEV 16 - typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param */ - /** bimtap of VDEVs that has tbtt offset updated */ - A_UINT32 vdev_map; -/* The TLVs for tbttoffset_list will follow this TLV. - * tbtt offset list in the order of the LSB to MSB in the vdev_map bitmap - * A_UINT32 tbttoffset_list[WMI_MAX_AP_VDEV]; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param */ + /** bimtap of VDEVs that has tbtt offset updated */ + A_UINT32 vdev_map; + /* The TLVs for tbttoffset_list will follow this TLV. + * tbtt offset list in the order of the LSB to MSB in the vdev_map bitmap + * A_UINT32 tbttoffset_list[WMI_MAX_AP_VDEV]; + */ } wmi_tbtt_offset_event_fixed_param; +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tbtt_offset_info */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** tbttoffset in TUs */ + A_UINT32 tbttoffset; +} wmi_tbtt_offset_info; + +/** Use this event if number of vdevs > 32 */ +typedef struct { + /* + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_tbtt_offset_ext_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 num_vdevs; + /* + * The TLVs for tbttoffset will follow this TLV. + * Of size num_vdevs * wmi_tbtt_offset_info + */ +} wmi_tbtt_offset_ext_event_fixed_param; /* Peer Specific commands and events */ typedef struct { - A_UINT32 percentage; /* in unit of 12.5% */ - A_UINT32 min_delta; /* in unit of Mbps */ + A_UINT32 percentage; /* in unit of 12.5% */ + A_UINT32 min_delta; /* in unit of Mbps */ } rate_delta_t; #define PEER_RATE_REPORT_COND_FLAG_DELTA 0x01 @@ -6682,31 +7393,46 @@ typedef struct { #define MAX_NUM_OF_RATE_THRESH 4 typedef struct { - A_UINT32 val_cond_flags; /* PEER_RATE_REPORT_COND_FLAG_DELTA, PEER_RATE_REPORT_COND_FLAG_THRESHOLD - Any of these two conditions or both of them can be set. */ - rate_delta_t rate_delta; - A_UINT32 rate_threshold[MAX_NUM_OF_RATE_THRESH]; /* In unit of Mbps. There are at most 4 thresholds. - If the threshold count is less than 4, set zero to - the one following the last threshold */ + /* + * PEER_RATE_REPORT_COND_FLAG_DELTA, + * PEER_RATE_REPORT_COND_FLAG_THRESHOLD + * Any of these two conditions or both of + * them can be set. + */ + A_UINT32 val_cond_flags; + rate_delta_t rate_delta; + /* + * In unit of Mbps. There are at most 4 thresholds + * If the threshold count is less than 4, set zero to + * the one following the last threshold + */ + A_UINT32 rate_threshold[MAX_NUM_OF_RATE_THRESH]; } report_cond_per_phy_t; enum peer_rate_report_cond_phy_type { - PEER_RATE_REPORT_COND_11B = 0, - PEER_RATE_REPORT_COND_11A_G, - PEER_RATE_REPORT_COND_11N, - PEER_RATE_REPORT_COND_11AC, - PEER_RATE_REPORT_COND_MAX_NUM + PEER_RATE_REPORT_COND_11B = 0, + PEER_RATE_REPORT_COND_11A_G, + PEER_RATE_REPORT_COND_11N, + PEER_RATE_REPORT_COND_11AC, + PEER_RATE_REPORT_COND_MAX_NUM }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_rate_report_condtion_fixed_param */ - A_UINT32 enable_rate_report; /* 1= enable, 0=disable */ - A_UINT32 report_backoff_time; /* in unit of msecond */ - A_UINT32 report_timer_period; /* in unit of msecond */ - /* In the following field, the array index means the phy type, - * please see enum peer_rate_report_cond_phy_type for detail */ - report_cond_per_phy_t cond_per_phy[PEER_RATE_REPORT_COND_MAX_NUM]; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_rate_report_condtion_fixed_param + */ + A_UINT32 tlv_header; + /* 1= enable, 0=disable */ + A_UINT32 enable_rate_report; + A_UINT32 report_backoff_time; /* in unit of msecond */ + A_UINT32 report_timer_period; /* in unit of msecond */ + /* + *In the following field, the array index means the phy type, + * please see enum peer_rate_report_cond_phy_type for detail + */ + report_cond_per_phy_t cond_per_phy[PEER_RATE_REPORT_COND_MAX_NUM]; } wmi_peer_set_rate_report_condition_fixed_param; /* Peer Type: @@ -6715,169 +7441,182 @@ typedef struct { * peer is explicitly a TDLS peer */ enum wmi_peer_type { - WMI_PEER_TYPE_DEFAULT = 0, /* Generic/Non-BSS/Self Peer */ - WMI_PEER_TYPE_BSS = 1, /* Peer is BSS Peer entry */ - WMI_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */ - WMI_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */ - WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ - WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ - /* Reserved from 128 - 255 for target internal use.*/ - WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ + WMI_PEER_TYPE_DEFAULT = 0, /* Generic/Non-BSS/Self Peer */ + WMI_PEER_TYPE_BSS = 1, /* Peer is BSS Peer entry */ + WMI_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */ + WMI_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */ + WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ + WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type + * is assigned up to 127 */ + /* Reserved from 128 - 255 for + * target internal use.*/ + WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ }; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** peer type: see enum values above */ - A_UINT32 peer_type; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** peer type: see enum values above */ + A_UINT32 peer_type; } wmi_peer_create_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_peer_delete_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** - * maximum block ack window size to use during a rx block ack negotiation, - * i.e. the maximum number of MPDUs per A-MPDU that will be received - */ - A_UINT32 rx_block_ack_win_limit; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** + * maximum block ack window size to use during a rx block ack + * negotiation, i.e. the maximum number of MPDUs per A-MPDU + * that will be received + */ + A_UINT32 rx_block_ack_win_limit; } wmi_peer_set_rx_blocksize_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** tid bitmap identifying the tids to flush */ - A_UINT32 peer_tid_bitmap; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** tid bitmap identifying the tids to flush */ + A_UINT32 peer_tid_bitmap; } wmi_peer_flush_tids_cmd_fixed_param; typedef struct { - /** rate mode . 0: disable fixed rate (auto rate) - * 1: legacy (non 11n) rate specified as ieee rate 2*Mbps - * 2: ht20 11n rate specified as mcs index - * 3: ht40 11n rate specified as mcs index - */ - A_UINT32 rate_mode; - /** 4 rate values for 4 rate series. series 0 is stored in byte 0 (LSB) - * and series 3 is stored at byte 3 (MSB) */ - A_UINT32 rate_series; - /** 4 retry counts for 4 rate series. retry count for rate 0 is stored in byte 0 (LSB) - * and retry count for rate 3 is stored at byte 3 (MSB) */ - A_UINT32 rate_retries; + /** rate mode . 0: disable fixed rate (auto rate) + * 1: legacy (non 11n) rate specified as ieee rate 2*Mbps + * 2: ht20 11n rate specified as mcs index + * 3: ht40 11n rate specified as mcs index + */ + A_UINT32 rate_mode; + /** 4 rate values for 4 rate series. series 0 is stored in byte 0 (LSB) + * and series 3 is stored at byte 3 (MSB) */ + A_UINT32 rate_series; + /** 4 retry counts for 4 rate series. retry count for rate 0 is stored in byte 0 (LSB) + * and retry count for rate 3 is stored at byte 3 (MSB) */ + A_UINT32 rate_retries; } wmi_fixed_rate; typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** fixed rate */ - wmi_fixed_rate peer_fixed_rate; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** fixed rate */ + wmi_fixed_rate peer_fixed_rate; } wmi_peer_fixed_rate_cmd; #define WMI_MGMT_TID 17 typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_addba_clear_resp_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_addba_clear_resp_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_addba_clear_resp_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_addba_send_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** Buffer/Window size*/ - A_UINT32 buffersize; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_addba_send_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** Buffer/Window size*/ + A_UINT32 buffersize; } wmi_addba_send_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_delba_send_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** Is Initiator */ - A_UINT32 initiator; - /** Reason code */ - A_UINT32 reasoncode; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_delba_send_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** Is Initiator */ + A_UINT32 initiator; + /** Reason code */ + A_UINT32 reasoncode; } wmi_delba_send_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_addba_setresponse_cmd_fixed_param */ - /** unique id identifying the vdev, generated by the caller */ - A_UINT32 vdev_id; - /** peer mac address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** status code */ - A_UINT32 statuscode; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_addba_setresponse_cmd_fixed_param */ + /** unique id identifying the vdev, generated by the caller */ + A_UINT32 vdev_id; + /** peer mac address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** status code */ + A_UINT32 statuscode; } wmi_addba_setresponse_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_send_singleamsdu_cmd_fixed_param */ - /** unique id identifying the vdev, generated by the caller */ - A_UINT32 vdev_id; - /** peer mac address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_send_singleamsdu_cmd_fixed_param */ + /** unique id identifying the vdev, generated by the caller */ + A_UINT32 vdev_id; + /** peer mac address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; } wmi_send_singleamsdu_cmd_fixed_param; /* Type of Station DTIM Power Save method */ enum { - /* For NORMAL DTIM, the parameter is the number of beacon intervals and - * also the same value as the listen interval. For this method, the - * station will wake up based on the listen interval. If this - * listen interval is not equal to DTIM, then the station may - * miss certain DTIM beacons. If this value is 1, then the - * station will wake up for every beacon. - */ - WMI_STA_DTIM_PS_NORMAL_DTIM = 0x01, - /* For MODULATED_DTIM, parameter is a multiple of DTIM beacons to skip. - * When this value is 1, then the station will wake at every DTIM beacon. - * If this value is >1, then the station will skip certain DTIM beacons. - * This value is the multiple of DTIM intervals that the station will - * wake up to receive the DTIM beacons. - */ - WMI_STA_DTIM_PS_MODULATED_DTIM = 0x02, + /* For NORMAL DTIM, the parameter is the number of beacon intervals and + * also the same value as the listen interval. For this method, the + * station will wake up based on the listen interval. If this + * listen interval is not equal to DTIM, then the station may + * miss certain DTIM beacons. If this value is 1, then the + * station will wake up for every beacon. + */ + WMI_STA_DTIM_PS_NORMAL_DTIM = 0x01, + /* For MODULATED_DTIM, parameter is a multiple of DTIM beacons to skip. + * When this value is 1, then the station will wake at every DTIM beacon. + * If this value is >1, then the station will skip certain DTIM beacons. + * This value is the multiple of DTIM intervals that the station will + * wake up to receive the DTIM beacons. + */ + WMI_STA_DTIM_PS_MODULATED_DTIM = 0x02, }; /* Parameter structure for the WMI_STA_DTIM_PS_METHOD_CMDID */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** Station DTIM Power Save method as defined above */ - A_UINT32 dtim_pwrsave_method; - /** DTIM PS value. Contents depends on the method */ - A_UINT32 value; - /** Modulated DTIM value */ - A_UINT32 MaxLIModulatedDTIM; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* Station DTIM Power Save method as defined above */ + A_UINT32 dtim_pwrsave_method; + /* DTIM PS value. Contents depends on the method */ + A_UINT32 value; + /* Modulated DTIM value */ + A_UINT32 MaxLIModulatedDTIM; } wmi_sta_dtim_ps_method_cmd_fixed_param; /* @@ -6909,34 +7648,36 @@ typedef struct { * should be 0. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_param */ - /** WMM Access category from 0 to 3 */ - A_UINT32 wmm_ac; - /** User priority to use in trigger frames. It is the TID - * value. This field needs to be specified and may not be - * equivalent to AC since some implementation may use the TSPEC - * to enable UAPSD and negotiate a particular user priority. */ - A_UINT32 user_priority; - /** service interval in ms */ - A_UINT32 service_interval; - /** Suspend interval in ms */ - A_UINT32 suspend_interval; - /** delay interval in ms */ - A_UINT32 delay_interval; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_param */ + /** WMM Access category from 0 to 3 */ + A_UINT32 wmm_ac; + /** User priority to use in trigger frames. It is the TID + * value. This field needs to be specified and may not be + * equivalent to AC since some implementation may use the TSPEC + * to enable UAPSD and negotiate a particular user priority. */ + A_UINT32 user_priority; + /** service interval in ms */ + A_UINT32 service_interval; + /** Suspend interval in ms */ + A_UINT32 suspend_interval; + /** delay interval in ms */ + A_UINT32 delay_interval; } wmi_sta_uapsd_auto_trig_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer mac address */ - wmi_mac_addr peer_macaddr; - /** Number of AC to specify */ - A_UINT32 num_ac; -/* - * Following this struc is the TLV: - * wmi_sta_uapsd_auto_trig_param ac_param[]; <-- Variable number of AC parameters (defined by field num_ac) - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_uapsd_auto_trig_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer mac address */ + wmi_mac_addr peer_macaddr; + /** Number of AC to specify */ + A_UINT32 num_ac; + /* + * Following this struc is the TLV: + * wmi_sta_uapsd_auto_trig_param ac_param[]; //Variable number of AC parameters (defined by field num_ac) + */ } wmi_sta_uapsd_auto_trig_cmd_fixed_param; @@ -6953,7 +7694,7 @@ typedef struct { /** USE 4 ADDR */ #define WMI_PEER_USE_4ADDR 0x6 /* set group membership status */ -#define WMI_PEER_MEMBERSHIP 0x7 +#define WMI_PEER_MEMBERSHIP 0x7 #define WMI_PEER_USERPOS 0x8 /* * A critical high-level protocol is being used with this peer. Target @@ -6969,7 +7710,7 @@ typedef struct { * For STA VDEV this peer corresponds to the AP's BSS peer. * For AP VDEV this peer corresponds to the remote peer STA. */ -#define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 +#define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 /* set Tx failure count threshold for the peer - Currently unused */ #define WMI_PEER_TX_FAIL_CNT_THR 0xA /* Enable H/W retry and Enable H/W Send CTS2S before Data */ @@ -6979,7 +7720,7 @@ typedef struct { #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC /** peer phy mode */ -#define WMI_PEER_PHYMODE 0xD +#define WMI_PEER_PHYMODE 0xD /** Use FIXED Pwr */ #define WMI_PEER_USE_FIXED_PWR 0xE /** Set peer fixed rate */ @@ -6993,9 +7734,9 @@ typedef struct { /** * default ring routing for peer data packets, * param_value = bit 0 for hash based routing enabled or not - * (value 1 is enabled, value 0 is disabled) - * bits 1:5 are for ring 32 (i.e. ring id value - * selected from 0 to 31 values) + * (value 1 is enabled, value 0 is disabled) + * bits 1:5 are for ring 32 (i.e. ring id value + * selected from 0 to 31 values) */ #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 @@ -7005,29 +7746,31 @@ typedef struct { #define WMI_PEER_MIMO_PS_DYNAMIC 0x2 typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** parameter id */ - A_UINT32 param_id; - /** parametr value */ - A_UINT32 param_value; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** parameter id */ + A_UINT32 param_id; + /** parametr value */ + A_UINT32 param_value; } wmi_peer_set_param_cmd_fixed_param; typedef union { - /* - * The A_UINT16 "mode" and "tx_rate" fields can only be directly used - * by the target or a little-endian host. - * A big-endian host needs to use the WMI_PEER_MAX_MIN_TX_xxx_GET/SET - * macros on the A_UINT32 "value" field. - */ - struct { - A_UINT16 mode; /* 0:CCK, 1:OFDM, 2:HT, 3:VHT (see WMI_RATE_PREAMBLE) */ - A_UINT16 tx_rate; /* see per-mode specs below */ - }; - A_UINT32 value; /* for use by big-endian host */ + /* + * The A_UINT16 "mode" and "tx_rate" fields can only be directly used + * by the target or a little-endian host. + * A big-endian host needs to use the WMI_PEER_MAX_MIN_TX_xxx_GET/SET + * macros on the A_UINT32 "value" field. + */ + struct { + /* 0:CCK, 1:OFDM, 2:HT, 3:VHT (see WMI_RATE_PREAMBLE) */ + A_UINT16 mode; + A_UINT16 tx_rate; /* see per-mode specs below */ + }; + A_UINT32 value; /* for use by big-endian host */ } wmi_peer_max_min_tx_rate; /* @@ -7040,7 +7783,8 @@ typedef union { #define WMI_PEER_MAX_MIN_TX_RATE_GET(value32) WMI_GET_BITS(value32, 16, 16) #define WMI_PEER_MAX_MIN_TX_RATE_SET(value32, tx_mode) WMI_SET_BITS(value32, 16, 16, tx_mode) -/* CCK max/min tx Rate description +/* + * CCK max/min tx Rate description * tx_rate = 0: 1 Mbps * tx_rate = 1: 2 Mbps * tx_rate = 2: 5.5 Mbps @@ -7048,14 +7792,15 @@ typedef union { * tx_rate = else: invalid */ enum { - WMI_MAX_CCK_TX_RATE_1M, /* up to 1M CCK Rate avaliable */ - WMI_MAX_CCK_TX_RATE_2M, /* up to 2M CCK Rate avaliable */ - WMI_MAX_CCK_TX_RATE_5_5M, /* up to 5.5M CCK Rate avaliable */ - WMI_MAX_CCK_TX_RATE_11M, /* up to 11M CCK Rate avaliable */ - WMI_MAX_CCK_TX_RATE = WMI_MAX_CCK_TX_RATE_11M, + WMI_MAX_CCK_TX_RATE_1M, /* up to 1M CCK Rate avaliable */ + WMI_MAX_CCK_TX_RATE_2M, /* up to 2M CCK Rate avaliable */ + WMI_MAX_CCK_TX_RATE_5_5M, /* up to 5.5M CCK Rate avaliable */ + WMI_MAX_CCK_TX_RATE_11M, /* up to 11M CCK Rate avaliable */ + WMI_MAX_CCK_TX_RATE = WMI_MAX_CCK_TX_RATE_11M, }; -/* OFDM max/min tx Rate description +/* + * OFDM max/min tx Rate description * tx_rate = 0: 6 Mbps * tx_rate = 1: 9 Mbps * tx_rate = 2: 12 Mbps @@ -7067,41 +7812,42 @@ enum { * tx_rate = else: invalid */ enum { - WMI_MAX_OFDM_TX_RATE_6M, /* up to 6M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_9M, /* up to 9M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_12M, /* up to 12M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_18M, /* up to 18M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_24M, /* up to 24M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_36M, /* up to 36M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_48M, /* up to 48M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE_54M, /* up to 54M OFDM Rate avaliable */ - WMI_MAX_OFDM_TX_RATE = WMI_MAX_OFDM_TX_RATE_54M, + WMI_MAX_OFDM_TX_RATE_6M, /* up to 6M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_9M, /* up to 9M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_12M, /* up to 12M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_18M, /* up to 18M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_24M, /* up to 24M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_36M, /* up to 36M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_48M, /* up to 48M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE_54M, /* up to 54M OFDM Rate avaliable */ + WMI_MAX_OFDM_TX_RATE = WMI_MAX_OFDM_TX_RATE_54M, }; -/* HT max/min tx rate description +/* + * HT max/min tx rate description * tx_rate = 0~7 : MCS Rate 0~7 * tx_rate=else : invalid. */ #define WMI_MAX_HT_TX_MCS 0x07 -/* VHT max/min tx rate description +/* + * VHT max/min tx rate description * tx_rate = 0~9 : MCS Rate 0~9 * tx_rate=else : invalid. */ #define WMI_MAX_VHT_TX_MCS 0x09 - #define MAX_SUPPORTED_RATES 128 typedef struct { - /** total number of rates */ - A_UINT32 num_rates; - /** - * rates (each 8bit value) packed into a 32 bit word. - * the rates are filled from least significant byte to most - * significant byte. - */ - A_UINT32 rates[(MAX_SUPPORTED_RATES / 4) + 1]; + /** total number of rates */ + A_UINT32 num_rates; + /** + * rates (each 8bit value) packed into a 32 bit word. + * the rates are filled from least significant byte to most + * significant byte. + */ + A_UINT32 rates[(MAX_SUPPORTED_RATES / 4) + 1]; } wmi_rate_set; /* NOTE: It would bea good idea to represent the Tx MCS @@ -7109,37 +7855,39 @@ typedef struct { * into multiple words for convenience */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vht_rate_set */ - A_UINT32 rx_max_rate; /* Max Rx data rate */ - A_UINT32 rx_mcs_set; /* Negotiated RX VHT rates */ - A_UINT32 tx_max_rate; /* Max Tx data rate */ - A_UINT32 tx_mcs_set; /* Negotiated TX VHT rates */ - A_UINT32 tx_max_mcs_nss; /* b0-b3: max mcs idx; b4-b7: max nss */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vht_rate_set */ + A_UINT32 rx_max_rate; /* Max Rx data rate */ + A_UINT32 rx_mcs_set; /* Negotiated RX VHT rates */ + A_UINT32 tx_max_rate; /* Max Tx data rate */ + A_UINT32 tx_mcs_set; /* Negotiated TX VHT rates */ + A_UINT32 tx_max_mcs_nss; /* b0-b3: max mcs idx; b4-b7: max nss */ } wmi_vht_rate_set; /* * IMPORTANT: Make sure the bit definitions here are consistent * with the ni_flags definitions in wlan_peer.h */ -#define WMI_PEER_AUTH 0x00000001 /* Authorized for data */ -#define WMI_PEER_QOS 0x00000002 /* QoS enabled */ -#define WMI_PEER_NEED_PTK_4_WAY 0x00000004 /* Needs PTK 4 way handshake for authorization */ -#define WMI_PEER_NEED_GTK_2_WAY 0x00000010 /* Needs GTK 2 way handshake after 4-way handshake */ -#define WMI_PEER_APSD 0x00000800 /* U-APSD power save enabled */ -#define WMI_PEER_HT 0x00001000 /* HT enabled */ -#define WMI_PEER_40MHZ 0x00002000 /* 40MHz enabld */ -#define WMI_PEER_STBC 0x00008000 /* STBC Enabled */ -#define WMI_PEER_LDPC 0x00010000 /* LDPC ENabled */ -#define WMI_PEER_DYN_MIMOPS 0x00020000 /* Dynamic MIMO PS Enabled */ -#define WMI_PEER_STATIC_MIMOPS 0x00040000 /* Static MIMO PS enabled */ -#define WMI_PEER_SPATIAL_MUX 0x00200000 /* SM Enabled */ -#define WMI_PEER_VHT 0x02000000 /* VHT Enabled */ -#define WMI_PEER_80MHZ 0x04000000 /* 80MHz enabld */ -#define WMI_PEER_PMF 0x08000000 /* Robust Management Frame Protection enabled */ +#define WMI_PEER_AUTH 0x00000001 /* Authorized for data */ +#define WMI_PEER_QOS 0x00000002 /* QoS enabled */ +#define WMI_PEER_NEED_PTK_4_WAY 0x00000004 /* Needs PTK 4 way handshake for authorization */ +#define WMI_PEER_NEED_GTK_2_WAY 0x00000010 /* Needs GTK 2 way handshake after 4-way handshake */ +#define WMI_PEER_HE 0x00000400 /* HE Enabled */ +#define WMI_PEER_APSD 0x00000800 /* U-APSD power save enabled */ +#define WMI_PEER_HT 0x00001000 /* HT enabled */ +#define WMI_PEER_40MHZ 0x00002000 /* 40MHz enabld */ +#define WMI_PEER_STBC 0x00008000 /* STBC Enabled */ +#define WMI_PEER_LDPC 0x00010000 /* LDPC ENabled */ +#define WMI_PEER_DYN_MIMOPS 0x00020000 /* Dynamic MIMO PS Enabled */ +#define WMI_PEER_STATIC_MIMOPS 0x00040000 /* Static MIMO PS enabled */ +#define WMI_PEER_SPATIAL_MUX 0x00200000 /* SM Enabled */ +#define WMI_PEER_VHT 0x02000000 /* VHT Enabled */ +#define WMI_PEER_80MHZ 0x04000000 /* 80MHz enabld */ +#define WMI_PEER_PMF 0x08000000 /* Robust Management Frame Protection enabled */ /** CAUTION TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. Need to be clean up */ -#define WMI_PEER_IS_P2P_CAPABLE 0x20000000 /* P2P capable peer */ -#define WMI_PEER_160MHZ 0x40000000 /* 160 MHz enabled */ -#define WMI_PEER_SAFEMODE_EN 0x80000000 /* Fips Mode Enabled */ +#define WMI_PEER_IS_P2P_CAPABLE 0x20000000 /* P2P capable peer */ +#define WMI_PEER_160MHZ 0x40000000 /* 160 MHz enabled */ +#define WMI_PEER_SAFEMODE_EN 0x80000000 /* Fips Mode Enabled */ /** * Peer rate capabilities. @@ -7158,6 +7906,7 @@ typedef struct { #define WMI_RC_HT_FLAG 0x08 /* HT */ #define WMI_RC_RTSCTS_FLAG 0x10 /* RTS-CTS */ #define WMI_RC_TX_STBC_FLAG 0x20 /* TX STBC */ +#define WMI_RC_TX_STBC_FLAG_S 5 /* TX STBC */ #define WMI_RC_RX_STBC_FLAG 0xC0 /* RX STBC ,2 bits */ #define WMI_RC_RX_STBC_FLAG_S 6 /* RX STBC ,2 bits */ #define WMI_RC_WEP_TKIP_FLAG 0x100 /* WEP/TKIP encryption */ @@ -7165,155 +7914,170 @@ typedef struct { #define WMI_RC_UAPSD_FLAG 0x400 /* UAPSD Rate Control */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param */ - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** VDEV id */ - A_UINT32 vdev_id; - /** assoc = 1 reassoc = 0 */ - A_UINT32 peer_new_assoc; - /** peer associd (16 bits) */ - A_UINT32 peer_associd; - /** peer station flags: see definition above */ - A_UINT32 peer_flags; - /** negotiated capabilities (lower 16 bits)*/ - A_UINT32 peer_caps; - /** Listen interval */ - A_UINT32 peer_listen_intval; - /** HT capabilties of the peer */ - A_UINT32 peer_ht_caps; - /** maximum rx A-MPDU length */ - A_UINT32 peer_max_mpdu; - /** mpdu density of the peer in usec(0 to 16) */ - A_UINT32 peer_mpdu_density; - /** peer rate capabilties see flags above */ - A_UINT32 peer_rate_caps; - /** num spatial streams */ - A_UINT32 peer_nss; - /** VHT capabilties of the peer */ - A_UINT32 peer_vht_caps; - /** phy mode */ - A_UINT32 peer_phymode; - /** HT Operation Element of the peer. Five bytes packed in 2 - * INT32 array and filled from lsb to msb. - * Note that the size of array peer_ht_info[] cannotbe changed - * without breaking WMI Compatibility. */ - A_UINT32 peer_ht_info[2]; - /** total number of negotiated legacy rate set. Also the sizeof - * peer_legacy_rates[] */ - A_UINT32 num_peer_legacy_rates; - /** total number of negotiated ht rate set. Also the sizeof - * peer_ht_rates[] */ - A_UINT32 num_peer_ht_rates; - /** - * Bitmap providing customized mapping of bandwidths to max Rx NSS - * for this peer. - * This is required since 802.11 standard currently facilitates peer to be - * able to advertise only a single max Rx NSS value across all bandwidths. - * Some QCA chipsets might need to be able to advertise a different max - * Rx NSS value for 160 MHz, than that for 80 MHz and lower. - * - * bit[2:0] : Represents value of Rx NSS for VHT 160 MHz - * bit[30:3]: Reserved - * bit[31] : MSB(0/1): 1 in case of valid data else all bits will be set - * to 0 by host - */ - A_UINT32 peer_bw_rxnss_override; - - /* 802.11ax capabilities */ - wmi_ppe_threshold peer_ppet; - A_UINT32 peer_he_cap_info; /* protocol-defined HE / 11ax capability flags */ - A_UINT32 peer_he_ops; /* HE operation contains BSS color */ - -/* Following this struc are the TLV's: - * A_UINT8 peer_legacy_rates[]; - * A_UINT8 peer_ht_rates[]; - * wmi_vht_rate_set peer_vht_rates; <-- VHT capabilties of the peer - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param */ + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** VDEV id */ + A_UINT32 vdev_id; + /** assoc = 1 reassoc = 0 */ + A_UINT32 peer_new_assoc; + /** peer associd (16 bits) */ + A_UINT32 peer_associd; + /** peer station flags: see definition above */ + A_UINT32 peer_flags; + /** negotiated capabilities (lower 16 bits)*/ + A_UINT32 peer_caps; + /** Listen interval */ + A_UINT32 peer_listen_intval; + /** HT capabilties of the peer */ + A_UINT32 peer_ht_caps; + /** maximum rx A-MPDU length */ + A_UINT32 peer_max_mpdu; + /** mpdu density of the peer in usec(0 to 16) */ + A_UINT32 peer_mpdu_density; + /** peer rate capabilties see flags above */ + A_UINT32 peer_rate_caps; + /** num spatial streams */ + A_UINT32 peer_nss; + /** VHT capabilties of the peer */ + A_UINT32 peer_vht_caps; + /** phy mode */ + A_UINT32 peer_phymode; + /** HT Operation Element of the peer. Five bytes packed in 2 + * INT32 array and filled from lsb to msb. + * Note that the size of array peer_ht_info[] cannotbe changed + * without breaking WMI Compatibility. */ + A_UINT32 peer_ht_info[2]; + /** total number of negotiated legacy rate set. Also the sizeof + * peer_legacy_rates[] */ + A_UINT32 num_peer_legacy_rates; + /** total number of negotiated ht rate set. Also the sizeof + * peer_ht_rates[] */ + A_UINT32 num_peer_ht_rates; + /* + * Bitmap providing customized mapping of bandwidths to max Rx NSS + * for this peer. + * This is required since 802.11 standard currently facilitates peer to + * be able to advertise only a single max Rx NSS value across all + * bandwidths. + * Some QCA chipsets might need to be able to advertise a different max + * Rx NSS value for 160 MHz, than that for 80 MHz and lower. + * + * bit[2:0] : Represents value of Rx NSS for VHT 160 MHz + * bit[30:3]: Reserved + * bit[31] : MSB(0/1): 1 in case of valid data else all bits will be + * set to 0 by host + */ + A_UINT32 peer_bw_rxnss_override; + /* 802.11ax capabilities */ + wmi_ppe_threshold peer_ppet; + /* protocol-defined HE / 11ax capability flags */ + A_UINT32 peer_he_cap_info; + A_UINT32 peer_he_ops; /* HE operation contains BSS color */ + A_UINT32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; + A_UINT32 peer_he_mcs; /* HE MCS/NSS set */ + /* Following this struct are the TLV's: + * A_UINT8 peer_legacy_rates[]; + * A_UINT8 peer_ht_rates[]; + * wmi_vht_rate_set peer_vht_rates; //VHT capabilties of the peer + */ } wmi_peer_assoc_complete_cmd_fixed_param; /* WDS Entry Flags */ #define WMI_WDS_FLAG_STATIC 0x1 /* Disable aging & learning */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_add_wds_entry_cmd_fixed_param */ - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** wds MAC addr */ - wmi_mac_addr wds_macaddr; - /* Flags associated with WDS entry - see WMI_WDS_FLAG defs */ - A_UINT32 flags; - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_add_wds_entry_cmd_fixed_param */ + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** wds MAC addr */ + wmi_mac_addr wds_macaddr; + /* Flags associated with WDS entry - see WMI_WDS_FLAG defs */ + A_UINT32 flags; + A_UINT32 vdev_id; } wmi_peer_add_wds_entry_cmd_fixed_param; +#define WMI_CHAN_INFO_START_RESP 0 +#define WMI_CHAN_INFO_END_RESP 1 + typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param */ - /** wds MAC addr */ - wmi_mac_addr wds_macaddr; - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param */ + /** wds MAC addr */ + wmi_mac_addr wds_macaddr; + A_UINT32 vdev_id; } wmi_peer_remove_wds_entry_cmd_fixed_param; - typedef struct { - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_peer_q_empty_callback_event; /* * Command to update an already existing WDS entry. Different address setting * combinations are possible. * - * Valid wds and peer -> Associated WDS entry peer ptr & flags will be updated. + * Valid wds and peer -> Associated WDS entry peer ptr & flags will be updated. * Valid wds and null peer -> Associated WDS entry flags will be updated. - * Null wds and Valid peer -> Flags will be updated for all WDS entries behind the peer. + * Null wds and Valid peer-> Flags will be updated for all WDS entries + * behind the peer. * Null wds and peer -> Flags will be updated for all WDS entries. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param */ - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** wds MAC addr */ - wmi_mac_addr wds_macaddr; - /* Flags associated with WDS entry */ - A_UINT32 flags; - A_UINT32 vdev_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** wds MAC addr */ + wmi_mac_addr wds_macaddr; + /* Flags associated with WDS entry */ + A_UINT32 flags; + A_UINT32 vdev_id; } wmi_peer_update_wds_entry_cmd_fixed_param; /** * Channel info WMI event */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param */ - /** Error code */ - A_UINT32 err_code; - /** Channel freq */ - A_UINT32 freq; - /** Read flags */ - A_UINT32 cmd_flags; - /** Noise Floor value */ - A_UINT32 noise_floor; - /** rx clear count */ - A_UINT32 rx_clear_count; - /** cycle count */ - A_UINT32 cycle_count; - /** channel tx power per range in 0.5dBm steps */ - A_UINT32 chan_tx_pwr_range; - /** channel tx power per throughput */ - A_UINT32 chan_tx_pwr_tp; - /** rx frame count (cumulative) */ - A_UINT32 rx_frame_count; - /** BSS rx cycle count */ - A_UINT32 my_bss_rx_cycle_count; - /** b-mode data rx time (units are microseconds) */ - A_UINT32 rx_11b_mode_data_duration; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param */ + /** Error code */ + A_UINT32 err_code; + /** Channel freq */ + A_UINT32 freq; + /** Read flags */ + A_UINT32 cmd_flags; + /** Noise Floor value */ + A_UINT32 noise_floor; + /** rx clear count */ + A_UINT32 rx_clear_count; + /** cycle count */ + A_UINT32 cycle_count; + /** channel tx power per range in 0.5dBm steps */ + A_UINT32 chan_tx_pwr_range; + /** channel tx power per throughput */ + A_UINT32 chan_tx_pwr_tp; + /** rx frame count (cumulative) */ + A_UINT32 rx_frame_count; + /** BSS rx cycle count */ + A_UINT32 my_bss_rx_cycle_count; + /** b-mode data rx time (units are microseconds) */ + A_UINT32 rx_11b_mode_data_duration; + /** tx frame count */ + A_UINT32 tx_frame_cnt; + /** mac clock */ + A_UINT32 mac_clk_mhz; } wmi_chan_info_event_fixed_param; /** * Non wlan interference event */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_dcs_cw_int */ - A_UINT32 channel; /* either number or freq in mhz*/ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_ath_dcs_cw_int */ + A_UINT32 channel; /* either number or freq in mhz */ } wlan_dcs_cw_int; #define ath_dcs_cw_int /* DEPRECATED */ wlan_dcs_cw_int /* alias */ @@ -7322,64 +8086,65 @@ typedef struct { * */ typedef struct _wlan_dcs_im_tgt_stats { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_dcs_im_tgt_stats_t */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wlan_dcs_im_tgt_stats_t + */ + A_UINT32 tlv_header; + /** current running TSF from the TSF-1 */ + A_UINT32 reg_tsf32; - /** current running TSF from the TSF-1 */ - A_UINT32 reg_tsf32; + /** Known last frame rssi, in case of multiple stations, if + * and at different ranges, this would not gaurantee that + * this is the least rssi. + */ + A_UINT32 last_ack_rssi; - /** Known last frame rssi, in case of multiple stations, if - * and at different ranges, this would not gaurantee that - * this is the least rssi. - */ - A_UINT32 last_ack_rssi; + /** Sum of all the failed durations in the last one second interval. + */ + A_UINT32 tx_waste_time; + /** count how many times the hal_rxerr_phy is marked, in this + * time period + */ + A_UINT32 rx_time; + A_UINT32 phyerr_cnt; - /** Sum of all the failed durations in the last one second interval. - */ - A_UINT32 tx_waste_time; - /** count how many times the hal_rxerr_phy is marked, in this - * time period - */ - A_UINT32 rx_time; - A_UINT32 phyerr_cnt; + /** + * WLAN IM stats from target to host + * + * Below statistics are sent from target to host periodically. + * These are collected at target as long as target is running + * and target chip is not in sleep. + * + */ - /** - * WLAN IM stats from target to host - * - * Below statistics are sent from target to host periodically. - * These are collected at target as long as target is running - * and target chip is not in sleep. - * - */ + /** listen time from ANI */ + A_INT32 listen_time; - /** listen time from ANI */ - A_INT32 listen_time; + /** tx frame count, MAC_PCU_TX_FRAME_CNT_ADDRESS */ + A_UINT32 reg_tx_frame_cnt; - /** tx frame count, MAC_PCU_TX_FRAME_CNT_ADDRESS */ - A_UINT32 reg_tx_frame_cnt; + /** rx frame count, MAC_PCU_RX_FRAME_CNT_ADDRESS */ + A_UINT32 reg_rx_frame_cnt; - /** rx frame count, MAC_PCU_RX_FRAME_CNT_ADDRESS */ - A_UINT32 reg_rx_frame_cnt; + /** rx clear count, MAC_PCU_RX_CLEAR_CNT_ADDRESS */ + A_UINT32 reg_rxclr_cnt; - /** rx clear count, MAC_PCU_RX_CLEAR_CNT_ADDRESS */ - A_UINT32 reg_rxclr_cnt; + /** total cycle counts MAC_PCU_CYCLE_CNT_ADDRESS */ + A_UINT32 reg_cycle_cnt; /* delta cycle count */ - /** total cycle counts MAC_PCU_CYCLE_CNT_ADDRESS */ - A_UINT32 reg_cycle_cnt; /* delta cycle count */ + /** extenstion channel rx clear count */ + A_UINT32 reg_rxclr_ext_cnt; - /** extenstion channel rx clear count */ - A_UINT32 reg_rxclr_ext_cnt; + /** OFDM phy error counts, MAC_PCU_PHY_ERR_CNT_1_ADDRESS */ + A_UINT32 reg_ofdm_phyerr_cnt; - /** OFDM phy error counts, MAC_PCU_PHY_ERR_CNT_1_ADDRESS */ - A_UINT32 reg_ofdm_phyerr_cnt; + /** CCK phy error count, MAC_PCU_PHY_ERR_CNT_2_ADDRESS */ + A_UINT32 reg_cck_phyerr_cnt; /* CCK err count since last reset, read from register */ + /** Channel noise floor (units are dBm) */ + A_INT32 chan_nf; - /** CCK phy error count, MAC_PCU_PHY_ERR_CNT_2_ADDRESS */ - A_UINT32 reg_cck_phyerr_cnt; /* CCK err count since last reset, read from register */ - - /** Channel noise floor (units are dBm) */ - A_INT32 chan_nf; - - /** BSS rx cycle count */ - A_UINT32 my_bss_rx_cycle_count; + /** BSS rx cycle count */ + A_UINT32 my_bss_rx_cycle_count; } wlan_dcs_im_tgt_stats_t; /** @@ -7392,63 +8157,78 @@ typedef struct _wlan_dcs_im_tgt_stats { * event would carry only stats. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param */ - /** - * Type of the event present, either the cw interference event, or the wlan_im stats - */ - A_UINT32 interference_type; /* type of interference, wlan or cw */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; -/* - * Following this struct are these TLVs. Note that they are both array of structures - * but can have at most one element. Which TLV is empty or has one element depends - * on the field interference_type. This is to emulate an union with cw_int and wlan_stat - * elements (not arrays). union { wlan_dcs_cw_int cw_int; wlan_dcs_im_tgt_stats_t wlan_stat; } int_event; - * - * wlan_dcs_cw_int cw_int[]; <-- cw_interference event - * wlan_dcs_im_tgt_stats_t wlan_stat[]; <-- wlan im interfernce stats - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param */ + /** + * Type of the event present, either the cw interference event, or the wlan_im stats + */ + A_UINT32 interference_type; /* type of interference, wlan or cw */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* + * Following this struct are these TLVs. Note that they are both array of structures + * but can have at most one element. Which TLV is empty or has one element depends + * on the field interference_type. This is to emulate an union with cw_int and wlan_stat + * elements (not arrays). union { wlan_dcs_cw_int cw_int; + * wlan_dcs_im_tgt_stats_t wlan_stat; } + * int_event; + * + * //cw_interference event + * wlan_dcs_cw_int cw_int[]; this element + * // wlan im interfernce stats + * wlan_dcs_im_tgt_stats_t wlan_stat[]; + */ } wmi_dcs_interference_event_fixed_param; enum wmi_peer_mcast_group_action { - wmi_peer_mcast_group_action_add = 0, - wmi_peer_mcast_group_action_del = 1 + wmi_peer_mcast_group_action_add = 0, + wmi_peer_mcast_group_action_del = 1 }; #define WMI_PEER_MCAST_GROUP_FLAG_ACTION_M 0x1 #define WMI_PEER_MCAST_GROUP_FLAG_ACTION_S 0 #define WMI_PEER_MCAST_GROUP_FLAG_WILDCARD_M 0x2 #define WMI_PEER_MCAST_GROUP_FLAG_WILDCARD_S 1 -#define WMI_PEER_MCAST_GROUP_FLAG_SRC_FILTER_EXCLUDE_M 0x4 /* flag to exclude an ip while filtering. set to exclude */ +/* flag to exclude an ip while filtering.set to exclude */ +#define WMI_PEER_MCAST_GROUP_FLAG_SRC_FILTER_EXCLUDE_M 0x4 #define WMI_PEER_MCAST_GROUP_FLAG_SRC_FILTER_EXCLUDE_S 2 -#define WMI_PEER_MCAST_GROUP_FLAG_IPV6_M 0x8 /* flag to say ipv4/ipv6. Will be set for ipv6 */ +/* flag to say ipv4/ipv6. Will be set for ipv6 */ +#define WMI_PEER_MCAST_GROUP_FLAG_IPV6_M 0x8 #define WMI_PEER_MCAST_GROUP_FLAG_IPV6_S 3 -#define WMI_PEER_MCAST_GROUP_FLAG_DELETEALL_M 0x10 /* delete all mcast table entries. */ +/* delete all mcast table entries. */ +#define WMI_PEER_MCAST_GROUP_FLAG_DELETEALL_M 0x10 #define WMI_PEER_MCAST_GROUP_FLAG_DELETEALL_S 4 /* multicast group membership commands */ /* TODO: Converting this will be tricky since it uses an union. - Also, the mac_addr is not aligned. We will convert to the wmi_mac_addr */ + Also, the mac_addr is not aligned. We will convert to the wmi_mac_addr */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_mcast_group_cmd_fixed_param */ - A_UINT32 flags; - wmi_mac_addr ucast_mac_addr; - /* in network byte order */ - /* for ipv4, bytes (12-15) should contain ip address and other lower bytes 0. ipv6 should have all bytes valid */ - A_UINT8 mcast_ip_addr[16]; - /* for ipv6, all 16 bytes has to be valid; for ipv4 last 4 bytes(12-15) has to be valid, rest all 0s */ - A_UINT8 mcast_ip_mask[16];/* zero out lower bytes if ipv4*/ - /* number of address filters - irrespective of ipv4/ipv6 addresses */ - A_UINT32 num_filter_addr; - /* this array should contain the src IPs that are to be filtered during find - The array should be packed. - If there are 2 ipv4 addresses, there should be 8 bytes and rest all 0s */ - A_UINT8 filter_addr[64]; /* 16 ipv4 addresses or 4 ipv6 addresses */ - A_UINT8 vdev_id; /* vdev of this mcast group */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_mcast_group_cmd_fixed_param */ + A_UINT32 flags; + wmi_mac_addr ucast_mac_addr; + /* + * for ipv4, bytes (12-15) should contain ip address and + * other lower bytes 0. ipv6 should have all bytes valid + */ + A_UINT8 mcast_ip_addr[16]; /* in network byte order */ + /* + * for ipv6, all 16 bytes has to be valid; + * for ipv4 last 4 bytes(12-15) has to be valid, rest all 0s + */ + A_UINT8 mcast_ip_mask[16]; /* zero out lower bytes if ipv4 */ + /* number of address filters - irrespective of ipv4/ipv6 addresses */ + A_UINT32 num_filter_addr; + /* + * this array should contain the src IPs that are to be filtered + * during find. The array should be packed. If there are 2 ipv4 + * addresses, there should be 8 bytes and rest all 0s + */ + A_UINT8 filter_addr[64]; /* 16 ipv4 addresses or 4 ipv6 addresses */ + A_UINT8 vdev_id; /* vdev of this mcast group */ } wmi_peer_mcast_group_cmd_fixed_param; - /** Offload Scan and Roaming related commands */ /** The FW performs 2 different kinds of offload scans independent * of host. One is Roam scan which is primarily performed on a @@ -7469,9 +8249,10 @@ typedef struct { * */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_mode_fixed_param */ - A_UINT32 roam_scan_mode; - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_mode_fixed_param */ + A_UINT32 roam_scan_mode; + A_UINT32 vdev_id; } wmi_roam_scan_mode_fixed_param; #define WMI_ROAM_SCAN_MODE_NONE 0x0 @@ -7481,11 +8262,11 @@ typedef struct { /* Note: WMI_ROAM_SCAN_MODE_ROAMOFFLOAD is one bit not conflict with LFR2.0 SCAN_MODE. */ #define WMI_ROAM_SCAN_MODE_ROAMOFFLOAD 0x4 - typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 command_arg; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 command_arg; } wmi_roam_scan_cmd_fixed_param; #define WMI_ROAM_SCAN_STOP_CMD 0x1 @@ -7496,24 +8277,25 @@ typedef struct { * Applicable when WMI_ROAM_SCAN_MODE is not set to none. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_rssi_threshold_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** roam scan rssi threshold */ - A_UINT32 roam_scan_rssi_thresh; - /** When using Hw generated beacon RSSI interrupts */ - A_UINT32 roam_rssi_thresh_diff; - /** 5G scan max count */ - A_UINT32 hirssi_scan_max_count; - /** 5G scan rssi change threshold value */ - A_UINT32 hirssi_scan_delta; - /** 5G scan upper bound */ - A_UINT32 hirssi_upper_bound; - /* The TLVs will follow. - * wmi_roam_scan_extended_threshold_param extended_param; - * wmi_roam_earlystop_rssi_thres_param earlystop_param; - * wmi_roam_dense_thres_param dense_param; - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_rssi_threshold_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** roam scan rssi threshold */ + A_UINT32 roam_scan_rssi_thresh; + /** When using Hw generated beacon RSSI interrupts */ + A_UINT32 roam_rssi_thresh_diff; + /** 5G scan max count */ + A_UINT32 hirssi_scan_max_count; + /** 5G scan rssi change threshold value */ + A_UINT32 hirssi_scan_delta; + /** 5G scan upper bound */ + A_UINT32 hirssi_upper_bound; + /* The TLVs will follow. + * wmi_roam_scan_extended_threshold_param extended_param; + * wmi_roam_earlystop_rssi_thres_param earlystop_param; + * wmi_roam_dense_thres_param dense_param; + */ } wmi_roam_scan_rssi_threshold_fixed_param; #define WMI_ROAM_5G_BOOST_PENALIZE_ALGO_FIXED 0x0 @@ -7522,30 +8304,38 @@ typedef struct { #define WMI_ROAM_5G_BOOST_PENALIZE_ALGO_EXP 0x3 typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_extended_threshold_param */ - A_UINT32 boost_threshold_5g; /** RSSI threshold above which 5GHz RSSI is favored */ - A_UINT32 penalty_threshold_5g; /** RSSI threshold below which 5GHz RSSI is penalized */ - A_UINT32 boost_algorithm_5g; /** 0 == fixed, 1 == linear, 2 == logarithm ..etc */ - A_UINT32 boost_factor_5g; /** factor by which 5GHz RSSI is boosted */ - A_UINT32 penalty_algorithm_5g; /** 0 == fixed, 1 == linear, 2 == logarithm ..etc */ - A_UINT32 penalty_factor_5g; /** factor by which 5GHz RSSI is penalized */ - A_UINT32 max_boost_5g; /** maximum boost that can be applied to a 5GHz RSSI */ - A_UINT32 max_penalty_5g; /** maximum penality that can be applied to a 5GHz RSSI */ - A_UINT32 good_rssi_threshold; /** RSSI below which roam is kicked in by background scan, although rssi is still good */ + /** TLV tag and len; tag equals + *WMITLV_TAG_STRUC_wmi_roam_scan_extended_threshold_param */ + A_UINT32 tlv_header; + A_UINT32 boost_threshold_5g; /** RSSI threshold above which 5GHz RSSI is favored */ + A_UINT32 penalty_threshold_5g; /** RSSI threshold below which 5GHz RSSI is penalized */ + A_UINT32 boost_algorithm_5g; /** 0 == fixed, 1 == linear, 2 == logarithm ..etc */ + A_UINT32 boost_factor_5g; /** factor by which 5GHz RSSI is boosted */ + A_UINT32 penalty_algorithm_5g; /** 0 == fixed, 1 == linear, 2 == logarithm ..etc */ + A_UINT32 penalty_factor_5g; /** factor by which 5GHz RSSI is penalized */ + A_UINT32 max_boost_5g; /** maximum boost that can be applied to a 5GHz RSSI */ + A_UINT32 max_penalty_5g; /** maximum penality that can be applied to a 5GHz RSSI */ + /** + * RSSI below which roam is kicked in by background scan + * although rssi is still good + */ + A_UINT32 good_rssi_threshold; } wmi_roam_scan_extended_threshold_param; + /** * WMI_ROAM_SCAN_PERIOD: period for roam scan. * Applicable when the scan mode is Periodic or both. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_period_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** roam scan period value */ - A_UINT32 roam_scan_period; - /** Aging for Roam scans */ - A_UINT32 roam_scan_age; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_period_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** roam scan period value */ + A_UINT32 roam_scan_period; + /** Aging for Roam scans */ + A_UINT32 roam_scan_age; } wmi_roam_scan_period_fixed_param; /** @@ -7555,15 +8345,16 @@ typedef struct { * Note scan is triggered based on the rssi threshold condition set by WMI_ROAM_SCAN_RSSI_THRESHOLD */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_rssi_change_threshold_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** roam scan rssi change threshold value */ - A_UINT32 roam_scan_rssi_change_thresh; - /** When using Hw generated beacon RSSI interrupts */ - A_UINT32 bcn_rssi_weight; - /** Minimum delay between two 5G scans */ - A_UINT32 hirssi_delay_btw_scans; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_rssi_change_threshold_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** roam scan rssi change threshold value */ + A_UINT32 roam_scan_rssi_change_thresh; + /** When using Hw generated beacon RSSI interrupts */ + A_UINT32 bcn_rssi_weight; + /** Minimum delay between two 5G scans */ + A_UINT32 hirssi_delay_btw_scans; } wmi_roam_scan_rssi_change_threshold_fixed_param; #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NONE 0x1 @@ -7573,15 +8364,16 @@ typedef struct { * TLV for roaming channel list */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_chan_list_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** WMI_CHAN_LIST_TAG */ - A_UINT32 chan_list_type; - /** # if channels to scan */ - A_UINT32 num_chan; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_chan_list_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** WMI_CHAN_LIST_TAG */ + A_UINT32 chan_list_type; + /** # if channels to scan */ + A_UINT32 num_chan; /** - * TLV (tag length value) parameters follow the wmi_roam_chan_list + * TLV (tag length value ) parameters follow the wmi_roam_chan_list * structure. The TLV's are: * A_UINT32 channel_list[]; **/ @@ -7589,36 +8381,36 @@ typedef struct { /** Authentication modes */ enum { - WMI_AUTH_NONE, /* no upper level auth */ - WMI_AUTH_OPEN, /* open */ - WMI_AUTH_SHARED, /* shared-key */ - WMI_AUTH_8021X, /* 802.1x */ - WMI_AUTH_AUTO, /* Auto */ - WMI_AUTH_WPA, /* WPA */ - WMI_AUTH_RSNA, /* WPA2/RSNA */ - WMI_AUTH_CCKM, /* CCKM */ - WMI_AUTH_WAPI, /* WAPI */ - WMI_AUTH_AUTO_PSK, - WMI_AUTH_WPA_PSK, - WMI_AUTH_RSNA_PSK, - WMI_AUTH_WAPI_PSK, - WMI_AUTH_FT_RSNA, /* 11r FT */ - WMI_AUTH_FT_RSNA_PSK, - WMI_AUTH_RSNA_PSK_SHA256, - WMI_AUTH_RSNA_8021X_SHA256, - WMI_AUTH_CCKM_WPA, - WMI_AUTH_CCKM_RSNA, + WMI_AUTH_NONE, /* no upper level auth */ + WMI_AUTH_OPEN, /* open */ + WMI_AUTH_SHARED, /* shared-key */ + WMI_AUTH_8021X, /* 802.1x */ + WMI_AUTH_AUTO, /* Auto */ + WMI_AUTH_WPA, /* WPA */ + WMI_AUTH_RSNA, /* WPA2/RSNA */ + WMI_AUTH_CCKM, /* CCKM */ + WMI_AUTH_WAPI, /* WAPI */ + WMI_AUTH_AUTO_PSK, + WMI_AUTH_WPA_PSK, + WMI_AUTH_RSNA_PSK, + WMI_AUTH_WAPI_PSK, + WMI_AUTH_FT_RSNA, /* 11r FT */ + WMI_AUTH_FT_RSNA_PSK, + WMI_AUTH_RSNA_PSK_SHA256, + WMI_AUTH_RSNA_8021X_SHA256, + WMI_AUTH_CCKM_WPA, + WMI_AUTH_CCKM_RSNA, }; typedef struct { - /** authentication mode (defined above) */ - A_UINT32 rsn_authmode; - /** unicast cipher set */ - A_UINT32 rsn_ucastcipherset; - /** mcast/group cipher set */ - A_UINT32 rsn_mcastcipherset; - /** mcast/group management frames cipher set */ - A_UINT32 rsn_mcastmgmtcipherset; + /** authentication mode (defined above) */ + A_UINT32 rsn_authmode; + /** unicast cipher set */ + A_UINT32 rsn_ucastcipherset; + /** mcast/group cipher set */ + A_UINT32 rsn_mcastcipherset; + /** mcast/group management frames cipher set */ + A_UINT32 rsn_mcastmgmtcipherset; } wmi_rsn_params; /** looking for a wps enabled AP */ @@ -7628,7 +8420,6 @@ typedef struct { /** looking for a PMF enabled AP */ #define WMI_AP_PROFILE_FLAG_PMF 0x4 - /** To match an open AP, the rs_authmode should be set to WMI_AUTH_NONE * and WMI_AP_PROFILE_FLAG_CRYPTO should be clear. * To match a WEP enabled AP, the rs_authmode should be set to WMI_AUTH_NONE @@ -7636,30 +8427,31 @@ typedef struct { */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ap_profile */ - /** flags as defined above */ - A_UINT32 flags; - /** - * rssi thresold value: the value of the the candidate AP should - * higher by this threshold than the rssi of the currrently associated AP. - */ - A_UINT32 rssi_threshold; - /** - * ssid vlaue to be matched. - */ - wmi_ssid ssid; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ap_profile */ + /** flags as defined above */ + A_UINT32 flags; + /** + * rssi thresold value: the value of the the candidate AP should + * higher by this threshold than the rssi of the currrently associated AP. + */ + A_UINT32 rssi_threshold; + /** + * ssid vlaue to be matched. + */ + wmi_ssid ssid; - /** - * security params to be matched. - */ - /** authentication mode (defined above) */ - A_UINT32 rsn_authmode; - /** unicast cipher set */ - A_UINT32 rsn_ucastcipherset; - /** mcast/group cipher set */ - A_UINT32 rsn_mcastcipherset; - /** mcast/group management frames cipher set */ - A_UINT32 rsn_mcastmgmtcipherset; + /** + * security params to be matched. + */ + /** authentication mode (defined above) */ + A_UINT32 rsn_authmode; + /** unicast cipher set */ + A_UINT32 rsn_ucastcipherset; + /** mcast/group cipher set */ + A_UINT32 rsn_mcastcipherset; + /** mcast/group management frames cipher set */ + A_UINT32 rsn_mcastmgmtcipherset; } wmi_ap_profile; /** Support early stop roaming scanning when finding a strong candidate AP @@ -7670,109 +8462,117 @@ typedef struct { * Earlystop threshold will be relaxed as each channel is scanned. */ typedef struct { - A_UINT32 tlv_header; - /* Minimum RSSI threshold value for early stop, unit is dB above NF. */ - A_UINT32 roam_earlystop_thres_min; - /* Maminum RSSI threshold value for early stop, unit is dB above NF. */ - A_UINT32 roam_earlystop_thres_max; + A_UINT32 tlv_header; + /* Minimum RSSI threshold value for early stop, unit is dB above NF. */ + A_UINT32 roam_earlystop_thres_min; + /* Maminum RSSI threshold value for early stop, unit is dB above NF. */ + A_UINT32 roam_earlystop_thres_max; } wmi_roam_earlystop_rssi_thres_param; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_dense_thres_param */ - A_UINT32 tlv_header; - /** rssi threshold offset under trffic and dense env */ - A_UINT32 roam_dense_rssi_thres_offset; - /** minimum number of APs to determine dense env */ - A_UINT32 roam_dense_min_aps; - /** initial dense status detected by host at the time of initial connection */ - A_UINT32 roam_dense_status; - /* traffic threshold to enable aggressive roaming in dense env; units are percent of medium occupancy, 0 - 100 */ - A_UINT32 roam_dense_traffic_thres; + /* TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_roam_dense_thres_param + */ + A_UINT32 tlv_header; + /* rssi threshold offset under trffic and dense env */ + A_UINT32 roam_dense_rssi_thres_offset; + /* minimum number of APs to determine dense env */ + A_UINT32 roam_dense_min_aps; + /* initial dense status detected by host + * at the time of initial connection */ + A_UINT32 roam_dense_status; + /* traffic threshold to enable aggressive roaming in dense env; + * units are percent of medium occupancy, 0 - 100 + */ + A_UINT32 roam_dense_traffic_thres; } wmi_roam_dense_thres_param; /** Beacon filter wmi command info */ #define BCN_FLT_MAX_SUPPORTED_IES 256 -#define BCN_FLT_MAX_ELEMS_IE_LIST (BCN_FLT_MAX_SUPPORTED_IES/32) +#define BCN_FLT_MAX_ELEMS_IE_LIST BCN_FLT_MAX_SUPPORTED_IES/32 typedef struct bss_bcn_stats { - A_UINT32 vdev_id; - A_UINT32 bss_bcnsdropped; - A_UINT32 bss_bcnsdelivered; + A_UINT32 vdev_id; + A_UINT32 bss_bcnsdropped; + A_UINT32 bss_bcnsdelivered; } wmi_bss_bcn_stats_t; typedef struct bcn_filter_stats { - A_UINT32 bcns_dropped; - A_UINT32 bcns_delivered; - A_UINT32 activefilters; - wmi_bss_bcn_stats_t bss_stats; + A_UINT32 bcns_dropped; + A_UINT32 bcns_delivered; + A_UINT32 activefilters; + wmi_bss_bcn_stats_t bss_stats; } wmi_bcnfilter_stats_t; typedef struct wmi_add_bcn_filter_cmd { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_add_bcn_filter_cmd_fixed_param */ - A_UINT32 vdev_id; -/* - * Following this structure is the TLV: - * A_UINT32 ie_map[BCN_FLT_MAX_ELEMS_IE_LIST]; - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_add_bcn_filter_cmd_fixed_param */ + A_UINT32 vdev_id; + /* + * Following this structure is the TLV: + * A_UINT32 ie_map[BCN_FLT_MAX_ELEMS_IE_LIST]; + */ } wmi_add_bcn_filter_cmd_fixed_param; typedef struct wmi_rmv_bcn_filter_cmd { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rmv_bcn_filter_cmd_fixed_param */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rmv_bcn_filter_cmd_fixed_param */ + A_UINT32 vdev_id; } wmi_rmv_bcn_filter_cmd_fixed_param; #define WMI_BCN_SEND_DTIM_ZERO 1 #define WMI_BCN_SEND_DTIM_BITCTL_SET 2 typedef struct wmi_bcn_send_from_host { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_send_from_host_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 data_len; - union { - A_UINT32 frag_ptr; /* Physical address of the frame */ - A_UINT32 frag_ptr_lo; /* LSBs of physical address of the frame */ - }; - A_UINT32 frame_ctrl; /* farme ctrl to setup PPDU desc */ - A_UINT32 dtim_flag; /* to control CABQ traffic */ - A_UINT32 bcn_antenna; /* Antenna for beacon transmission */ - A_UINT32 frag_ptr_hi; /* MSBs of physical address of the frame */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_send_from_host_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 data_len; + union { + A_UINT32 frag_ptr; /* Physical address of the frame */ + A_UINT32 frag_ptr_lo; /* LSB of physical address of the frame */ + }; + A_UINT32 frame_ctrl; /* farme ctrl to setup PPDU desc */ + A_UINT32 dtim_flag; /* to control CABQ traffic */ + A_UINT32 bcn_antenna; /* Antenna for beacon transmission */ + A_UINT32 frag_ptr_hi; /* MSBs of physical address of the frame */ } wmi_bcn_send_from_host_cmd_fixed_param; /* cmd to support bcn snd for all vaps at once */ typedef struct wmi_pdev_send_bcn { - A_UINT32 num_vdevs; - wmi_bcn_send_from_host_cmd_fixed_param bcn_cmd[1]; + A_UINT32 num_vdevs; + wmi_bcn_send_from_host_cmd_fixed_param bcn_cmd[1]; } wmi_pdev_send_bcn_cmd_t; /* * WMI_ROAM_AP_PROFILE: AP profile of connected AP for roaming. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param */ - /** id of AP criteria */ - A_UINT32 id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param */ + /** id of AP criteria */ + A_UINT32 id; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; -/* - * Following this structure is the TLV: - * wmi_ap_profile ap_profile; <-- AP profile info - */ + /* + * Following this structure is the TLV: + * wmi_ap_profile ap_profile; //AP profile info + */ } wmi_roam_ap_profile_fixed_param; /** * WMI_OFL_SCAN_ADD_AP_PROFILE: add an AP profile. */ typedef struct { - /** id of AP criteria */ - A_UINT32 id; + /** id of AP criteria */ + A_UINT32 id; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; - /** AP profile info */ - wmi_ap_profile ap_profile; + /** AP profile info */ + wmi_ap_profile ap_profile; } wmi_ofl_scan_add_ap_profile; @@ -7780,10 +8580,10 @@ typedef struct { * WMI_OFL_SCAN_REMOVE_AP_CRITERIA: remove an ap profile. */ typedef struct { - /** id of AP criteria */ - A_UINT32 id; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + /** id of AP criteria */ + A_UINT32 id; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_ofl_scan_remove_ap_profile; /** @@ -7792,8 +8592,8 @@ typedef struct { * scan. */ typedef struct { - /** offload scan period value, used for scans used when not connected */ - A_UINT32 ofl_scan_period; + /** offload scan period value, used for scans used when not connected */ + A_UINT32 ofl_scan_period; } wmi_ofl_scan_period; /* Do not modify XXX_BYTES or XXX_LEN below as it is fixed by standard */ @@ -7804,65 +8604,74 @@ typedef struct { #define ROAM_OFFLOAD_R0KH_ID_MAX_LEN (48) #define ROAM_OFFLOAD_NUM_MCS_SET (16) -/* This TLV will be filled only in case roam offload for wpa2-psk/okc/ese/11r is enabled */ +/* This TLV will be filled only in case roam offload + * for wpa2-psk/okc/ese/11r is enabled */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_offload_fixed_param */ - A_UINT32 rssi_cat_gap; /* gap for every category bucket */ - A_UINT32 prefer_5g; /* prefer select 5G candidate */ - A_UINT32 select_5g_margin; - A_UINT32 reassoc_failure_timeout; /* reassoc failure timeout */ - A_UINT32 capability; - A_UINT32 ht_caps_info; - A_UINT32 ampdu_param; - A_UINT32 ht_ext_cap; - A_UINT32 ht_txbf; - A_UINT32 asel_cap; - A_UINT32 qos_enabled; - A_UINT32 qos_caps; - A_UINT32 wmm_caps; - A_UINT32 mcsset[ROAM_OFFLOAD_NUM_MCS_SET>>2]; /* since this 4 byte aligned, we don't declare it as tlv array */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_offload_fixed_param */ + A_UINT32 rssi_cat_gap; /* gap for every category bucket */ + A_UINT32 prefer_5g; /* prefer select 5G candidate */ + A_UINT32 select_5g_margin; + A_UINT32 reassoc_failure_timeout; /* reassoc failure timeout */ + A_UINT32 capability; + A_UINT32 ht_caps_info; + A_UINT32 ampdu_param; + A_UINT32 ht_ext_cap; + A_UINT32 ht_txbf; + A_UINT32 asel_cap; + A_UINT32 qos_enabled; + A_UINT32 qos_caps; + A_UINT32 wmm_caps; + A_UINT32 mcsset[ROAM_OFFLOAD_NUM_MCS_SET >> 2]; /* since this 4 byte aligned, + * we don't declare it as + * tlv array */ } wmi_roam_offload_tlv_param; - /* flags for 11i offload */ -#define WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED 0 /* okc is enabled */ +#define WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED 0 /* okc is enabled */ /* from bit 1 to bit 31 are reserved */ #define WMI_SET_ROAM_OFFLOAD_OKC_ENABLED(flag) do { \ - (flag) |= (1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED); \ - } while (0) + (flag) |= (1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED); \ +} while (0) #define WMI_SET_ROAM_OFFLOAD_OKC_DISABLED(flag) do { \ - (flag) &= ~(1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED); \ - } while (0) + (flag) &= ~(1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED); \ +} while (0) -#define WMI_GET_ROAM_OFFLOAD_OKC_ENABLED(flag) \ - ((flag) & (1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED)) +#define WMI_GET_ROAM_OFFLOAD_OKC_ENABLED(flag) \ + ((flag) & (1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED)) /* This TLV will be filled only in case of wpa-psk/wpa2-psk */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_11i_offload_fixed_param */ - A_UINT32 flags; /** flags. see WMI_ROAM_OFFLOAD_FLAG_ above */ - A_UINT32 pmk[ROAM_OFFLOAD_PMK_BYTES>>2]; /* pmk offload. As this 4 byte aligned, we don't declare it as tlv array */ - A_UINT32 pmk_len; /**the length of pmk. in normal case it should be 32, but for LEAP, is should be 16*/ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_11i_offload_fixed_param */ + A_UINT32 flags; + /** flags. see WMI_ROAM_OFFLOAD_FLAG_ above */ + A_UINT32 pmk[ROAM_OFFLOAD_PMK_BYTES >> 2]; /* pmk offload. As this 4 byte aligned, we don't declare it as tlv array */ + A_UINT32 pmk_len; + /**the length of pmk. in normal case it should be 32, but for LEAP, is should be 16*/ } wmi_roam_11i_offload_tlv_param; /* This TLV will be filled only in case of 11R*/ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_11r_offload_fixed_param */ - A_UINT32 mdie_present; - A_UINT32 mdid; - A_UINT32 r0kh_id[ROAM_OFFLOAD_R0KH_ID_MAX_LEN>>2]; - A_UINT32 r0kh_id_len; - A_UINT32 psk_msk[ROAM_OFFLOAD_PSK_MSK_BYTES>>2]; /* psk/msk offload. As this 4 byte aligned, we don't declare it as tlv array */ - A_UINT32 psk_msk_len; /**length of psk_msk*/ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_11r_offload_fixed_param */ + A_UINT32 mdie_present; + A_UINT32 mdid; + A_UINT32 r0kh_id[ROAM_OFFLOAD_R0KH_ID_MAX_LEN >> 2]; + A_UINT32 r0kh_id_len; + A_UINT32 psk_msk[ROAM_OFFLOAD_PSK_MSK_BYTES >> 2]; /* psk/msk offload. As this 4 byte aligned, we don't declare it as tlv array */ + A_UINT32 psk_msk_len; + /**length of psk_msk*/ } wmi_roam_11r_offload_tlv_param; /* This TLV will be filled only in case of ESE */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ese_offload_fixed_param */ - A_UINT32 krk[ROAM_OFFLOAD_KRK_BYTES>>2]; /* KRK offload. As this 4 byte aligned, we don't declare it as tlv array */ - A_UINT32 btk[ROAM_OFFLOAD_BTK_BYTES>>2]; /* BTK offload. As this 4 byte aligned, we don't declare it as tlv array */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ese_offload_fixed_param */ + A_UINT32 krk[ROAM_OFFLOAD_KRK_BYTES >> 2]; /* KRK offload. As this 4 byte aligned, we don't declare it as tlv array */ + A_UINT32 btk[ROAM_OFFLOAD_BTK_BYTES >> 2]; /* BTK offload. As this 4 byte aligned, we don't declare it as tlv array */ } wmi_roam_ese_offload_tlv_param; /** WMI_ROAM_EVENT: roam event triggering the host roam logic. @@ -7871,30 +8680,34 @@ typedef struct { * from the current AP. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** reason for roam event */ - A_UINT32 reason; - /** associated AP's rssi calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI*/ - A_UINT32 rssi; - /** roam notification */ - A_UINT32 notif; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** reason for roam event */ + A_UINT32 reason; + /** associated AP's rssi calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI*/ + A_UINT32 rssi; + /** roam notification */ + A_UINT32 notif; + } wmi_roam_event_fixed_param; - /* roam_reason: bits 0-3 */ -#define WMI_ROAM_REASON_INVALID 0x0 /** invalid reason. Do not interpret reason field */ + +/** invalid reason. Do not interpret reason field */ +#define WMI_ROAM_REASON_INVALID 0x0 #define WMI_ROAM_REASON_BETTER_AP 0x1 /** found a better AP */ #define WMI_ROAM_REASON_BMISS 0x2 /** beacon miss detected */ #define WMI_ROAM_REASON_DEAUTH 0x2 /** deauth/disassoc received */ #define WMI_ROAM_REASON_LOW_RSSI 0x3 /** connected AP's low rssi condition detected */ #define WMI_ROAM_REASON_SUITABLE_AP 0x4 /** found another AP that matches - SSID and Security profile in - WMI_ROAM_AP_PROFILE, found during scan - triggered upon FINAL_BMISS **/ + SSID and Security profile in + WMI_ROAM_AP_PROFILE, found during scan + triggered upon FINAL_BMISS **/ #define WMI_ROAM_REASON_HO_FAILED 0x5 /** LFR3.0 roaming failed, indicate the disconnection to host */ -/** WMI_ROAM_REASON_INVOKE_ROAM_FAIL: + +/* + * WMI_ROAM_REASON_INVOKE_ROAM_FAIL: * Result code of WMI_ROAM_INVOKE_CMDID. * Any roaming failure before reassociation will be indicated to host * with this reason. @@ -7905,64 +8718,69 @@ typedef struct { /* reserved up through 0xF */ /* subnet status: bits 4-5 */ -typedef enum -{ - WMI_ROAM_SUBNET_CHANGE_STATUS_UNKNOWN = 0, - WMI_ROAM_SUBNET_CHANGE_STATUS_UNCHANGED, - WMI_ROAM_SUBNET_CHANGE_STATUS_CHANGED, +typedef enum { + WMI_ROAM_SUBNET_CHANGE_STATUS_UNKNOWN = 0, + WMI_ROAM_SUBNET_CHANGE_STATUS_UNCHANGED, + WMI_ROAM_SUBNET_CHANGE_STATUS_CHANGED, } wmi_roam_subnet_change_status; #define WMI_ROAM_SUBNET_CHANGE_STATUS_MASK 0x30 #define WMI_ROAM_SUBNET_CHANGE_STATUS_SHIFT 4 #define WMI_SET_ROAM_SUBNET_CHANGE_STATUS(roam_reason, status) \ - do { \ - (roam_reason) |= \ - (((status) << WMI_ROAM_SUBNET_CHANGE_STATUS_SHIFT) & \ - WMI_ROAM_SUBNET_CHANGE_STATUS_MASK); \ - } while (0) + do { \ + (roam_reason) |= \ + (((status) << WMI_ROAM_SUBNET_CHANGE_STATUS_SHIFT) & \ + WMI_ROAM_SUBNET_CHANGE_STATUS_MASK); \ + } while (0) #define WMI_GET_ROAM_SUBNET_CHANGE_STATUS(roam_reason) \ - (((roam_reason) & WMI_ROAM_SUBNET_CHANGE_STATUS_MASK) >> \ - WMI_ROAM_SUBNET_CHANGE_STATUS_SHIFT) + (((roam_reason) & WMI_ROAM_SUBNET_CHANGE_STATUS_MASK) >> \ + WMI_ROAM_SUBNET_CHANGE_STATUS_SHIFT) /* roaming notification */ -#define WMI_ROAM_NOTIF_INVALID 0x0 /** invalid notification. Do not interpret notif field */ -#define WMI_ROAM_NOTIF_ROAM_START 0x1 /** indicate that roaming is started. sent only in non WOW state */ -#define WMI_ROAM_NOTIF_ROAM_ABORT 0x2 /** indicate that roaming is aborted. sent only in non WOW state */ +/** invalid notification. Do not interpret notif field */ +#define WMI_ROAM_NOTIF_INVALID 0x0 +/** indicate that roaming is started. sent only in non WOW state */ +#define WMI_ROAM_NOTIF_ROAM_START 0x1 +/** indicate that roaming is aborted. sent only in non WOW state */ +#define WMI_ROAM_NOTIF_ROAM_ABORT 0x2 /**whenever RIC request information change, host driver should pass all ric related information to firmware (now only support tsepc) -* Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on these informations -*/ -typedef struct -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ric_request_fixed_param */ - A_UINT32 vdev_id; /**unique id identifying the VDEV, generated by the caller*/ - A_UINT32 num_ric_request; /**number of ric request ie send to firmware.(max value is 2 now)*/ - A_UINT32 is_add_ric; /**support add ric or delete ric*/ + * Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on these informations + */ +typedef struct { + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ric_request_fixed_param */ + A_UINT32 vdev_id; + /**unique id identifying the VDEV, generated by the caller*/ + A_UINT32 num_ric_request; + /**number of ric request ie send to firmware.(max value is 2 now)*/ + A_UINT32 is_add_ric; + /**support add ric or delete ric*/ } wmi_ric_request_fixed_param; /**tspec element: refer to 8.4.2.32 of 802.11 2012 spec -* these elements are used to construct tspec field in RIC request, which allow station to require specific TS when 11r roaming -*/ -typedef struct{ - A_UINT32 tlv_header; - A_UINT32 ts_info; /** bits value of TS Info field.*/ - A_UINT32 nominal_msdu_size; /**Nominal MSDU Size field*/ - A_UINT32 maximum_msdu_size; /**The Maximum MSDU Size field*/ - A_UINT32 min_service_interval; /**The Minimum Service Interval field*/ - A_UINT32 max_service_interval; /**The Maximum Service Interval field*/ - A_UINT32 inactivity_interval; /**The Inactivity Interval field*/ - A_UINT32 suspension_interval; /**The Suspension Interval field*/ - A_UINT32 svc_start_time; /**The Service Start Time field*/ - A_UINT32 min_data_rate; /**The Minimum Data Rate field*/ - A_UINT32 mean_data_rate; /**The Mean Data Rate field*/ - A_UINT32 peak_data_rate; /**The Peak Data Rate field*/ - A_UINT32 max_burst_size; /**The Burst Size field*/ - A_UINT32 delay_bound; /**The Delay Bound field*/ - A_UINT32 min_phy_rate; /**The Minimum PHY Rate field*/ - A_UINT32 surplus_bw_allowance; /**The Surplus Bandwidth Allowance field*/ - A_UINT32 medium_time; /**The Medium Time field,in units of 32 us/s.*/ + * these elements are used to construct tspec field in RIC request, which allow station to require specific TS when 11r roaming + */ +typedef struct { + A_UINT32 tlv_header; + A_UINT32 ts_info; /** bits value of TS Info field.*/ + A_UINT32 nominal_msdu_size; /**Nominal MSDU Size field*/ + A_UINT32 maximum_msdu_size; /**The Maximum MSDU Size field*/ + A_UINT32 min_service_interval; /**The Minimum Service Interval field*/ + A_UINT32 max_service_interval; /**The Maximum Service Interval field*/ + A_UINT32 inactivity_interval; /**The Inactivity Interval field*/ + A_UINT32 suspension_interval; /**The Suspension Interval field*/ + A_UINT32 svc_start_time; /**The Service Start Time field*/ + A_UINT32 min_data_rate; /**The Minimum Data Rate field*/ + A_UINT32 mean_data_rate; /**The Mean Data Rate field*/ + A_UINT32 peak_data_rate; /**The Peak Data Rate field*/ + A_UINT32 max_burst_size; /**The Burst Size field*/ + A_UINT32 delay_bound; /**The Delay Bound field*/ + A_UINT32 min_phy_rate; /**The Minimum PHY Rate field*/ + A_UINT32 surplus_bw_allowance; /**The Surplus Bandwidth Allowance field*/ + A_UINT32 medium_time; /**The Medium Time field,in units of 32 us/s.*/ } wmi_ric_tspec; /* flags for roam_invoke_cmd */ @@ -7975,15 +8793,15 @@ typedef struct{ /* from bit 3 to bit 31 are reserved */ #define WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE(flag) do { \ - (flag) |= (1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE); \ - } while (0) + (flag) |= (1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE); \ + } while (0) #define WMI_CLEAR_ROAM_INVOKE_ADD_CH_TO_CACHE(flag) do { \ - (flag) &= ~(1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE); \ - } while (0) + (flag) &= ~(1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE); \ + } while (0) #define WMI_GET_ROAM_INVOKE_ADD_CH_TO_CACHE(flag) \ - ((flag) & (1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE)) + ((flag) & (1 << WMI_SET_ROAM_INVOKE_ADD_CH_TO_CACHE)) #define WMI_ROAM_INVOKE_SCAN_MODE_FIXED_CH 0 /* scan given channel only */ @@ -7994,66 +8812,75 @@ typedef struct{ #define WMI_ROAM_INVOKE_AP_SEL_ANY_BSSID 1 /* roam to any BSSID */ /** WMI_ROAM_INVOKE_CMD: command to invoke roaming forcefully -* -if is zero and is not given, roaming is not executed. -if is zero and = 0 - = 0 - = 0 - |= WMI_ROAM_INVOKE_FLAG_ADD_CH_TO_CACHE - = do not fill (there will be no actual roaming because of ap_sel_mode is zero, but no BSSID is given) - = channel list to be added -*/ + * + * if is zero and is not given, roaming is not executed. + * if is zero and = 0 + * = 0 + * = 0 + * |= WMI_ROAM_INVOKE_FLAG_ADD_CH_TO_CACHE + * = do not fill (there will be no actual roaming because of ap_sel_mode is zero, but no BSSID is given) + * = channel list to be added + */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_invoke_fixed_param */ - A_UINT32 vdev_id; /** Unique id identifying the VDEV on which roaming is invoked */ - A_UINT32 flags; /** flags. see WMI_ROAM_INVOKE_FLAG_ above */ - A_UINT32 roam_scan_mode; /** see WMI_ROAM_INVOKE_SCAN_ above */ - A_UINT32 roam_ap_sel_mode; /** see WMI_ROAM_INVOKE_AP_SEL_ above */ - A_UINT32 roam_delay; /** 0 = immediate roam, 1-2^32 = roam after this delay (msec) */ - A_UINT32 num_chan; /** # if channels to scan. In the TLV channel_list[] */ - A_UINT32 num_bssid; /** number of bssids. In the TLV bssid_list[] */ - /** - * TLV (tag length value) parameters follows roam_invoke_req - * The TLV's are: - * A_UINT32 channel_list[]; - * wmi_mac_addr bssid_list[]; - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_invoke_fixed_param */ + A_UINT32 vdev_id; /** Unique id identifying the VDEV on which roaming is invoked */ + A_UINT32 flags; /** flags. see WMI_ROAM_INVOKE_FLAG_ above */ + A_UINT32 roam_scan_mode; /** see WMI_ROAM_INVOKE_SCAN_ above */ + A_UINT32 roam_ap_sel_mode; /** see WMI_ROAM_INVOKE_AP_SEL_ above */ + A_UINT32 roam_delay; /** 0 = immediate roam, 1-2^32 = roam after this delay (msec) */ + A_UINT32 num_chan; /** # if channels to scan. In the TLV channel_list[] */ + A_UINT32 num_bssid; /** number of bssids. In the TLV bssid_list[] */ + /** + * TLV (tag length value ) parameters follows roam_invoke_req + * The TLV's are: + * A_UINT32 channel_list[]; + * wmi_mac_addr bssid_list[]; + */ } wmi_roam_invoke_cmd_fixed_param; /* Definition for op_bitmap */ enum { - ROAM_FILTER_OP_BITMAP_BLACK_LIST = 0x1, - ROAM_FILTER_OP_BITMAP_WHITE_LIST = 0x2, - ROAM_FILTER_OP_BITMAP_PREFER_BSSID = 0x4, + ROAM_FILTER_OP_BITMAP_BLACK_LIST = 0x1, + ROAM_FILTER_OP_BITMAP_WHITE_LIST = 0x2, + ROAM_FILTER_OP_BITMAP_PREFER_BSSID = 0x4, }; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_filter_list_fixed_param */ - A_UINT32 vdev_id; /** Unique id identifying the VDEV on which roaming filter is adopted */ - A_UINT32 flags; /** flags for filter */ - A_UINT32 op_bitmap; /** 32 bit bitmap to be set on. bit0 = first param, bit 1 = second param...etc. Can be or'ed */ - A_UINT32 num_bssid_black_list; /* number of blacklist in the TLV variable bssid_black_list */ - A_UINT32 num_ssid_white_list; /* number of whitelist in the TLV variable ssid_white_list */ - A_UINT32 num_bssid_preferred_list; /* only for lfr 3.0. number of preferred list & factor in the TLV */ - /** - * TLV (tag length value) parameters follows roam_filter_list_cmd - * The TLV's are: - * wmi_mac_addr bssid_black_list[]; - * wmi_ssid ssid_white_list[]; - * wmi_mac_addr bssid_preferred_list[]; - * A_UINT32 bssid_preferred_factor[]; - */ + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_filter_list_fixed_param */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV on which roaming filter is adopted */ + A_UINT32 vdev_id; + A_UINT32 flags; /** flags for filter */ + /** 32 bit bitmap to be set on. + * bit0 = first param, + * bit 1 = second param...etc. Can be or'ed + */ + A_UINT32 op_bitmap; + /* number of blacklist in the TLV variable bssid_black_list */ + A_UINT32 num_bssid_black_list; + /* number of whitelist in the TLV variable ssid_white_list */ + A_UINT32 num_ssid_white_list; + /* only for lfr 3.0. number of preferred list & factor in the TLV */ + A_UINT32 num_bssid_preferred_list; + /** + * TLV (tag length value ) parameters follows roam_filter_list_cmd + * The TLV's are: + * wmi_mac_addr bssid_black_list[]; + * wmi_ssid ssid_white_list[]; + * wmi_mac_addr bssid_preferred_list[]; + * A_UINT32 bssid_preferred_factor[]; + */ } wmi_roam_filter_fixed_param; typedef struct { - A_UINT8 address[4]; /* IPV4 address in Network Byte Order */ + A_UINT8 address[4]; /* IPV4 address in Network Byte Order */ } WMI_IPV4_ADDR; typedef struct _WMI_IPV6_ADDR { - A_UINT8 address[16]; /* IPV6 in Network Byte Order */ + A_UINT8 address[16]; /* IPV6 in Network Byte Order */ } WMI_IPV6_ADDR; /* flags for subnet change detection */ @@ -8063,52 +8890,57 @@ typedef struct _WMI_IPV6_ADDR { /* set IPv4 enabled/disabled flag and get the flag */ #define WMI_SET_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED(flag) do { \ - (flag) |= (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED); \ + (flag) |= (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED); \ } while (0) #define WMI_SET_ROAM_SUBNET_CHANGE_FLAG_IP4_DISABLED(flag) do { \ - (flag) &= ~(1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED); \ + (flag) &= ~(1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED); \ } while (0) #define WMI_GET_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED(flag) \ - ((flag) & (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED)) + ((flag) & (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP4_ENABLED)) /* set IPv6 enabled flag, disabled and get the flag */ #define WMI_SET_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED(flag) do { \ - (flag) |= (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED); \ + (flag) |= (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED); \ } while (0) #define WMI_SET_ROAM_SUBNET_CHANGE_FLAG_IP6_DISABLED(flag) do { \ - (flag) &= ~(1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED); \ + (flag) &= ~(1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED); \ } while (0) #define WMI_GET_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED(flag) \ - ((flag) & (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED)) + ((flag) & (1 << WMI_ROAM_SUBNET_CHANGE_FLAG_IP6_ENABLED)) /** * WMI_ROAM_SUBNET_CHANGE_CONFIG : Pass the gateway IP and MAC addresses * to FW. FW uses these parameters for subnet change detection. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_subnet_change_config_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** IPv4/IPv6 enabled/disabled */ - /** This flag sets the WMI_SET_ROAM_SUBNET_CHANGE_FLAG_xxx_ENABLED/DISABLED */ - A_UINT32 flag; - /** Gateway MAC address */ - wmi_mac_addr inet_gw_mac_addr; - /** IP addresses */ - WMI_IPV4_ADDR inet_gw_ip_v4_addr; - WMI_IPV6_ADDR inet_gw_ip_v6_addr; - /** Number of software retries for ARP/Neighbor solicitation request */ - A_UINT32 max_retries; - /** timeout in milliseconds for each ARP request*/ - A_UINT32 timeout; - /** number of skipped aps **/ - A_UINT32 num_skip_subnet_change_detection_bssid_list; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_roam_subnet_change_config_fixed_param + */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** IPv4/IPv6 enabled/disabled */ + /** This flag sets the WMI_SET_ROAM_SUBNET_CHANGE_FLAG_xxx_ENABLED/ + DISABLED */ + A_UINT32 flag; + /** Gateway MAC address */ + wmi_mac_addr inet_gw_mac_addr; + /** IP addresses */ + WMI_IPV4_ADDR inet_gw_ip_v4_addr; + WMI_IPV6_ADDR inet_gw_ip_v6_addr; + /** Number of software retries for ARP/Neighbor solicitation request */ + A_UINT32 max_retries; + /** timeout in milliseconds for each ARP request*/ + A_UINT32 timeout; + /** number of skipped aps **/ + A_UINT32 num_skip_subnet_change_detection_bssid_list; /** - * TLV (tag length value) parameters follows roam_subnet_change_config_cmd + * TLV (tag length value ) parameters follows roam_subnet_change_config_cmd * structure. The TLV's are: * wmi_mac_addr skip_subnet_change_detection_bssid_list []; **/ @@ -8127,13 +8959,13 @@ typedef struct { * FW will respond to probe requests while in listen state. */ typedef struct { - /* number of secondary device types,supported */ - A_UINT32 num_secondary_dev_types; -/** - * followed by 8 bytes of primary device id and - * num_secondary_dev_types * 8 bytes of secondary device - * id. - */ + /* number of secondary device types,supported */ + A_UINT32 num_secondary_dev_types; + /** + * followed by 8 bytes of primary device id and + * num_secondary_dev_types * 8 bytes of secondary device + * id. + */ } wmi_p2p_dev_set_device_info; /** WMI_P2P_DEV_SET_DISCOVERABILITY: enable/disable discoverability @@ -8142,8 +8974,8 @@ typedef struct { */ typedef struct { - /* 1:enable disoverability, 0:disable discoverability */ - A_UINT32 enable_discoverability; + /* 1:enable disoverability, 0:disable discoverability */ + A_UINT32 enable_discoverability; } wmi_p2p_set_discoverability; /** WMI_P2P_GO_SET_BEACON_IE: P2P IE to be added to @@ -8152,14 +8984,14 @@ typedef struct { * template set by WMI_BCN_TMPL_CMDID command. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_go_set_beacon_ie_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* ie length */ - A_UINT32 ie_buf_len; -/* Following this structure is the TLV byte stream of ie data of length ie_buf_len: - * A_UINT8 ie_data[]; <-- length in byte given by field num_data. - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_go_set_beacon_ie_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* ie length */ + A_UINT32 ie_buf_len; + /* Following this structure is the TLV byte stream of ie data of length ie_buf_len: + * A_UINT8 ie_data[]; // length in byte given by field num_data. + */ } wmi_p2p_go_set_beacon_ie_fixed_param; @@ -8169,518 +9001,553 @@ typedef struct { * template set by WMI_PRB_TMPL_CMDID command. */ typedef struct { - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* ie length */ - A_UINT32 ie_buf_len; -/*followed by byte stream of ie data of length ie_buf_len */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* ie length */ + A_UINT32 ie_buf_len; + /*followed by byte stream of ie data of length ie_buf_len */ } wmi_p2p_go_set_probe_resp_ie; /** WMI_P2P_SET_VENDOR_IE_DATA_CMDID: Vendor specific P2P IE data, which will * be used by the FW to parse the P2P NoA attribute in beacons, probe resposes * and action frames received by the P2P Client. - * Note: This command is currently used only for Apple P2P implementation. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_set_vendor_ie_data_cmd_fixed_param */ - /** OS specific P2P IE OUI (3 bytes) + OUI type (1 byte) */ - A_UINT32 p2p_ie_oui_type; - /** OS specific NoA Attribute ID */ - A_UINT32 p2p_noa_attribute; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_set_vendor_ie_data_cmd_fixed_param */ + /** OS specific P2P IE OUI (3 bytes) + OUI type (1 byte) */ + A_UINT32 p2p_ie_oui_type; + /** OS specific NoA Attribute ID */ + A_UINT32 p2p_noa_attribute; } wmi_p2p_set_vendor_ie_data_cmd_fixed_param; /*----P2P disc offload definition ----*/ typedef struct { - A_UINT32 pattern_type; -/** - * TLV (tag length value) paramerters follow the pattern structure. - * TLV can contain bssid list, ssid list and - * ie. the TLV tags are defined above; - */ + A_UINT32 pattern_type; + /** + * TLV (tag length value ) paramerters follow the pattern structure. + * TLV can contain bssid list, ssid list and + * ie. the TLV tags are defined above; + */ } wmi_p2p_disc_offload_pattern_cmd; typedef struct { - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* mgmt type of the ie*/ - A_UINT32 mgmt_type; - /* ie length */ - A_UINT32 ie_buf_len; -/*followed by byte stream of ie data of length ie_buf_len */ + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* mgmt type of the ie */ + A_UINT32 mgmt_type; + /* ie length */ + A_UINT32 ie_buf_len; + /*followed by byte stream of ie data of length ie_buf_len */ } wmi_p2p_disc_offload_appie_cmd; typedef struct { - /* enable/disable p2p find offload*/ - A_UINT32 enable; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* p2p find type */ - A_UINT32 disc_type; - /* p2p find perodic */ - A_UINT32 perodic; - /* p2p find listen channel */ - A_UINT32 listen_channel; - /* p2p find full channel number */ - A_UINT32 num_scan_chans; -/** - * TLV (tag length value) paramerters follow the pattern structure. - * TLV contain channel list - */ + /* enable/disable p2p find offload */ + A_UINT32 enable; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* p2p find type */ + A_UINT32 disc_type; + /* p2p find perodic */ + A_UINT32 perodic; + /* p2p find listen channel */ + A_UINT32 listen_channel; + /* p2p find full channel number */ + A_UINT32 num_scan_chans; + /** + * TLV (tag length value ) paramerters follow the pattern structure. + * TLV contain channel list + */ } wmi_p2p_disc_offload_config_cmd; /*----P2P OppPS definition ----*/ typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_set_oppps_cmd_fixed_param */ - A_UINT32 tlv_header; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* OppPS attributes */ - /** Bit 0: Indicate enable/disable of OppPS - * Bits 7-1: Ctwindow in TUs - * Bits 31-8: Reserved - */ - A_UINT32 oppps_attr; + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_set_oppps_cmd_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* OppPS attributes */ + /** Bit 0: Indicate enable/disable of OppPS + * Bits 7-1: Ctwindow in TUs + * Bits 31-8: Reserved + */ + A_UINT32 oppps_attr; } wmi_p2p_set_oppps_cmd_fixed_param; -#define WMI_UNIFIED_OPPPS_ATTR_ENALBED 0x1 -#define WMI_UNIFIED_OPPPS_ATTR_ENALBED_S 0 +#define WMI_UNIFIED_OPPPS_ATTR_ENALBED 0x1 +#define WMI_UNIFIED_OPPPS_ATTR_ENALBED_S 0 -#define WMI_UNIFIED_OPPPS_ATTR_IS_ENABLED(hdr) \ - WMI_F_MS((hdr)->oppps_attr, WMI_UNIFIED_OPPPS_ATTR_ENALBED) +#define WMI_UNIFIED_OPPPS_ATTR_IS_ENABLED(hdr) \ + WMI_F_MS((hdr)->oppps_attr, WMI_UNIFIED_OPPPS_ATTR_ENALBED) -#define WMI_UNIFIED_OPPPS_ATTR_ENABLED_SET(hdr) \ - WMI_F_RMW((hdr)->oppps_attr, 0x1, \ - WMI_UNIFIED_OPPPS_ATTR_ENALBED); +#define WMI_UNIFIED_OPPPS_ATTR_ENABLED_SET(hdr) \ + WMI_F_RMW((hdr)->oppps_attr, 0x1, \ + WMI_UNIFIED_OPPPS_ATTR_ENALBED); -#define WMI_UNIFIED_OPPPS_ATTR_CTWIN 0xfe -#define WMI_UNIFIED_OPPPS_ATTR_CTWIN_S 1 +#define WMI_UNIFIED_OPPPS_ATTR_CTWIN 0xfe +#define WMI_UNIFIED_OPPPS_ATTR_CTWIN_S 1 -#define WMI_UNIFIED_OPPPS_ATTR_CTWIN_GET(hdr) \ - WMI_F_MS((hdr)->oppps_attr, WMI_UNIFIED_OPPPS_ATTR_CTWIN) +#define WMI_UNIFIED_OPPPS_ATTR_CTWIN_GET(hdr) \ + WMI_F_MS((hdr)->oppps_attr, WMI_UNIFIED_OPPPS_ATTR_CTWIN) -#define WMI_UNIFIED_OPPPS_ATTR_CTWIN_SET(hdr, v) \ - WMI_F_RMW((hdr)->oppps_attr, (v) & 0x7f, \ - WMI_UNIFIED_OPPPS_ATTR_CTWIN); +#define WMI_UNIFIED_OPPPS_ATTR_CTWIN_SET(hdr, v) \ + WMI_F_RMW((hdr)->oppps_attr, (v) & 0x7f, \ + WMI_UNIFIED_OPPPS_ATTR_CTWIN); typedef enum p2p_lo_start_ctrl_flags_e { - P2P_LO_START_CTRL_FLAG_FLUSH_LISTEN_RESULT = 1 << 0, /* flush prob. req when host is awake */ + /* flush prob. req when host is awake */ + P2P_LO_START_CTRL_FLAG_FLUSH_LISTEN_RESULT = 1 << 0, } p2p_lo_start_ctrl_flags; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 ctl_flags; /* refer to enum_p2p_lo_start_ctrl_flags_e */ - A_UINT32 channel; /* MHz */ - A_UINT32 period; /* ms */ - A_UINT32 interval; /* ms, interval should be larger than period */ - A_UINT32 count; /* 0 means forever */ - /* - * device_types_len specifies the number of bytes in the - * device_types_data[] byte-array TLV that follows this TLV. - * The data in device_types_data[] is in 8-byte elements, so - * device_types_len will be a multiple of 8. - */ - A_UINT32 device_types_len; - /* - * prob_resp_len specifies the number of bytes in the - * prob_resp_data[] byte-array TLV that follows this TLV. - */ - A_UINT32 prob_resp_len; - /* - * Two other TLVs follow this TLV: - * A_UINT8 device_types_data[device_types_len]; - * A_UINT8 prob_resp_data[prob_resp_len]; - * The information in device_types_data[] and prob_resp_data[] - * needs to be provided to the target in over-the-air byte order. - * On a big-endian host, if device_types_data and prob_resp_data - * are initially in the correct over-the-air byte order, - * the automatic byteswap for endianness-correction during WMI - * message download will mess up the byte order. - * Thus, a big-endian host needs to explicitly byte-swap the bytes - * within each quad-byte segment of device_types_data[] and - * prob_resp_data[], so that the automatic byte-swap applied during - * WMI download from a big-endian host to the little-endian target - * will restore device_types_data and prob_resp_data into the - * correct byte ordering. - */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 ctl_flags; /* refer to enum_p2p_lo_start_ctrl_flags_e */ + A_UINT32 channel; /* MHz */ + A_UINT32 period; /* ms */ + A_UINT32 interval; /* ms, interval should be larger than period */ + A_UINT32 count; /* 0 means forever */ + /* + * device_types_len specifies the number of bytes in the + * device_types_data[] byte-array TLV that follows this TLV. + * The data in device_types_data[] is in 8-byte elements, so + * device_types_len will be a multiple of 8. + */ + A_UINT32 device_types_len; + /* + * prob_resp_len specifies the number of bytes in the + * prob_resp_data[] byte-array TLV that follows this TLV. + */ + A_UINT32 prob_resp_len; + /* + * Two other TLVs follow this TLV: + * A_UINT8 device_types_data[device_types_len]; + * A_UINT8 prob_resp_data[prob_resp_len]; + * The information in device_types_data[] and prob_resp_data[] + * needs to be provided to the target in over-the-air byte order. + * On a big-endian host, if device_types_data and prob_resp_data + * are initially in the correct over-the-air byte order, + * the automatic byteswap for endianness-correction during WMI + * message download will mess up the byte order. + * Thus, a big-endian host needs to explicitly byte-swap the bytes + * within each quad-byte segment of device_types_data[] and + * prob_resp_data[], so that the automatic byte-swap applied during + * WMI download from a big-endian host to the little-endian target + * will restore device_types_data and prob_resp_data into the + * correct byte ordering. + */ } wmi_p2p_lo_start_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; + A_UINT32 tlv_header; + A_UINT32 vdev_id; } wmi_p2p_lo_stop_cmd_fixed_param; typedef enum p2p_lo_stopped_reason_e { - P2P_LO_STOPPED_REASON_COMPLETE = 0, /* finished as scheduled */ - P2P_LO_STOPPED_REASON_RECV_STOP_CMD, /* host stops it */ - P2P_LO_STOPPED_REASON_INVALID_LO_PAR, /* invalid listen offload par */ - P2P_LO_STOPPED_REASON_FW_NOT_SUPPORT, /* vdev cannot support it right now */ + /* finished as scheduled */ + P2P_LO_STOPPED_REASON_COMPLETE = 0, + /* host stops it */ + P2P_LO_STOPPED_REASON_RECV_STOP_CMD, + /* invalid listen offload par */ + P2P_LO_STOPPED_REASON_INVALID_LO_PAR, + /* vdev cannot support it right now */ + P2P_LO_STOPPED_REASON_FW_NOT_SUPPORT, } p2p_lo_stopped_reason; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 reason;/* refer to p2p_lo_stopped_reason_e */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 reason; /* refer to p2p_lo_stopped_reason_e */ } wmi_p2p_lo_stopped_event_fixed_param; typedef enum { - WMI_MNT_FILTER_CONFIG_MANAGER, - WMI_MNT_FILTER_CONFIG_CONTROL, - WMI_MNT_FILTER_CONFIG_DATA, - WMI_MNT_FILTER_CONFIG_ALL, - WMI_MNT_FILTER_CONFIG_UNKNOWN, + WMI_MNT_FILTER_CONFIG_MANAGER, + WMI_MNT_FILTER_CONFIG_CONTROL, + WMI_MNT_FILTER_CONFIG_DATA, + WMI_MNT_FILTER_CONFIG_ALL, + WMI_MNT_FILTER_CONFIG_UNKNOWN, } WMI_MNT_FILTER_CONFIG_TYPE; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 clear_or_set; - A_UINT32 configure_type; /* see WMI_MNT_FILTER_CONFIG_TYPE */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 clear_or_set; + A_UINT32 configure_type; /* see WMI_MNT_FILTER_CONFIG_TYPE */ } wmi_mnt_filter_cmd_fixed_param; typedef struct { - A_UINT32 time32; /* upper 32 bits of time stamp */ - A_UINT32 time0; /* lower 32 bits of time stamp */ + A_UINT32 time32; /* upper 32 bits of time stamp */ + A_UINT32 time0; /* lower 32 bits of time stamp */ } A_TIME64; typedef enum wmi_peer_sta_kickout_reason { - WMI_PEER_STA_KICKOUT_REASON_UNSPECIFIED = 0, /* default value to preserve legacy behavior */ - WMI_PEER_STA_KICKOUT_REASON_XRETRY = 1, - WMI_PEER_STA_KICKOUT_REASON_INACTIVITY = 2, - WMI_PEER_STA_KICKOUT_REASON_IBSS_DISCONNECT = 3, - WMI_PEER_STA_KICKOUT_REASON_TDLS_DISCONNECT = 4, /* TDLS peer has disappeared. All tx is failing */ - WMI_PEER_STA_KICKOUT_REASON_SA_QUERY_TIMEOUT = 5, + WMI_PEER_STA_KICKOUT_REASON_UNSPECIFIED = 0, /* default value to preserve legacy behavior */ + WMI_PEER_STA_KICKOUT_REASON_XRETRY = 1, + WMI_PEER_STA_KICKOUT_REASON_INACTIVITY = 2, + WMI_PEER_STA_KICKOUT_REASON_IBSS_DISCONNECT = 3, + WMI_PEER_STA_KICKOUT_REASON_TDLS_DISCONNECT = 4, /* TDLS peer has disappeared. All tx is failing */ + WMI_PEER_STA_KICKOUT_REASON_SA_QUERY_TIMEOUT = 5, } PEER_KICKOUT_REASON; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_sta_kickout_event_fixed_param */ - /** peer mac address */ - wmi_mac_addr peer_macaddr; - /** Reason code, defined as above */ - A_UINT32 reason; - /** RSSI of the last bcn (averaged) in dB. 0 means Noise Floor value */ - A_UINT32 rssi; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_sta_kickout_event_fixed_param */ + /** peer mac address */ + wmi_mac_addr peer_macaddr; + /** Reason code, defined as above */ + A_UINT32 reason; + /** RSSI of the last bcn (averaged) in dB. 0 means Noise Floor value */ + A_UINT32 rssi; } wmi_peer_sta_kickout_event_fixed_param; #define WMI_WLAN_PROFILE_MAX_HIST 3 #define WMI_WLAN_PROFILE_MAX_BIN_CNT 32 typedef struct _wmi_wlan_profile_t { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_t */ - A_UINT32 id; - A_UINT32 cnt; - A_UINT32 tot; - A_UINT32 min; - A_UINT32 max; - A_UINT32 hist_intvl; - A_UINT32 hist[WMI_WLAN_PROFILE_MAX_HIST]; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_t */ + A_UINT32 id; + A_UINT32 cnt; + A_UINT32 tot; + A_UINT32 min; + A_UINT32 max; + A_UINT32 hist_intvl; + A_UINT32 hist[WMI_WLAN_PROFILE_MAX_HIST]; } wmi_wlan_profile_t; typedef struct _wmi_wlan_profile_ctx_t { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_ctx_t */ - A_UINT32 tot; /* time in us */ - A_UINT32 tx_msdu_cnt; - A_UINT32 tx_mpdu_cnt; - A_UINT32 tx_ppdu_cnt; - A_UINT32 rx_msdu_cnt; - A_UINT32 rx_mpdu_cnt; - A_UINT32 bin_count; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_ctx_t */ + A_UINT32 tot; /* time in us */ + A_UINT32 tx_msdu_cnt; + A_UINT32 tx_mpdu_cnt; + A_UINT32 tx_ppdu_cnt; + A_UINT32 rx_msdu_cnt; + A_UINT32 rx_mpdu_cnt; + A_UINT32 bin_count; } wmi_wlan_profile_ctx_t; - typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_trigger_cmd_fixed_param */ - A_UINT32 enable; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_trigger_cmd_fixed_param */ + A_UINT32 enable; } wmi_wlan_profile_trigger_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_get_prof_data_cmd_fixed_param */ - A_UINT32 value; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_get_prof_data_cmd_fixed_param */ + A_UINT32 value; } wmi_wlan_profile_get_prof_data_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_set_hist_intvl_cmd_fixed_param */ - A_UINT32 profile_id; - A_UINT32 value; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_set_hist_intvl_cmd_fixed_param */ + A_UINT32 profile_id; + A_UINT32 value; } wmi_wlan_profile_set_hist_intvl_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_enable_profile_id_cmd_fixed_param */ - A_UINT32 profile_id; - A_UINT32 enable; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlan_profile_enable_profile_id_cmd_fixed_param */ + A_UINT32 profile_id; + A_UINT32 enable; } wmi_wlan_profile_enable_profile_id_cmd_fixed_param; /*Wifi header is upto 26, LLC is 8, with 14 byte duplicate in 802.3 header, that's 26+8-14=20. - 146-128=18. So this means it is converted to non-QoS header. Riva FW take care of the QOS/non-QOS - when comparing wifi header.*/ + 146-128=18. So this means it is converted to non-QoS header. Riva FW take care of the QOS/non-QOS + when comparing wifi header.*/ /* NOTE: WOW_DEFAULT_BITMAP_PATTERN_SIZE(_DWORD) and WOW_DEFAULT_BITMASK_SIZE(_DWORD) can't be changed without breaking the compatibility */ #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 146 -#define WOW_DEFAULT_BITMAP_PATTERN_SIZE_DWORD 37 /* Convert WOW_DEFAULT_EVT_BUF_SIZE into Int32 size */ +#define WOW_DEFAULT_BITMAP_PATTERN_SIZE_DWORD 37 /* Convert WOW_DEFAULT_EVT_BUF_SIZE into Int32 size */ #define WOW_DEFAULT_BITMASK_SIZE 146 #define WOW_DEFAULT_BITMASK_SIZE_DWORD 37 #define WOW_MAX_BITMAP_FILTERS 32 #define WOW_DEFAULT_MAGIG_PATTERN_MATCH_CNT 16 -#define WOW_EXTEND_PATTERN_MATCH_CNT 16 -#define WOW_SHORT_PATTERN_MATCH_CNT 8 -#define WOW_DEFAULT_EVT_BUF_SIZE 148 /* Maximum 148 bytes of the data is copied starting from header incase if the match is found. - The 148 comes from (128 - 14) payload size + 8bytes LLC + 26bytes MAC header*/ +#define WOW_EXTEND_PATTERN_MATCH_CNT 16 +#define WOW_SHORT_PATTERN_MATCH_CNT 8 +#define WOW_DEFAULT_EVT_BUF_SIZE 148 /* Maximum 148 bytes of the data is copied starting from header incase if the match is found. + The 148 comes from (128 - 14 ) payload size + 8bytes LLC + 26bytes MAC header */ #define WOW_DEFAULT_IOAC_PATTERN_SIZE 6 #define WOW_DEFAULT_IOAC_PATTERN_SIZE_DWORD 2 #define WOW_DEFAULT_IOAC_RANDOM_SIZE 6 #define WOW_DEFAULT_IOAC_RANDOM_SIZE_DWORD 2 #define WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_SIZE 120 #define WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_SIZE_DWORD 30 -#define WOW_DEFAULT_IOAC_SOCKET_PATTERN_SIZE 32 +#define WOW_DEFAULT_IOAC_SOCKET_PATTERN_SIZE 32 #define WOW_DEFAULT_IOAC_SOCKET_PATTERN_SIZE_DWORD 8 -#define WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_REV_SIZE 32 +#define WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_REV_SIZE 32 #define WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_REV_SIZE_DWORD 8 #define WOW_DEFAULT_IOAC_SOCKET_PATTERN_ACKNAK_SIZE 128 #define WOW_DEFAULT_IOAC_SOCKET_PATTERN_ACKNAK_SIZE_DWORD 32 typedef enum pattern_type_e { - WOW_PATTERN_MIN = 0, - WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, - WOW_IPV4_SYNC_PATTERN, - WOW_IPV6_SYNC_PATTERN, - WOW_WILD_CARD_PATTERN, - WOW_TIMER_PATTERN, - WOW_MAGIC_PATTERN, - WOW_IPV6_RA_PATTERN, - WOW_IOAC_PKT_PATTERN, - WOW_IOAC_TMR_PATTERN, - WOW_IOAC_SOCK_PATTERN, - WOW_PATTERN_MAX + WOW_PATTERN_MIN = 0, + WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, + WOW_IPV4_SYNC_PATTERN, + WOW_IPV6_SYNC_PATTERN, + WOW_WILD_CARD_PATTERN, + WOW_TIMER_PATTERN, + WOW_MAGIC_PATTERN, + WOW_IPV6_RA_PATTERN, + WOW_IOAC_PKT_PATTERN, + WOW_IOAC_TMR_PATTERN, + WOW_IOAC_SOCK_PATTERN, + WOW_PATTERN_MAX } WOW_PATTERN_TYPE; typedef enum event_type_e { - WOW_BMISS_EVENT = 0, - WOW_BETTER_AP_EVENT, - WOW_DEAUTH_RECVD_EVENT, - WOW_MAGIC_PKT_RECVD_EVENT, - WOW_GTK_ERR_EVENT, - WOW_FOURWAY_HSHAKE_EVENT, - WOW_EAPOL_RECVD_EVENT, - WOW_NLO_DETECTED_EVENT, - WOW_DISASSOC_RECVD_EVENT, - WOW_PATTERN_MATCH_EVENT, - WOW_CSA_IE_EVENT, - WOW_PROBE_REQ_WPS_IE_EVENT, - WOW_AUTH_REQ_EVENT, - WOW_ASSOC_REQ_EVENT, - WOW_HTT_EVENT, - WOW_RA_MATCH_EVENT, - WOW_HOST_AUTO_SHUTDOWN_EVENT, - WOW_IOAC_MAGIC_EVENT, - WOW_IOAC_SHORT_EVENT, - WOW_IOAC_EXTEND_EVENT, - WOW_IOAC_TIMER_EVENT, - WOW_DFS_PHYERR_RADAR_EVENT, - WOW_BEACON_EVENT, - WOW_CLIENT_KICKOUT_EVENT, - WOW_NAN_EVENT, - WOW_EXTSCAN_EVENT, - WOW_IOAC_REV_KA_FAIL_EVENT, - WOW_IOAC_SOCK_EVENT, - WOW_NLO_SCAN_COMPLETE_EVENT, - WOW_NAN_DATA_EVENT, - WOW_NAN_RTT_EVENT, /* DEPRECATED, UNUSED */ - WOW_OEM_RESPONSE_EVENT = WOW_NAN_RTT_EVENT, /* reuse deprecated event value */ - WOW_TDLS_CONN_TRACKER_EVENT, - WOW_CRITICAL_LOG_EVENT, + WOW_BMISS_EVENT = 0, + WOW_BETTER_AP_EVENT, + WOW_DEAUTH_RECVD_EVENT, + WOW_MAGIC_PKT_RECVD_EVENT, + WOW_GTK_ERR_EVENT, + WOW_FOURWAY_HSHAKE_EVENT, + WOW_EAPOL_RECVD_EVENT, + WOW_NLO_DETECTED_EVENT, + WOW_DISASSOC_RECVD_EVENT, + WOW_PATTERN_MATCH_EVENT, + WOW_CSA_IE_EVENT, + WOW_PROBE_REQ_WPS_IE_EVENT, + WOW_AUTH_REQ_EVENT, + WOW_ASSOC_REQ_EVENT, + WOW_HTT_EVENT, + WOW_RA_MATCH_EVENT, + WOW_HOST_AUTO_SHUTDOWN_EVENT, + WOW_IOAC_MAGIC_EVENT, + WOW_IOAC_SHORT_EVENT, + WOW_IOAC_EXTEND_EVENT, + WOW_IOAC_TIMER_EVENT, + WOW_DFS_PHYERR_RADAR_EVENT, + WOW_BEACON_EVENT, + WOW_CLIENT_KICKOUT_EVENT, + WOW_NAN_EVENT, + WOW_EXTSCAN_EVENT, + WOW_IOAC_REV_KA_FAIL_EVENT, + WOW_IOAC_SOCK_EVENT, + WOW_NLO_SCAN_COMPLETE_EVENT, + WOW_NAN_DATA_EVENT, + WOW_NAN_RTT_EVENT, /* DEPRECATED, UNUSED */ + /* reuse deprecated event value */ + WOW_OEM_RESPONSE_EVENT = WOW_NAN_RTT_EVENT, + WOW_TDLS_CONN_TRACKER_EVENT, + WOW_CRITICAL_LOG_EVENT, } WOW_WAKE_EVENT_TYPE; typedef enum wake_reason_e { - WOW_REASON_UNSPECIFIED = -1, - WOW_REASON_NLOD = 0, - WOW_REASON_AP_ASSOC_LOST, - WOW_REASON_LOW_RSSI, - WOW_REASON_DEAUTH_RECVD, - WOW_REASON_DISASSOC_RECVD, - WOW_REASON_GTK_HS_ERR, - WOW_REASON_EAP_REQ, - WOW_REASON_FOURWAY_HS_RECV, - WOW_REASON_TIMER_INTR_RECV, - WOW_REASON_PATTERN_MATCH_FOUND, - WOW_REASON_RECV_MAGIC_PATTERN, - WOW_REASON_P2P_DISC, - WOW_REASON_WLAN_HB, - WOW_REASON_CSA_EVENT, - WOW_REASON_PROBE_REQ_WPS_IE_RECV, - WOW_REASON_AUTH_REQ_RECV, - WOW_REASON_ASSOC_REQ_RECV, - WOW_REASON_HTT_EVENT, - WOW_REASON_RA_MATCH, - WOW_REASON_HOST_AUTO_SHUTDOWN, - WOW_REASON_IOAC_MAGIC_EVENT, - WOW_REASON_IOAC_SHORT_EVENT, - WOW_REASON_IOAC_EXTEND_EVENT, - WOW_REASON_IOAC_TIMER_EVENT, - WOW_REASON_ROAM_HO, - WOW_REASON_DFS_PHYERR_RADADR_EVENT, - WOW_REASON_BEACON_RECV, - WOW_REASON_CLIENT_KICKOUT_EVENT, - WOW_REASON_NAN_EVENT, - WOW_REASON_EXTSCAN, - WOW_REASON_RSSI_BREACH_EVENT, - WOW_REASON_IOAC_REV_KA_FAIL_EVENT, - WOW_REASON_IOAC_SOCK_EVENT, - WOW_REASON_NLO_SCAN_COMPLETE, - WOW_REASON_PACKET_FILTER_MATCH, - WOW_REASON_ASSOC_RES_RECV, - WOW_REASON_REASSOC_REQ_RECV, - WOW_REASON_REASSOC_RES_RECV, - WOW_REASON_ACTION_FRAME_RECV, - WOW_REASON_BPF_ALLOW, - WOW_REASON_NAN_DATA, - WOW_REASON_NAN_RTT, /* DEPRECATED, UNUSED */ - WOW_REASON_OEM_RESPONSE_EVENT = WOW_REASON_NAN_RTT, /* reuse deprecated reason value */ - WOW_REASON_TDLS_CONN_TRACKER_EVENT, - WOW_REASON_CRITICAL_LOG, - WOW_REASON_P2P_LISTEN_OFFLOAD, - WOW_REASON_NAN_EVENT_WAKE_HOST, - WOW_REASON_DEBUG_TEST = 0xFF, + WOW_REASON_UNSPECIFIED = -1, + WOW_REASON_NLOD = 0, + WOW_REASON_AP_ASSOC_LOST, + WOW_REASON_LOW_RSSI, + WOW_REASON_DEAUTH_RECVD, + WOW_REASON_DISASSOC_RECVD, + WOW_REASON_GTK_HS_ERR, + WOW_REASON_EAP_REQ, + WOW_REASON_FOURWAY_HS_RECV, + WOW_REASON_TIMER_INTR_RECV, + WOW_REASON_PATTERN_MATCH_FOUND, + WOW_REASON_RECV_MAGIC_PATTERN, + WOW_REASON_P2P_DISC, + WOW_REASON_WLAN_HB, + WOW_REASON_CSA_EVENT, + WOW_REASON_PROBE_REQ_WPS_IE_RECV, + WOW_REASON_AUTH_REQ_RECV, + WOW_REASON_ASSOC_REQ_RECV, + WOW_REASON_HTT_EVENT, + WOW_REASON_RA_MATCH, + WOW_REASON_HOST_AUTO_SHUTDOWN, + WOW_REASON_IOAC_MAGIC_EVENT, + WOW_REASON_IOAC_SHORT_EVENT, + WOW_REASON_IOAC_EXTEND_EVENT, + WOW_REASON_IOAC_TIMER_EVENT, + WOW_REASON_ROAM_HO, + WOW_REASON_DFS_PHYERR_RADADR_EVENT, + WOW_REASON_BEACON_RECV, + WOW_REASON_CLIENT_KICKOUT_EVENT, + WOW_REASON_NAN_EVENT, + WOW_REASON_EXTSCAN, + WOW_REASON_RSSI_BREACH_EVENT, + WOW_REASON_IOAC_REV_KA_FAIL_EVENT, + WOW_REASON_IOAC_SOCK_EVENT, + WOW_REASON_NLO_SCAN_COMPLETE, + WOW_REASON_PACKET_FILTER_MATCH, + WOW_REASON_ASSOC_RES_RECV, + WOW_REASON_REASSOC_REQ_RECV, + WOW_REASON_REASSOC_RES_RECV, + WOW_REASON_ACTION_FRAME_RECV, + WOW_REASON_BPF_ALLOW, + WOW_REASON_NAN_DATA, + WOW_REASON_NAN_RTT, /* DEPRECATED, UNUSED */ + /* reuse deprecated reason value */ + WOW_REASON_OEM_RESPONSE_EVENT = WOW_REASON_NAN_RTT, + WOW_REASON_TDLS_CONN_TRACKER_EVENT, + WOW_REASON_CRITICAL_LOG, + WOW_REASON_P2P_LISTEN_OFFLOAD, + WOW_REASON_NAN_EVENT_WAKE_HOST, + WOW_REASON_DEBUG_TEST = 0xFF, } WOW_WAKE_REASON_TYPE; - typedef enum { - WOW_IFACE_PAUSE_ENABLED, - WOW_IFACE_PAUSE_DISABLED + WOW_IFACE_PAUSE_ENABLED, + WOW_IFACE_PAUSE_DISABLED } WOW_IFACE_STATUS; enum { - WMI_WOW_FLAG_IGNORE_PCIE_RESET = 0x00000001, /* some win10 platfrom will not assert pcie_reset for wow.*/ - /* WMI_WOW_FLAG_SEND_PM_PME - * Some platforms have issues if the PM_PME message is sent after WoW, - * so don't send PM_PME after WoW unless the host uses this flag - * to request it. - */ - WMI_WOW_FLAG_SEND_PM_PME = 0x00000002, + /* some win10 platfrom will not assert pcie_reset for wow.*/ + WMI_WOW_FLAG_IGNORE_PCIE_RESET = 0x00000001, + /* + * WMI_WOW_FLAG_SEND_PM_PME + * Some platforms have issues if the PM_PME message is sent after WoW, + * so don't send PM_PME after WoW unless the host uses this flag + * to request it. + */ + WMI_WOW_FLAG_SEND_PM_PME = 0x00000002, + /* Flag to indicate unit test */ + WMI_WOW_FLAG_UNIT_TEST_ENABLE = 0x00000004, + /* Force HTC wakeup */ + WMI_WOW_FLAG_DO_HTC_WAKEUP = 0x00000008, }; + typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_enable_cmd_fixed_param */ - A_UINT32 enable; - A_UINT32 pause_iface_config; - A_UINT32 flags; /* WMI_WOW_FLAG enums */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_enable_cmd_fixed_param */ + A_UINT32 enable; + A_UINT32 pause_iface_config; + A_UINT32 flags; /* WMI_WOW_FLAG enums */ } wmi_wow_enable_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */ - /** Reserved for future use */ - A_UINT32 reserved0; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */ + /** Reserved for future use */ + A_UINT32 reserved0; } wmi_wow_hostwakeup_from_sleep_cmd_fixed_param; #define WOW_ICMPV6_NA_FILTER_DISABLE 0 #define WOW_ICMPV6_NA_FILTER_ENABLE 1 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 enable; /* WOW_ICMPV6_NA_FILTER_ENABLE/DISABLE */ + /* TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 enable; /* WOW_ICMPV6_NA_FILTER_ENABLE/DISABLE */ } wmi_wow_enable_icmpv6_na_flt_cmd_fixed_param; typedef struct bitmap_pattern_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_BITMAP_PATTERN_T */ - A_UINT32 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE_DWORD]; - A_UINT32 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE_DWORD]; - A_UINT32 pattern_offset; - A_UINT32 pattern_len; - A_UINT32 bitmask_len; - A_UINT32 pattern_id; /* must be less than max_bitmap_filters */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_BITMAP_PATTERN_T */ + A_UINT32 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE_DWORD]; + A_UINT32 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE_DWORD]; + A_UINT32 pattern_offset; + A_UINT32 pattern_len; + A_UINT32 bitmask_len; + A_UINT32 pattern_id; /* must be less than max_bitmap_filters */ } WOW_BITMAP_PATTERN_T; typedef struct ipv4_sync_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IPV4_SYNC_PATTERN_T */ - A_UINT32 ipv4_src_addr; - A_UINT32 ipv4_dst_addr; - A_UINT32 tcp_src_prt; - A_UINT32 tcp_dst_prt; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IPV4_SYNC_PATTERN_T */ + A_UINT32 ipv4_src_addr; + A_UINT32 ipv4_dst_addr; + A_UINT32 tcp_src_prt; + A_UINT32 tcp_dst_prt; } WOW_IPV4_SYNC_PATTERN_T; typedef struct ipv6_sync_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IPV6_SYNC_PATTERN_T */ - A_UINT32 ipv6_src_addr[4]; - A_UINT32 ipv6_dst_addr[4]; - A_UINT32 tcp_src_prt; - A_UINT32 tcp_dst_prt; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IPV6_SYNC_PATTERN_T */ + A_UINT32 ipv6_src_addr[4]; + A_UINT32 ipv6_dst_addr[4]; + A_UINT32 tcp_src_prt; + A_UINT32 tcp_dst_prt; } WOW_IPV6_SYNC_PATTERN_T; -typedef struct WOW_MAGIC_PATTERN_CMD -{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_MAGIC_PATTERN_CMD */ - wmi_mac_addr macaddr; +typedef struct WOW_MAGIC_PATTERN_CMD { + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_MAGIC_PATTERN_CMD */ + wmi_mac_addr macaddr; } WOW_MAGIC_PATTERN_CMD; typedef enum wow_ioac_pattern_type { - WOW_IOAC_MAGIC_PATTERN = 1, - WOW_IOAC_SHORT_PATTERN, - WOW_IOAC_EXTEND_PATTERN, + WOW_IOAC_MAGIC_PATTERN = 1, + WOW_IOAC_SHORT_PATTERN, + WOW_IOAC_EXTEND_PATTERN, } WOW_IOAC_PATTERN_TYPE; typedef struct ioac_sock_pattern_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IOAC_SOCK_PATTERN_T */ - A_UINT32 id; - A_UINT32 local_ipv4; - A_UINT32 remote_ipv4; - A_UINT32 local_port; - A_UINT32 remote_port; - A_UINT32 pattern_len; /* units = bytes */ - A_UINT32 pattern[WOW_DEFAULT_IOAC_SOCKET_PATTERN_SIZE_DWORD]; - WMI_IPV6_ADDR local_ipv6; - WMI_IPV6_ADDR remote_ipv6; - A_UINT32 ack_nak_len; - A_UINT32 ackpkt[WOW_DEFAULT_IOAC_SOCKET_PATTERN_ACKNAK_SIZE_DWORD]; - A_UINT32 nakpkt[WOW_DEFAULT_IOAC_SOCKET_PATTERN_ACKNAK_SIZE_DWORD]; + /** + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_WOW_IOAC_SOCK_PATTERN_T + */ + A_UINT32 tlv_header; + A_UINT32 id; + A_UINT32 local_ipv4; + A_UINT32 remote_ipv4; + A_UINT32 local_port; + A_UINT32 remote_port; + A_UINT32 pattern_len; /* units = bytes */ + A_UINT32 pattern[WOW_DEFAULT_IOAC_SOCKET_PATTERN_SIZE_DWORD]; + WMI_IPV6_ADDR local_ipv6; + WMI_IPV6_ADDR remote_ipv6; + A_UINT32 ack_nak_len; + A_UINT32 ackpkt[WOW_DEFAULT_IOAC_SOCKET_PATTERN_ACKNAK_SIZE_DWORD]; + A_UINT32 nakpkt[WOW_DEFAULT_IOAC_SOCKET_PATTERN_ACKNAK_SIZE_DWORD]; } WOW_IOAC_SOCK_PATTERN_T; typedef struct ioac_pkt_pattern_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IOAC_PKT_PATTERN_T */ - A_UINT32 pattern_type; - A_UINT32 pattern[WOW_DEFAULT_IOAC_PATTERN_SIZE_DWORD]; - A_UINT32 random[WOW_DEFAULT_IOAC_RANDOM_SIZE_DWORD]; - A_UINT32 pattern_len; - A_UINT32 random_len; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IOAC_PKT_PATTERN_T */ + A_UINT32 pattern_type; + A_UINT32 pattern[WOW_DEFAULT_IOAC_PATTERN_SIZE_DWORD]; + A_UINT32 random[WOW_DEFAULT_IOAC_RANDOM_SIZE_DWORD]; + A_UINT32 pattern_len; + A_UINT32 random_len; } WOW_IOAC_PKT_PATTERN_T; typedef struct ioac_tmr_pattern_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IOAC_TMR_PATTERN_T */ - A_UINT32 wake_in_s; - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_IOAC_TMR_PATTERN_T */ + A_UINT32 wake_in_s; + A_UINT32 vdev_id; } WOW_IOAC_TMR_PATTERN_T; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param */ - A_UINT32 nID; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param */ + A_UINT32 nID; } WMI_WOW_IOAC_ADD_KEEPALIVE_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param */ - A_UINT32 nID; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param */ + A_UINT32 nID; } WMI_WOW_IOAC_DEL_KEEPALIVE_CMD_fixed_param; typedef struct ioac_keepalive_s { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_KEEPALIVE_T */ - A_UINT32 keepalive_pkt_buf[WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_SIZE_DWORD]; - A_UINT32 keepalive_pkt_len; - A_UINT32 period_in_ms; - A_UINT32 vdev_id; - A_UINT32 max_loss_cnt; - A_UINT32 local_ipv4; - A_UINT32 remote_ipv4; - A_UINT32 local_port; - A_UINT32 remote_port; - A_UINT32 recv_period_in_ms; - A_UINT32 rev_ka_size; - A_UINT32 rev_ka_data[WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_REV_SIZE_DWORD]; - WMI_IPV6_ADDR local_ipv6; - WMI_IPV6_ADDR remote_ipv6; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_KEEPALIVE_T */ + A_UINT32 + keepalive_pkt_buf + [WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_SIZE_DWORD]; + A_UINT32 keepalive_pkt_len; + A_UINT32 period_in_ms; + A_UINT32 vdev_id; + A_UINT32 max_loss_cnt; + A_UINT32 local_ipv4; + A_UINT32 remote_ipv4; + A_UINT32 local_port; + A_UINT32 remote_port; + A_UINT32 recv_period_in_ms; + A_UINT32 rev_ka_size; + A_UINT32 rev_ka_data[WOW_DEFAULT_IOAC_KEEP_ALIVE_PKT_REV_SIZE_DWORD]; + WMI_IPV6_ADDR local_ipv6; + WMI_IPV6_ADDR remote_ipv6; } WMI_WOW_IOAC_KEEPALIVE_T; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 pattern_type; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 pattern_type; /* * Following this struct are these TLVs. Note that they are all array of structures * but can have at most one element. Which TLV is empty or has one element depends @@ -8691,47 +9558,48 @@ typedef struct { } WMI_WOW_IOAC_ADD_PATTERN_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 pattern_type; - A_UINT32 pattern_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 pattern_type; + A_UINT32 pattern_id; } WMI_WOW_IOAC_DEL_PATTERN_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_ADD_PATTERN_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 pattern_id; - A_UINT32 pattern_type; -/* - * Following this struct are these TLVs. Note that they are all array of structures - * but can have at most one element. Which TLV is empty or has one element depends - * on the field pattern_type. This is to emulate an union. - * WOW_BITMAP_PATTERN_T pattern_info_bitmap[]; - * WOW_IPV4_SYNC_PATTERN_T pattern_info_ipv4[]; - * WOW_IPV6_SYNC_PATTERN_T pattern_info_ipv6[]; - * WOW_MAGIC_PATTERN_CMD pattern_info_magic_pattern[]; - * A_UINT32 pattern_info_timeout[]; - * A_UINT32 ra_ratelimit_interval; - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_ADD_PATTERN_CMD_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 pattern_id; + A_UINT32 pattern_type; + /* + * Following this struct are these TLVs. Note that they are all array of structures + * but can have at most one element. Which TLV is empty or has one element depends + * on the field pattern_type. This is to emulate an union. + * WOW_BITMAP_PATTERN_T pattern_info_bitmap[]; + * WOW_IPV4_SYNC_PATTERN_T pattern_info_ipv4[]; + * WOW_IPV6_SYNC_PATTERN_T pattern_info_ipv6[]; + * WOW_MAGIC_PATTERN_CMD pattern_info_magic_pattern[]; + * A_UINT32 pattern_info_timeout[]; + * A_UINT32 ra_ratelimit_interval; + */ } WMI_WOW_ADD_PATTERN_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_DEL_PATTERN_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 pattern_id; - A_UINT32 pattern_type; + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_DEL_PATTERN_CMD_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 pattern_id; + A_UINT32 pattern_type; } WMI_WOW_DEL_PATTERN_CMD_fixed_param; #define WMI_WOW_MAX_EVENT_BM_LEN 4 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_ADD_DEL_EVT_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 is_add; - union { - A_UINT32 event_bitmap; - A_UINT32 event_bitmaps[WMI_WOW_MAX_EVENT_BM_LEN]; - }; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_ADD_DEL_EVT_CMD_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 is_add; + union { + A_UINT32 event_bitmap; + A_UINT32 event_bitmaps[WMI_WOW_MAX_EVENT_BM_LEN]; + }; } WMI_WOW_ADD_DEL_EVT_CMD_fixed_param; /* @@ -8740,84 +9608,120 @@ typedef struct { * AP to the entity in the IP network that sent the UDP packet to this STA. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 enable; /* 1: enable, 0: disable*/ - /* dest_port - - * bits 7:0 contain the LSB of the UDP dest port, - * bits 15:8 contain the MSB of the UDP dest port - */ - A_UINT32 dest_port; - A_UINT32 pattern_len; /* length in byte of pattern[] */ - A_UINT32 response_len; /* length in byte of response[] */ -/* Following this struct are the TLV's: - * A_UINT8 pattern[]; <-- payload of UDP packet to be checked, network byte order - * A_UINT8 response[]; <-- payload of UDP packet to be response, network byte order - */ + /* + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 enable; /* 1: enable, 0: disable */ + /* + * dest_port - + * bits 7:0 contain the LSB of the UDP dest port, + * bits 15:8 contain the MSB of the UDP dest port + */ + A_UINT32 dest_port; + A_UINT32 pattern_len; /* length in byte of pattern[] */ + A_UINT32 response_len; /* length in byte of response[] */ + /* + * Following this struct are the TLV's: + * payload of UDP packet to be checked, network byte order + * A_UINT8 pattern[]; + * payload of UDP packet to be response, network byte order + * A_UINT8 response[]; + */ } WMI_WOW_UDP_SVC_OFLD_CMD_fixed_param; /* - * This structure is used to set the pattern for WOW host wakeup pin pulse pattern confirguration. + * This structure is used to set the pattern for WOW host wakeup pin pulse + * pattern confirguration. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_HOSTWAKEUP_PIN_PATTERN_CONFIG_CMD_fixed_param */ - A_UINT32 enable; /* 1: enable, 0: disable */ - A_UINT32 pin; /* pin for host wakeup */ - A_UINT32 interval_low; /* interval for keeping low voltage, unit: ms */ - A_UINT32 interval_high; /* interval for keeping high voltage, unit: ms */ - A_UINT32 repeat_cnt; /* repeat times for pulse (0xffffffff means forever) */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_WOW_HOSTWAKEUP_PIN_PATTERN_CONFIG_CMD_fixed_param + */ + A_UINT32 tlv_header; + + /* 1: enable, 0: disable */ + A_UINT32 enable; + + /* pin for host wakeup */ + A_UINT32 pin; + + /* interval for keeping low voltage, unit: ms */ + A_UINT32 interval_low; + + /* interval for keeping high voltage, unit: ms */ + A_UINT32 interval_high; + + /* repeat times for pulse (0xffffffff means forever) */ + A_UINT32 repeat_cnt; } WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD_fixed_param; #define MAX_SUPPORTED_ACTION_CATEGORY 256 #define MAX_SUPPORTED_ACTION_CATEGORY_ELE_LIST (MAX_SUPPORTED_ACTION_CATEGORY/32) typedef enum { - WOW_ACTION_WAKEUP_OPERATION_RESET = 0, - WOW_ACTION_WAKEUP_OPERATION_SET, - WOW_ACTION_WAKEUP_OPERATION_ADD_SET, - WOW_ACTION_WAKEUP_OPERATION_DELETE_SET, + WOW_ACTION_WAKEUP_OPERATION_RESET = 0, + WOW_ACTION_WAKEUP_OPERATION_SET, + WOW_ACTION_WAKEUP_OPERATION_ADD_SET, + WOW_ACTION_WAKEUP_OPERATION_DELETE_SET, } WOW_ACTION_WAKEUP_OPERATION; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_WOW_SET_ACTION_WAKE_UP_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 operation; /* 0 reset to fw default, 1 set the bits, 2 add the setting bits, 3 delete the setting bits */ - A_UINT32 action_category_map[MAX_SUPPORTED_ACTION_CATEGORY_ELE_LIST]; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_WOW_SET_ACTION_WAKE_UP_CMD_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* + * 0 reset to fw default, 1 set the bits, 2 add the setting bits, + * 3 delete the setting bits + */ + A_UINT32 operation; + A_UINT32 action_category_map[MAX_SUPPORTED_ACTION_CATEGORY_ELE_LIST]; } WMI_WOW_SET_ACTION_WAKE_UP_CMD_fixed_param; + typedef struct wow_event_info_s { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 flag; /*This is current reserved.*/ - A_INT32 wake_reason; - A_UINT32 data_len; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_EVENT_INFO_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 flag; /*This is current reserved. */ + A_INT32 wake_reason; + A_UINT32 data_len; } WOW_EVENT_INFO_fixed_param; typedef struct wow_initial_wakeup_event_s { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WOW_INITIAL_WAKEUP_EVENT_fixed_param */ - A_UINT32 vdev_id; + /* + * TLV tag and len; tag equals + * WOW_INITIAL_WAKEUP_EVENT_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; } WOW_INITIAL_WAKEUP_EVENT_fixed_param; typedef enum { - WOW_EVENT_INFO_TYPE_PACKET = 0x0001, - WOW_EVENT_INFO_TYPE_BITMAP, - WOW_EVENT_INFO_TYPE_GTKIGTK, + WOW_EVENT_INFO_TYPE_PACKET = 0x0001, + WOW_EVENT_INFO_TYPE_BITMAP, + WOW_EVENT_INFO_TYPE_GTKIGTK, } WOW_EVENT_INFO_TYPE; typedef struct wow_event_info_section_s { - A_UINT32 data_type; - A_UINT32 data_len; + A_UINT32 data_type; + A_UINT32 data_len; } WOW_EVENT_INFO_SECTION; typedef struct wow_event_info_section_packet_s { - A_UINT8 packet[WOW_DEFAULT_EVT_BUF_SIZE]; + A_UINT8 packet[WOW_DEFAULT_EVT_BUF_SIZE]; } WOW_EVENT_INFO_SECTION_PACKET; typedef struct wow_event_info_section_bitmap_s { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_EVENT_INFO_SECTION_BITMAP */ - A_UINT32 flag; /*This is current reserved.*/ - A_UINT32 value; /*This could be the pattern id for bitmap pattern.*/ - A_UINT32 org_len; /*The length of the orginal packet.*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WOW_EVENT_INFO_SECTION_BITMAP */ + A_UINT32 flag; /*This is current reserved. */ + A_UINT32 value; /*This could be the pattern id for bitmap pattern. */ + A_UINT32 org_len; /*The length of the orginal packet. */ } WOW_EVENT_INFO_SECTION_BITMAP; /** @@ -8842,173 +9746,175 @@ typedef struct wow_event_info_section_bitmap_s { * */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_d0_wow_enable_disable_cmd_fixed_param */ - A_UINT32 enable; /* 1 = enable, 0 = disable */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_d0_wow_enable_disable_cmd_fixed_param */ + A_UINT32 enable; /* 1 = enable, 0 = disable */ } wmi_d0_wow_enable_disable_cmd_fixed_param; - typedef enum extend_wow_type_e { - EXTWOW_TYPE_APP_TYPE1, /* extend wow type: only enable wakeup for app type1 */ - EXTWOW_TYPE_APP_TYPE2, /* extend wow type: only enable wakeup for app type2 */ - EXTWOW_TYPE_APP_TYPE1_2, /* extend wow type: enable wakeup for app type1&2 */ - EXTWOW_TYPE_APP_PULSETEST, - EXTWOW_DISABLED = 255, + EXTWOW_TYPE_APP_TYPE1, /* extend wow type: only enable wakeup for app type1 */ + EXTWOW_TYPE_APP_TYPE2, /* extend wow type: only enable wakeup for app type2 */ + EXTWOW_TYPE_APP_TYPE1_2, /* extend wow type: enable wakeup for app type1&2 */ + EXTWOW_TYPE_APP_PULSETEST, + EXTWOW_DISABLED = 255, } EXTWOW_TYPE; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_extwow_enable_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 type; - A_UINT32 wakeup_pin_num; - A_UINT32 swol_pulsetest_type; - A_UINT32 swol_pulsetest_application; + A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_extwow_enable_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 type; + A_UINT32 wakeup_pin_num; + A_UINT32 swol_pulsetest_type; + A_UINT32 swol_pulsetest_application; } wmi_extwow_enable_cmd_fixed_param; #define SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX 8 #define SWOL_INDOOR_KEY_LEN 16 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_extwow_set_app_type1_params_cmd_fixed_param */ - A_UINT32 vdev_id; - wmi_mac_addr wakee_mac; - A_UINT8 ident[8]; - A_UINT8 passwd[16]; - A_UINT32 ident_len; - A_UINT32 passwd_len; + A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_extwow_set_app_type1_params_cmd_fixed_param */ + A_UINT32 vdev_id; + wmi_mac_addr wakee_mac; + A_UINT8 ident[8]; + A_UINT8 passwd[16]; + A_UINT32 ident_len; + A_UINT32 passwd_len; - /* indoor check parameters */ - /* key for mac addresses specified in swol_indoor_key_mac - * Big-endian hosts need to byte-swap the bytes within each 4-byte - * segment of this array, so the bytes will return to their original - * order when the entire WMI message contents are byte-swapped to - * convert from big-endian to little-endian format. - */ - A_UINT8 swol_indoor_key[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX][SWOL_INDOOR_KEY_LEN]; - /* key length for specified mac address index - * Big-endian hosts need to byte-swap the bytes within each 4-byte - * segment of this array, so the bytes will return to their original - * order when the entire WMI message contents are byte-swapped to - * convert from big-endian to little-endian format. - */ - A_UINT8 swol_indoor_key_len[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX]; - /* mac address array allowed to wakeup host*/ - wmi_mac_addr swol_indoor_key_mac[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX]; - /* app mask for the mac addresses specified in swol_indoor_key_mac */ - A_UINT32 swol_indoor_app_mask[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX]; - A_UINT32 swol_indoor_waker_check; /* whether to do indoor waker check */ - A_UINT32 swol_indoor_pw_check; /* whether to check password */ - A_UINT32 swol_indoor_pattern; /* wakeup pattern */ - A_UINT32 swol_indoor_exception; /* wakeup when exception happens */ - A_UINT32 swol_indoor_exception_app; - A_UINT32 swol_assist_enable; /* whether to enable IoT mode */ + /* indoor check parameters */ + /* key for mac addresses specified in swol_indoor_key_mac + * Big-endian hosts need to byte-swap the bytes within each 4-byte + * segment of this array, so the bytes will return to their original + * order when the entire WMI message contents are byte-swapped to + * convert from big-endian to little-endian format. + */ + A_UINT8 swol_indoor_key[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX][SWOL_INDOOR_KEY_LEN]; + /* key length for specified mac address index + * Big-endian hosts need to byte-swap the bytes within each 4-byte + * segment of this array, so the bytes will return to their original + * order when the entire WMI message contents are byte-swapped to + * convert from big-endian to little-endian format. + */ + A_UINT8 swol_indoor_key_len[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX]; + /* mac address array allowed to wakeup host*/ + wmi_mac_addr swol_indoor_key_mac[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX]; + /* app mask for the mac addresses specified in swol_indoor_key_mac */ + A_UINT32 swol_indoor_app_mask[SWOL_INDOOR_MAC_ADDRESS_INDEX_MAX]; + A_UINT32 swol_indoor_waker_check; /* whether to do indoor waker check */ + A_UINT32 swol_indoor_pw_check; /* whether to check password */ + A_UINT32 swol_indoor_pattern; /* wakeup pattern */ + A_UINT32 swol_indoor_exception; /* wakeup when exception happens */ + A_UINT32 swol_indoor_exception_app; + A_UINT32 swol_assist_enable; /* whether to enable IoT mode */ } wmi_extwow_set_app_type1_params_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_extwow_set_app_type2_params_cmd_fixed_param */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_extwow_set_app_type2_params_cmd_fixed_param */ + A_UINT32 vdev_id; - A_UINT8 rc4_key[16]; - A_UINT32 rc4_key_len; + A_UINT8 rc4_key[16]; + A_UINT32 rc4_key_len; - /** ip header parameter */ - A_UINT32 ip_id; /* NC id */ - A_UINT32 ip_device_ip; /* NC IP address */ - A_UINT32 ip_server_ip; /* Push server IP address */ + /** ip header parameter */ + A_UINT32 ip_id; /* NC id */ + A_UINT32 ip_device_ip; /* NC IP address */ + A_UINT32 ip_server_ip; /* Push server IP address */ - /** tcp header parameter */ - A_UINT16 tcp_src_port; /* NC TCP port */ - A_UINT16 tcp_dst_port; /* Push server TCP port */ - A_UINT32 tcp_seq; - A_UINT32 tcp_ack_seq; + /** tcp header parameter */ + A_UINT16 tcp_src_port; /* NC TCP port */ + A_UINT16 tcp_dst_port; /* Push server TCP port */ + A_UINT32 tcp_seq; + A_UINT32 tcp_ack_seq; - A_UINT32 keepalive_init; /* Initial ping interval */ - A_UINT32 keepalive_min; /* Minimum ping interval */ - A_UINT32 keepalive_max; /* Maximum ping interval */ - A_UINT32 keepalive_inc; /* Increment of ping interval */ + A_UINT32 keepalive_init; /* Initial ping interval */ + A_UINT32 keepalive_min; /* Minimum ping interval */ + A_UINT32 keepalive_max; /* Maximum ping interval */ + A_UINT32 keepalive_inc; /* Increment of ping interval */ - wmi_mac_addr gateway_mac; - A_UINT32 tcp_tx_timeout_val; - A_UINT32 tcp_rx_timeout_val; + wmi_mac_addr gateway_mac; + A_UINT32 tcp_tx_timeout_val; + A_UINT32 tcp_rx_timeout_val; - /** add extra parameter for backward-compatible */ - /* - * For all byte arrays, natural order is used. E.g. - * rc4_write_sandbox[0] holds the 1st RC4 S-box byte, - * rc4_write_sandbox[1] holds the 2nd RC4 S-box byte, etc. - */ + /** add extra parameter for backward-compatible */ + /* + * For all byte arrays, natural order is used. E.g. + * rc4_write_sandbox[0] holds the 1st RC4 S-box byte, + * rc4_write_sandbox[1] holds the 2nd RC4 S-box byte, etc. + */ - /* used to encrypt transmit packet such as keep-alive */ - A_UINT8 rc4_write_sandbox[256]; - A_UINT32 rc4_write_x; - A_UINT32 rc4_write_y; + /* used to encrypt transmit packet such as keep-alive */ + A_UINT8 rc4_write_sandbox[256]; + A_UINT32 rc4_write_x; + A_UINT32 rc4_write_y; - /* used to decrypt received packet such as wow data */ - A_UINT8 rc4_read_sandbox[256]; - A_UINT32 rc4_read_x; - A_UINT32 rc4_read_y; + /* used to decrypt received packet such as wow data */ + A_UINT8 rc4_read_sandbox[256]; + A_UINT32 rc4_read_x; + A_UINT32 rc4_read_y; - /* used to caculate HMAC hash for transmit packet such as keep-alive */ - A_UINT8 ssl_write_seq[8]; - A_UINT8 ssl_sha1_write_key[64]; - A_UINT32 ssl_sha1_write_key_len; + /* used to caculate HMAC hash for transmit packet such as keep-alive */ + A_UINT8 ssl_write_seq[8]; + A_UINT8 ssl_sha1_write_key[64]; + A_UINT32 ssl_sha1_write_key_len; - /* used to calculate HAMC hash for receive packet such as wow data */ - A_UINT8 ssl_read_seq[8]; - A_UINT8 ssl_sha1_read_key[64]; - A_UINT32 ssl_sha1_read_key_len; + /* used to calculate HAMC hash for receive packet such as wow data */ + A_UINT8 ssl_read_seq[8]; + A_UINT8 ssl_sha1_read_key[64]; + A_UINT32 ssl_sha1_read_key_len; - /* optional element for specifying TCP options data to include in - * transmit packets such as keep-alive - */ - A_UINT32 tcp_options_len; - A_UINT8 tcp_options[40]; + /* optional element for specifying TCP options data to include in + * transmit packets such as keep-alive + */ + A_UINT32 tcp_options_len; + A_UINT8 tcp_options[40]; - A_UINT32 async_id; /* keep-alive request id */ + A_UINT32 async_id; /* keep-alive request id */ } wmi_extwow_set_app_type2_params_cmd_fixed_param; - -#define WMI_RXERR_CRC 0x01 /* CRC error on frame */ -#define WMI_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ -#define WMI_RXERR_MIC 0x10 /* Michael MIC decrypt error */ -#define WMI_RXERR_KEY_CACHE_MISS 0x20 /* No/incorrect key matter in h/w */ +#define WMI_RXERR_CRC 0x01 /* CRC error on frame */ +#define WMI_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ +#define WMI_RXERR_MIC 0x10 /* Michael MIC decrypt error */ +#define WMI_RXERR_KEY_CACHE_MISS 0x20 /* No/incorrect key matter in h/w */ typedef enum { - PKT_PWR_SAVE_PAID_MATCH = 0x0001, - PKT_PWR_SAVE_GID_MATCH = 0x0002, - PKT_PWR_SAVE_EARLY_TIM_CLEAR = 0x0004, - PKT_PWR_SAVE_EARLY_DTIM_CLEAR = 0x0008, - PKT_PWR_SAVE_EOF_PAD_DELIM = 0x0010, - PKT_PWR_SAVE_MACADDR_MISMATCH = 0x0020, - PKT_PWR_SAVE_DELIM_CRC_FAIL = 0x0040, - PKT_PWR_SAVE_GID_NSTS_ZERO = 0x0080, - PKT_PWR_SAVE_RSSI_CHECK = 0x0100, - PKT_PWR_SAVE_5G_EBT = 0x0200, - PKT_PWR_SAVE_2G_EBT = 0x0400, - WMI_PKT_PWR_SAVE_MAX = 0x0800, + PKT_PWR_SAVE_PAID_MATCH = 0x0001, + PKT_PWR_SAVE_GID_MATCH = 0x0002, + PKT_PWR_SAVE_EARLY_TIM_CLEAR = 0x0004, + PKT_PWR_SAVE_EARLY_DTIM_CLEAR = 0x0008, + PKT_PWR_SAVE_EOF_PAD_DELIM = 0x0010, + PKT_PWR_SAVE_MACADDR_MISMATCH = 0x0020, + PKT_PWR_SAVE_DELIM_CRC_FAIL = 0x0040, + PKT_PWR_SAVE_GID_NSTS_ZERO = 0x0080, + PKT_PWR_SAVE_RSSI_CHECK = 0x0100, + PKT_PWR_SAVE_5G_EBT = 0x0200, + PKT_PWR_SAVE_2G_EBT = 0x0400, + WMI_PKT_PWR_SAVE_MAX = 0x0800, } WMI_PKT_PWR_SAVE_TYPE; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ftm_intg_cmd_fixed_param */ - A_UINT32 num_data; /** length in byte of data[]. */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; -/* This structure is used to send Factory Test Mode [FTM] command - * from host to firmware for integrated chips which are binary blobs. - * Following this structure is the TLV: - * A_UINT8 data[]; <-- length in byte given by field num_data. - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ftm_intg_cmd_fixed_param */ + A_UINT32 num_data; + /** length in byte of data[]. */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* This structure is used to send Factory Test Mode [FTM] command + * from host to firmware for integrated chips which are binary blobs. + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field num_data. + */ } wmi_ftm_intg_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ftm_intg_event_fixed_param */ - A_UINT32 num_data; /** length in byte of data[]. */ -/* This structure is used to receive Factory Test Mode [FTM] event - * from firmware to host for integrated chips which are binary blobs. - * Following this structure is the TLV: - * A_UINT8 data[]; <-- length in byte given by field num_data. - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ftm_intg_event_fixed_param */ + A_UINT32 num_data; + /** length in byte of data[]. */ + /* This structure is used to receive Factory Test Mode [FTM] event + * from firmware to host for integrated chips which are binary blobs. + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field num_data. + */ } wmi_ftm_intg_event_fixed_param; #define WMI_MAX_NS_OFFLOADS 2 @@ -9019,121 +9925,120 @@ typedef struct { #define WMI_ARPOFF_FLAGS_REMOTE_IP_VALID (1 << 2) /* remote IP field is valid */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_ARP_OFFLOAD_TUPLE */ - A_UINT32 flags; /* flags */ - A_UINT8 target_ipaddr[4]; /* IPV4 addresses of the local node*/ - A_UINT8 remote_ipaddr[4]; /* source address of the remote node requesting the ARP (qualifier) */ - wmi_mac_addr target_mac; /* mac address for this tuple, if not valid, the local MAC is used */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_ARP_OFFLOAD_TUPLE */ + A_UINT32 flags; /* flags */ + A_UINT8 target_ipaddr[4]; /* IPV4 addresses of the local node */ + A_UINT8 remote_ipaddr[4]; /* source address of the remote node requesting the ARP (qualifier) */ + wmi_mac_addr target_mac; /* mac address for this tuple, if not valid, the local MAC is used */ } WMI_ARP_OFFLOAD_TUPLE; -#define WMI_NSOFF_FLAGS_VALID (1 << 0) /* the tuple entry is valid */ -#define WMI_NSOFF_FLAGS_MAC_VALID (1 << 1) /* the target mac address is valid */ -#define WMI_NSOFF_FLAGS_REMOTE_IP_VALID (1 << 2) /* remote IP field is valid */ -#define WMI_NSOFF_FLAGS_IS_IPV6_ANYCAST (1 << 3) /* whether the configured IPv6 address is anycast */ +#define WMI_NSOFF_FLAGS_VALID (1 << 0) /* the tuple entry is valid */ +#define WMI_NSOFF_FLAGS_MAC_VALID (1 << 1) /* the target mac address is valid */ +#define WMI_NSOFF_FLAGS_REMOTE_IP_VALID (1 << 2) /* remote IP field is valid */ +/* whether the configured IPv6 address is anycast */ +#define WMI_NSOFF_FLAGS_IS_IPV6_ANYCAST (1 << 3) #define WMI_NSOFF_MAX_TARGET_IPS 2 typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_NS_OFFLOAD_TUPLE */ - A_UINT32 flags; /* flags */ - /* NOTE: This size of array target_ipaddr[] cannot be changed without breaking WMI compatibility. */ - WMI_IPV6_ADDR target_ipaddr[WMI_NSOFF_MAX_TARGET_IPS]; /* IPV6 target addresses of the local node */ - WMI_IPV6_ADDR solicitation_ipaddr; /* multi-cast source IP addresses for receiving solicitations */ - WMI_IPV6_ADDR remote_ipaddr; /* address of remote node requesting the solicitation (qualifier) */ - wmi_mac_addr target_mac; /* mac address for this tuple, if not valid, the local MAC is used */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_NS_OFFLOAD_TUPLE */ + A_UINT32 flags; /* flags */ + /* NOTE: This size of array target_ipaddr[] cannot be changed without breaking WMI compatibility. */ + WMI_IPV6_ADDR target_ipaddr[WMI_NSOFF_MAX_TARGET_IPS]; /* IPV6 target addresses of the local node */ + WMI_IPV6_ADDR solicitation_ipaddr; /* multi-cast source IP addresses for receiving solicitations */ + WMI_IPV6_ADDR remote_ipaddr; /* address of remote node requesting the solicitation (qualifier) */ + wmi_mac_addr target_mac; /* mac address for this tuple, if not valid, the local MAC is used */ } WMI_NS_OFFLOAD_TUPLE; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param */ - A_UINT32 flags; - A_UINT32 vdev_id; - A_UINT32 num_ns_ext_tuples; -/* Following this structure are the TLVs: - * WMI_NS_OFFLOAD_TUPLE ns_tuples[WMI_MAX_NS_OFFLOADS]; - * WMI_ARP_OFFLOAD_TUPLE arp_tuples[WMI_MAX_ARP_OFFLOADS]; - * WMI_NS_OFFLOAD_TUPLE ns_ext_tuples[]; <-- size based on num_ns_ext_tuples - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param */ + A_UINT32 flags; + A_UINT32 vdev_id; + A_UINT32 num_ns_ext_tuples; + /* Following this structure are the TLVs: + * WMI_NS_OFFLOAD_TUPLE ns_tuples[WMI_MAX_NS_OFFLOADS]; + * WMI_ARP_OFFLOAD_TUPLE arp_tuples[WMI_MAX_ARP_OFFLOADS]; + * size of ns_ext_tuples is based on num_ns_ext_tuples + * WMI_NS_OFFLOAD_TUPLE ns_ext_tuples[]; + */ } WMI_SET_ARP_NS_OFFLOAD_CMD_fixed_param; - typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 pattern_id; - A_UINT32 timeout; - A_UINT32 length; - /*Following this would be the pattern - A_UINT8 pattern[] of length specifed by length - field in the structure.*/ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 pattern_id; + A_UINT32 timeout; + A_UINT32 length; + /* Following this would be the pattern + A_UINT8 pattern[] of length specifed by length + field in the structure. */ } WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param; - typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 pattern_id; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 pattern_id; } WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_addba_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** Initiator (1) or Responder (0) for this aggregation */ - A_UINT32 initiator; - /** size of the negotiated window */ - A_UINT32 window_size; - /** starting sequence number (only valid for initiator) */ - A_UINT32 ssn; - /** timeout field represents the time to wait for Block Ack in - * initiator case and the time to wait for BAR in responder - * case. 0 represents no timeout. */ - A_UINT32 timeout; - /* BA policy: immediate ACK (0) or delayed ACK (1) */ - A_UINT32 policy; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_addba_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** Initiator (1) or Responder (0) for this aggregation */ + A_UINT32 initiator; + /** size of the negotiated window */ + A_UINT32 window_size; + /** starting sequence number (only valid for initiator) */ + A_UINT32 ssn; + /** timeout field represents the time to wait for Block Ack in + * initiator case and the time to wait for BAR in responder + * case. 0 represents no timeout. */ + A_UINT32 timeout; + /* BA policy: immediate ACK (0) or delayed ACK (1) */ + A_UINT32 policy; } wmi_peer_tid_addba_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_delba_cmd */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** Initiator (1) or Responder (0) for this aggregation */ - A_UINT32 initiator; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_delba_cmd */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** Initiator (1) or Responder (0) for this aggregation */ + A_UINT32 initiator; } wmi_peer_tid_delba_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_addba_complete_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** Event status */ - A_UINT32 status; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_addba_complete_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** Event status */ + A_UINT32 status; } wmi_tx_addba_complete_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_delba_complete_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** Tid number */ - A_UINT32 tid; - /** Event status */ - A_UINT32 status; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_delba_complete_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** Tid number */ + A_UINT32 tid; + /** Event status */ + A_UINT32 status; } wmi_tx_delba_complete_event_fixed_param; - - - /* * Structure to request sequence numbers for a given * peer station on different TIDs. The TIDs are @@ -9144,21 +10049,20 @@ typedef struct { * numbers for the peer on all the TIDs requested * and send back a response in a WMI event. */ -typedef struct -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals - WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_sub_struct_param */ - wmi_mac_addr peer_macaddr; - A_UINT32 tidBitmap; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals + WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_sub_struct_param */ + wmi_mac_addr peer_macaddr; + A_UINT32 tidBitmap; } wmi_ba_req_ssn; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals - WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** Number of requested SSN In the TLV wmi_ba_req_ssn[] */ - A_UINT32 num_ba_req_ssn; + A_UINT32 tlv_header; /* TLV tag and len; tag equals + WMITLV_TAG_STRUC_wmi_ba_req_ssn_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** Number of requested SSN In the TLV wmi_ba_req_ssn[] */ + A_UINT32 num_ba_req_ssn; /* Following this struc are the TLV's: * wmi_ba_req_ssn ba_req_ssn_list; All peer and tidBitMap for which the ssn is requested */ @@ -9176,38 +10080,35 @@ typedef struct { * Structure to send response sequence numbers * for a give peer and tidmap. */ -typedef struct -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals - WMITLV_TAG_STRUC_wmi_ba_req_ssn_event_sub_struct_param */ - wmi_mac_addr peer_macaddr; - /* A boolean to indicate if ssn is present */ - A_UINT32 ssn_present_for_tid[WMI_MAX_TC]; - /* The ssn from target, valid only if - * ssn_present_for_tid[tidn] equals 1 - */ - A_UINT32 ssn_for_tid[WMI_MAX_TC]; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals + WMITLV_TAG_STRUC_wmi_ba_req_ssn_event_sub_struct_param */ + wmi_mac_addr peer_macaddr; + /* A bool to indicate if ssn is present */ + A_UINT32 ssn_present_for_tid[WMI_MAX_TC]; + /* The ssn from target, valid only if + * ssn_present_for_tid[tidn] equals 1 + */ + A_UINT32 ssn_for_tid[WMI_MAX_TC]; } wmi_ba_event_ssn; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals - WMITLV_TAG_STRUC_wmi_ba_rsp_ssn_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** Event status, success or failure of the overall operation */ - A_UINT32 status; - /** Number of requested SSN In the TLV wmi_ba_req_ssn[] */ - A_UINT32 num_ba_event_ssn; + A_UINT32 tlv_header; /* TLV tag and len; tag equals + WMITLV_TAG_STRUC_wmi_ba_rsp_ssn_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** Event status, success or failure of the overall operation */ + A_UINT32 status; + /** Number of requested SSN In the TLV wmi_ba_req_ssn[] */ + A_UINT32 num_ba_event_ssn; /* Following this struc are the TLV's: * wmi_ba_event_ssn ba_event_ssn_list; All peer and tidBitMap for which the ssn is requested */ } wmi_ba_rsp_ssn_event_fixed_param; - enum wmi_aggr_state_req_type { - - WMI_DISABLE_AGGREGATION, - WMI_ENABLE_AGGREGATION + WMI_DISABLE_AGGREGATION, + WMI_ENABLE_AGGREGATION }; /* @@ -9215,59 +10116,58 @@ enum wmi_aggr_state_req_type { * when esco call is begins the coex module in fw genrated this event to host to * disable the RX aggregation and after completion of the esco call fw will indicate to * enable back the Rx aggregation . -*/ + */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_aggr_state_trig_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** req_type contains values from enum - * wmi_aggr_state_req_type; 0 (disable) 1(enable) */ - A_UINT32 req_type; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_aggr_state_trig_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** req_type contains values from enum + * wmi_aggr_state_req_type; 0 (disable) 1(enable) */ + A_UINT32 req_type; } wmi_aggr_state_trig_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** MAC address used for installing */ - wmi_mac_addr peer_macaddr; - /** key index */ - A_UINT32 key_ix; - /** key flags */ - A_UINT32 key_flags; - /** Event status */ - A_UINT32 status; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** MAC address used for installing */ + wmi_mac_addr peer_macaddr; + /** key index */ + A_UINT32 key_ix; + /** key flags */ + A_UINT32 key_flags; + /** Event status */ + A_UINT32 status; } wmi_vdev_install_key_complete_event_fixed_param; typedef enum _WMI_NLO_AUTH_ALGORITHM { - WMI_NLO_AUTH_ALGO_80211_OPEN = 1, - WMI_NLO_AUTH_ALGO_80211_SHARED_KEY = 2, - WMI_NLO_AUTH_ALGO_WPA = 3, - WMI_NLO_AUTH_ALGO_WPA_PSK = 4, - WMI_NLO_AUTH_ALGO_WPA_NONE = 5, - WMI_NLO_AUTH_ALGO_RSNA = 6, - WMI_NLO_AUTH_ALGO_RSNA_PSK = 7, + WMI_NLO_AUTH_ALGO_80211_OPEN = 1, + WMI_NLO_AUTH_ALGO_80211_SHARED_KEY = 2, + WMI_NLO_AUTH_ALGO_WPA = 3, + WMI_NLO_AUTH_ALGO_WPA_PSK = 4, + WMI_NLO_AUTH_ALGO_WPA_NONE = 5, + WMI_NLO_AUTH_ALGO_RSNA = 6, + WMI_NLO_AUTH_ALGO_RSNA_PSK = 7, } WMI_NLO_AUTH_ALGORITHM; typedef enum _WMI_NLO_CIPHER_ALGORITHM { - WMI_NLO_CIPHER_ALGO_NONE = 0x00, - WMI_NLO_CIPHER_ALGO_WEP40 = 0x01, - WMI_NLO_CIPHER_ALGO_TKIP = 0x02, - WMI_NLO_CIPHER_ALGO_CCMP = 0x04, - WMI_NLO_CIPHER_ALGO_WEP104 = 0x05, - WMI_NLO_CIPHER_ALGO_BIP = 0x06, - WMI_NLO_CIPHER_ALGO_WPA_USE_GROUP = 0x100, - WMI_NLO_CIPHER_ALGO_RSN_USE_GROUP = 0x100, - WMI_NLO_CIPHER_ALGO_WEP = 0x101, + WMI_NLO_CIPHER_ALGO_NONE = 0x00, + WMI_NLO_CIPHER_ALGO_WEP40 = 0x01, + WMI_NLO_CIPHER_ALGO_TKIP = 0x02, + WMI_NLO_CIPHER_ALGO_CCMP = 0x04, + WMI_NLO_CIPHER_ALGO_WEP104 = 0x05, + WMI_NLO_CIPHER_ALGO_BIP = 0x06, + WMI_NLO_CIPHER_ALGO_WPA_USE_GROUP = 0x100, + WMI_NLO_CIPHER_ALGO_RSN_USE_GROUP = 0x100, + WMI_NLO_CIPHER_ALGO_WEP = 0x101, } WMI_NLO_CIPHER_ALGORITHM; /* SSID broadcast type passed in NLO params */ -typedef enum _WMI_NLO_SSID_BcastNwType -{ - WMI_NLO_BCAST_UNKNOWN = 0, - WMI_NLO_BCAST_NORMAL = 1, - WMI_NLO_BCAST_HIDDEN = 2, +typedef enum _WMI_NLO_SSID_BcastNwType { + WMI_NLO_BCAST_UNKNOWN = 0, + WMI_NLO_BCAST_NORMAL = 1, + WMI_NLO_BCAST_HIDDEN = 2, } WMI_NLO_SSID_BcastNwType; #define WMI_NLO_MAX_SSIDS 16 @@ -9279,8 +10179,8 @@ typedef enum _WMI_NLO_SSID_BcastNwType #define WMI_NLO_CONFIG_SLOW_SCAN (0x1 << 4) #define WMI_NLO_CONFIG_FAST_SCAN (0x1 << 5) #define WMI_NLO_CONFIG_SSID_HIDE_EN (0x1 << 6) - -/* This bit is used to indicate if EPNO Profile is enabled */ +/* This bit is used to indicate if EPNO or supplicant PNO is enabled. Only + * one of them can be enabled at a given time */ #define WMI_NLO_CONFIG_ENLO (0x1 << 7) #define WMI_NLO_CONFIG_SCAN_PASSIVE (0x1 << 8) #define WMI_NLO_CONFIG_ENLO_RESET (0x1 << 9) @@ -9293,9 +10193,7 @@ typedef enum _WMI_NLO_SSID_BcastNwType #define WMI_ENLO_FLAG_G_BAND 4 /* Whether strict matching is required (i.e. firmware shall not match on the entire SSID) */ #define WMI_ENLO_FLAG_STRICT_MATCH 8 - -/* Code for matching the beacon AUTH IE - additional codes TBD */ -/* open */ +/* Code for matching the beacon AUTH IE - additional codes TBD open */ #define WMI_ENLO_AUTH_CODE_OPEN 1 /* WPA_PSK or WPA2PSK */ #define WMI_ENLO_AUTH_CODE_PSK 2 @@ -9303,149 +10201,152 @@ typedef enum _WMI_NLO_SSID_BcastNwType #define WMI_ENLO_AUTH_CODE_EAPOL 4 /* NOTE: wmi_nlo_ssid_param structure can't be changed without breaking the compatibility */ -typedef struct wmi_nlo_ssid_param -{ - A_UINT32 valid; - wmi_ssid ssid; +typedef struct wmi_nlo_ssid_param { + A_UINT32 valid; + wmi_ssid ssid; } wmi_nlo_ssid_param; /* NOTE: wmi_nlo_enc_param structure can't be changed without breaking the compatibility */ -typedef struct wmi_nlo_enc_param -{ - A_UINT32 valid; - A_UINT32 enc_type; +typedef struct wmi_nlo_enc_param { + A_UINT32 valid; + A_UINT32 enc_type; } wmi_nlo_enc_param; /* NOTE: wmi_nlo_auth_param structure can't be changed without breaking the compatibility */ -typedef struct wmi_nlo_auth_param -{ - A_UINT32 valid; - A_UINT32 auth_type; +typedef struct wmi_nlo_auth_param { + A_UINT32 valid; + A_UINT32 auth_type; } wmi_nlo_auth_param; /* NOTE: wmi_nlo_bcast_nw_param structure can't be changed without breaking the compatibility */ -typedef struct wmi_nlo_bcast_nw_param -{ - A_UINT32 valid; -/* If WMI_NLO_CONFIG_EPNO is not set. Supplicant PNO is enabled. The value should be true/false -Otherwise EPNO is enabled. bcast_nw_type would be used as a bit flag contains WMI_ENLO_FLAG_XXX */ - A_UINT32 bcast_nw_type; +typedef struct wmi_nlo_bcast_nw_param { + A_UINT32 valid; + /** + * If WMI_NLO_CONFIG_EPNO is not set. Supplicant PNO is enabled. The value + * should be true/false.Otherwise EPNO is enabled. bcast_nw_type would be used + * as a bit flag contains WMI_ENLO_FLAG_XXX + */ + A_UINT32 bcast_nw_type; } wmi_nlo_bcast_nw_param; /* NOTE: wmi_nlo_rssi_param structure can't be changed without breaking the compatibility */ -typedef struct wmi_nlo_rssi_param -{ - A_UINT32 valid; - A_INT32 rssi; +typedef struct wmi_nlo_rssi_param { + A_UINT32 valid; + A_INT32 rssi; } wmi_nlo_rssi_param; typedef struct nlo_configured_parameters { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_nlo_configured_parameters */ - wmi_nlo_ssid_param ssid; - wmi_nlo_enc_param enc_type; - wmi_nlo_auth_param auth_type; - wmi_nlo_rssi_param rssi_cond; - wmi_nlo_bcast_nw_param bcast_nw_type; /* indicates if the SSID is hidden or not */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_nlo_configured_parameters */ + wmi_nlo_ssid_param ssid; + wmi_nlo_enc_param enc_type; + wmi_nlo_auth_param auth_type; + wmi_nlo_rssi_param rssi_cond; + wmi_nlo_bcast_nw_param bcast_nw_type; /* indicates if the SSID is hidden or not */ } nlo_configured_parameters; - /* Support channel prediction for PNO scan after scanning top_k_num channels * if stationary_threshold is met. */ typedef struct nlo_channel_prediction_cfg { - A_UINT32 tlv_header; - /* Enable or disable this feature. */ - A_UINT32 enable; - /* Top K channels will be scanned before deciding whether to further scan - * or stop. Minimum value is 3 and maximum is 5. */ - A_UINT32 top_k_num; - /* Preconfigured stationary threshold. - * Lesser value means more conservative. Bigger value means more aggressive. - * Maximum is 100 and mininum is 0. */ - A_UINT32 stationary_threshold; - /* Periodic full channel scan in milliseconds unit. - * After full_scan_period_ms since last full scan, channel prediction - * scan is suppressed and will do full scan. - * This is to help detecting sudden AP power-on or -off. Value 0 means no - * full scan at all (not recommended). - */ - A_UINT32 full_scan_period_ms; + A_UINT32 tlv_header; + /* Enable or disable this feature. */ + A_UINT32 enable; + /* Top K channels will be scanned before deciding whether to further + * scan or stop. Minimum value is 3 and maximum is 5. */ + A_UINT32 top_k_num; + /* Preconfigured stationary threshold. Lesser value means more + * conservative. Bigger value means more aggressive. + * Maximum is 100 and mininum is 0. */ + A_UINT32 stationary_threshold; + /* Periodic full channel scan in milliseconds unit. + * After full_scan_period_ms since last full scan, channel prediction + * scan is suppressed and will do full scan. + * This is to help detecting sudden AP power-on or -off. + * Value 0 means no full scan at all (not recommended). + */ + A_UINT32 full_scan_period_ms; } nlo_channel_prediction_cfg; typedef struct enlo_candidate_score_params_t { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_enlo_candidate_score_param */ - A_INT32 min5GHz_rssi; /* minimum 5GHz RSSI for a BSSID to be considered (units = dBm) */ - A_INT32 min24GHz_rssi; /* minimum 2.4GHz RSSI for a BSSID to be considered (units = dBm) */ - A_UINT32 initial_score_max; /* the maximum score that a network can have before bonuses */ - /* current_connection_bonus: - * only report when there is a network's score this much higher - * than the current connection - */ - A_UINT32 current_connection_bonus; - A_UINT32 same_network_bonus; /* score bonus for all networks with the same network flag */ - A_UINT32 secure_bonus; /* score bonus for networks that are not open */ - A_UINT32 band5GHz_bonus; /* 5GHz RSSI score bonus (applied to all 5GHz networks) */ + /* + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_enlo_candidate_score_param + */ + A_UINT32 tlv_header; + /* minimum 5GHz RSSI for a BSSID to be considered (units = dBm) */ + A_INT32 min5GHz_rssi; + /* minimum 2.4GHz RSSI for a BSSID to be considered (units = dBm) */ + A_INT32 min24GHz_rssi; + /* the maximum score that a network can have before bonuses */ + A_UINT32 initial_score_max; + /* current_connection_bonus: + * only report when there is a network's score this much higher + * than the current connection + */ + A_UINT32 current_connection_bonus; + /* score bonus for all networks with the same network flag */ + A_UINT32 same_network_bonus; + /* score bonus for networks that are not open */ + A_UINT32 secure_bonus; + /* 5GHz RSSI score bonus (applied to all 5GHz networks) */ + A_UINT32 band5GHz_bonus; } enlo_candidate_score_params; typedef struct wmi_nlo_config { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param */ - A_UINT32 flags; - A_UINT32 vdev_id; - A_UINT32 fast_scan_max_cycles; - A_UINT32 active_dwell_time; - A_UINT32 passive_dwell_time; /* PDT in msecs */ - A_UINT32 probe_bundle_size; - A_UINT32 rest_time; /* ART = IRT */ - A_UINT32 max_rest_time; /* Max value that can be reached after SBM */ - A_UINT32 scan_backoff_multiplier; /* SBM */ - A_UINT32 fast_scan_period; /* SCBM */ - A_UINT32 slow_scan_period; /* specific to windows */ - A_UINT32 no_of_ssids; - A_UINT32 num_of_channels; - A_UINT32 delay_start_time; /* NLO scan start delay time in milliseconds */ -/* The TLVs will follow. - * nlo_configured_parameters nlo_list[]; - * A_UINT32 channel_list[]; - * nlo_channel_prediction_cfg ch_prediction_cfg; - * enlo_candidate_score_params candidate_score_params; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param */ + A_UINT32 flags; + A_UINT32 vdev_id; + A_UINT32 fast_scan_max_cycles; + A_UINT32 active_dwell_time; + A_UINT32 passive_dwell_time; /* PDT in msecs */ + A_UINT32 probe_bundle_size; + A_UINT32 rest_time; /* ART = IRT */ + A_UINT32 max_rest_time; /* Max value that can be reached after SBM */ + A_UINT32 scan_backoff_multiplier; /* SBM */ + A_UINT32 fast_scan_period; /* SCBM */ + A_UINT32 slow_scan_period; /* specific to windows */ + A_UINT32 no_of_ssids; + A_UINT32 num_of_channels; + A_UINT32 delay_start_time; /* NLO scan start delay time in milliseconds */ + /* The TLVs will follow. + * nlo_configured_parameters nlo_list[]; + * A_UINT32 channel_list[]; + * nlo_channel_prediction_cfg ch_prediction_cfg; + * enlo_candidate_score_params candidate_score_params; + */ + } wmi_nlo_config_cmd_fixed_param; -typedef struct wmi_nlo_event -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nlo_event */ - A_UINT32 vdev_id; +typedef struct wmi_nlo_event { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nlo_event */ + A_UINT32 vdev_id; } wmi_nlo_event; - /* WMI_PASSPOINT_CONFIG_SET * Sets a list for passpoint networks for PNO purposes; * it should be matched against any passpoint networks found * during regular PNO scan. */ -#define WMI_PASSPOINT_CONFIG_SET (0x1 << 0) +#define WMI_PASSPOINT_CONFIG_SET (0x1 << 0) /* WMI_PASSPOINT_CONFIG_RESET * Reset passpoint network list - * no Passpoint networks should be matched after this. */ #define WMI_PASSPOINT_CONFIG_RESET (0x1 << 1) - #define PASSPOINT_REALM_LEN 256 #define PASSPOINT_ROAMING_CONSORTIUM_ID_LEN 5 #define PASSPOINT_ROAMING_CONSORTIUM_ID_NUM 16 #define PASSPOINT_PLMN_ID_LEN 3 #define PASSPOINT_PLMN_ID_ALLOC_LEN /* round up to A_UINT32 boundary */ \ - (((PASSPOINT_PLMN_ID_LEN + 3) >> 2) << 2) + (((PASSPOINT_PLMN_ID_LEN + 3) >> 2) << 2) /* * Confirm PASSPOINT_REALM_LEN is a multiple of 4, so the - * A_UINT8 realm[PASSPOINT_REALM_LEN] + * A_UINT8 realm[PASSPOINT_REALM_LEN] * array will end on a 4-byte boundary. * (This 4-byte alignment simplifies endianness-correction byte swapping.) */ -A_COMPILE_TIME_ASSERT( - check_passpoint_realm_size, - (PASSPOINT_REALM_LEN % sizeof(A_UINT32)) == 0); +A_COMPILE_TIME_ASSERT(check_passpoint_realm_size, (PASSPOINT_REALM_LEN % sizeof(A_UINT32)) == 0); /* * Confirm the product of PASSPOINT_ROAMING_CONSORTIUM_ID_NUM and @@ -9453,87 +10354,93 @@ A_COMPILE_TIME_ASSERT( * roaming_consortium_ids array below will end on a 4-byte boundary. * (This 4-byte alignment simplifies endianness-correction byte swapping.) */ -A_COMPILE_TIME_ASSERT( - check_passpoint_roaming_consortium_ids_size, - ((PASSPOINT_ROAMING_CONSORTIUM_ID_NUM*PASSPOINT_ROAMING_CONSORTIUM_ID_LEN) % sizeof(A_UINT32)) == 0); +A_COMPILE_TIME_ASSERT(check_passpoint_roaming_consortium_ids_size, +((PASSPOINT_ROAMING_CONSORTIUM_ID_NUM*PASSPOINT_ROAMING_CONSORTIUM_ID_LEN) % sizeof(A_UINT32)) == 0); /* wildcard ID to allow an action (reset) to apply to all networks */ #define WMI_PASSPOINT_NETWORK_ID_WILDCARD 0xFFFFFFFF typedef struct wmi_passpoint_config { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_passpoint_config_cmd_fixed_param */ - /* (network) id - * identifier of the matched network, report this in event - * This id can be a wildcard (WMI_PASSPOINT_NETWORK_ID_WILDCARD) - * that indicates the action should be applied to all networks. - * Currently, the only action that is applied to all networks is "reset". - * If a non-wildcard ID is specified, that particular network is configured. - * If a wildcard ID is specified, all networks are reset. - */ - A_UINT32 id; - A_UINT32 req_id; - A_UINT8 realm[PASSPOINT_REALM_LEN]; /*null terminated UTF8 encoded realm, 0 if unspecified*/ - A_UINT8 roaming_consortium_ids[PASSPOINT_ROAMING_CONSORTIUM_ID_NUM][PASSPOINT_ROAMING_CONSORTIUM_ID_LEN]; /*roaming consortium ids to match, 0s if unspecified*/ - /*This would be bytes-stream as same as defition of realm id in 802.11 standard*/ - A_UINT8 plmn[PASSPOINT_PLMN_ID_ALLOC_LEN]; /*PLMN id mcc/mnc combination as per rules, 0s if unspecified */ + /* TLV tag and len; tag equals wmi_passpoint_config_cmd_fixed_param */ + A_UINT32 tlv_header; + /* (network) id + * identifier of the matched network, report this in event + * This id can be a wildcard (WMI_PASSPOINT_NETWORK_ID_WILDCARD) + * that indicates the action should be applied to all networks. + * Currently, the only action that is applied to all networks is "reset". + * If a non-wildcard ID is specified, that particular network is configured. + * If a wildcard ID is specified, all networks are reset. + */ + A_UINT32 id; + A_UINT32 req_id; + /*null terminated UTF8 encoded realm, 0 if unspecified*/ + A_UINT8 realm[PASSPOINT_REALM_LEN]; + /*roaming consortium ids to match, 0s if unspecified*/ + A_UINT8 roaming_consortium_ids[PASSPOINT_ROAMING_CONSORTIUM_ID_NUM][PASSPOINT_ROAMING_CONSORTIUM_ID_LEN]; + /*This would be bytes-stream as same as defition of realm id in 802.11 standard*/ + /*PLMN id mcc/mnc combination as per rules, 0s if unspecified */ + A_UINT8 plmn[PASSPOINT_PLMN_ID_ALLOC_LEN]; } wmi_passpoint_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_passpoint_event_hdr */ - A_UINT32 id; /* identifier of the matched network */ - A_UINT32 vdev_id; - A_UINT32 timestamp; /* time since boot (in microsecond) when the result was retrieved*/ - wmi_ssid ssid; - wmi_mac_addr bssid; /* bssid of the network */ - A_UINT32 channel_mhz; /* channel frequency in MHz */ - A_UINT32 rssi; /* rssi value */ - A_UINT32 rtt; /* timestamp in nanoseconds*/ - A_UINT32 rtt_sd; /* standard deviation in rtt */ - A_UINT32 beacon_period; /* beacon advertised in the beacon */ - A_UINT32 capability; /* capabilities advertised in the beacon */ - A_UINT32 ie_length; /* size of the ie_data blob */ - A_UINT32 anqp_length; /* length of ANQP blob */ -/* Following this structure is the byte stream of ie data of length ie_buf_len: - * A_UINT8 ie_data[]; <-- length in byte given by field ie_length, blob of ie data in beacon - * A_UINT8 anqp_ie[]; <-- length in byte given by field anqp_len, blob of anqp data of IE - * Implicitly, combing ie_data and anqp_ie into a single bufp, and the bytes stream of each ie should be same as BEACON/Action-frm by 802.11 spec. - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals +wmi_passpoint_event_hdr */ + A_UINT32 id; /* identifier of the matched network */ + A_UINT32 vdev_id; + A_UINT32 timestamp; /* time since boot (in microsecond) when the +result was retrieved*/ + wmi_ssid ssid; + wmi_mac_addr bssid; /* bssid of the network */ + A_UINT32 channel_mhz; /* channel frequency in MHz */ + A_UINT32 rssi; /* rssi value */ + A_UINT32 rtt; /* timestamp in nanoseconds*/ + A_UINT32 rtt_sd; /* standard deviation in rtt */ + A_UINT32 beacon_period; /* beacon advertised in the beacon */ + A_UINT32 capability; /* capabilities advertised in the beacon */ + A_UINT32 ie_length; /* size of the ie_data blob */ + A_UINT32 anqp_length; /* length of ANQP blob */ + /** + * Following this structure is the byte stream of ie data of length ie_buf_len: + * A_UINT8 ie_data[]; // length in byte given by field ie_length, blob of ie data in beacon + * A_UINT8 anqp_ie[]; // length in byte given by field anqp_len, blob of anqp data of IE + * Implicitly, combing ie_data and anqp_ie into a single bufp, and the bytes + * stream of each ie should be same as BEACON/Action-frm by 802.11 spec + */ } wmi_passpoint_event_hdr; - -#define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 +#define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 /** Enable GTK offload, and provided parameters KEK,KCK and replay counter values */ -#define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 +#define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 /** Disable GTK offload */ -#define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 +#define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 /** Read GTK offload parameters, generates WMI_GTK_OFFLOAD_STATUS_EVENT */ -#define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 +#define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 enum wmi_chatter_mode { - /* Chatter enter/exit happens - * automatically based on preset - * params - */ - WMI_CHATTER_MODE_AUTO, - /* Chatter enter is triggered - * manually by the user - */ - WMI_CHATTER_MODE_MANUAL_ENTER, - /* Chatter exit is triggered - * manually by the user - */ - WMI_CHATTER_MODE_MANUAL_EXIT, - /* Placeholder max value, always last*/ - WMI_CHATTER_MODE_MAX + /* Chatter enter/exit happens + * automatically based on preset + * params + */ + WMI_CHATTER_MODE_AUTO, + /* Chatter enter is triggered + * manually by the user + */ + WMI_CHATTER_MODE_MANUAL_ENTER, + /* Chatter exit is triggered + * manually by the user + */ + WMI_CHATTER_MODE_MANUAL_EXIT, + /* Placeholder max value, always last */ + WMI_CHATTER_MODE_MAX }; enum wmi_chatter_query_type { - /*query coalescing filter match counter*/ - WMI_CHATTER_QUERY_FILTER_MATCH_CNT, - WMI_CHATTER_QUERY_MAX + /*query coalescing filter match counter */ + WMI_CHATTER_QUERY_FILTER_MATCH_CNT, + WMI_CHATTER_QUERY_MAX }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_set_mode_cmd_fixed_param */ - A_UINT32 chatter_mode; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_set_mode_cmd_fixed_param */ + A_UINT32 chatter_mode; } wmi_chatter_set_mode_cmd_fixed_param; /** maximum number of filter supported*/ @@ -9555,49 +10462,49 @@ typedef struct { /** coalescing field test*/ typedef struct _chatter_pkt_coalescing_hdr_test { - /** offset from start of mac header, for windows native wifi host driver - * should assume standard 802.11 frame format without QoS info and address4 - * FW would account for any non-stand fields for final offset value. - */ - A_UINT32 offset; - A_UINT32 length; /* length of test field*/ - A_UINT32 test; /*equal, not equal or masked equal*/ - A_UINT32 mask[CHATTER_MAX_TEST_FIELD_LEN32]; /*mask byte stream*/ - A_UINT32 value[CHATTER_MAX_TEST_FIELD_LEN32]; /*value byte stream*/ + /** offset from start of mac header, for windows native wifi host driver + * should assume standard 802.11 frame format without QoS info and address4 + * FW would account for any non-stand fields for final offset value. + */ + A_UINT32 offset; + A_UINT32 length; /* length of test field */ + A_UINT32 test; /*equal, not equal or masked equal */ + A_UINT32 mask[CHATTER_MAX_TEST_FIELD_LEN32]; /*mask byte stream */ + A_UINT32 value[CHATTER_MAX_TEST_FIELD_LEN32]; /*value byte stream */ } chatter_pkt_coalescing_hdr_test; /** packet coalescing filter*/ typedef struct _chatter_pkt_coalescing_filter { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_pkt_coalescing_filter */ - A_UINT32 filter_id; /*unique id assigned by OS*/ - A_UINT32 max_coalescing_delay; /*max miliseconds 1st pkt can be hold*/ - A_UINT32 pkt_type; /*unicast/multicast/broadcast*/ - A_UINT32 num_of_test_field; /*number of field test in table*/ - chatter_pkt_coalescing_hdr_test test_fields[CHATTER_MAX_FIELD_TEST]; /*field test tbl*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_pkt_coalescing_filter */ + A_UINT32 filter_id; /*unique id assigned by OS */ + A_UINT32 max_coalescing_delay; /*max miliseconds 1st pkt can be hold */ + A_UINT32 pkt_type; /*unicast/multicast/broadcast */ + A_UINT32 num_of_test_field; /*number of field test in table */ + chatter_pkt_coalescing_hdr_test test_fields[CHATTER_MAX_FIELD_TEST]; /*field test tbl */ } chatter_pkt_coalescing_filter; /** packet coalescing filter add command*/ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param */ - A_UINT32 num_of_filters; -/* Following this tlv, there comes an array of structure of type chatter_pkt_coalescing_filter - chatter_pkt_coalescing_filter rx_filter[1];*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param */ + A_UINT32 num_of_filters; + /* Following this tlv, there comes an array of structure of type chatter_pkt_coalescing_filter + chatter_pkt_coalescing_filter rx_filter[1]; */ } wmi_chatter_coalescing_add_filter_cmd_fixed_param; /** packet coalescing filter delete command*/ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_coalescing_delete_filter_cmd_fixed_param */ - A_UINT32 filter_id; /*filter id which will be deleted*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_coalescing_delete_filter_cmd_fixed_param */ + A_UINT32 filter_id; /*filter id which will be deleted */ } wmi_chatter_coalescing_delete_filter_cmd_fixed_param; /** packet coalescing query command*/ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_coalescing_query_cmd_fixed_param */ - A_UINT32 type; /*type of query*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_coalescing_query_cmd_fixed_param */ + A_UINT32 type; /*type of query */ } wmi_chatter_coalescing_query_cmd_fixed_param; /** chatter query reply event*/ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_query_reply_event_fixed_param */ - A_UINT32 type; /*query type*/ - A_UINT32 filter_match_cnt; /*coalescing filter match counter*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chatter_query_reply_event_fixed_param */ + A_UINT32 type; /*query type */ + A_UINT32 filter_match_cnt; /*coalescing filter match counter */ } wmi_chatter_query_reply_event_fixed_param; /* NOTE: This constants GTK_OFFLOAD_KEK_BYTES, GTK_OFFLOAD_KCK_BYTES, and GTK_REPLAY_COUNTER_BYTES @@ -9610,150 +10517,158 @@ typedef struct { #define IGTK_PN_SIZE 6 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param */ - A_UINT32 vdev_id; /** unique id identifying the VDEV */ - A_UINT32 flags; /* status flags */ - A_UINT32 refresh_cnt; /* number of successful GTK refresh exchanges since last SET operation */ - A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; /* current replay counter */ - A_UINT8 igtk_keyIndex; /* Use if IGTK_OFFLOAD is defined */ - A_UINT8 igtk_keyLength; /* Use if IGTK_OFFLOAD is defined */ - A_UINT8 igtk_keyRSC[IGTK_PN_SIZE]; /* key replay sequence counter *//* Use if IGTK_OFFLOAD is defined */ - A_UINT8 igtk_key[WMI_MAX_KEY_LEN]; /* Use if IGTK_OFFLOAD is defined */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param */ + A_UINT32 vdev_id; + /** unique id identifying the VDEV */ + A_UINT32 flags; /* status flags */ + A_UINT32 refresh_cnt; /* number of successful GTK refresh exchanges since last SET operation */ + A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; /* current replay counter */ + A_UINT8 igtk_keyIndex; /* Use if IGTK_OFFLOAD is defined */ + A_UINT8 igtk_keyLength; /* Use if IGTK_OFFLOAD is defined */ + A_UINT8 igtk_keyRSC[IGTK_PN_SIZE]; /* key replay sequence counter *//* Use if IGTK_OFFLOAD is defined */ + A_UINT8 igtk_key[WMI_MAX_KEY_LEN]; /* Use if IGTK_OFFLOAD is defined */ } WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param */ - A_UINT32 vdev_id; /** unique id identifying the VDEV */ - A_UINT32 flags; /* control flags, GTK offload command use high byte */ - /* The size of following 3 arrays cannot be changed without breaking WMI compatibility. */ - A_UINT8 KEK[GTK_OFFLOAD_KEK_BYTES]; /* key encryption key */ - A_UINT8 KCK[GTK_OFFLOAD_KCK_BYTES]; /* key confirmation key */ - A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; /* replay counter for re-key */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param */ + A_UINT32 vdev_id; /** unique id identifying the VDEV */ + A_UINT32 flags; /* control flags, GTK offload command use high byte */ + /* The size of following 3 arrays cannot be changed without breaking WMI compatibility. */ + A_UINT8 KEK[GTK_OFFLOAD_KEK_BYTES]; /* key encryption key */ + A_UINT8 KCK[GTK_OFFLOAD_KCK_BYTES]; /* key confirmation key */ + A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; /* replay counter for re-key */ } WMI_GTK_OFFLOAD_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 sa_query_retry_interval; /* in msec */ - A_UINT32 sa_query_max_retry_count; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 sa_query_retry_interval; /* in msec */ + A_UINT32 sa_query_max_retry_count; } WMI_PMF_OFFLOAD_SET_SA_QUERY_CMD_fixed_param; typedef enum { - WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, /* 802.11 NULL frame */ - WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, /* ARP response */ - WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, /*ETHERNET LOOPBACK*/ - WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, /* gratuitous ARP req*/ + WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, /* 802.11 NULL frame */ + WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, /* ARP response */ + WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, /*ETHERNET LOOPBACK */ + /* gratuitous ARP req*/ + WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, } WMI_STA_KEEPALIVE_METHOD; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_STA_KEEPALVE_ARP_RESPONSE */ - WMI_IPV4_ADDR sender_prot_addr; /* Sender protocol address */ - WMI_IPV4_ADDR target_prot_addr; /* Target protocol address */ - wmi_mac_addr dest_mac_addr; /* destination MAC address */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_STA_KEEPALVE_ARP_RESPONSE */ + WMI_IPV4_ADDR sender_prot_addr; /* Sender protocol address */ + WMI_IPV4_ADDR target_prot_addr; /* Target protocol address */ + wmi_mac_addr dest_mac_addr; /* destination MAC address */ } WMI_STA_KEEPALVE_ARP_RESPONSE; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_STA_KEEPALIVE_CMD_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 enable; /* 1 - Enable, 0 - disable */ - A_UINT32 method; /* keep alive method */ - A_UINT32 interval; /* time interval in seconds */ -/* - * NOTE: following this structure is the TLV for ARP Resonse: - * WMI_STA_KEEPALVE_ARP_RESPONSE arp_resp; <-- ARP response - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_STA_KEEPALIVE_CMD_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 enable; /* 1 - Enable, 0 - disable */ + A_UINT32 method; /* keep alive method */ + A_UINT32 interval; /* time interval in seconds */ + /* + * NOTE: following this structure is the TLV for ARP Resonse: + * WMI_STA_KEEPALVE_ARP_RESPONSE arp_resp; // ARP response + */ } WMI_STA_KEEPALIVE_CMD_fixed_param; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 action; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 action; } WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param; typedef WMI_VDEV_WNM_SLEEPMODE_CMD_fixed_param WMI_STA_WNMSLEEP_CMD; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_keepalive_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 keepaliveInterval; /* seconds */ - A_UINT32 keepaliveMethod; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_keepalive_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 keepaliveInterval; /* seconds */ + A_UINT32 keepaliveMethod; } wmi_vdev_set_keepalive_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_cmd_fixed_param */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_cmd_fixed_param */ + A_UINT32 vdev_id; } wmi_vdev_get_keepalive_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 keepaliveInterval; /* seconds */ - A_UINT32 keepaliveMethod; /* seconds */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 keepaliveInterval; /* seconds */ + A_UINT32 keepaliveMethod; /* seconds */ } wmi_vdev_get_keepalive_event_fixed_param; -typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; #define IPSEC_NATKEEPALIVE_FILTER_DISABLE 0 -#define IPSEC_NATKEEPALIVE_FILTER_ENABLE 1 - A_UINT32 action; -} WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param; -typedef WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD; +#define IPSEC_NATKEEPALIVE_FILTER_ENABLE 1 typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 mcc_tbttmode; - wmi_mac_addr mcc_bssid; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 action; +} WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param; + +typedef WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD_fixed_param +WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 mcc_tbttmode; + wmi_mac_addr mcc_bssid; } wmi_vdev_mcc_set_tbtt_mode_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* home vdev id */ - A_UINT32 meas_token; /* from measure request frame */ - A_UINT32 dialog_token; - A_UINT32 number_bursts; /* zero keep sending until cancel, bigger than 0 means times e.g. 1,2 */ - A_UINT32 burst_interval; /* unit in mill seconds, interval between consecutive burst*/ - A_UINT32 burst_cycle; /* times cycle through within one burst */ - A_UINT32 tx_power; /* for path frame */ - A_UINT32 off_duration; /* uint in mill seconds, channel off duraiton for path loss frame sending */ - wmi_mac_addr dest_mac; /* multicast DA, for path loss frame */ - A_UINT32 num_chans; + A_UINT32 tlv_header; + A_UINT32 vdev_id; /* home vdev id */ + A_UINT32 meas_token; /* from measure request frame */ + A_UINT32 dialog_token; + A_UINT32 number_bursts; /* zero keep sending until cancel, bigger than 0 means times e.g. 1,2 */ + A_UINT32 burst_interval; /* unit in mill seconds, interval between consecutive burst */ + A_UINT32 burst_cycle; /* times cycle through within one burst */ + A_UINT32 tx_power; /* for path frame */ + A_UINT32 off_duration; /* uint in mill seconds, channel off duraiton for path loss frame sending */ + wmi_mac_addr dest_mac; /* multicast DA, for path loss frame */ + A_UINT32 num_chans; } wmi_vdev_plmreq_start_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 meas_token; /* same value from req*/ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 meas_token; /* same value from req */ } wmi_vdev_plmreq_stop_cmd_fixed_param; typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_set_noa_cmd_fixed_param */ - A_UINT32 tlv_header; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* enable/disable NoA */ - A_UINT32 enable; - /** number of NoA desc. In the TLV noa_descriptor[] */ - A_UINT32 num_noa; - /** - * TLV (tag length value) paramerters follow the pattern structure. - * TLV contain NoA desc with num of num_noa - */ + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_set_noa_cmd_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* enable/disable NoA */ + A_UINT32 enable; + /** number of NoA desc. In the TLV noa_descriptor[] */ + A_UINT32 num_noa; + /** + * TLV (tag length value ) paramerters follow the pattern structure. + * TLV contain NoA desc with num of num_noa + */ } wmi_p2p_set_noa_cmd_fixed_param; typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_unit_test_cmd_fixed_param */ - A_UINT32 tlv_header; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* Identify the wlan module */ - A_UINT32 module_id; - /* Num of test arguments passed */ - A_UINT32 num_args; + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_unit_test_cmd_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* Identify the wlan module */ + A_UINT32 module_id; + /* Num of test arguments passed */ + A_UINT32 num_args; /** - * TLV (tag length value) parameters follow the wmi_roam_chan_list + * TLV (tag length value ) parameters follow the wmi_roam_chan_list * structure. The TLV's are: - * A_UINT32 args[]; + * A_UINT32 args[]; **/ } wmi_unit_test_cmd_fixed_param; @@ -9761,216 +10676,226 @@ typedef struct { * after it received WMI_ROAM_SYNCH_EVENTID. */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; } wmi_roam_synch_complete_fixed_param; - typedef enum { - RECOVERY_SIM_ASSERT = 0x01, - RECOVERY_SIM_NO_DETECT = 0x02, - RECOVERY_SIM_CTR_EP_FULL = 0x03, - RECOVERY_SIM_EMPTY_POINT = 0x04, - RECOVERY_SIM_STACK_OV = 0x05, - RECOVERY_SIM_INFINITE_LOOP = 0x06, - RECOVERY_SIM_PCIE_LINKDOWN = 0x07, - RECOVERY_SIM_SELF_RECOVERY = 0x08, + RECOVERY_SIM_ASSERT = 0x01, + RECOVERY_SIM_NO_DETECT = 0x02, + RECOVERY_SIM_CTR_EP_FULL = 0x03, + RECOVERY_SIM_EMPTY_POINT = 0x04, + RECOVERY_SIM_STACK_OV = 0x05, + RECOVERY_SIM_INFINITE_LOOP = 0x06, + RECOVERY_SIM_PCIE_LINKDOWN = 0x07, + RECOVERY_SIM_SELF_RECOVERY = 0x08, } RECOVERY_SIM_TYPE; /* WMI_FORCE_FW_HANG_CMDID */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_FORCE_FW_HANG_CMD_fixed_param */ - A_UINT32 type; /*0:unused 1: ASSERT, 2: not respond detect command,3: simulate ep-full(),4:...*/ - A_UINT32 delay_time_ms; /*0xffffffff means the simulate will delay for random time (0 ~0xffffffff ms)*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_FORCE_FW_HANG_CMD_fixed_param */ + A_UINT32 type; /*0:unused 1: ASSERT, 2: not respond detect command,3: simulate ep-full(),4:... */ + A_UINT32 delay_time_ms; /*0xffffffff means the simulate will delay for random time (0 ~0xffffffff ms) */ } WMI_FORCE_FW_HANG_CMD_fixed_param; typedef enum { - WMI_MCAST_FILTER_SET = 1, - WMI_MCAST_FILTER_DELETE + WMI_MCAST_FILTER_SET = 1, + WMI_MCAST_FILTER_DELETE } WMI_SET_SINGLE_MCAST_FILTER_OP; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 index; - A_UINT32 action; - wmi_mac_addr mcastbdcastaddr; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 index; + A_UINT32 action; + wmi_mac_addr mcastbdcastaddr; } WMI_SET_MCASTBCAST_FILTER_CMD_fixed_param; typedef enum { - WMI_MULTIPLE_MCAST_FILTER_CLEAR = 1, /* clear all previous mc list */ - WMI_MULTIPLE_MCAST_FILTER_SET, /* clear all previous mc list, and set new list */ - WMI_MULTIPLE_MCAST_FILTER_DELETE, /* delete one/multiple mc list */ - WMI_MULTIPLE_MCAST_FILTER_ADD /* add one/multiple mc list */ + WMI_MULTIPLE_MCAST_FILTER_CLEAR = 1, /* clear all previous mc list */ + /* clear all previous mc list, and set new list */ + WMI_MULTIPLE_MCAST_FILTER_SET, + WMI_MULTIPLE_MCAST_FILTER_DELETE, /* delete one/multiple mc list */ + WMI_MULTIPLE_MCAST_FILTER_ADD /* add one/multiple mc list */ } WMI_MULTIPLE_MCAST_FILTER_OP; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 operation; /* refer WMI_MULTIPLE_MCAST_FILTER_OP */ - A_UINT32 num_mcastaddrs; /* number of elements in the subsequent mcast addr list */ -/** - * TLV (tag length value) parameters follow the - * structure. The TLV's are: - * wmi_mac_addr mcastaddr_list[num_mcastaddrs]; - */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 operation; /* refer WMI_MULTIPLE_MCAST_FILTER_OP */ + /* number of elements in the subsequent mcast addr list */ + A_UINT32 num_mcastaddrs; + /** + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * wmi_mac_addr mcastaddr_list[num_mcastaddrs]; + */ } WMI_SET_MULTIPLE_MCAST_FILTER_CMD_fixed_param; /* WMI_DBGLOG_TIME_STAMP_SYNC_CMDID */ typedef enum { - WMI_TIME_STAMP_SYNC_MODE_MS, /* millisecond units */ - WMI_TIME_STAMP_SYNC_MODE_US, /* microsecond units */ + WMI_TIME_STAMP_SYNC_MODE_MS, /* millisecond units */ + WMI_TIME_STAMP_SYNC_MODE_US, /* microsecond units */ } WMI_TIME_STAMP_SYNC_MODE; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dbglog_time_stamp_sync_cmd_fixed_param */ - A_UINT32 mode; /* 0: millisec, 1: microsec (see WMI_TIME_STAMP_SYNC_MODE) */ - A_UINT32 time_stamp_low; /* lower 32 bits of remote time stamp */ - A_UINT32 time_stamp_high; /* higher 32 bits of remote time stamp */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dbglog_time_stamp_sync_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* 0: millisec, 1: microsec (see WMI_TIME_STAMP_SYNC_MODE) */ + A_UINT32 mode; + A_UINT32 time_stamp_low; /* lower 32 bits of remote time stamp */ + A_UINT32 time_stamp_high; /* higher 32 bits of remote time stamp */ } WMI_DBGLOG_TIME_STAMP_SYNC_CMD_fixed_param; + /* GPIO Command and Event data structures */ /* WMI_GPIO_CONFIG_CMDID */ enum { - WMI_GPIO_PULL_NONE, - WMI_GPIO_PULL_UP, - WMI_GPIO_PULL_DOWN, + WMI_GPIO_PULL_NONE, + WMI_GPIO_PULL_UP, + WMI_GPIO_PULL_DOWN, }; enum { - WMI_GPIO_INTTYPE_DISABLE, - WMI_GPIO_INTTYPE_RISING_EDGE, - WMI_GPIO_INTTYPE_FALLING_EDGE, - WMI_GPIO_INTTYPE_BOTH_EDGE, - WMI_GPIO_INTTYPE_LEVEL_LOW, - WMI_GPIO_INTTYPE_LEVEL_HIGH + WMI_GPIO_INTTYPE_DISABLE, + WMI_GPIO_INTTYPE_RISING_EDGE, + WMI_GPIO_INTTYPE_FALLING_EDGE, + WMI_GPIO_INTTYPE_BOTH_EDGE, + WMI_GPIO_INTTYPE_LEVEL_LOW, + WMI_GPIO_INTTYPE_LEVEL_HIGH }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_config_cmd_fixed_param */ - A_UINT32 gpio_num; /* GPIO number to be setup */ - A_UINT32 input; /* 0 - Output/ 1 - Input */ - A_UINT32 pull_type; /* Pull type defined above */ - A_UINT32 intr_mode; /* Interrupt mode defined above (Input) */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_config_cmd_fixed_param */ + A_UINT32 gpio_num; /* GPIO number to be setup */ + A_UINT32 input; /* 0 - Output/ 1 - Input */ + A_UINT32 pull_type; /* Pull type defined above */ + A_UINT32 intr_mode; /* Interrupt mode defined above (Input) */ } wmi_gpio_config_cmd_fixed_param; /* WMI_GPIO_OUTPUT_CMDID */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param */ - A_UINT32 gpio_num; /* GPIO number to be setup */ - A_UINT32 set; /* Set the GPIO pin*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param */ + A_UINT32 gpio_num; /* GPIO number to be setup */ + A_UINT32 set; /* Set the GPIO pin */ } wmi_gpio_output_cmd_fixed_param; /* WMI_GPIO_INPUT_EVENTID */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param */ - A_UINT32 gpio_num; /* GPIO number which changed state */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param */ + A_UINT32 gpio_num; /* GPIO number which changed state */ } wmi_gpio_input_event_fixed_param; /* WMI_P2P_DISC_EVENTID */ enum { - P2P_DISC_SEARCH_PROB_REQ_HIT = 0, /* prob req hit the p2p find pattern */ - P2P_DISC_SEARCH_PROB_RESP_HIT, /* prob resp hit the p2p find pattern */ + P2P_DISC_SEARCH_PROB_REQ_HIT = 0, /* prob req hit the p2p find pattern */ + P2P_DISC_SEARCH_PROB_RESP_HIT, /* prob resp hit the p2p find pattern */ }; enum { - P2P_DISC_MODE_SEARCH = 0, /* do search when p2p find offload*/ - P2P_DISC_MODE_LISTEN, /* do listen when p2p find offload*/ - P2P_DISC_MODE_AUTO, /* do listen and search when p2p find offload*/ + P2P_DISC_MODE_SEARCH = 0, /* do search when p2p find offload */ + P2P_DISC_MODE_LISTEN, /* do listen when p2p find offload */ + P2P_DISC_MODE_AUTO, /* do listen and search when p2p find offload */ }; enum { - P2P_DISC_PATTERN_TYPE_BSSID = 0, /* BSSID pattern */ - P2P_DISC_PATTERN_TYPE_DEV_NAME, /* device name pattern */ + P2P_DISC_PATTERN_TYPE_BSSID = 0, /* BSSID pattern */ + P2P_DISC_PATTERN_TYPE_DEV_NAME, /* device name pattern */ }; typedef struct { - A_UINT32 vdev_id; - A_UINT32 reason; /* P2P DISC wake up reason*/ + A_UINT32 vdev_id; + A_UINT32 reason; /* P2P DISC wake up reason */ } wmi_p2p_disc_event; -typedef WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param WOW_EVENT_INFO_SECTION_GTKIGTK; +typedef WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param +WOW_EVENT_INFO_SECTION_GTKIGTK; typedef enum { - WMI_FAKE_TXBFER_SEND_NDPA, - WMI_FAKE_TXBFER_SEND_MU, - WMI_FAKE_TXBFER_NDPA_FBTYPE, - WMI_FAKE_TXBFER_NDPA_NCIDX, - WMI_FAKE_TXBFER_NDPA_POLL, - WMI_FAKE_TXBFER_NDPA_BW, - WMI_FAKE_TXBFER_NDPA_PREAMBLE, - WMI_FAKE_TXBFER_NDPA_RATE, - WMI_FAKE_TXBFER_NDP_BW, - WMI_FAKE_TXBFER_NDP_NSS, - WMI_TXBFEE_ENABLE_UPLOAD_H, - WMI_TXBFEE_ENABLE_CAPTURE_H, - WMI_TXBFEE_SET_CBF_TBL, - WMI_TXBFEE_CBF_TBL_LSIG, - WMI_TXBFEE_CBF_TBL_SIGA1, - WMI_TXBFEE_CBF_TBL_SIGA2, - WMI_TXBFEE_CBF_TBL_SIGB, - WMI_TXBFEE_CBF_TBL_PAD, - WMI_TXBFEE_CBF_TBL_DUR, - WMI_TXBFEE_SU_NCIDX, - WMI_TXBFEE_CBIDX, - WMI_TXBFEE_NGIDX, + WMI_FAKE_TXBFER_SEND_NDPA, + WMI_FAKE_TXBFER_SEND_MU, + WMI_FAKE_TXBFER_NDPA_FBTYPE, + WMI_FAKE_TXBFER_NDPA_NCIDX, + WMI_FAKE_TXBFER_NDPA_POLL, + WMI_FAKE_TXBFER_NDPA_BW, + WMI_FAKE_TXBFER_NDPA_PREAMBLE, + WMI_FAKE_TXBFER_NDPA_RATE, + WMI_FAKE_TXBFER_NDP_BW, + WMI_FAKE_TXBFER_NDP_NSS, + WMI_TXBFEE_ENABLE_UPLOAD_H, + WMI_TXBFEE_ENABLE_CAPTURE_H, + WMI_TXBFEE_SET_CBF_TBL, + WMI_TXBFEE_CBF_TBL_LSIG, + WMI_TXBFEE_CBF_TBL_SIGA1, + WMI_TXBFEE_CBF_TBL_SIGA2, + WMI_TXBFEE_CBF_TBL_SIGB, + WMI_TXBFEE_CBF_TBL_PAD, + WMI_TXBFEE_CBF_TBL_DUR, + WMI_TXBFEE_SU_NCIDX, + WMI_TXBFEE_CBIDX, + WMI_TXBFEE_NGIDX, } WMI_TXBF_PARAM_ID; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_txbf_cmd_fixed_param */ - /** parameter id */ - A_UINT32 param_id; - /** parameter value */ - A_UINT32 param_value; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_txbf_cmd_fixed_param */ + /** parameter id */ + A_UINT32 param_id; + /** parameter value */ + A_UINT32 param_value; } wmi_txbf_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_upload_h_hdr */ - A_UINT32 h_length; - A_UINT32 cv_length; -/* This TLV is followed by array of bytes: - * A_UINT8 bufp[]; <-- h_cv info buffer - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_upload_h_hdr */ + A_UINT32 h_length; + A_UINT32 cv_length; + /* This TLV is followed by array of bytes: + * // h_cv info buffer + * A_UINT8 bufp[]; + */ } wmi_upload_h_hdr; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_capture_h_event_hdr */ - A_UINT32 svd_num; - A_UINT32 tone_num; - A_UINT32 reserved; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_capture_h_event_hdr */ + A_UINT32 svd_num; + A_UINT32 tone_num; + A_UINT32 reserved; } wmi_capture_h_event_hdr; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avoid_freq_range_desc */ - A_UINT32 start_freq; /* start frequency, not channel center freq */ - A_UINT32 end_freq; /* end frequency */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avoid_freq_range_desc */ + A_UINT32 start_freq; /* start frequency, not channel center freq */ + A_UINT32 end_freq; /* end frequency */ } wmi_avoid_freq_range_desc; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avoid_freq_ranges_event_fixed_param */ - /* bad channel range count, multi range is allowed, 0 means all channel clear */ - A_UINT32 num_freq_ranges; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avoid_freq_ranges_event_fixed_param */ + /* bad channel range count, multi range is allowed, 0 means all channel clear */ + A_UINT32 num_freq_ranges; -/* The TLVs will follow. - * multi range with num_freq_ranges, LTE advance multi carrier, CDMA,etc - * wmi_avoid_freq_range_desc avd_freq_range[]; <-- message buffer, NULL terminated - */ + /* The TLVs will follow. + * multi range with num_freq_ranges, LTE advance multi carrier, CDMA,etc + * wmi_avoid_freq_range_desc avd_freq_range[]; // message buffer, NULL terminated + */ } wmi_avoid_freq_ranges_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gtk_rekey_fail_event_fixed_param */ - /** Reserved for future use */ - A_UINT32 reserved0; - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gtk_rekey_fail_event_fixed_param */ + /** Reserved for future use */ + A_UINT32 reserved0; + A_UINT32 vdev_id; } wmi_gtk_rekey_fail_event_fixed_param; enum wmm_ac_downgrade_policy { - WMM_AC_DOWNGRADE_DEPRIO, - WMM_AC_DOWNGRADE_DROP, - WMM_AC_DOWNGRADE_INVALID, + WMM_AC_DOWNGRADE_DEPRIO, + WMM_AC_DOWNGRADE_DROP, + WMM_AC_DOWNGRADE_INVALID, }; /* WMM EDCA Params type */ @@ -9979,104 +10904,169 @@ enum wmm_ac_downgrade_policy { #define WMM_PARAM_TYPE_11AX_EDCA 1 typedef struct { - A_UINT32 tlv_header; - A_UINT32 cwmin; - A_UINT32 cwmax; - A_UINT32 aifs; - A_UINT32 txoplimit; - A_UINT32 acm; - A_UINT32 no_ack; + A_UINT32 tlv_header; + A_UINT32 cwmin; + A_UINT32 cwmax; + A_UINT32 aifs; + A_UINT32 txoplimit; + A_UINT32 acm; + A_UINT32 no_ack; } wmi_wmm_vparams; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - wmi_wmm_vparams wmm_params[4]; /* 0 be, 1 bk, 2 vi, 3 vo */ - A_UINT32 wmm_param_type; /* see WMM_PARAM_TYPE_xxx defs */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + wmi_wmm_vparams wmm_params[4]; /* 0 be, 1 bk, 2 vi, 3 vo */ + A_UINT32 wmm_param_type; /* see WMM_PARAM_TYPE_xxx defs */ } wmi_vdev_set_wmm_params_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 gtxRTMask[2]; /* for HT and VHT rate masks */ - A_UINT32 userGtxMask; /* host request for GTX mask */ - A_UINT32 gtxPERThreshold; /* default: 10% */ - A_UINT32 gtxPERMargin; /* default: 2% */ - A_UINT32 gtxTPCstep; /* default: 1 */ - A_UINT32 gtxTPCMin; /* default: 5 */ - A_UINT32 gtxBWMask; /* 20/40/80/160 Mhz */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 gtxRTMask[2]; /* for HT and VHT rate masks */ + A_UINT32 userGtxMask; /* host request for GTX mask */ + A_UINT32 gtxPERThreshold; /* default: 10% */ + A_UINT32 gtxPERMargin; /* default: 2% */ + A_UINT32 gtxTPCstep; /* default: 1 */ + A_UINT32 gtxTPCMin; /* default: 5 */ + A_UINT32 gtxBWMask; /* 20/40/80/160 Mhz */ } wmi_vdev_set_gtx_params_cmd_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 ac; - A_UINT32 medium_time_us; /* per second unit, the Admitted time granted, unit in micro seconds */ - A_UINT32 downgrade_type; +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 ac; + A_UINT32 medium_time_us; /* per second unit, the Admitted time granted, unit in micro seconds */ + A_UINT32 downgrade_type; } wmi_vdev_wmm_addts_cmd_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 ac; +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 ac; } wmi_vdev_wmm_delts_cmd_fixed_param; /* DEPRECATED */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_dfs_enable_cmd_fixed_param */ - /** Reserved for future use */ - A_UINT32 reserved0; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_dfs_enable_cmd_fixed_param */ + /** Reserved for future use */ + A_UINT32 reserved0; } wmi_pdev_dfs_enable_cmd_fixed_param; /* DEPRECATED */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_dfs_disable_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_dfs_disable_cmd_fixed_param */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_dfs_disable_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_ena_cmd_fixed_param - */ - A_UINT32 tlv_header; - - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_ena_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_dfs_phyerr_filter_ena_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_dis_cmd_fixed_param - */ - A_UINT32 tlv_header; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dfs_phyerr_filter_dis_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_dfs_phyerr_filter_dis_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; + A_UINT32 pdev_id; +} wmi_pdev_dfs_phyerr_offload_enable_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 pdev_id; +} wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param; + +typedef enum { + QUICK_OCAC = 0, + EXTENSIVE_OCAC, +} WMI_ADFS_OCAC_MODE; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 ocac_mode; /* WMI_ADFS_OCAC_MODE */ + A_UINT32 min_duration_ms; /* in milliseconds */ + A_UINT32 max_duration_ms; /* in milliseconds */ + A_UINT32 chan_freq; /* in MHz */ + A_UINT32 chan_width; /* in MHz */ + A_UINT32 center_freq; /* in MHz */ +} wmi_vdev_adfs_ch_cfg_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; +} wmi_vdev_adfs_ocac_abort_cmd_fixed_param; + +typedef enum { + IN_SERVICE_MODE = 0, + OCAC_MODE, +} WMI_DFS_RADAR_DETECTION_MODE; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 pdev_id; + /* In-service mode or O-CAC mode */ + A_UINT32 detection_mode; /* WMI_DFS_RADAR_DETECTION_MODE */ + A_UINT32 chan_freq; /* in MHz */ + A_UINT32 chan_width; /* in MHz */ + A_UINT32 detector_id; + A_UINT32 segment_id; + A_UINT32 timestamp; + A_UINT32 is_chirp; +} wmi_pdev_dfs_radar_detection_event_fixed_param; + +typedef enum { + OCAC_COMPLETE = 0, + OCAC_ABORT, +} WMI_VDEV_OCAC_COMPLETE_STATUS; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 chan_freq; /* in MHz */ + A_UINT32 chan_width; /* in MHz */ + A_UINT32 center_freq; /* in MHz */ + A_UINT32 status; /* WMI_VDEV_OCAC_COMPLETE_STATUS */ +} wmi_vdev_adfs_ocac_complete_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; +} wmi_vdev_dfs_cac_complete_event_fixed_param; + /** TDLS COMMANDS */ /* WMI_TDLS_SET_STATE_CMDID */ /* TDLS State */ enum wmi_tdls_state { - /** TDLS disable */ - WMI_TDLS_DISABLE, - /** TDLS enabled - no firmware connection tracking/notifications */ - WMI_TDLS_ENABLE_PASSIVE, - /** TDLS enabled - with firmware connection tracking/notifications */ - WMI_TDLS_ENABLE_ACTIVE, - /** TDLS enabled - firmware waits for peer mac for connection tracking */ - WMI_TDLS_ENABLE_ACTIVE_EXTERNAL_CONTROL, - /** TDLS enabled - TDLS connection tracking is done in host */ - WMI_TDLS_ENABLE_CONNECTION_TRACKER_IN_HOST, + /** TDLS disable */ + WMI_TDLS_DISABLE, + /** TDLS enabled - no firmware connection tracking/notifications */ + WMI_TDLS_ENABLE_PASSIVE, + /** TDLS enabled - with firmware connection tracking/notifications */ + WMI_TDLS_ENABLE_ACTIVE, + /* TDLS enabled - firmware waits for peer mac for connection tracking */ + WMI_TDLS_ENABLE_ACTIVE_EXTERNAL_CONTROL, + /** TDLS enabled - TDLS connection tracking is done in host */ + WMI_TDLS_ENABLE_CONNECTION_TRACKER_IN_HOST, }; /* TDLS Options */ @@ -10085,99 +11075,102 @@ enum wmi_tdls_state { #define WMI_TDLS_SLEEP_STA_EN (1 << 2) /** TDLS Sleep STA support (not currently supported) */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_set_state_cmd_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** Enable/Disable TDLS (wmi_tdls_state) */ - A_UINT32 state; - /** Duration (in ms) over which to calculate tx/rx threshold to trigger TDLS Discovery */ - A_UINT32 notification_interval_ms; - /** number of packets OVER which notify/suggest TDLS Discovery: - * if current tx pps counter / notification interval >= threshold - * then a notification will be sent to host to advise TDLS Discovery */ - A_UINT32 tx_discovery_threshold; - /** number of packets UNDER which notify/suggest TDLS Teardown: - * if current tx pps counter / notification interval < threshold - * then a notification will be sent to host to advise TDLS Tear down */ - A_UINT32 tx_teardown_threshold; - /** Absolute RSSI value under which notify/suggest TDLS Teardown */ - A_INT32 rssi_teardown_threshold; - /** Peer RSSI < (AP RSSI + delta) will trigger a teardown */ - A_INT32 rssi_delta; - /** TDLS Option Control - * Off-Channel, Buffer STA, (later)Sleep STA support */ - A_UINT32 tdls_options; - /* Buffering time in number of beacon intervals */ - A_UINT32 tdls_peer_traffic_ind_window; - /* Wait time for PTR frame */ - A_UINT32 tdls_peer_traffic_response_timeout_ms; - /* Self PUAPSD mask */ - A_UINT32 tdls_puapsd_mask; - /* Inactivity timeout */ - A_UINT32 tdls_puapsd_inactivity_time_ms; - /* Max of rx frame during SP */ - A_UINT32 tdls_puapsd_rx_frame_threshold; - /**Duration (in ms) over which to check whether TDLS link needs to be torn down */ - A_UINT32 teardown_notification_ms; - /**STA kickout threshold for TDLS peer */ - A_UINT32 tdls_peer_kickout_threshold; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_set_state_cmd_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** Enable/Disable TDLS (wmi_tdls_state) */ + A_UINT32 state; + /* Duration (in ms) over which to calculate tx/rx threshold + * to trigger TDLS Discovery + */ + A_UINT32 notification_interval_ms; + /** number of packets OVER which notify/suggest TDLS Discovery: + * if current tx pps counter / notification interval >= threshold + * then a notification will be sent to host to advise TDLS Discovery */ + A_UINT32 tx_discovery_threshold; + /** number of packets UNDER which notify/suggest TDLS Teardown: + * if current tx pps counter / notification interval < threshold + * then a notification will be sent to host to advise TDLS Tear down */ + A_UINT32 tx_teardown_threshold; + /** Absolute RSSI value under which notify/suggest TDLS Teardown */ + A_INT32 rssi_teardown_threshold; + /** Peer RSSI < (AP RSSI + delta) will trigger a teardown */ + A_INT32 rssi_delta; + /** TDLS Option Control + * Off-Channel, Buffer STA, (later)Sleep STA support */ + A_UINT32 tdls_options; + /* Buffering time in number of beacon intervals */ + A_UINT32 tdls_peer_traffic_ind_window; + /* Wait time for PTR frame */ + A_UINT32 tdls_peer_traffic_response_timeout_ms; + /* Self PUAPSD mask */ + A_UINT32 tdls_puapsd_mask; + /* Inactivity timeout */ + A_UINT32 tdls_puapsd_inactivity_time_ms; + /* Max of rx frame during SP */ + A_UINT32 tdls_puapsd_rx_frame_threshold; + /* Duration (in ms) over which to check whether TDLS link + * needs to be torn down + */ + A_UINT32 teardown_notification_ms; + /* STA kickout threshold for TDLS peer */ + A_UINT32 tdls_peer_kickout_threshold; } wmi_tdls_set_state_cmd_fixed_param; /* WMI_TDLS_PEER_UPDATE_CMDID */ enum wmi_tdls_peer_state { - /** tx peer TDLS link setup now starting, traffic to DA should be - * paused (except TDLS frames) until state is moved to CONNECTED (or - * TEARDOWN on setup failure) */ - WMI_TDLS_PEER_STATE_PEERING, - /** tx peer TDLS link established, running (all traffic to DA unpaused) */ - WMI_TDLS_PEER_STATE_CONNECTED, - /** tx peer TDLS link tear down started (link paused, any frames - * queued for DA will be requeued back through the AP)*/ - WMI_TDLS_PEER_STATE_TEARDOWN, - /** Add peer mac into connection table */ - WMI_TDLS_PEER_ADD_MAC_ADDR, - /** Remove peer mac from connection table */ - WMI_TDLS_PEER_REMOVE_MAC_ADDR, + /** tx peer TDLS link setup now starting, traffic to DA should be + * paused (except TDLS frames) until state is moved to CONNECTED (or + * TEARDOWN on setup failure) */ + WMI_TDLS_PEER_STATE_PEERING, + /** tx peer TDLS link established, running (all traffic to DA unpaused) */ + WMI_TDLS_PEER_STATE_CONNECTED, + /** tx peer TDLS link tear down started (link paused, any frames + * queued for DA will be requeued back through the AP)*/ + WMI_TDLS_PEER_STATE_TEARDOWN, + /* Add peer mac into connection table */ + WMI_TDLS_PEER_ADD_MAC_ADDR, + /* Remove peer mac from connection table */ + WMI_TDLS_PEER_REMOVE_MAC_ADDR, }; /* NB: These defines are fixed, and cannot be changed without breaking WMI compatibility */ -#define WMI_TDLS_MAX_SUPP_CHANNELS 128 #define WMI_TDLS_MAX_SUPP_OPER_CLASSES 32 typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_capabilities */ - A_UINT32 tlv_header; - /* Peer's QoS Info - for U-APSD */ - /* AC FLAGS - accessed through macros below */ - /* Ack, SP, More Data Ack - accessed through macros below */ - A_UINT32 peer_qos; - /*TDLS Peer's U-APSD Buffer STA Support*/ - A_UINT32 buff_sta_support; - /*TDLS off channel related params */ - A_UINT32 off_chan_support; - A_UINT32 peer_curr_operclass; - A_UINT32 self_curr_operclass; - /* Number of channels available for off channel operation */ - A_UINT32 peer_chan_len; - A_UINT32 peer_operclass_len; - A_UINT8 peer_operclass[WMI_TDLS_MAX_SUPP_OPER_CLASSES]; - /* Is peer initiator or responder of TDLS setup request */ - A_UINT32 is_peer_responder; - /* Preferred off channel number as configured by user */ - A_UINT32 pref_offchan_num; - /* Preferred off channel bandwidth as configured by user */ - A_UINT32 pref_offchan_bw; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_capabilities */ + A_UINT32 tlv_header; + /* Peer's QoS Info - for U-APSD */ + /* AC FLAGS - accessed through macros below */ + /* Ack, SP, More Data Ack - accessed through macros below */ + A_UINT32 peer_qos; + /*TDLS Peer's U-APSD Buffer STA Support */ + A_UINT32 buff_sta_support; + /*TDLS off channel related params */ + A_UINT32 off_chan_support; + A_UINT32 peer_curr_operclass; + A_UINT32 self_curr_operclass; + /* Number of channels available for off channel operation */ + A_UINT32 peer_chan_len; + A_UINT32 peer_operclass_len; + A_UINT8 peer_operclass[WMI_TDLS_MAX_SUPP_OPER_CLASSES]; + /* Is peer initiator or responder of TDLS setup request */ + A_UINT32 is_peer_responder; + /* Preferred off channel number as configured by user */ + A_UINT32 pref_offchan_num; + /* Preferred off channel bandwidth as configured by user */ + A_UINT32 pref_offchan_bw; - /** Followed by the variable length TLV peer_chan_list: - * wmi_channel peer_chan_list[]. - * Array size would be peer_chan_len. - * This array is intersected channels which is supported by both peer - * and DUT. freq1 in chan_info shall be same as mhz, freq2 shall be 0. - * FW shall compute BW for an offchan based on peer's ht/vht cap - * received in peer_assoc cmd during change STA operation - */ - } wmi_tdls_peer_capabilities; + /** Followed by the variable length TLV peer_chan_list: + * wmi_channel peer_chan_list[]. + * Array size would be peer_chan_len. + * This array is intersected channels which is supported by both peer + * and DUT. freq1 in chan_info shall be same as mhz, freq2 shall be 0. + * FW shall compute BW for an offchan based on peer's ht/vht cap + * received in peer_assoc cmd during change STA operation + */ +} wmi_tdls_peer_capabilities; #define WMI_TDLS_QOS_VO_FLAG 0 #define WMI_TDLS_QOS_VI_FLAG 1 @@ -10187,236 +11180,244 @@ typedef struct { #define WMI_TDLS_QOS_SP_FLAG 5 #define WMI_TDLS_QOS_MOREDATA_FLAG 7 -#define WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps,flag) do { \ - (ppeer_caps)->peer_qos |= (1 << flag); \ - } while (0) -#define WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps,flag) \ - (((ppeer_caps)->peer_qos & (1 << flag)) >> flag) +#define WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, flag) do { \ + (ppeer_caps)->peer_qos |= (1 << flag); \ +} while (0) +#define WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, flag) \ + (((ppeer_caps)->peer_qos & (1 << flag)) >> flag) #define WMI_SET_TDLS_PEER_VO_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VO_FLAG) + WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VO_FLAG) #define WMI_GET_TDLS_PEER_VO_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VO_FLAG) + WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VO_FLAG) #define WMI_SET_TDLS_PEER_VI_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VI_FLAG) + WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VI_FLAG) #define WMI_GET_TDLS_PEER_VI_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VI_FLAG) + WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_VI_FLAG) #define WMI_SET_TDLS_PEER_BK_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BK_FLAG) + WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BK_FLAG) #define WMI_GET_TDLS_PEER_BK_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BK_FLAG) + WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BK_FLAG) #define WMI_SET_TDLS_PEER_BE_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BE_FLAG) + WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BE_FLAG) #define WMI_GET_TDLS_PEER_BE_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BE_FLAG) -#define WMI_SET_TDLS_PEER_ACK_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_ACK_FLAG) -#define WMI_GET_TDLS_PEER_ACK_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_ACK_FLAG) + WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_BE_FLAG) +#define WMI_SET_TDLS_PEER_ACK_UAPSD(ppeer_caps) \ + WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_ACK_FLAG) +#define WMI_GET_TDLS_PEER_ACK_UAPSD(ppeer_caps) \ + WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_ACK_FLAG) /* SP has 2 bits */ -#define WMI_SET_TDLS_PEER_SP_UAPSD(ppeer_caps,val) do { \ - (ppeer_caps)->peer_qos |= (((val) & 0x3) << WMI_TDLS_QOS_SP_FLAG); \ - } while (0) +#define WMI_SET_TDLS_PEER_SP_UAPSD(ppeer_caps, val) do { \ + (ppeer_caps)->peer_qos |= (((val)&0x3) << WMI_TDLS_QOS_SP_FLAG); \ +} while (0) #define WMI_GET_TDLS_PEER_SP_UAPSD(ppeer_caps) \ - (((ppeer_caps)->peer_qos & (0x3 << WMI_TDLS_QOS_SP_FLAG)) >> WMI_TDLS_QOS_SP_FLAG) + (((ppeer_caps)->peer_qos & (0x3 << WMI_TDLS_QOS_SP_FLAG)) >> WMI_TDLS_QOS_SP_FLAG) #define WMI_SET_TDLS_PEER_MORE_DATA_ACK_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_MOREDATA_FLAG) + WMI_TDLS_PEER_SET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_MOREDATA_FLAG) #define WMI_GET_TDLS_PEER_MORE_DATA_ACK_UAPSD(ppeer_caps) \ - WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_MOREDATA_FLAG) + WMI_TDLS_PEER_GET_QOS_FLAG(ppeer_caps, WMI_TDLS_QOS_MOREDATA_FLAG) - -#define WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd,flag) do { \ - (pset_cmd)->tdls_puapsd_mask |= (1 << flag); \ - } while (0) -#define WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd,flag) \ - (((pset_cmd)->tdls_puapsd_mask & (1 << flag)) >> flag) +#define WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, flag) do { \ + (pset_cmd)->tdls_puapsd_mask |= (1 << flag); \ +} while (0) +#define WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, flag) \ + (((pset_cmd)->tdls_puapsd_mask & (1 << flag)) >> flag) #define WMI_SET_TDLS_SELF_VO_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VO_FLAG) + WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VO_FLAG) #define WMI_GET_TDLS_SELF_VO_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VO_FLAG) + WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VO_FLAG) #define WMI_SET_TDLS_SELF_VI_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VI_FLAG) + WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VI_FLAG) #define WMI_GET_TDLS_SELF_VI_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VI_FLAG) + WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_VI_FLAG) #define WMI_SET_TDLS_SELF_BK_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BK_FLAG) + WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BK_FLAG) #define WMI_GET_TDLS_SELF__BK_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BK_FLAG) + WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BK_FLAG) #define WMI_SET_TDLS_SELF_BE_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BE_FLAG) + WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BE_FLAG) #define WMI_GET_TDLS_SELF_BE_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BE_FLAG) + WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_BE_FLAG) #define WMI_SET_TDLS_SELF_ACK_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_ACK_FLAG) + WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_ACK_FLAG) #define WMI_GET_TDLS_SELF_ACK_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_ACK_FLAG) + WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_ACK_FLAG) /* SP has 2 bits */ -#define WMI_SET_TDLS_SELF_SP_UAPSD(pset_cmd,val) do { \ - (pset_cmd)->tdls_puapsd_mask |= (((val) & 0x3) << WMI_TDLS_QOS_SP_FLAG); \ - } while (0) +#define WMI_SET_TDLS_SELF_SP_UAPSD(pset_cmd, val) do { \ + (pset_cmd)->tdls_puapsd_mask |= (((val)&0x3) << WMI_TDLS_QOS_SP_FLAG); \ +} while (0) #define WMI_GET_TDLS_SELF_SP_UAPSD(pset_cmd) \ - (((pset_cmd)->tdls_puapsd_mask & (0x3 << WMI_TDLS_QOS_SP_FLAG)) >> WMI_TDLS_QOS_SP_FLAG) - -#define WMI_SET_TDLS_SELF_MORE_DATA_ACK_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_MOREDATA_FLAG) -#define WMI_GET_TDLS_SELF_MORE_DATA_ACK_UAPSD(pset_cmd) \ - WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_MOREDATA_FLAG) + (((pset_cmd)->tdls_puapsd_mask & (0x3 << WMI_TDLS_QOS_SP_FLAG)) >> WMI_TDLS_QOS_SP_FLAG) +#define WMI_SET_TDLS_SELF_MORE_DATA_ACK_UAPSD(pset_cmd) \ + WMI_TDLS_SELF_SET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_MOREDATA_FLAG) +#define WMI_GET_TDLS_SELF_MORE_DATA_ACK_UAPSD(pset_cmd) \ + WMI_TDLS_SELF_GET_QOS_FLAG(pset_cmd, WMI_TDLS_QOS_MOREDATA_FLAG) typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** new TDLS state for peer (wmi_tdls_peer_state) */ - A_UINT32 peer_state; - /* The TLV for wmi_tdls_peer_capabilities will follow. - * wmi_tdls_peer_capabilities peer_caps; - */ - /** Followed by the variable length TLV chan_info: - * wmi_channel chan_info[] */ + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** new TDLS state for peer (wmi_tdls_peer_state) */ + A_UINT32 peer_state; + /* The TLV for wmi_tdls_peer_capabilities will follow. + * wmi_tdls_peer_capabilities peer_caps; + */ + /** Followed by the variable length TLV chan_info: + * wmi_channel chan_info[] */ } wmi_tdls_peer_update_cmd_fixed_param; /* WMI_TDLS_SET_OFFCHAN_MODE_CMDID */ - /* bitmap 20, 40, 80 or 160 MHz wide channel */ -#define WMI_TDLS_OFFCHAN_20MHZ 0x1 /* 20 MHz wide channel */ -#define WMI_TDLS_OFFCHAN_40MHZ 0x2 /* 40 MHz wide channel */ -#define WMI_TDLS_OFFCHAN_80MHZ 0x4 /* 80 MHz wide channel */ -#define WMI_TDLS_OFFCHAN_160MHZ 0x8 /* 160 MHz wide channel */ - +#define WMI_TDLS_OFFCHAN_20MHZ 0x1 /* 20 MHz wide channel */ +#define WMI_TDLS_OFFCHAN_40MHZ 0x2 /* 40 MHz wide channel */ +#define WMI_TDLS_OFFCHAN_80MHZ 0x4 /* 80 MHz wide channel */ +#define WMI_TDLS_OFFCHAN_160MHZ 0x8 /* 160 MHz wide channel */ enum wmi_tdls_offchan_mode { - WMI_TDLS_ENABLE_OFFCHANNEL, - WMI_TDLS_DISABLE_OFFCHANNEL + WMI_TDLS_ENABLE_OFFCHANNEL, + WMI_TDLS_DISABLE_OFFCHANNEL }; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** Enable/Disable TDLS offchannel */ - A_UINT32 offchan_mode; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /* Is peer initiator or responder of TDLS setup request */ - A_UINT32 is_peer_responder; - /* off channel number*/ - A_UINT32 offchan_num; - /* off channel bandwidth bitmap, e.g. WMI_OFFCHAN_20MHZ */ - A_UINT32 offchan_bw_bitmap; - /* operating class for offchan */ - A_UINT32 offchan_oper_class; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** Enable/Disable TDLS offchannel */ + A_UINT32 offchan_mode; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /* Is peer initiator or responder of TDLS setup request */ + A_UINT32 is_peer_responder; + /* off channel number */ + A_UINT32 offchan_num; + /* off channel bandwidth bitmap, e.g. WMI_OFFCHAN_20MHZ */ + A_UINT32 offchan_bw_bitmap; + /* operating class for offchan */ + A_UINT32 offchan_oper_class; } wmi_tdls_set_offchan_mode_cmd_fixed_param; - /** TDLS EVENTS */ enum wmi_tdls_peer_notification { - /** tdls discovery recommended for peer (based - * on tx bytes per second > tx_discover threshold) */ - WMI_TDLS_SHOULD_DISCOVER, - /** tdls link tear down recommended for peer - * due to tx bytes per second below tx_teardown_threshold - * NB: this notification sent once */ - WMI_TDLS_SHOULD_TEARDOWN, - /** tx peer TDLS link tear down complete */ - WMI_TDLS_PEER_DISCONNECTED, - /** TDLS/BT role change notification for connection tracker */ - WMI_TDLS_CONNECTION_TRACKER_NOTIFICATION, + /** tdls discovery recommended for peer (based + * on tx bytes per second > tx_discover threshold) */ + WMI_TDLS_SHOULD_DISCOVER, + /** tdls link tear down recommended for peer + * due to tx bytes per second below tx_teardown_threshold + * NB: this notification sent once */ + WMI_TDLS_SHOULD_TEARDOWN, + /** tx peer TDLS link tear down complete */ + WMI_TDLS_PEER_DISCONNECTED, + /** TDLS/BT role change notification for connection tracker */ + WMI_TDLS_CONNECTION_TRACKER_NOTIFICATION, }; enum wmi_tdls_peer_reason { - /** tdls teardown recommended due to low transmits */ - WMI_TDLS_TEARDOWN_REASON_TX, - /** tdls link tear down recommended due to poor RSSI */ - WMI_TDLS_TEARDOWN_REASON_RSSI, - /** tdls link tear down recommended due to offchannel scan */ - WMI_TDLS_TEARDOWN_REASON_SCAN, - /** tdls peer disconnected due to peer deletion */ - WMI_TDLS_DISCONNECTED_REASON_PEER_DELETE, - /** tdls peer disconnected due to PTR timeout */ - WMI_TDLS_TEARDOWN_REASON_PTR_TIMEOUT, - /** tdls peer disconnected due wrong PTR format */ - WMI_TDLS_TEARDOWN_REASON_BAD_PTR, - /** tdls peer not responding */ - WMI_TDLS_TEARDOWN_REASON_NO_RESPONSE, - /** tdls entered buffer STA role, TDLS connection tracker needs to handle this */ - WMI_TDLS_ENTER_BUF_STA, - /** tdls exited buffer STA role, TDLS connection tracker needs to handle this */ - WMI_TDLS_EXIT_BUF_STA, - /** BT entered busy mode, TDLS connection tracker needs to handle this */ - WMI_TDLS_ENTER_BT_BUSY_MODE, - /** BT exited busy mode, TDLS connection tracker needs to handle this */ - WMI_TDLS_EXIT_BT_BUSY_MODE, - /** TDLS module received a scan start event, TDLS connection tracker needs to handle this */ - WMI_TDLS_SCAN_STARTED_EVENT, - /** TDLS module received a scan complete event, TDLS connection tracker needs to handle this */ - WMI_TDLS_SCAN_COMPLETED_EVENT, + /** tdls teardown recommended due to low transmits */ + WMI_TDLS_TEARDOWN_REASON_TX, + /** tdls link tear down recommended due to poor RSSI */ + WMI_TDLS_TEARDOWN_REASON_RSSI, + /** tdls link tear down recommended due to offchannel scan */ + WMI_TDLS_TEARDOWN_REASON_SCAN, + /** tdls peer disconnected due to peer deletion */ + WMI_TDLS_DISCONNECTED_REASON_PEER_DELETE, + /** tdls peer disconnected due to PTR timeout */ + WMI_TDLS_TEARDOWN_REASON_PTR_TIMEOUT, + /** tdls peer disconnected due wrong PTR format */ + WMI_TDLS_TEARDOWN_REASON_BAD_PTR, + /** tdls peer not responding */ + WMI_TDLS_TEARDOWN_REASON_NO_RESPONSE, + /* + * tdls entered buffer STA role, TDLS connection tracker + * needs to handle this + */ + WMI_TDLS_ENTER_BUF_STA, + /* + * tdls exited buffer STA role, TDLS connection tracker + * needs to handle this + */ + WMI_TDLS_EXIT_BUF_STA, + /* BT entered busy mode, TDLS connection tracker needs to handle this */ + WMI_TDLS_ENTER_BT_BUSY_MODE, + /** BT exited busy mode, TDLS connection tracker needs to handle this */ + WMI_TDLS_EXIT_BT_BUSY_MODE, + /* + * TDLS module received a scan start event, TDLS connection tracker + * needs to handle this + */ + WMI_TDLS_SCAN_STARTED_EVENT, + /* + * TDLS module received a scan complete event, TDLS connection tracker + * needs to handle this + */ + WMI_TDLS_SCAN_COMPLETED_EVENT, }; /* WMI_TDLS_PEER_EVENTID */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_event_fixed_param */ - A_UINT32 tlv_header; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /** TDLS peer status (wmi_tdls_peer_notification)*/ - A_UINT32 peer_status; - /** TDLS peer reason (wmi_tdls_peer_reason) */ - A_UINT32 peer_reason; - /** unique id identifying the VDEV */ - A_UINT32 vdev_id; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_event_fixed_param */ + A_UINT32 tlv_header; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /** TDLS peer status (wmi_tdls_peer_notification)*/ + A_UINT32 peer_status; + /** TDLS peer reason (wmi_tdls_peer_reason) */ + A_UINT32 peer_reason; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; } wmi_tdls_peer_event_fixed_param; /* NOTE: wmi_vdev_mcc_bcn_intvl_change_event_fixed_param would be deprecated. Please - don't use this for any new implementations */ + don't use this for any new implementations */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_mcc_bcn_intvl_change_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* New beacon interval to be used for the specified VDEV suggested by firmware */ - A_UINT32 new_bcn_intvl; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_mcc_bcn_intvl_change_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* New beacon interval to be used for the specified VDEV suggested by firmware */ + A_UINT32 new_bcn_intvl; } wmi_vdev_mcc_bcn_intvl_change_event_fixed_param; /* WMI_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMDID */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param */ - A_UINT32 tlv_header; - /** 1: enable fw based adaptive ocs, - * 0: disable fw based adaptive ocs - */ - A_UINT32 enable; - /** This field contains the MAC identifier in order to lookup the appropriate OCS instance. */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param */ + A_UINT32 tlv_header; + /** 1: enable fw based adaptive ocs, + * 0: disable fw based adaptive ocs + */ + A_UINT32 enable; + /** This field contains the MAC identifier in order to lookup the appropriate OCS instance. */ + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; } wmi_resmgr_adaptive_ocs_enable_disable_cmd_fixed_param; /* WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID */ typedef struct { - /* Frequency of the channel for which the quota is set */ - A_UINT32 chan_mhz; - /* Requested channel time quota expressed as percentage */ - A_UINT32 channel_time_quota; + /* Frequency of the channel for which the quota is set */ + A_UINT32 chan_mhz; + /* Requested channel time quota expressed as percentage */ + A_UINT32 channel_time_quota; } wmi_resmgr_chan_time_quota; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resmgr_set_chan_time_quota_cmd_fixed_param */ - A_UINT32 tlv_header; - /** number of channel time quota command structures - * (wmi_resmgr_chan_time_quota) 1 or 2 - */ - A_UINT32 num_chans; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resmgr_set_chan_time_quota_cmd_fixed_param */ + A_UINT32 tlv_header; + /** number of channel time quota command structures + * (wmi_resmgr_chan_time_quota) 1 or 2 + */ + A_UINT32 num_chans; /* This TLV is followed by another TLV of array of bytes * A_UINT8 data[]; * This data array contains @@ -10426,19 +11427,19 @@ typedef struct { /* WMI_RESMGR_SET_CHAN_LATENCY_CMDID */ typedef struct { - /* Frequency of the channel for which the latency is set */ - A_UINT32 chan_mhz; - /* Requested channel latency in milliseconds */ - A_UINT32 latency; + /* Frequency of the channel for which the latency is set */ + A_UINT32 chan_mhz; + /* Requested channel latency in milliseconds */ + A_UINT32 latency; } wmi_resmgr_chan_latency; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resmgr_set_chan_latency_cmd_fixed_param */ - A_UINT32 tlv_header; - /** number of channel latency command structures - * (wmi_resmgr_chan_latency) 1 or 2 - */ - A_UINT32 num_chans; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_resmgr_set_chan_latency_cmd_fixed_param */ + A_UINT32 tlv_header; + /** number of channel latency command structures + * (wmi_resmgr_chan_latency) 1 or 2 + */ + A_UINT32 num_chans; /* This TLV is followed by another TLV of array of bytes * A_UINT8 data[]; * This data array contains @@ -10450,313 +11451,310 @@ typedef struct { /** STA SMPS Forced Mode */ typedef enum { - WMI_SMPS_FORCED_MODE_NONE = 0, - WMI_SMPS_FORCED_MODE_DISABLED, - WMI_SMPS_FORCED_MODE_STATIC, - WMI_SMPS_FORCED_MODE_DYNAMIC + WMI_SMPS_FORCED_MODE_NONE = 0, + WMI_SMPS_FORCED_MODE_DISABLED, + WMI_SMPS_FORCED_MODE_STATIC, + WMI_SMPS_FORCED_MODE_DYNAMIC } wmi_sta_smps_forced_mode; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** The mode of SMPS that is to be forced in the FW. */ - A_UINT32 forced_mode; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_cmd_fixed_param */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** The mode of SMPS that is to be forced in the FW. */ + A_UINT32 forced_mode; } wmi_sta_smps_force_mode_cmd_fixed_param; /** wlan HB commands */ #define WMI_WLAN_HB_ITEM_UDP 0x1 #define WMI_WLAN_HB_ITEM_TCP 0x2 -#define WMI_WLAN_HB_MAX_FILTER_SIZE 32 /* should be equal to WLAN_HB_MAX_FILTER_SIZE, - must be a multiple of 4 bytes */ +#define WMI_WLAN_HB_MAX_FILTER_SIZE 32 /* should be equal to WLAN_HB_MAX_FILTER_SIZE, must be a multiple of 4 bytes */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_hb_set_enable_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 enable; - A_UINT32 item; - A_UINT32 session; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_hb_set_enable_cmd_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 enable; + A_UINT32 item; + A_UINT32 session; } wmi_hb_set_enable_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_hb_set_tcp_params_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 srv_ip; - A_UINT32 dev_ip; - A_UINT32 seq; - A_UINT32 src_port; - A_UINT32 dst_port; - A_UINT32 interval; - A_UINT32 timeout; - A_UINT32 session; - wmi_mac_addr gateway_mac; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_hb_set_tcp_params_cmd_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 srv_ip; + A_UINT32 dev_ip; + A_UINT32 seq; + A_UINT32 src_port; + A_UINT32 dst_port; + A_UINT32 interval; + A_UINT32 timeout; + A_UINT32 session; + wmi_mac_addr gateway_mac; } wmi_hb_set_tcp_params_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_hb_set_tcp_pkt_filter_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 length; - A_UINT32 offset; - A_UINT32 session; - A_UINT8 filter[WMI_WLAN_HB_MAX_FILTER_SIZE]; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_hb_set_tcp_pkt_filter_cmd_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 length; + A_UINT32 offset; + A_UINT32 session; + A_UINT8 filter[WMI_WLAN_HB_MAX_FILTER_SIZE]; } wmi_hb_set_tcp_pkt_filter_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_hb_set_udp_params_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 srv_ip; - A_UINT32 dev_ip; - A_UINT32 src_port; - A_UINT32 dst_port; - A_UINT32 interval; - A_UINT32 timeout; - A_UINT32 session; - wmi_mac_addr gateway_mac; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_hb_set_udp_params_cmd_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 srv_ip; + A_UINT32 dev_ip; + A_UINT32 src_port; + A_UINT32 dst_port; + A_UINT32 interval; + A_UINT32 timeout; + A_UINT32 session; + wmi_mac_addr gateway_mac; } wmi_hb_set_udp_params_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_hb_set_udp_pkt_filter_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 length; - A_UINT32 offset; - A_UINT32 session; - A_UINT8 filter[WMI_WLAN_HB_MAX_FILTER_SIZE]; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_hb_set_udp_pkt_filter_cmd_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 length; + A_UINT32 offset; + A_UINT32 session; + A_UINT8 filter[WMI_WLAN_HB_MAX_FILTER_SIZE]; } wmi_hb_set_udp_pkt_filter_cmd_fixed_param; /** wlan HB events */ typedef enum { - WMI_WLAN_HB_REASON_UNKNOWN = 0, - WMI_WLAN_HB_REASON_TCP_TIMEOUT = 1, - WMI_WLAN_HB_REASON_UDP_TIMEOUT = 2, + WMI_WLAN_HB_REASON_UNKNOWN = 0, + WMI_WLAN_HB_REASON_TCP_TIMEOUT = 1, + WMI_WLAN_HB_REASON_UDP_TIMEOUT = 2, } WMI_HB_WAKEUP_REASON; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_hb_ind_event_fixed_param */ - A_UINT32 vdev_id; /* unique id identifying the VDEV */ - A_UINT32 session; /* Session ID from driver */ - A_UINT32 reason; /* wakeup reason */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_hb_ind_event_fixed_param */ + A_UINT32 vdev_id; /* unique id identifying the VDEV */ + A_UINT32 session; /* Session ID from driver */ + A_UINT32 reason; /* wakeup reason */ } wmi_hb_ind_event_fixed_param; /** WMI_STA_SMPS_PARAM_CMDID */ typedef enum { - /** RSSI threshold to enter Dynamic SMPS mode from inactive mode */ - WMI_STA_SMPS_PARAM_UPPER_RSSI_THRESH = 0, - /** RSSI threshold to enter Stalled-D-SMPS mode from D-SMPS mode or - * to enter D-SMPS mode from Stalled-D-SMPS mode */ - WMI_STA_SMPS_PARAM_STALL_RSSI_THRESH = 1, - /** RSSI threshold to disable SMPS modes */ - WMI_STA_SMPS_PARAM_LOWER_RSSI_THRESH = 2, - /** Upper threshold for beacon-RSSI. Used to reduce RX chainmask. */ - WMI_STA_SMPS_PARAM_UPPER_BRSSI_THRESH = 3, - /** Lower threshold for beacon-RSSI. Used to increase RX chainmask. */ - WMI_STA_SMPS_PARAM_LOWER_BRSSI_THRESH = 4, - /** Enable/Disable DTIM 1chRx feature */ - WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5 + /** RSSI threshold to enter Dynamic SMPS mode from inactive mode */ + WMI_STA_SMPS_PARAM_UPPER_RSSI_THRESH = 0, + /** RSSI threshold to enter Stalled-D-SMPS mode from D-SMPS mode or + * to enter D-SMPS mode from Stalled-D-SMPS mode */ + WMI_STA_SMPS_PARAM_STALL_RSSI_THRESH = 1, + /** RSSI threshold to disable SMPS modes */ + WMI_STA_SMPS_PARAM_LOWER_RSSI_THRESH = 2, + /** Upper threshold for beacon-RSSI. Used to reduce RX chainmask. */ + WMI_STA_SMPS_PARAM_UPPER_BRSSI_THRESH = 3, + /** Lower threshold for beacon-RSSI. Used to increase RX chainmask. */ + WMI_STA_SMPS_PARAM_LOWER_BRSSI_THRESH = 4, + /** Enable/Disable DTIM 1chRx feature */ + WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5 } wmi_sta_smps_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_sta_smps_param_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** SMPS parameter (see wmi_sta_smps_param) */ - A_UINT32 param; - /** Value of SMPS parameter */ - A_UINT32 value; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_sta_smps_param_cmd_fixed_param */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** SMPS parameter (see wmi_sta_smps_param) */ + A_UINT32 param; + /** Value of SMPS parameter */ + A_UINT32 value; } wmi_sta_smps_param_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mcc_sched_sta_traffic_stats */ - A_UINT32 tlv_header; - /* TX stats */ - A_UINT32 txBytesPushed; - A_UINT32 txPacketsPushed; - /* RX stats */ - A_UINT32 rxBytesRcvd; - A_UINT32 rxPacketsRcvd; - A_UINT32 rxTimeTotal; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mcc_sched_sta_traffic_stats */ + A_UINT32 tlv_header; + /* TX stats */ + A_UINT32 txBytesPushed; + A_UINT32 txPacketsPushed; + /* RX stats */ + A_UINT32 rxBytesRcvd; + A_UINT32 rxPacketsRcvd; + A_UINT32 rxTimeTotal; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_mcc_sched_sta_traffic_stats; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mcc_sched_traffic_stats_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Duration over which the host stats were collected */ - A_UINT32 duration; - /** Number of stations filled in following stats array */ - A_UINT32 num_sta; - /* Following this struct are the TLVs: - * wmi_mcc_sched_sta_traffic_stats mcc_sched_sta_traffic_stats_list; - */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mcc_sched_traffic_stats_cmd_fixed_param */ + A_UINT32 tlv_header; + /** Duration over which the host stats were collected */ + A_UINT32 duration; + /** Number of stations filled in following stats array */ + A_UINT32 num_sta; + /* Following this struct are the TLVs: + * wmi_mcc_sched_sta_traffic_stats mcc_sched_sta_traffic_stats_list; + */ } wmi_mcc_sched_traffic_stats_cmd_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_enable_cmd_fixed_param */ - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /*Batch scan enable command parameters*/ - A_UINT32 scanInterval; - A_UINT32 numScan2Batch; - A_UINT32 bestNetworks; - A_UINT32 rfBand; - A_UINT32 rtt; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_enable_cmd_fixed_param */ + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /*Batch scan enable command parameters */ + A_UINT32 scanInterval; + A_UINT32 numScan2Batch; + A_UINT32 bestNetworks; + A_UINT32 rfBand; + A_UINT32 rtt; } wmi_batch_scan_enable_cmd_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_enabled_event_fixed_param */ - A_UINT32 supportedMscan; -} wmi_batch_scan_enabled_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_enabled_event_fixed_param */ + A_UINT32 supportedMscan; +} wmi_batch_scan_enabled_event_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_disable_cmd_fixed_param */ - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - A_UINT32 param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_disable_cmd_fixed_param */ +/* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + A_UINT32 param; } wmi_batch_scan_disable_cmd_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_trigger_result_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - A_UINT32 param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_batch_scan_trigger_result_cmd_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + A_UINT32 param; } wmi_batch_scan_trigger_result_cmd_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; - wmi_mac_addr bssid; /* BSSID */ - wmi_ssid ssid; /* SSID */ - A_UINT32 ch; /* Channel */ - A_UINT32 rssi; /* RSSI or Level */ - /* Timestamp when Network was found. Used to calculate age based on timestamp in GET_RSP msg header */ - A_UINT32 timestamp; +typedef struct { + A_UINT32 tlv_header; + wmi_mac_addr bssid; /* BSSID */ + wmi_ssid ssid; /* SSID */ + A_UINT32 ch; /* Channel */ + A_UINT32 rssi; /* RSSI or Level */ + /* Timestamp when Network was found. Used to calculate age based on timestamp in GET_RSP msg header */ + A_UINT32 timestamp; } wmi_batch_scan_result_network_info; -typedef struct -{ - A_UINT32 tlv_header; - A_UINT32 scanId; /* Scan List ID. */ - /* No of AP in a Scan Result. Should be same as bestNetwork in SET_REQ msg */ - A_UINT32 numNetworksInScanList; - A_UINT32 netWorkStartIndex; /* indicate the start index of network info*/ +typedef struct { + A_UINT32 tlv_header; + A_UINT32 scanId; /* Scan List ID. */ + /* No of AP in a Scan Result. Should be same as bestNetwork in SET_REQ msg */ + A_UINT32 numNetworksInScanList; + A_UINT32 netWorkStartIndex; /* indicate the start index of network info */ } wmi_batch_scan_result_scan_list; -#define LPI_IE_BITMAP_BSSID 0x00000001 /* if this bit is set, bssid of the scan response frame is sent as the first IE in the data buffer sent to LOWI LP. */ -#define LPI_IE_BITMAP_IS_PROBE 0x00000002 /* send true or false based on scan response frame being a Probe Rsp or not */ -#define LPI_IE_BITMAP_SSID 0x00000004 /* send ssid from received scan response frame */ -#define LPI_IE_BITMAP_RSSI 0x00000008 /* send RSSI value reported by HW for the received scan response after adjusting with noise floor */ -#define LPI_IE_BITMAP_CHAN 0x00000010 /* send channel number from the received scan response */ -#define LPI_IE_BITMAP_AP_TX_PWR 0x00000020 /* send Tx power from TPC IE of scan rsp */ -#define LPI_IE_BITMAP_TX_RATE 0x00000040 /* send rate of the received frame as reported by HW. */ -#define LPI_IE_BITMAP_80211_MC_SUPPORT 0x00000080 /* send true or false based on the received scan rsp was from a 11mc supported AP or not. */ -#define LPI_IE_BITMAP_TSF_TIMER_VALUE 0x00000100 /* send timestamp reported in the received scan rsp frame. */ -#define LPI_IE_BITMAP_AGE_OF_MEASUREMENT 0x00000200 /* (current system time - received time) = duration of time scan rsp frame data is kept in the buffer before sending to LOWI LP. */ +#define LPI_IE_BITMAP_BSSID 0x00000001 /* if this bit is set, bssid of the scan response frame is sent as the first IE in the data buffer sent to LOWI LP.*/ +#define LPI_IE_BITMAP_IS_PROBE 0x00000002 /*send true or false based on scan response frame being a Probe Rsp or not*/ +#define LPI_IE_BITMAP_SSID 0x00000004 /*send ssid from received scan response frame*/ +#define LPI_IE_BITMAP_RSSI 0x00000008 /* end RSSI value reported by HW for the received scan response after adjusting with noise floor*/ +#define LPI_IE_BITMAP_CHAN 0x00000010 /*send channel number from the received scan response*/ +#define LPI_IE_BITMAP_AP_TX_PWR 0x00000020 /* sen Tx power from TPC IE of scan rsp*/ +#define LPI_IE_BITMAP_TX_RATE 0x00000040 /*send rate of the received frame as reported by HW.*/ +#define LPI_IE_BITMAP_80211_MC_SUPPORT 0x00000080 /*send true or false based on the received scan rsp was from a 11mc supported AP or not.*/ +#define LPI_IE_BITMAP_TSF_TIMER_VALUE 0x00000100 /*send timestamp reported in the received scan rsp frame.*/ +#define LPI_IE_BITMAP_AGE_OF_MEASUREMENT 0x00000200 /* current system time - received time) = duration of time scan rsp frame data is kept in the buffer before sending to LOWI LP.*/ /* * TEMPORARY alias of incorrect old name the correct name. * This alias will be removed once all references to the old name have been fixed. */ #define LPI_IE_BITMAP_AGE_OF_MESAUREMENT LPI_IE_BITMAP_AGE_OF_MEASUREMENT -#define LPI_IE_BITMAP_CONN_STATUS 0x00000400 /* If an infra STA is active and connected to an AP, true value is sent else false. */ -#define LPI_IE_BITMAP_MSAP_IE 0x00000800 /* info on the vendor specific proprietary IE MSAP */ -#define LPI_IE_BITMAP_SEC_STATUS 0x00001000 /* we indicate true or false based on if the AP has WPA or RSN security enabled */ -#define LPI_IE_BITMAP_DEVICE_TYPE 0x00002000 /* info about the beacons coming from an AP or P2P or NAN device. */ -#define LPI_IE_BITMAP_CHAN_IS_PASSIVE 0x00004000 /* info on whether the scan rsp was received from a passive channel */ -#define LPI_IE_BITMAP_DWELL_TIME 0x00008000 /* send the scan dwell time of the channel on which the current scan rsp frame was received. */ -#define LPI_IE_BITMAP_BAND_CENTER_FREQ1 0x00010000 /* the center frequencies in case AP is supporting wider channels than 20 MHz */ -#define LPI_IE_BITMAP_BAND_CENTER_FREQ2 0x00020000 /* same as above */ -#define LPI_IE_BITMAP_PHY_MODE 0x00040000 /* PHY mode indicates a, b, ,g, ac and other combinations */ -#define LPI_IE_BITMAP_SCAN_MODULE_ID 0x00080000 /* scan module id indicates the scan client who originated the scan */ -#define LPI_IE_BITMAP_SCAN_ID 0x00100000 /* extscan inserts the scan cycle count for this value; other scan clients can insert the scan id of the scan, if needed. */ -#define LPI_IE_BITMAP_FLAGS 0x00200000 /* reserved as a bitmap to indicate more scan information; one such use being to indicate if the on-going scan is interrupted or not */ -#define LPI_IE_BITMAP_CACHING_REQD 0x00400000 /* extscan will use this field to indicate if this frame info needs to be cached in LOWI LP or not */ -#define LPI_IE_BITMAP_REPORT_CONTEXT_HUB 0x00800000 /* extscan will use this field to indicate to LOWI LP whether to report result to context hub or not. */ +#define LPI_IE_BITMAP_CONN_STATUS 0x00000400 /* If an infra STA is active and connected to an AP, true value is sent else false.*/ +#define LPI_IE_BITMAP_MSAP_IE 0x00000800 /* info on the vendor specific proprietary IE MSAP*/ +#define LPI_IE_BITMAP_SEC_STATUS 0x00001000 /* we indicate true or false based on if the AP has WPA or RSN security enabled*/ +#define LPI_IE_BITMAP_DEVICE_TYPE 0x00002000 /* info about the beacons coming from an AP or P2P or NAN device.*/ +#define LPI_IE_BITMAP_CHAN_IS_PASSIVE 0x00004000 /* info on whether the scan rsp was received from a passive channel*/ +#define LPI_IE_BITMAP_DWELL_TIME 0x00008000 /* send the scan dwell time of the channel on which the current scan rsp frame was received.*/ +#define LPI_IE_BITMAP_BAND_CENTER_FREQ1 0x00010000 /* the center frequencies in case AP is supporting wider channels than 20 MHz*/ +#define LPI_IE_BITMAP_BAND_CENTER_FREQ2 0x00020000 /* same as above*/ +#define LPI_IE_BITMAP_PHY_MODE 0x00040000 /* PHY mode indicates a, b, ,g, ac and other combinations*/ +#define LPI_IE_BITMAP_SCAN_MODULE_ID 0x00080000 /* scan module id indicates the scan client who originated the scan*/ +#define LPI_IE_BITMAP_SCAN_ID 0x00100000 /*extscan inserts the scan cycle count for this value; other scan clients can insert the scan id of the scan, if needed.*/ +#define LPI_IE_BITMAP_FLAGS 0x00200000 /* reserved as a bitmap to indicate more scan information; one such use being to indicate if the on-going scan is interrupted or not*/ +#define LPI_IE_BITMAP_CACHING_REQD 0x00400000 /*extscan will use this field to indicate if this frame info needs to be cached in LOWI LP or not*/ +/* + * extscan will use this field to indicate to + * LOWI LP whether to report result to context hub or not + */ +#define LPI_IE_BITMAP_REPORT_CONTEXT_HUB 0x00800000 #define LPI_IE_BITMAP_ALL 0xFFFFFFFF typedef struct { - A_UINT32 tlv_header; - /**A_BOOL indicates LPI mgmt snooping enable/disable*/ - A_UINT32 enable; - /**LPI snooping mode*/ - A_UINT32 snooping_mode; - /** LPI interested IEs in snooping context */ - A_UINT32 ie_bitmap; + A_UINT32 tlv_header; + /**A_BOOL indicates LPI mgmt snooping enable/disable*/ + A_UINT32 enable; + /**LPI snooping mode*/ + A_UINT32 snooping_mode; + /** LPI interested IEs in snooping context */ + A_UINT32 ie_bitmap; } wmi_lpi_mgmt_snooping_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */ - /** Scan ID */ - A_UINT32 scan_id; - /** Scan requestor ID */ - A_UINT32 scan_req_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** LPI interested IEs in scan context */ - A_UINT32 ie_bitmap; - /** Scan Priority, input to scan scheduler */ - A_UINT32 scan_priority; - /** dwell time in msec on active channels */ - A_UINT32 dwell_time_active; - /** dwell time in msec on passive channels */ - A_UINT32 dwell_time_passive; - /** min time in msec on the BSS channel,only valid if atleast one VDEV is active*/ - A_UINT32 min_rest_time; - /** max rest time in msec on the BSS channel,only valid if at least one VDEV is active*/ - /** the scanner will rest on the bss channel at least min_rest_time. after min_rest_time the scanner - * will start checking for tx/rx activity on all VDEVs. if there is no activity the scanner will - * switch to off channel. if there is activity the scanner will let the radio on the bss channel - * until max_rest_time expires.at max_rest_time scanner will switch to off channel - * irrespective of activity. activity is determined by the idle_time parameter. - */ - A_UINT32 max_rest_time; - /** time before sending next set of probe requests. - * The scanner keeps repeating probe requests transmission with period specified by repeat_probe_time. - * The number of probe requests specified depends on the ssid_list and bssid_list - */ - A_UINT32 repeat_probe_time; - /** time in msec between 2 consequetive probe requests with in a set. */ - A_UINT32 probe_spacing_time; - /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity */ - A_UINT32 idle_time; - /** maximum time in msec allowed for scan */ - A_UINT32 max_scan_time; - /** delay in msec before sending first probe request after switching to a channel */ - A_UINT32 probe_delay; - /** Scan control flags */ - A_UINT32 scan_ctrl_flags; - /** Burst duration time in msec*/ - A_UINT32 burst_duration; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */ + /** Scan ID */ + A_UINT32 scan_id; + /** Scan requestor ID */ + A_UINT32 scan_req_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** LPI interested IEs in scan context */ + A_UINT32 ie_bitmap; + /** Scan Priority, input to scan scheduler */ + A_UINT32 scan_priority; + /** dwell time in msec on active channels */ + A_UINT32 dwell_time_active; + /** dwell time in msec on passive channels */ + A_UINT32 dwell_time_passive; + /** min time in msec on the BSS channel,only valid if atleast one VDEV is active*/ + A_UINT32 min_rest_time; + /** max rest time in msec on the BSS channel,only valid if at least one VDEV is active*/ + /** the scanner will rest on the bss channel at least min_rest_time. after min_rest_time the scanner + * will start checking for tx/rx activity on all VDEVs. if there is no activity the scanner will + * switch to off channel. if there is activity the scanner will let the radio on the bss channel + * until max_rest_time expires.at max_rest_time scanner will switch to off channel + * irrespective of activity. activity is determined by the idle_time parameter. + */ + A_UINT32 max_rest_time; + /** time before sending next set of probe requests. + * The scanner keeps repeating probe requests transmission with period specified by repeat_probe_time. + * The number of probe requests specified depends on the ssid_list and bssid_list + */ + A_UINT32 repeat_probe_time; + /** time in msec between 2 consequetive probe requests with in a set. */ + A_UINT32 probe_spacing_time; + /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity */ + A_UINT32 idle_time; + /** maximum time in msec allowed for scan */ + A_UINT32 max_scan_time; + /** delay in msec before sending first probe request after switching to a channel */ + A_UINT32 probe_delay; + /** Scan control flags */ + A_UINT32 scan_ctrl_flags; + /** Burst duration time in msec*/ + A_UINT32 burst_duration; - /** # if channels to scan. In the TLV channel_list[] */ - A_UINT32 num_chan; - /** number of bssids. In the TLV bssid_list[] */ - A_UINT32 num_bssid; - /** number of ssid. In the TLV ssid_list[] */ - A_UINT32 num_ssids; - /** number of bytes in ie data. In the TLV ie_data[] */ - A_UINT32 ie_len; + /** # if channels to scan. In the TLV channel_list[] */ + A_UINT32 num_chan; + /** number of bssids. In the TLV bssid_list[] */ + A_UINT32 num_bssid; + /** number of ssid. In the TLV ssid_list[] */ + A_UINT32 num_ssids; + /** number of bytes in ie data. In the TLV ie_data[] */ + A_UINT32 ie_len; /** - * TLV (tag length value) parameters follow the scan_cmd + * TLV (tag length value ) parameters follow the scan_cmd * structure. The TLV's are: * A_UINT32 channel_list[]; * wmi_ssid ssid_list[]; @@ -10766,93 +11764,89 @@ typedef struct { } wmi_lpi_start_scan_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */ - /** Scan requestor ID */ - A_UINT32 scan_req_id; - /** Scan ID */ - A_UINT32 scan_id; - /** - * Req Type - * req_type should be WMI_SCAN_STOP_ONE, WMI_SCN_STOP_VAP_ALL or WMI_SCAN_STOP_ALL - * WMI_SCAN_STOP_ONE indicates to stop a specific scan with scan_id - * WMI_SCN_STOP_VAP_ALL indicates to stop all scan requests on a specific vDev with vdev_id - * WMI_SCAN_STOP_ALL indicates to stop all scan requests in both Scheduler's queue and Scan Engine - */ - A_UINT32 req_type; - /** - * vDev ID - * used when req_type equals to WMI_SCN_STOP_VAP_ALL, it indexed the vDev on which to stop the scan - */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */ + /** Scan requestor ID */ + A_UINT32 scan_req_id; + /** Scan ID */ + A_UINT32 scan_id; + /** + * Req Type + * req_type should be WMI_SCAN_STOP_ONE, WMI_SCN_STOP_VAP_ALL or WMI_SCAN_STOP_ALL + * WMI_SCAN_STOP_ONE indicates to stop a specific scan with scan_id + * WMI_SCN_STOP_VAP_ALL indicates to stop all scan requests on a specific vDev with vdev_id + * WMI_SCAN_STOP_ALL indicates to stop all scan requests in both Scheduler's queue and Scan Engine + */ + A_UINT32 req_type; + /** + * vDev ID + * used when req_type equals to WMI_SCN_STOP_VAP_ALL, it indexed the vDev on which to stop the scan + */ + A_UINT32 vdev_id; } wmi_lpi_stop_scan_cmd_fixed_param; typedef enum { - WMI_LPI_DEVICE_TYPE_AP = 1, - WMI_LPI_DEVICE_TYPE_P2P = 2, - WMI_LPI_DEVICE_TYPE_NAN = 3, + WMI_LPI_DEVICE_TYPE_AP = 1, + WMI_LPI_DEVICE_TYPE_P2P = 2, + WMI_LPI_DEVICE_TYPE_NAN = 3, } wmi_lpi_device_type; -typedef struct -{ - A_UINT32 tlv_header; - /** Scan requestor ID */ - A_UINT32 scan_req_id; - A_UINT32 ie_bitmap; - A_UINT32 data_len; -} wmi_lpi_result_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; + /** Scan requestor ID */ + A_UINT32 scan_req_id; + A_UINT32 ie_bitmap; + A_UINT32 data_len; +} wmi_lpi_result_event_fixed_param; typedef enum { - /** User scan Request completed */ - WMI_LPI_STATUS_SCAN_REQ_COMPLED = 0, - /** User Request was never serviced */ - WMI_LPI_STATUS_DROPPED_REQ = 1, - /** Illegal channel Req */ - WMI_LPI_STATUS_ILLEGAL_CHAN_REQ = 2, - /** Illegal Operation Req */ - WMI_LPI_STATUS_ILLEGAL_OPER_REQ = 3, - /** Request Aborted */ - WMI_LPI_STATUS_REQ_ABORTED = 4, - /** Request Timed Out */ - WMI_LPI_STATUS_REQ_TIME_OUT = 5, - /** Medium Busy, already there - * is a scan is going on */ - WMI_LPI_STATUS_MEDIUM_BUSY = 6, - /** Extscan is the scan client whose scan complete event is triggered */ - WMI_LPI_STATUS_EXTSCAN_CYCLE_AND_SCAN_REQ_COMPLETED = 7, + /** User scan Request completed */ + WMI_LPI_STATUS_SCAN_REQ_COMPLED = 0, + /** User Request was never serviced */ + WMI_LPI_STATUS_DROPPED_REQ = 1, + /** Illegal channel Req */ + WMI_LPI_STATUS_ILLEGAL_CHAN_REQ = 2, + /** Illegal Operation Req */ + WMI_LPI_STATUS_ILLEGAL_OPER_REQ = 3, + /** Request Aborted */ + WMI_LPI_STATUS_REQ_ABORTED = 4, + /** Request Timed Out */ + WMI_LPI_STATUS_REQ_TIME_OUT = 5, + /** Medium Busy, already there + * is a scan is going on */ + WMI_LPI_STATUS_MEDIUM_BUSY = 6, + /* Extscan is the scan client whose scan complete event is triggered */ + WMI_LPI_STATUS_EXTSCAN_CYCLE_AND_SCAN_REQ_COMPLETED = 7, } wmi_lpi_staus; -typedef struct -{ - A_UINT32 tlv_header; - wmi_lpi_staus status; - /** Scan requestor ID */ - A_UINT32 scan_req_id; -} wmi_lpi_status_event_fixed_param; - - -typedef struct -{ - A_UINT32 tlv_header; - wmi_mac_addr bssid; - wmi_ssid ssid; - A_UINT32 freq; - A_UINT32 rssi; - A_UINT32 vdev_id; -} wmi_lpi_handoff_event_fixed_param; -typedef struct -{ - A_UINT32 tlv_header; - A_UINT32 timestamp; /*timestamp of batch scan event*/ - A_UINT32 numScanLists; /*number of scan in this event*/ - A_UINT32 isLastResult; /*is this event a last event of the whole batch scan*/ -} wmi_batch_scan_result_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; + wmi_lpi_staus status; + /** Scan requestor ID */ + A_UINT32 scan_req_id; +} wmi_lpi_status_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_noa_event_fixed_param */ - A_UINT32 vdev_id; -/* This TLV is followed by p2p_noa_info for vdev : - * wmi_p2p_noa_info p2p_noa_info; - */ + A_UINT32 tlv_header; + wmi_mac_addr bssid; + wmi_ssid ssid; + A_UINT32 freq; + A_UINT32 rssi; + A_UINT32 vdev_id; +} wmi_lpi_handoff_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 timestamp; /*timestamp of batch scan event */ + A_UINT32 numScanLists; /*number of scan in this event */ + A_UINT32 isLastResult; /*is this event a last event of the whole batch scan */ +} wmi_batch_scan_result_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_p2p_noa_event_fixed_param */ + A_UINT32 vdev_id; + /* This TLV is followed by p2p_noa_info for vdev : + * wmi_p2p_noa_info p2p_noa_info; + */ } wmi_p2p_noa_event_fixed_param; #define WMI_RFKILL_CFG_RADIO_LEVEL_OFFSET 6 @@ -10865,203 +11859,215 @@ typedef struct { #define WMI_RFKILL_CFG_PIN_AS_GPIO_MASK 0xf typedef struct { - /** TLV tag and len; tag equals - * */ - A_UINT32 tlv_header; - /** gpip pin number */ - A_UINT32 gpio_pin_num; - /** gpio interupt type */ - A_UINT32 int_type; - /** RF radio status */ - A_UINT32 radio_state; + /** TLV tag and len; tag equals + * */ + A_UINT32 tlv_header; + /** gpip pin number */ + A_UINT32 gpio_pin_num; + /** gpio interupt type */ + A_UINT32 int_type; + /** RF radio status */ + A_UINT32 radio_state; } wmi_rfkill_mode_param; typedef enum { - WMI_SET_LED_SYS_POWEROFF, - WMI_SET_LED_SYS_S3_SUSPEND, - WMI_SET_LED_SYS_S4_S5, - WMI_SET_LED_SYS_DRIVER_DISABLE, - WMI_SET_LED_SYS_WAKEUP, - WMI_SET_LED_SYS_ALWAYS_ON, /* just for test! */ - WMI_SET_LED_SYS_POWERON, + WMI_SET_LED_SYS_POWEROFF, + WMI_SET_LED_SYS_S3_SUSPEND, + WMI_SET_LED_SYS_S4_S5, + WMI_SET_LED_SYS_DRIVER_DISABLE, + WMI_SET_LED_SYS_WAKEUP, + WMI_SET_LED_SYS_ALWAYS_ON, /* just for test! */ + WMI_SET_LED_SYS_POWERON, } wmi_led_sys_state_param; typedef enum { - WMI_CONFIG_LED_TO_VDD = 0, - WMI_CONFIG_LED_TO_GND = 1, + WMI_CONFIG_LED_TO_VDD = 0, + WMI_CONFIG_LED_TO_GND = 1, } wmi_config_led_connect_type; typedef enum { - WMI_CONFIG_LED_NOT_WITH_BT = 0, - WMI_CONFIG_LED_WITH_BT = 1, + WMI_CONFIG_LED_NOT_WITH_BT = 0, + WMI_CONFIG_LED_WITH_BT = 1, } wmi_config_led_with_bt_flag; typedef enum { - WMI_CONFIG_LED_DISABLE = 0, - WMI_CONFIG_LED_ENABLE = 1, + WMI_CONFIG_LED_DISABLE = 0, + WMI_CONFIG_LED_ENABLE = 1, } wmi_config_led_enable_flag; typedef enum { - WMI_CONFIG_LED_HIGH_UNSPECIFIED = 0, - WMI_CONFIG_LED_HIGH_OFF = 1, - WMI_CONFIG_LED_HIGH_ON = 2, + WMI_CONFIG_LED_HIGH_UNSPECIFIED = 0, + WMI_CONFIG_LED_HIGH_OFF = 1, + WMI_CONFIG_LED_HIGH_ON = 2, } wmi_config_led_on_flag; typedef enum { - WMI_CONFIG_LED_UNSPECIFIED = 0, - WMI_CONFIG_LED_ON = 1, - WMI_CONFIG_LED_OFF = 2, - WMI_CONFIG_LED_DIM = 3, - WMI_CONFIG_LED_BLINK = 4, - WMI_CONFIG_LED_TXRX = 5, + WMI_CONFIG_LED_UNSPECIFIED = 0, + WMI_CONFIG_LED_ON = 1, + WMI_CONFIG_LED_OFF = 2, + WMI_CONFIG_LED_DIM = 3, + WMI_CONFIG_LED_BLINK = 4, + WMI_CONFIG_LED_TXRX = 5, } wmi_config_led_operation_type; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_pdev_set_led_config_cmd_fixed_param */ - A_UINT32 tlv_header; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_led_config_cmd_fixed_param */ + A_UINT32 tlv_header; /* Set GPIO pin */ - A_UINT32 led_gpio_pin; + A_UINT32 led_gpio_pin; /* Set connect type defined in wmi_config_led_connect_type */ - A_UINT32 connect_type; - /* Set flag defined in wmi_config_led_with_bt_flag*/ - A_UINT32 with_bt; + A_UINT32 connect_type; + /* Set flag defined in wmi_config_led_with_bt_flag */ + A_UINT32 with_bt; /* Set LED enablement defined in wmi_config_led_enable_flag */ A_UINT32 led_enable; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /* see wmi_config_led_operation_type enum */ - A_UINT32 led_operation_type; - /* see wmi_config_led_on_flag enum */ - A_UINT32 led_on_flag; /* configure high/low on/off sense */ - A_UINT32 led_on_interval; /* for blink function; unit: ms */ - A_UINT32 led_off_interval; /* for blink function; unit: ms */ - A_UINT32 led_repeat_cnt; /* for blink function: how many blinks */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* see wmi_config_led_operation_type enum */ + A_UINT32 led_operation_type; + /* see wmi_config_led_on_flag enum */ + A_UINT32 led_on_flag; /* configure high/low on/off sense */ + A_UINT32 led_on_interval; /* for blink function; unit: ms */ + A_UINT32 led_off_interval; /* for blink function; unit: ms */ + A_UINT32 led_repeat_cnt; /* for blink function: how many blinks */ } wmi_pdev_set_led_config_cmd_fixed_param; #define WMI_WNTS_CFG_GPIO_PIN_NUM_OFFSET 0 -#define WMI_WNTS_CFG_GPIO_PIN_NUM_MASK 0xff +#define WMI_WNTS_CFG_GPIO_PIN_NUM_MASK 0xff /** WMI_PEER_INFO_REQ_CMDID * Request FW to provide peer info */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_info_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** In order to get the peer info for a single peer, host shall - * issue the peer_mac_address of that peer. For getting the - * info all peers, the host shall issue 0xFFFFFFFF as the mac - * address. The firmware will return the peer info for all the - * peers on the specified vdev_id */ - wmi_mac_addr peer_mac_address; - /** vdev id */ - A_UINT32 vdev_id; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_info_req_cmd_fixed_param */ + A_UINT32 tlv_header; + /** In order to get the peer info for a single peer, host shall + * issue the peer_mac_address of that peer. For getting the + * info all peers, the host shall issue 0xFFFFFFFF as the mac + * address. The firmware will return the peer info for all the + * peers on the specified vdev_id */ + wmi_mac_addr peer_mac_address; + /** vdev id */ + A_UINT32 vdev_id; } wmi_peer_info_req_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_info */ - A_UINT32 tlv_header; - /** mac addr of the peer */ - wmi_mac_addr peer_mac_address; - /** data_rate of the peer */ - A_UINT32 data_rate; - /** rssi of the peer */ - A_UINT32 rssi; - /** tx fail count */ - A_UINT32 tx_fail_cnt; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_info */ + A_UINT32 tlv_header; + /** mac addr of the peer */ + wmi_mac_addr peer_mac_address; + /** data_rate of the peer */ + A_UINT32 data_rate; + /** rssi of the peer */ + A_UINT32 rssi; + /** tx fail count */ + A_UINT32 tx_fail_cnt; } wmi_peer_info; /** FW response with the peer info */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_info_event_fixed_param */ - A_UINT32 tlv_header; - /** number of peers in peer_info */ - A_UINT32 num_peers; - /* Set to 1 only if vdev_id field is valid */ - A_UINT32 valid_vdev_id; - /* VDEV to which the peer belongs to */ - A_UINT32 vdev_id; - /* This TLV is followed by another TLV of array of structs - * wmi_peer_info peer_info[]; - */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_info_event_fixed_param */ + A_UINT32 tlv_header; + /** number of peers in peer_info */ + A_UINT32 num_peers; + /* Set to 1 only if vdev_id field is valid */ + A_UINT32 valid_vdev_id; + /* VDEV to which the peer belongs to */ + A_UINT32 vdev_id; + /* This TLV is followed by another TLV of array of structs + * wmi_peer_info peer_info[]; + */ } wmi_peer_info_event_fixed_param; -/** WMI_PEER_ANTDIV_INFO_REQ_CMDID - * Request FW to provide peer info */ +/** + * WMI_PEER_ANTDIV_INFO_REQ_CMDID + * Request FW to provide peer info + */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_antdiv_info_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** In order to get the peer antdiv info for a single peer, host shall - * issue the peer_mac_address of that peer. For getting the - * info all peers, the host shall issue 0xFFFFFFFF as the mac - * address. The firmware will return the peer info for all the - * peers on the specified vdev_id */ - wmi_mac_addr peer_mac_address; - /** vdev id */ - A_UINT32 vdev_id; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_antdiv_info_req_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** + * In order to get the peer antdiv info for a single peer, host shall + * issue the peer_mac_address of that peer. For getting the + * info all peers, the host shall issue 0xFFFFFFFF as the mac + * address. The firmware will return the peer info for all the + * peers on the specified vdev_id + */ + wmi_mac_addr peer_mac_address; + /** vdev id */ + A_UINT32 vdev_id; } wmi_peer_antdiv_info_req_cmd_fixed_param; /** FW response with the peer antdiv info */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_antdiv_info_event_fixed_param */ - A_UINT32 tlv_header; - /** number of peers in peer_info */ - A_UINT32 num_peers; - /* VDEV to which the peer belongs to */ - A_UINT32 vdev_id; - /* This TLV is followed by another TLV of array of structs - * wmi_peer_antdiv_info peer_antdiv_info[]; - */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_antdiv_info_event_fixed_param + */ + A_UINT32 tlv_header; + /** number of peers in peer_info */ + A_UINT32 num_peers; + /** VDEV to which the peer belongs to */ + A_UINT32 vdev_id; + /** + * This TLV is followed by another TLV of array of structs + * wmi_peer_antdiv_info peer_antdiv_info[]; + */ } wmi_peer_antdiv_info_event_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_antdiv_info */ - A_UINT32 tlv_header; - /** mac addr of the peer */ - wmi_mac_addr peer_mac_address; - /** per chain rssi of the peer, for up to 8 chains. - * Each chain's entry reports the RSSI for different bandwidths: - * bits 7:0 -> primary 20 MHz - * bits 15:8 -> secondary 20 MHz of 40 MHz channel (if applicable) - * bits 23:16 -> secondary 40 MHz of 80 MHz channel (if applicable) - * bits 31:24 -> secondary 80 MHz of 160 MHz channel (if applicable) - * Each of these 8-bit RSSI reports is in dB units, with respect to - * the noise floor. - * 0x80 means invalid. - * All unused bytes within used chain_rssi indices shall be set to 0x80. - * All unused chain_rssi indices shall be set to 0x80808080. - */ - A_INT32 chain_rssi[8]; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_antdiv_info + */ + A_UINT32 tlv_header; + /** mac addr of the peer */ + wmi_mac_addr peer_mac_address; + /** + * per chain rssi of the peer, for up to 8 chains. + * Each chain's entry reports the RSSI for different bandwidths: + * bits 7:0 -> primary 20 MHz + * bits 15:8 -> secondary 20 MHz of 40 MHz channel (if applicable) + * bits 23:16 -> secondary 40 MHz of 80 MHz channel (if applicable) + * bits 31:24 -> secondary 80 MHz of 160 MHz channel (if applicable) + * Each of these 8-bit RSSI reports is in dB units, with respect to + * the noise floor. + * 0x80 means invalid. + * All unused bytes within used chain_rssi indices shall be + * set to 0x80. + * All unused chain_rssi indices shall be set to 0x80808080. + */ + A_INT32 chain_rssi[8]; } wmi_peer_antdiv_info; /** FW response when tx failure count has reached threshold * for a peer */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_peer_tx_fail_cnt_thr_event_fixed_param */ - A_UINT32 tlv_header; - /** vdev id*/ - A_UINT32 vdev_id; - /** mac address */ - wmi_mac_addr peer_mac_address; - /** tx failure count - will eventually be removed and not used */ - A_UINT32 tx_fail_cnt; - /** seq number of the nth tx_fail_event */ - A_UINT32 seq_no; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_tx_fail_cnt_thr_event_fixed_param */ + A_UINT32 tlv_header; + /** vdev id*/ + A_UINT32 vdev_id; + /** mac address */ + wmi_mac_addr peer_mac_address; + /** tx failure count- will eventually be removed and not used * */ + A_UINT32 tx_fail_cnt; + /** seq number of the nth tx_fail_event */ + A_UINT32 seq_no; } wmi_peer_tx_fail_cnt_thr_event_fixed_param; enum wmi_rmc_mode { - /** Disable RMC */ - WMI_RMC_MODE_DISABLED = 0, - /** Enable RMC */ - WMI_RMC_MODE_ENABLED = 1, + /** Disable RMC */ + WMI_RMC_MODE_DISABLED = 0, + /** Enable RMC */ + WMI_RMC_MODE_ENABLED = 1, }; /** Enable RMC transmitter functionality. Upon @@ -11069,50 +12075,50 @@ enum wmi_rmc_mode { * reliablity. This is a vendor * proprietary feature. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_rmc_set_mode_cmd_fixed_param */ - A_UINT32 tlv_header; - /** vdev id*/ - A_UINT32 vdev_id; - /** enable_rmc contains values from enum wmi_rmc_mode; - * Default value: 0 (disabled) */ - A_UINT32 enable_rmc; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_rmc_set_mode_cmd_fixed_param */ + A_UINT32 tlv_header; + /** vdev id*/ + A_UINT32 vdev_id; + /** enable_rmc contains values from enum wmi_rmc_mode; + * Default value: 0 (disabled) */ + A_UINT32 enable_rmc; } wmi_rmc_set_mode_cmd_fixed_param; /** Configure transmission periodicity of action frames in a * RMC network for the multicast transmitter */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_rmc_set_action_period_cmd_fixed_param */ - A_UINT32 tlv_header; - /** vdev id */ - A_UINT32 vdev_id; - /** time period in milliseconds. Default: 300 ms. - An action frame indicating the current leader is transmitted by the - RMC transmitter once every 'periodity_msec' */ - A_UINT32 periodicity_msec; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_rmc_set_action_period_cmd_fixed_param */ + A_UINT32 tlv_header; + /** vdev id */ + A_UINT32 vdev_id; + /** time period in milliseconds. Default: 300 ms. + An action frame indicating the current leader is transmitted by the + RMC transmitter once every 'periodity_msec' */ + A_UINT32 periodicity_msec; } wmi_rmc_set_action_period_cmd_fixed_param; /** Optimise Leader selection process in RMC functionality. For * Enhancement/Debug purposes only */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_rmc_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** vdev id */ - A_UINT32 vdev_id; - /** flags :: - * 0x0001 - Enable beacon averaging - * 0x0002 - Force leader selection - * 0x0004 - Enable Timer based leader switch - * 0x0008 - Use qos/NULL based for multicast reliability */ - A_UINT32 flags; - /** control leader change timeperiod (in seconds) */ - A_UINT32 peridocity_leader_switch; - /** control activity timeout value for data rx (in seconds) */ - A_UINT32 data_activity_timeout; - /** mac address of leader */ - wmi_mac_addr forced_leader_mac_addr; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_rmc_config_cmd_fixed_param */ + A_UINT32 tlv_header; + /** vdev id */ + A_UINT32 vdev_id; + /** flags :: + * 0x0001 - Enable beacon averaging + * 0x0002 - Force leader selection + * 0x0004 - Enable Timer based leader switch + * 0x0008 - Use qos/NULL based for multicast reliability */ + A_UINT32 flags; + /** control leader change timeperiod (in seconds) */ + A_UINT32 peridocity_leader_switch; + /** control activity timeout value for data rx (in seconds) */ + A_UINT32 data_activity_timeout; + /** mac address of leader */ + wmi_mac_addr forced_leader_mac_addr; } wmi_rmc_config_cmd_fixed_param; /** MHF is generally implemented in @@ -11124,155 +12130,160 @@ typedef struct { * the next hop using next hop's mac address. This is a vendor * proprietary feature. */ enum wmi_mhf_ofl_mode { - /** Disable MHF offload */ - WMI_MHF_OFL_MODE_DISABLED = 0, - /** Enable MHF offload */ - WMI_MHF_OFL_MODE_ENABLED = 1, + /** Disable MHF offload */ + WMI_MHF_OFL_MODE_DISABLED = 0, + /** Enable MHF offload */ + WMI_MHF_OFL_MODE_ENABLED = 1, }; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mhf_offload_set_mode_cmd_fixed_param */ - A_UINT32 tlv_header; - /** vdev id*/ - A_UINT32 vdev_id; - /** enable_mhf_ofl contains values from enum - * wmi_mhf_ofl_mode; Default value: 0 (disabled) */ - A_UINT32 enable_mhf_ofl; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mhf_offload_set_mode_cmd_fixed_param */ + A_UINT32 tlv_header; + /** vdev id*/ + A_UINT32 vdev_id; + /** enable_mhf_ofl contains values from enum + * wmi_mhf_ofl_mode; Default value: 0 (disabled) */ + A_UINT32 enable_mhf_ofl; } wmi_mhf_offload_set_mode_cmd_fixed_param; enum wmi_mhf_ofl_table_action { - /** Create MHF offload table in FW */ - WMI_MHF_OFL_TBL_CREATE = 0, - /** Append to existing MHF offload table */ - WMI_MHF_OFL_TBL_APPEND = 1, - /** Flush entire MHF offload table in FW */ - WMI_MHF_OFL_TBL_FLUSH = 2, + /** Create forwarding offload table in FW */ + WMI_MHF_OFL_TBL_CREATE = 0, + /** Append to existing MHF offload table */ + WMI_MHF_OFL_TBL_APPEND = 1, + /** Flush entire MHF offload table in FW */ + WMI_MHF_OFL_TBL_FLUSH = 2, }; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mhf_offload_plumb_routing_table_cmd_fixed_param */ - A_UINT32 tlv_header; - /** vdev id*/ - A_UINT32 vdev_id; - /** action corresponds to values from enum - * wmi_mhf_ofl_table_action */ - A_UINT32 action; - /** number of entries in the table */ - A_UINT32 num_entries; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mhf_offload_plumb_routing_table_cmd_fixed_param */ + A_UINT32 tlv_header; + /** vdev id*/ + A_UINT32 vdev_id; + /** action corresponds to values from enum + * wmi_mhf_ofl_table_action */ + A_UINT32 action; + /** number of entries in the table */ + A_UINT32 num_entries; /** Followed by the variable length TLV * wmi_mhf_offload_routing_table_entry entries[] */ } wmi_mhf_offload_plumb_routing_table_cmd; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mhf_offload_routing_table_entry */ - A_UINT32 tlv_header; - /** Destination node's IP address */ - WMI_IPV4_ADDR dest_ipv4_addr; - /** Next hop node's MAC address */ - wmi_mac_addr next_hop_mac_addr; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mhf_offload_routing_table_entry */ + A_UINT32 tlv_header; + /** Destination node's IP address */ + WMI_IPV4_ADDR dest_ipv4_addr; + /** Next hop node's MAC address */ + wmi_mac_addr next_hop_mac_addr; } wmi_mhf_offload_routing_table_entry; typedef struct { - /** tlv tag and len, tag equals - * WMITLV_TAG_STRUC_wmi_dfs_radar_event */ - A_UINT32 tlv_header; + /** tlv tag and len, tag equals + * WMITLV_TAG_STRUC_wmi_dfs_radar_event */ + A_UINT32 tlv_header; - /** full 64 tsf timestamp get from MAC tsf timer indicates - * the time that the radar event uploading to host, split - * it to high 32 bit and lower 32 bit in fulltsf_high and - * full_tsf_low - */ - A_UINT32 upload_fullts_low; - A_UINT32 upload_fullts_high; + /** full 64 tsf timestamp get from MAC tsf timer indicates + * the time that the radar event uploading to host, split + * it to high 32 bit and lower 32 bit in fulltsf_high and + * full_tsf_low + */ + A_UINT32 upload_fullts_low; + A_UINT32 upload_fullts_high; - /** timestamp indicates the time when DFS pulse is detected - * equal to ppdu_end_ts - radar_pusle_summary_ts_offset - */ - A_UINT32 pulse_detect_ts; + /** timestamp indicates the time when DFS pulse is detected + * equal to ppdu_end_ts - radar_pusle_summary_ts_offset + */ + A_UINT32 pulse_detect_ts; - /** the duaration of the pulse in us */ - A_UINT32 pulse_duration; + /** the duaration of the pulse in us */ + A_UINT32 pulse_duration; - /** the center frequency of the radar pulse detected, KHz */ - A_UINT32 pulse_center_freq; + /** the center frequency of the radar pulse detected, KHz */ + A_UINT32 pulse_center_freq; - /** bandwidth of current DFS channel, MHz */ - A_UINT32 ch_bandwidth; + /** bandwidth of current DFS channel, MHz */ + A_UINT32 ch_bandwidth; - /** center channel frequency1 of current DFS channel, MHz */ - A_UINT16 ch_center_freq1; + /** center channel frequency1 of current DFS channel, MHz */ + A_UINT16 ch_center_freq1; - /** center channel frequency2 of current DFS channel, MHz, - * reserved for 160 BW mode - */ - A_UINT16 ch_center_freq2; + /** center channel frequency2 of current DFS channel, MHz, + * reserved for 160 BW mode + */ + A_UINT16 ch_center_freq2; - /** flag to indicate if this pulse is chirp */ - A_UINT8 pulse_is_chirp; + /** flag to indicate if this pulse is chirp */ + A_UINT8 pulse_is_chirp; - /** RSSI recorded in the ppdu */ - A_UINT8 rssi; + /** RSSI recorded in the ppdu */ + A_UINT8 rssi; - /** extened RSSI info */ - A_UINT8 rssi_ext; + /** extened RSSI info */ + A_UINT8 rssi_ext; - union { - A_UINT8 pmac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT8 pdev_id; - }; + /** For 4-byte aligment padding */ + A_UINT8 reserved; - /** index of peak magnitude bin (signed) */ - A_INT32 peak_sidx; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT8 pmac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT8 pdev_id; + }; + + /** index of peak magnitude bin (signed) */ + A_INT32 peak_sidx; } wmi_dfs_radar_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param */ - /*Thermal thresholds*/ - A_UINT32 lower_thresh_degreeC; /* in degree C*/ - A_UINT32 upper_thresh_degreeC; /* in degree C*/ + /*Thermal thresholds */ + A_UINT32 lower_thresh_degreeC; /* in degree C */ + A_UINT32 upper_thresh_degreeC; /* in degree C */ - /*Enable/Disable Thermal Monitoring for Mitigation*/ - A_UINT32 enable; + /*Enable/Disable Thermal Monitoring for Mitigation */ + A_UINT32 enable; } wmi_thermal_mgmt_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_thermal_mgmt_event_fixed_param */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_thermal_mgmt_event_fixed_param */ - A_UINT32 temperature_degreeC;/* temperature in degree C*/ + A_UINT32 temperature_degreeC; /* temperature in degree C */ } wmi_thermal_mgmt_event_fixed_param; /** -* This command is sent from WLAN host driver to firmware to + * This command is sent from WLAN host driver to firmware to * request firmware to configure auto shutdown timer in fw * 0 - Disable <1-19600>-Enabled and timer value is seconds (86400 seconds = 1 day maximum> */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_host_auto_shutdown_cfg_cmd_param */ - A_UINT32 timer_value; /** timer value; 0=disable */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_host_auto_shutdown_cfg_cmd_param */ + A_UINT32 timer_value; + /** timer value; 0=disable */ } wmi_host_auto_shutdown_cfg_cmd_fixed_param; enum wmi_host_auto_shutdown_reason { - WMI_HOST_AUTO_SHUTDOWN_REASON_UNKNOWN = 0, - WMI_HOST_AUTO_SHUTDOWN_REASON_TIMER_EXPIRY = 1, - WMI_HOST_AUTO_SHUTDOWN_REASON_MAX, + WMI_HOST_AUTO_SHUTDOWN_REASON_UNKNOWN = 0, + WMI_HOST_AUTO_SHUTDOWN_REASON_TIMER_EXPIRY = 1, + WMI_HOST_AUTO_SHUTDOWN_REASON_MAX, }; /* WMI_HOST_AUTO_SHUTDOWN_EVENTID */ -typedef struct{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_host_auto_shutdown_event_fixed_param */ - A_UINT32 shutdown_reason; /* value: wmi_host_auto_shutdown_reason */ +typedef struct { + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_host_auto_shutdown_event_fixed_param */ + A_UINT32 shutdown_reason; /* value: wmi_host_auto_shutdown_reason */ } wmi_host_auto_shutdown_event_fixed_param; - - /** New WMI command to support TPC CHAINMASK ADJUSTMENT ACCORDING TO a set of conditions specified in the command. * fw will save c tpc offset/chainmask along with conditions and adjust tpc/chainmask when condition meet. * This command is only used by some customer for verification test. It is not for end-user. @@ -11334,43 +12345,43 @@ typedef struct{ /** Bit map definition for basic_config_info starts */ #define WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET_S 0 #define WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET (0x1f << WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET_S) -#define WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET) -#define WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET_SET(x,z) WMI_F_RMW(x,(z) & 0x1f,WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET) +#define WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET) +#define WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET_SET(x, z) WMI_F_RMW(x, (z) & 0x1f, WMI_TPC_CHAINMASK_CONFIG_TPC_OFFSET) #define WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET_S 5 #define WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET (0x1f << WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET_S) -#define WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET) -#define WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET_SET(x,z) WMI_F_RMW(x, (z) & 0x1f, WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET) +#define WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET) +#define WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET_SET(x, z) WMI_F_RMW(x, (z) & 0x1f, WMI_TPC_CHAINMASK_CONFIG_ACK_OFFSET) #define WMI_TPC_CHAINMASK_CONFIG_CHAINMASK_S 10 #define WMI_TPC_CHAINMASK_CONFIG_CHAINMASK (0x3 << WMI_TPC_CHAINMASK_CONFIG_CHAINMASK_S) -#define WMI_TPC_CHAINMASK_CONFIG_CHAINMASK_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_CHAINMASK) -#define WMI_TPC_CHAINMASK_CONFIG_CHAINMASK_SET(x,z) WMI_F_RMW(x, (z) & 0x3, WMI_TPC_CHAINMASK_CONFIG_CHAINMASK) +#define WMI_TPC_CHAINMASK_CONFIG_CHAINMASK_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_CHAINMASK) +#define WMI_TPC_CHAINMASK_CONFIG_CHAINMASK_SET(x, z) WMI_F_RMW(x, (z)&0x3, WMI_TPC_CHAINMASK_CONFIG_CHAINMASK) #define WMI_TPC_CHAINMASK_CONFIG_BT_S 12 #define WMI_TPC_CHAINMASK_CONFIG_BT (0x3 << WMI_TPC_CHAINMASK_CONFIG_BT_S) -#define WMI_TPC_CHAINMASK_CONFIG_BT_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_BT) -#define WMI_TPC_CHAINMASK_CONFIG_BT_SET(x,z) WMI_F_RMW(x, (z) & 0x3, WMI_TPC_CHAINMASK_CONFIG_BT) +#define WMI_TPC_CHAINMASK_CONFIG_BT_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_BT) +#define WMI_TPC_CHAINMASK_CONFIG_BT_SET(x, z) WMI_F_RMW(x, (z)&0x3, WMI_TPC_CHAINMASK_CONFIG_BT) #define WMI_TPC_CHAINMASK_CONFIG_STBC_S 14 #define WMI_TPC_CHAINMASK_CONFIG_STBC (0x3 << WMI_TPC_CHAINMASK_CONFIG_STBC_S) -#define WMI_TPC_CHAINMASK_CONFIG_STBC_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_STBC) -#define WMI_TPC_CHAINMASK_CONFIG_STBC_SET(x,z) WMI_F_RMW(x, (z) & 0x3, WMI_TPC_CHAINMASK_CONFIG_STBC) +#define WMI_TPC_CHAINMASK_CONFIG_STBC_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_STBC) +#define WMI_TPC_CHAINMASK_CONFIG_STBC_SET(x, z) WMI_F_RMW(x, (z) & 0x3, WMI_TPC_CHAINMASK_CONFIG_STBC) #define WMI_TPC_CHAINMASK_CONFIG_BAND_S 16 #define WMI_TPC_CHAINMASK_CONFIG_BAND (0x1 << WMI_TPC_CHAINMASK_CONFIG_BAND_S) -#define WMI_TPC_CHAINMASK_CONFIG_BAND_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_BAND) -#define WMI_TPC_CHAINMASK_CONFIG_BAND_SET(x,z) WMI_F_RMW(x, (z) & 0x1, WMI_TPC_CHAINMASK_CONFIG_BAND) +#define WMI_TPC_CHAINMASK_CONFIG_BAND_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_BAND) +#define WMI_TPC_CHAINMASK_CONFIG_BAND_SET(x, z) WMI_F_RMW(x, (z) & 0x1, WMI_TPC_CHAINMASK_CONFIG_BAND) #define WMI_TPC_CHAINMASK_CONFIG_STREAM_S 17 #define WMI_TPC_CHAINMASK_CONFIG_STREAM (0x1 << WMI_TPC_CHAINMASK_CONFIG_STREAM_S) -#define WMI_TPC_CHAINMASK_CONFIG_STREAM_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_STREAM) -#define WMI_TPC_CHAINMASK_CONFIG_STREAM_SET(x,z) WMI_F_RMW(x, (z) & 0x1, WMI_TPC_CHAINMASK_CONFIG_STREAM) +#define WMI_TPC_CHAINMASK_CONFIG_STREAM_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_STREAM) +#define WMI_TPC_CHAINMASK_CONFIG_STREAM_SET(x, z) WMI_F_RMW(x, (z)&0x1, WMI_TPC_CHAINMASK_CONFIG_STREAM) #define WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_S 18 #define WMI_TPC_CHAINMASK_CONFIG_PHY_MODE (0x7 << WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_S) -#define WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_PHY_MODE) -#define WMI_TPC_CHAINAMSK_CONFIG_PHY_MODE_SET(x,z) WMI_F_RMW(x, (z) & 0x7, WMI_TPC_CHAINMASK_CONFIG_PHY_MODE) +#define WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_PHY_MODE) +#define WMI_TPC_CHAINAMSK_CONFIG_PHY_MODE_SET(x, z) WMI_F_RMW(x, (z)&0x7, WMI_TPC_CHAINMASK_CONFIG_PHY_MODE) #define WMI_TPC_CHAINMASK_CONFIG_CHANNEL_S 21 /* @@ -11380,8 +12391,8 @@ typedef struct{ */ #define WMI_TPC_CHAINMASK_CONFIG_CHANNEL_EXIST WMI_TPC_CHAINMASK_CONFIG_CHANNEL #define WMI_TPC_CHAINMASK_CONFIG_CHANNEL (0x1 << WMI_TPC_CHAINMASK_CONFIG_CHANNEL_S) -#define WMI_TPC_CHAINMASK_CONFIG_CHANNEL_GET(x) WMI_F_MS(x,WMI_TPC_CHAINMASK_CONFIG_CHANNEL) -#define WMI_TPC_CHAINMASK_CONFIG_CHANNEL_SET(x,z) WMI_F_RMW(x, (z) & 0x1, WMI_TPC_CHAINMASK_CONFIG_CHANNEL) +#define WMI_TPC_CHAINMASK_CONFIG_CHANNEL_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_CHANNEL) +#define WMI_TPC_CHAINMASK_CONFIG_CHANNEL_SET(x, z) WMI_F_RMW(x, (z)&0x1, WMI_TPC_CHAINMASK_CONFIG_CHANNEL) #define WMI_TPC_CHAINMASK_CONFIG_RATE_S 22 /* @@ -11392,94 +12403,102 @@ typedef struct{ #define WMI_TPC_CHAINMASK_CONFIG_RATE_EXIST WMI_TPC_CHAINMASK_CONFIG_RATE #define WMI_TPC_CHAINMASK_CONFIG_RATE (0x1 << WMI_TPC_CHAINMASK_CONFIG_RATE_S) #define WMI_TPC_CHAINMASK_CONFIG_RATE_GET(x) WMI_F_MS(x, WMI_TPC_CHAINMASK_CONFIG_RATE) -#define WMI_TPC_CHAINMASK_CONFIG_RATE_SET(x,z) WMI_F_RMW(x, (z) & 0x1, WMI_TPC_CHAINMASK_CONFIG_RATE) +#define WMI_TPC_CHAINMASK_CONFIG_RATE_SET(x, z) WMI_F_RMW(x, (z)&0x1, WMI_TPC_CHAINMASK_CONFIG_RATE) /** Bit map definition for basic_config_info ends */ -typedef struct{ - A_UINT32 tlv_header; - /** Basic condition defined as bit map above, bitmap is chosen to save memory. - * Bit0 ~ Bit4: tpc offset which will be adjusted if condtion matches, the unit is 0.5dB. bit4 indicates signed - * Bit5 ~ Bit9: ack offset which will be adjusted if condtion matches, the unit is 0.5dB. bit9 indicates signed - * Bit10 ~ Bit11: chainmask b'00: don't care, b'01: force to use chain0, b'10: force to use chain1, b'11: force to use chain0&chain1 - * Bit12 ~ Bit13: bt condition b'00: don't care, b'01: apply only when bt on, b'10: apply only when bt off, b'11: reserved - * Bit14 ~ Bit15: stbc condition b'00: don't care, b'01: apply only when stbc on, b'10: apply only when stbc off, b'11: reserved - * Bit16 : band condition b'0: 2G, b'1: 5G - * Bit17 : stream condition: b'0: 1 stream, b'1: 2 streams - * Bit18 ~ Bit20: phy mode condition: b'000: 11b 2g, b'001: 11g 2g, b'010: 11n 2g, b'011: 11n+11ac 2g, b'100: 11a, b'101: 11n 5g, b'110: 11ac 5g, b'111: 11n+11ac 5g - * Bit21 : channel bit, if this bit is 0, then the following channel field is ignored - * Bit22 : rate bit, if this bit is 0, then the following rate0&rate1 is ignored. - * Bit23 ~ Bit31: reserved - */ - A_UINT32 basic_config_info; +typedef struct { + A_UINT32 tlv_header; + /** Basic condition defined as bit map above, bitmap is chosen to save memory. + * Bit0 ~ Bit4: tpc offset which will be adjusted if condtion matches, the unit is 0.5dB. bit4 indicates signed + * Bit5 ~ Bit9: ack offset which will be adjusted if condtion matches, the unit is 0.5dB. bit9 indicates signed + * Bit10 ~ Bit11: chainmask b'00: don't care, b'01: force to use chain0, b'10: force to use chain1, b'11: force to use chain0&chain1 + * Bit12 ~ Bit13: bt condition b'00: don't care, b'01: apply only when bt on, b'10: apply only when bt off, b'11: reserved + * Bit14 ~ Bit15: stbc condition b'00: don't care, b'01: apply only when stbc on, b'10: apply only when stbc off, b'11: reserved + * Bit16 : band condition b'0: 2G, b'1: 5G + * Bit17 : stream condition: b'0: 1 stream, b'1: 2 streams + * Bit18 ~ Bit20: phy mode condition: b'000: 11b 2g, b'001: 11g 2g, b'010: 11n 2g, b'011: 11n+11ac 2g, b'100: 11a, b'101: 11n 5g, b'110: 11ac 5g, b'111: 11n+11ac 5g + * Bit21 : channel bit, if this bit is 0, then the following channel field is ignored + * Bit22 : rate bit, if this bit is 0, then the following rate0&rate1 is ignored. + * Bit23 ~ Bit31: reserved + */ + A_UINT32 basic_config_info; - /** channel mapping bit rule: The lower bit corresponds with smaller channel. - * it depends on Bit14 of basic_config_info - * Total 24 channels for 5G - * 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 149 153 157 161 165 - * Total 14 channels for 2G - * 1 ~ 14 - */ - A_UINT32 channel; + /** channel mapping bit rule: The lower bit corresponds with smaller channel. + * it depends on Bit14 of basic_config_info + * Total 24 channels for 5G + * 36 40 44 48 52 56 60 64 100 104 108 112 116 120 124 128 132 136 140 149 153 157 161 165 + * Total 14 channels for 2G + * 1 ~ 14 + */ + A_UINT32 channel; - /** rate mapping bit rule: The lower bit corresponds with lower rate. - * it depends on Bit16 ~ Bit18 of basic_config_info, "phy mode condition" - * Legacy rates , 11b, 11g, 11A - * 11n one stream (ht20, ht40) 8+8 - * 11n two streams (ht20, ht40) 8+8 - * 11ac one stream (vht20, vht40, vht80) 10+10+10 - * 11ac two streams (vht20, vht40, vht80) 10+10+10 - */ - A_UINT32 rate0; - /** For example, for 11b, when rate0 equals 0x3, it means if actual_rate in [ "1Mbps", "2Mbps"] connection, the rate condition is true. - * For example, for 11g/11a, when rate0 equals 0xf0,it means "54Mbps", "48Mbps", "36Mbps", "24Mb's" is selected, while "18Mbps", "12Mbps", "9Mbps", "6Mbps" is not selected - */ + /** rate mapping bit rule: The lower bit corresponds with lower rate. + * it depends on Bit16 ~ Bit18 of basic_config_info, "phy mode condition" + * Legacy rates , 11b, 11g, 11A + * 11n one stream ( ht20, ht40 ) 8+8 + * 11n two streams ( ht20, ht40 ) 8+8 + * 11ac one stream ( vht20, vht40, vht80 ) 10+10+10 + * 11ac two streams (vht20, vht40, vht80 ) 10+10+10 + */ + A_UINT32 rate0; + /** For example, for 11b, when rate0 equals 0x3, it means if actual_rate in [ "1Mbps", "2Mbps"] connection, the rate condition is true. + * For example, for 11g/11a, when rate0 equals 0xf0,it means "54Mbps", "48Mbps", "36Mbps", "24Mb's" is selected, while "18Mbps", "12Mbps", "9Mbps", "6Mbps" is not selected + */ - /** only used for "11n+11ac" combined phy_mode, (WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_11N_11AC_2G , WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_11N_11AC_5G) in this case, 11n rates begins on rate0, while 11ac rates begins on rate1 - */ - A_UINT32 rate1; + /** only used for "11n+11ac" combined phy_mode, (WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_11N_11AC_2G , WMI_TPC_CHAINMASK_CONFIG_PHY_MODE_11N_11AC_5G) in this case, 11n rates begins on rate0, while 11ac rates begins on rate1 + */ + A_UINT32 rate1; } wmi_tpc_chainmask_config; #define WMI_TPC_CHAINMASK_CONFIG_DISABLE 0 /** control the off for the tpc & chainmask*/ #define WMI_TPC_CHAINMASK_CONFIG_ENABLE 1 /** control the on for the tpc & chainmask*/ -typedef struct{ - A_UINT32 tlv_header; - A_UINT32 enable; /** enable to set tpc & chainmask when condtions meet, 0: disabled, 1: enabled. */ - A_UINT32 num_tpc_chainmask_configs; - /** following this structure is num_tpc_chainmask_configs number of wmi_tpc_chainmask_config */ +typedef struct { + A_UINT32 tlv_header; + A_UINT32 enable; + /** enable to set tpc & chainmask when condtions meet, 0: disabled, 1: enabled. */ + A_UINT32 num_tpc_chainmask_configs; + /** following this structure is num_tpc_chainmask_configs number of wmi_tpc_chainmask_config */ } wmi_tpc_chainmask_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_cmd_param */ - A_UINT32 data_len; /** length in byte of data[]. */ -/* This structure is used to send REQ binary blobs -* from application/service to firmware where Host drv is pass through . -* Following this structure is the TLV: -* A_UINT8 data[]; <-- length in byte given by field data_len. -*/ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_cmd_param */ + A_UINT32 data_len; + /** length in byte of data[]. */ + /* This structure is used to send REQ binary blobs + * from application/service to firmware where Host drv is pass through . + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field data_len. + */ } wmi_nan_cmd_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_event_hdr */ - A_UINT32 data_len; /** length in byte of data[]. */ -/* This structure is used to send REQ binary blobs -* from firmware to application/service where Host drv is pass through . -* Following this structure is the TLV: -* A_UINT8 data[]; <-- length in byte given by field data_len. -*/ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_event_hdr */ + A_UINT32 data_len; + /** length in byte of data[]. */ + /* This structure is used to send REQ binary blobs + * from firmware to application/service where Host drv is pass through . + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field data_len. + */ } wmi_nan_event_hdr; /** * Event to indicate NAN discovery interface created */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** NAN interface MAC address */ - wmi_mac_addr nan_interface_macaddr; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** NAN interface MAC address */ + wmi_mac_addr nan_interface_macaddr; } wmi_nan_disc_iface_created_event_fixed_param_PROTOTYPE; #define wmi_nan_disc_iface_created_event_fixed_param wmi_nan_disc_iface_created_event_fixed_param_PROTOTYPE @@ -11488,10 +12507,13 @@ typedef struct { * Event to indicate NAN discovery interface deleted */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_iface_deleted_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_nan_disc_iface_deleted_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; } wmi_nan_disc_iface_deleted_event_fixed_param_PROTOTYPE; #define wmi_nan_disc_iface_deleted_event_fixed_param wmi_nan_disc_iface_deleted_event_fixed_param_PROTOTYPE @@ -11500,12 +12522,15 @@ typedef struct { * Event to indicate NAN device started new cluster */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_started_cluster_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** NAN Cluster ID */ - A_UINT32 nan_cluster_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_nan_started_cluster_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** NAN Cluster ID */ + A_UINT32 nan_cluster_id; } wmi_nan_started_cluster_event_fixed_param_PROTOTYPE; #define wmi_nan_started_cluster_event_fixed_param wmi_nan_started_cluster_event_fixed_param_PROTOTYPE @@ -11514,12 +12539,15 @@ typedef struct { * Event to indicate NAN device joined to cluster */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** NAN Cluster ID */ - A_UINT32 nan_cluster_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** NAN Cluster ID */ + A_UINT32 nan_cluster_id; } wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE; #define wmi_nan_joined_cluster_event_fixed_param wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE @@ -11530,10 +12558,13 @@ typedef struct { * NAN Data get capabilities req */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param */ - A_UINT32 tlv_header; - /** unique id generated in upper layer for the transaction */ - A_UINT32 transaction_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param + */ + A_UINT32 tlv_header; + /** unique id generated in upper layer for the transaction */ + A_UINT32 transaction_id; } wmi_ndi_get_cap_req_fixed_param_PROTOTYPE; #define wmi_ndi_get_cap_req_fixed_param wmi_ndi_get_cap_req_fixed_param_PROTOTYPE @@ -11542,38 +12573,53 @@ typedef struct { * NDP Response code */ typedef enum { - NDP_RSP_CODE_REQUEST_ACCEPT = 0x00, - NDP_RSP_CODE_REQUEST_REJECT = 0x01, - NDP_RSP_CODE_REQUEST_DEFER = 0x02, + NDP_RSP_CODE_REQUEST_ACCEPT = 0x00, + NDP_RSP_CODE_REQUEST_REJECT = 0x01, + NDP_RSP_CODE_REQUEST_DEFER = 0x02, } wmi_ndp_rsp_code_PROTOTYPE; #define wmi_ndp_rsp_code wmi_ndp_rsp_code_PROTOTYPE +/** +* NDP Channel configuration type +*/ +typedef enum { + WMI_NDP_CHANNEL_NOT_REQUESTED = 0, /* Channel will not configured */ + WMI_NDP_REQUEST_CHANNEL_SETUP = 1, /* Channel will be provided and is optional/hint */ + WMI_NDP_FORCE_CHANNEL_SETUP = 2/* NDP must start on the provided channel */ +} wmi_ndp_channel_cfg_PROTOTYPE; + +#define wmi_ndp_channel_cfg wmi_ndp_channel_cfg_PROTOTYPE /** * NDP Initiator requesting a data session */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** unique id generated in upper layer for the transaction */ - A_UINT32 transaction_id; - /** Unique Instance Id identifying the Responder's service */ - A_UINT32 service_instance_id; - /** Discovery MAC addr of the publisher/peer */ - wmi_mac_addr peer_discovery_mac_addr; - /** Actual number of bytes in TLV ndp_cfg */ - A_UINT32 ndp_cfg_len; - /** Actual number of bytes in TLV ndp_app_info */ - A_UINT32 ndp_app_info_len; - /** - * TLV (tag length value) parameters follow the ndp_initiator_req - * structure. The TLV's are: - * wmi_channel channel; - * A_UINT8 ndp_cfg[]; - * A_UINT8 ndp_app_info[]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** unique id generated in upper layer for the transaction */ + A_UINT32 transaction_id; + /** Unique Instance Id identifying the Responder's service */ + A_UINT32 service_instance_id; + /** Discovery MAC addr of the publisher/peer */ + wmi_mac_addr peer_discovery_mac_addr; + /* Actual number of bytes in TLV ndp_cfg */ + A_UINT32 ndp_cfg_len; + /* Actual number of bytes in TLV ndp_app_info */ + A_UINT32 ndp_app_info_len; + /** NDP channel configuration type defined in wmi_ndp_channel_cfg */ + A_UINT32 ndp_channel_cfg; + /** + * TLV (tag length value ) parameters follow the ndp_initiator_req + * structure. The TLV's are: + * wmi_channel channel; + * A_UINT8 ndp_cfg[]; + * A_UINT8 ndp_app_info[]; + */ } wmi_ndp_initiator_req_fixed_param_PROTOTYPE; #define wmi_ndp_initiator_req_fixed_param wmi_ndp_initiator_req_fixed_param_PROTOTYPE @@ -11583,29 +12629,32 @@ typedef struct { * for data request indication from the peer */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_responder_req_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** unique id generated in upper layer for the transaction */ - A_UINT32 transaction_id; - /** - * Unique token Id generated on the initiator/responder - * side used for a NDP session between two NAN devices - */ - A_UINT32 ndp_instance_id; - /** Response Code defined in wmi_ndp_rsp_code */ - A_UINT32 rsp_code; - /** Number of bytes in TLV ndp_cfg */ - A_UINT32 ndp_cfg_len; - /** Number of bytes in TLV ndp_app_info */ - A_UINT32 ndp_app_info_len; - /** - * TLV (tag length value) parameters follow the ndp_responder_req - * structure. The TLV's are: - * A_UINT8 ndp_cfg[]; - * A_UINT8 ndp_app_info[]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_responder_req_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** unique id generated in upper layer for the transaction */ + A_UINT32 transaction_id; + /** + * Unique token Id generated on the initiator/responder + * side used for a NDP session between two NAN devices + */ + A_UINT32 ndp_instance_id; + /** Response Code defined in wmi_ndp_rsp_code */ + A_UINT32 rsp_code; + /** Number of bytes in TLV ndp_cfg */ + A_UINT32 ndp_cfg_len; + /** Number of bytes in TLV ndp_app_info */ + A_UINT32 ndp_app_info_len; + /** + * TLV (tag length value ) parameters follow the ndp_responder_req + * structure. The TLV's are: + * A_UINT8 ndp_cfg[]; + * A_UINT8 ndp_app_info[]; + */ } wmi_ndp_responder_req_fixed_param_PROTOTYPE; #define wmi_ndp_responder_req_fixed_param wmi_ndp_responder_req_fixed_param_PROTOTYPE @@ -11614,9 +12663,9 @@ typedef struct { * NDP end type */ typedef enum { - WMI_NDP_END_TYPE_UNSPECIFIED = 0x00, - WMI_NDP_END_TYPE_PEER_UNAVAILABLE = 0x01, - WMI_NDP_END_TYPE_OTA_FRAME = 0x02, + WMI_NDP_END_TYPE_UNSPECIFIED = 0x00, + WMI_NDP_END_TYPE_PEER_UNAVAILABLE = 0x01, + WMI_NDP_END_TYPE_OTA_FRAME = 0x02, } wmi_ndp_end_type_PROTOTYPE; #define wmi_ndp_end_type wmi_ndp_end_type_PROTOTYPE @@ -11625,9 +12674,9 @@ typedef enum { * NDP end reason code */ typedef enum { - WMI_NDP_END_REASON_UNSPECIFIED = 0x00, - WMI_NDP_END_REASON_INACTIVITY = 0x01, - WMI_NDP_END_REASON_PEER_DATA_END = 0x02, + WMI_NDP_END_REASON_UNSPECIFIED = 0x00, + WMI_NDP_END_REASON_INACTIVITY = 0x01, + WMI_NDP_END_REASON_PEER_DATA_END = 0x02, } wmi_ndp_end_reason_code_PROTOTYPE; #define wmi_ndp_end_reason_code wmi_ndp_end_reason_code_PROTOTYPE @@ -11636,10 +12685,10 @@ typedef enum { * NDP end request */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_end_req */ - A_UINT32 tlv_header; - /** NDP instance id */ - A_UINT32 ndp_instance_id; + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_end_req */ + A_UINT32 tlv_header; + /** NDP instance id */ + A_UINT32 ndp_instance_id; } wmi_ndp_end_req_PROTOTYPE; #define wmi_ndp_end_req wmi_ndp_end_req_PROTOTYPE @@ -11648,15 +12697,18 @@ typedef struct { * NDP End request */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_end_req_fixed_param */ - A_UINT32 tlv_header; - /** unique id generated in upper layer for the transaction */ - A_UINT32 transaction_id; - /** - * TLV (tag length value) parameters follow the ndp_end_req - * structure. The TLV's are: - * wmi_ndp_end_req ndp_end_req_list[]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_end_req_fixed_param + */ + A_UINT32 tlv_header; + /** unique id generated in upper layer for the transaction */ + A_UINT32 transaction_id; + /** + * TLV (tag length value ) parameters follow the ndp_end_req + * structure. The TLV's are: + * wmi_ndp_end_req ndp_end_req_list[]; + */ } wmi_ndp_end_req_fixed_param_PROTOTYPE; #define wmi_ndp_end_req_fixed_param wmi_ndp_end_req_fixed_param_PROTOTYPE @@ -11667,18 +12719,21 @@ typedef struct { * Event to indicate NAN Data Interface capabilities cmd */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndi_cap_rsp_event_fixed_param */ - A_UINT32 tlv_header; - /** Copy of transaction_id received in wmi_ndi_get_cap_req */ - A_UINT32 transaction_id; - /** Max ndi interface support */ - A_UINT32 max_ndi_interfaces; - /** Max ndp sessions can support */ - A_UINT32 max_ndp_sessions; - /** Max number of peer's per ndi */ - A_UINT32 max_peers_per_ndi; - /** which combination of bands is supported - see NAN_DATA_SUPPORTED_BAND enums */ - A_UINT32 nan_data_supported_bands; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndi_cap_rsp_event_fixed_param + */ + A_UINT32 tlv_header; + /** Copy of transaction_id received in wmi_ndi_get_cap_req */ + A_UINT32 transaction_id; + /** Max ndi interface support */ + A_UINT32 max_ndi_interfaces; + /** Max ndp sessions can support */ + A_UINT32 max_ndp_sessions; + /** Max number of peer's per ndi */ + A_UINT32 max_peers_per_ndi; + /** which combination of bands is supported - see NAN_DATA_SUPPORTED_BAND enums */ + A_UINT32 nan_data_supported_bands; } wmi_ndi_cap_rsp_event_fixed_param_PROTOTYPE; #define wmi_ndi_cap_rsp_event_fixed_param wmi_ndi_cap_rsp_event_fixed_param_PROTOTYPE @@ -11687,8 +12742,8 @@ typedef struct { * NDP command response code */ typedef enum { - NDP_CMD_RSP_STATUS_SUCCESS = 0x00, - NDP_CMD_RSP_STATUS_ERROR = 0x01, + NDP_CMD_RSP_STATUS_SUCCESS = 0x00, + NDP_CMD_RSP_STATUS_ERROR = 0x01, } wmi_ndp_cmd_rsp_status_PROTOTYPE; #define wmi_ndp_cmd_rsp_status wmi_ndp_cmd_rsp_status_PROTOTYPE @@ -11697,20 +12752,23 @@ typedef enum { * Event response for wmi_ndp_initiator_req */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_initiator_rsp_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** Copy of transaction_id received in wmi_ndp_initiator_req */ - A_UINT32 transaction_id; - /** Response status defined in wmi_ndp_cmd_rsp_status*/ - A_UINT32 rsp_status; - A_UINT32 reason_code; - /** - * Unique token Id generated on the initiator/responder - * side used for a NDP session between two NAN devices - */ - A_UINT32 ndp_instance_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_initiator_rsp_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** Copy of transaction_id received in wmi_ndp_initiator_req */ + A_UINT32 transaction_id; + /** Response status defined in wmi_ndp_cmd_rsp_status*/ + A_UINT32 rsp_status; + A_UINT32 reason_code; + /* + * Unique token Id generated on the initiator/responder + * side used for a NDP session between two NAN devices + */ + A_UINT32 ndp_instance_id; } wmi_ndp_initiator_rsp_event_fixed_param_PROTOTYPE; #define wmi_ndp_initiator_rsp_event_fixed_param wmi_ndp_initiator_rsp_event_fixed_param_PROTOTYPE @@ -11719,22 +12777,27 @@ typedef struct { * Event response for wmi_ndp_responder_req cmd */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** Copy of transaction_id received in wmi_ndp_responder_req */ - A_UINT32 transaction_id; - /** Response status defined in wmi_ndp_cmd_rsp_status*/ - A_UINT32 rsp_status; - A_UINT32 reason_code; - /** - * Unique token Id generated on the initiator/responder - * side used for a NDP session between two NAN devices - */ - A_UINT32 ndp_instance_id; - /** NDI mac address of the peer */ - wmi_mac_addr peer_ndi_mac_addr; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_responder_rsp_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** Copy of transaction_id received in wmi_ndp_responder_req */ + A_UINT32 transaction_id; + /** Response status defined in wmi_ndp_cmd_rsp_status*/ + A_UINT32 rsp_status; + A_UINT32 reason_code; + /* + * Unique token Id generated on the initiator/responder + * side used for a NDP session between two NAN devices + */ + A_UINT32 ndp_instance_id; + /* NDI mac address of the peer */ + wmi_mac_addr peer_ndi_mac_addr; + /** Host can create peer if this entry is TRUE */ + A_UINT32 create_peer; } wmi_ndp_responder_rsp_event_fixed_param_PROTOTYPE; #define wmi_ndp_responder_rsp_event_fixed_param wmi_ndp_responder_rsp_event_fixed_param_PROTOTYPE @@ -11742,10 +12805,13 @@ typedef struct { * Active ndp instance id */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_active_ndp_instance_id */ - A_UINT32 tlv_header; - /** NDP instance id */ - A_UINT32 ndp_instance_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_active_ndp_instance_id + */ + A_UINT32 tlv_header; + /* NDP instance id */ + A_UINT32 ndp_instance_id; } wmi_active_ndp_instance_id_PROTOTYPE; #define wmi_active_ndp_instance_id wmi_active_ndp_instance_id_PROTOTYPE @@ -11754,14 +12820,17 @@ typedef struct { * NDP end response per ndi */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_end_rsp_per_ndi */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** Peer MAC addr */ - wmi_mac_addr peer_mac_addr; - /** Number of active ndps on this ndi */ - A_UINT32 num_active_ndps_on_ndi; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_end_rsp_per_ndi + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** Peer MAC addr */ + wmi_mac_addr peer_mac_addr; + /** Number of active ndps on this ndi */ + A_UINT32 num_active_ndps_on_ndi; } wmi_ndp_end_rsp_per_ndi_PROTOTYPE; #define wmi_ndp_end_rsp_per_ndi wmi_ndp_end_rsp_per_ndi_PROTOTYPE @@ -11770,19 +12839,22 @@ typedef struct { * Event response for wmi_ndp_end_req cmd */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_end_rsp_event_fixed_param */ - A_UINT32 tlv_header; - /** Copy of transaction_id received in wmi_ndp_end_req */ - A_UINT32 transaction_id; - /** Response status defined in wmi_ndp_cmd_rsp_status*/ - A_UINT32 rsp_status; - A_UINT32 reason_code; - /** - * TLV (tag length value) parameters follow the ndp_end_rsp - * structure. The TLV's are: - * wmi_ndp_end_rsp_per_ndi ndp_end_rsp_per_ndis[]; - * wmi_active_ndp_instance_id active_ndp_instances_id[]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_end_rsp_event_fixed_param + */ + A_UINT32 tlv_header; + /** Copy of transaction_id received in wmi_ndp_end_req */ + A_UINT32 transaction_id; + /** Response status defined in wmi_ndp_cmd_rsp_status*/ + A_UINT32 rsp_status; + A_UINT32 reason_code; + /** + * TLV (tag length value ) parameters follow the ndp_end_rsp + * structure. The TLV's are: + * wmi_ndp_end_rsp_per_ndi ndp_end_rsp_per_ndis[]; + * wmi_active_ndp_instance_id active_ndp_instances_id[]; + */ } wmi_ndp_end_rsp_event_fixed_param_PROTOTYPE; #define wmi_ndp_end_rsp_event_fixed_param wmi_ndp_end_rsp_event_fixed_param_PROTOTYPE @@ -11793,8 +12865,8 @@ typedef struct { * NDP self role */ typedef enum { - WMI_NDP_INITIATOR_ROLE, - WMI_NDP_RESPONDER_ROLE, + WMI_NDP_INITIATOR_ROLE, + WMI_NDP_RESPONDER_ROLE, } wmi_ndp_self_role_PROTOTYPE; #define wmi_ndp_self_role wmi_ndp_self_role_PROTOTYPE @@ -11803,49 +12875,54 @@ typedef enum { * NDP accept policy */ typedef enum { - WMI_NDP_ACCEPT_POLICY_NONE, - WMI_NDP_ACCEPT_POLICY_ALL, + WMI_NDP_ACCEPT_POLICY_NONE, + WMI_NDP_ACCEPT_POLICY_ALL, } wmi_ndp_accept_policy_PROTOTYPE; #define wmi_ndp_accept_policy wmi_ndp_accept_policy_PROTOTYPE /** * Event indication received on the responder side when a NDP Initiator request/ - * NDP session is initiated on the Initiator side (self role will be NDP_RESPONDER_ROLE) + * NDP session is initiated on the Initiator side + * (self role will be NDP_RESPONDER_ROLE) * * Event indication received on the initiator side when a - * NDP responder request on the Initiator side (self role will be NDP_INITIATOR_ROLE) + * NDP responder request on the Initiator side + * (self role will be NDP_INITIATOR_ROLE) */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** Self NDP Role defined in wmi_ndp_self_role */ - A_UINT32 self_ndp_role; - /** Accept policy defined in wmi_ndp_accept_policy */ - A_UINT32 accept_policy; - /** Unique Instance Id corresponding to a service/session. */ - A_UINT32 service_instance_id; - /** Discovery MAC addr of the peer/initiator */ - wmi_mac_addr peer_discovery_mac_addr; - /** NDI mac address of the peer */ - wmi_mac_addr peer_ndi_mac_addr; - /** - * Unique token Id generated on the initiator/responder - * side used for a NDP session between two NAN devices - */ - A_UINT32 ndp_instance_id; - /** Number of bytes in TLV wmi_ndp_cfg */ - A_UINT32 ndp_cfg_len; - /** Number of bytes in TLV wmi_ndp_app_info */ - A_UINT32 ndp_app_info_len; - /** - * TLV (tag length value) parameters follow the ndp_indication - * structure. The TLV's are: - * A_UINT8 ndp_cfg[]; - * A_UINT8 ndp_app_info[]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** Self NDP Role defined in wmi_ndp_self_role */ + A_UINT32 self_ndp_role; + /** Accept policy defined in wmi_ndp_accept_policy */ + A_UINT32 accept_policy; + /** Unique Instance Id corresponding to a service/session. */ + A_UINT32 service_instance_id; + /** Discovery MAC addr of the peer/initiator */ + wmi_mac_addr peer_discovery_mac_addr; + /* NDI mac address of the peer */ + wmi_mac_addr peer_ndi_mac_addr; + /** + * Unique token Id generated on the initiator/responder + * side used for a NDP session between two NAN devices + */ + A_UINT32 ndp_instance_id; + /** Number of bytes in TLV wmi_ndp_cfg */ + A_UINT32 ndp_cfg_len; + /** Number of bytes in TLV wmi_ndp_app_info */ + A_UINT32 ndp_app_info_len; + /** + * TLV (tag length value ) parameters follow the ndp_indication + * structure. The TLV's are: + * A_UINT8 ndp_cfg[]; + * A_UINT8 ndp_app_info[]; + */ } wmi_ndp_indication_event_fixed_param_PROTOTYPE; #define wmi_ndp_indication_event_fixed_param wmi_ndp_indication_event_fixed_param_PROTOTYPE @@ -11855,33 +12932,39 @@ typedef struct { * initiator and responder side confirming a NDP session */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** - * Unique token Id generated on the initiator/responder - * side used for a NDP session between two NAN devices - */ - A_UINT32 ndp_instance_id; - /** NDI mac address of the peer (required to derive target ipv6 address) */ - wmi_mac_addr peer_ndi_mac_addr; - /** Response Code defined in wmi_ndp_rsp_code */ - A_UINT32 rsp_code; - /** Number of bytes in TLV wmi_ndp_cfg */ - A_UINT32 ndp_cfg_len; - /** Number of bytes in TLV wmi_ndp_app_info */ - A_UINT32 ndp_app_info_len; - /** Reason Code */ - A_UINT32 reason_code; - /** Number of active ndps on this peer */ - A_UINT32 num_active_ndps_on_peer; - /** - * TLV (tag length value) parameters follow the ndp_confirm - * structure. The TLV's are: - * A_UINT8 ndp_cfg[]; - * A_UINT8 ndp_app_info[]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param + */ + A_UINT32 tlv_header; + /** Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** + * Unique token Id generated on the initiator/responder + * side used for a NDP session between two NAN devices + */ + A_UINT32 ndp_instance_id; + /* + * NDI mac address of the peer + * (required to derive target ipv6 address) + */ + wmi_mac_addr peer_ndi_mac_addr; + /** Response Code defined in wmi_ndp_rsp_code */ + A_UINT32 rsp_code; + /** Number of bytes in TLV wmi_ndp_cfg */ + A_UINT32 ndp_cfg_len; + /** Number of bytes in TLV wmi_ndp_app_info */ + A_UINT32 ndp_app_info_len; + /** Reason Code */ + A_UINT32 reason_code; + /** Number of active ndps on this peer */ + A_UINT32 num_active_ndps_on_peer; + /** + * TLV (tag length value ) parameters follow the ndp_confirm + * structure. The TLV's are: + * A_UINT8 ndp_cfg[]; + * A_UINT8 ndp_app_info[]; + */ } wmi_ndp_confirm_event_fixed_param_PROTOTYPE; #define wmi_ndp_confirm_event_fixed_param wmi_ndp_confirm_event_fixed_param_PROTOTYPE @@ -11890,34 +12973,37 @@ typedef struct { * Event indication received on the initiator/responder side terminating a NDP session */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_end_indication */ - A_UINT32 tlv_header; - /** type defined in wmi_ndp_end_type */ - A_UINT32 type; - /** Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** reason_code defined in wmi_ndp_end_reason_code */ - A_UINT32 reason_code; - /** NDP instance id */ - A_UINT32 ndp_instance_id; - /** NDI MAC addr of the peer */ - wmi_mac_addr peer_ndi_mac_addr; - /** Number of active ndps on this peer */ - A_UINT32 num_active_ndps_on_peer; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ndp_end_indication + */ + A_UINT32 tlv_header; + /** type defined in wmi_ndp_end_type */ + A_UINT32 type; + /* Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** reason_code defined in wmi_ndp_end_reason_code */ + A_UINT32 reason_code; + /** NDP instance id */ + A_UINT32 ndp_instance_id; + /* NDI MAC addr of the peer */ + wmi_mac_addr peer_ndi_mac_addr; + /* Number of active ndps on this peer */ + A_UINT32 num_active_ndps_on_peer; } wmi_ndp_end_indication_PROTOTYPE; #define wmi_ndp_end_indication wmi_ndp_end_indication_PROTOTYPE typedef struct { - A_UINT32 tlv_header; - A_UINT32 num_data; - /* followed by WMITLV_TAG_ARRAY_BYTE */ + A_UINT32 tlv_header; + A_UINT32 num_data; + /* followed by WMITLV_TAG_ARRAY_BYTE */ } wmi_diag_data_container_event_fixed_param; enum { - WMI_PDEV_PARAM_TXPOWER_REASON_NONE = 0, - WMI_PDEV_PARAM_TXPOWER_REASON_SAR, - WMI_PDEV_PARAM_TXPOWER_REASON_MAX + WMI_PDEV_PARAM_TXPOWER_REASON_NONE = 0, + WMI_PDEV_PARAM_TXPOWER_REASON_SAR, + WMI_PDEV_PARAM_TXPOWER_REASON_MAX }; #define PDEV_PARAM_TXPOWER_VALUE_MASK 0x000000FF @@ -11927,16 +13013,16 @@ enum { #define PDEV_PARAM_TXPOWER_REASON_SHIFT 8 #define SET_PDEV_PARAM_TXPOWER_VALUE(txpower_param, value) \ - ((txpower_param) &= ~PDEV_PARAM_TXPOWER_VALUE_MASK, (txpower_param) |= ((value) << PDEV_PARAM_TXPOWER_VALUE_SHIFT)) + ((txpower_param) &= ~PDEV_PARAM_TXPOWER_VALUE_MASK, (txpower_param) |= ((value) << PDEV_PARAM_TXPOWER_VALUE_SHIFT)) -#define SET_PDEV_PARAM_TXPOWER_REASON(txpower_param, value) \ - ((txpower_param) &= ~PDEV_PARAM_TXPOWER_REASON_MASK, (txpower_param) |= ((value) << PDEV_PARAM_TXPOWER_REASON_SHIFT)) +#define SET_PDEV_PARAM_TXPOWER_REASON(txpower_param, value) \ + ((txpower_param) &= ~PDEV_PARAM_TXPOWER_REASON_MASK, (txpower_param) |= ((value) << PDEV_PARAM_TXPOWER_REASON_SHIFT)) -#define GET_PDEV_PARAM_TXPOWER_VALUE(txpower_param) \ - (((txpower_param) & PDEV_PARAM_TXPOWER_VALUE_MASK) >> PDEV_PARAM_TXPOWER_VALUE_SHIFT) +#define GET_PDEV_PARAM_TXPOWER_VALUE(txpower_param) \ + (((txpower_param) & PDEV_PARAM_TXPOWER_VALUE_MASK) >> PDEV_PARAM_TXPOWER_VALUE_SHIFT) -#define GET_PDEV_PARAM_TXPOWER_REASON(txpower_param) \ - (((txpower_param) & PDEV_PARAM_TXPOWER_REASON_MASK) >> PDEV_PARAM_TXPOWER_REASON_SHIFT) +#define GET_PDEV_PARAM_TXPOWER_REASON(txpower_param) \ + (((txpower_param) & PDEV_PARAM_TXPOWER_REASON_MASK) >> PDEV_PARAM_TXPOWER_REASON_SHIFT) /** * This command is sent from WLAN host driver to firmware to @@ -11953,19 +13039,125 @@ enum { * UART before modem is powered on. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_modem_power_state_cmd_param */ - A_UINT32 tlv_header; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_modem_power_state_cmd_param */ + A_UINT32 tlv_header; - /** Modem power state parameter */ - A_UINT32 modem_power_state; + /** Modem power state parameter */ + A_UINT32 modem_power_state; } wmi_modem_power_state_cmd_param; enum { - WMI_MODEM_STATE_OFF = 0, - WMI_MODEM_STATE_ON + WMI_MODEM_STATE_OFF = 0, + WMI_MODEM_STATE_ON }; +/** + * This command is sent from WLAN host driver to firmware to + * notify the updated Specific Absorption Rate (SAR) limits. + * A critical regulation for FCC compliance, OEMs require methods to set + * limits on TX power of WLAN/WWAN. + * Host would receive instructions on what to set the limits per + * band/chain/modulation to, it would then interpret and send the limits + * to FW using this WMI message. + * Since it is possible to have too many commands to fit into one message, + * FW will keep receiving the messages, until it finds one with + * commit_limits = 1, at which point it will apply all the received + * specifications. + */ + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sar_limits_cmd_param */ + A_UINT32 tlv_header; + + /** when set to WMI_SAR_FEATURE_ON, enable SAR feature; + * if set to WMI_SAR_FEATURE_OFF, disable feature; + * if set to WMI_SAR_FEATURE_NO_CHANGE, do not alter state of feature; + */ + + A_UINT32 sar_enable; + + /** number of items in sar_limits[] */ + A_UINT32 num_limit_rows; + /** once received and is set to 1, FW will calculate the power limits + * and send set_power command to apply them. + * Otherwise just update local values stored in FW until a future msg + * with commit_limits=1 arrives. + */ + + A_UINT32 commit_limits; + + /** + * TLV (tag length value) parameters follow the sar_limit_cmd_row + * structure. The TLV's are: + * wmi_sar_limit_cmd_row sar_limits[]; + */ +} wmi_sar_limits_cmd_fixed_param; + +enum wmi_sar_feature_state_flags { + WMI_SAR_FEATURE_OFF = 0, + WMI_SAR_FEATURE_ON_SET_0, + WMI_SAR_FEATURE_ON_SET_1, + WMI_SAR_FEATURE_ON_SET_2, + WMI_SAR_FEATURE_ON_SET_3, + WMI_SAR_FEATURE_ON_SET_4, + WMI_SAR_FEATURE_NO_CHANGE +}; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sar_limit_cmd_row */ + + /** Current values: WMI_SAR_2G_ID, WMI_SAR_5G_ID. Can be extended by adding + * new band_id values . + */ + A_UINT32 band_id; + + A_UINT32 chain_id; + + /** Current values: WMI_SAR_MOD_CCK, WMI_SAR_MOD_OFDM */ + A_UINT32 mod_id; + + /** actual power limit value, in steps of 0.5 dBm */ + A_UINT32 limit_value; + + /** in case the OEM doesn't care about one of the qualifiers from above, + * the bit for that qualifier within the validity_bitmap can be set to 0 + * so that limit is applied to all possible cases of this qualifier + * (i.e. if a qualifier's validity_bitmap flag is 0, the qualifier is + * treated as a wildcard). + * Current masks: + * WMI_SAR_BAND_ID_VALID_MASK + * WMI_SAR_CHAIN_ID_VALID_MASK + * WMI_SAR_MOD_ID_VALID_MASK + * Example: if !WMI_IS_SAR_MOD_ID_VALID(bitmap), + * it means apply same limit_value to both WMI_SAR_MOD_CCK and + * WMI_SAR_MOD_OFDM cases. + */ + + A_UINT32 validity_bitmap; +} wmi_sar_limit_cmd_row; + +enum wmi_sar_band_id_flags { + WMI_SAR_2G_ID = 0, + WMI_SAR_5G_ID +}; + +enum wmi_sar_mod_id_flags { + WMI_SAR_MOD_CCK = 0, + WMI_SAR_MOD_OFDM +}; + +#define WMI_SAR_BAND_ID_VALID_MASK (0x1) +#define WMI_SAR_CHAIN_ID_VALID_MASK (0x2) +#define WMI_SAR_MOD_ID_VALID_MASK (0x4) + +#define WMI_SET_SAR_BAND_ID_VALID(bitmap) ((bitmap) |= WMI_SAR_BAND_ID_VALID_MASK) +#define WMI_SET_SAR_CHAIN_ID_VALID(bitmap) ((bitmap) |= WMI_SAR_CHAIN_ID_VALID_MASK) +#define WMI_SET_SAR_MOD_ID_VALID(bitmap) ((bitmap) |= WMI_SAR_MOD_ID_VALID_MASK) + +#define WMI_IS_SAR_BAND_ID_VALID(bitmap) ((bitmap) & WMI_SAR_BAND_ID_VALID_MASK) +#define WMI_IS_SAR_CHAIN_ID_VALID(bitmap) ((bitmap) & WMI_SAR_CHAIN_ID_VALID_MASK) +#define WMI_IS_SAR_MOD_ID_VALID(bitmap) ((bitmap) & WMI_SAR_MOD_ID_VALID_MASK) #define WMI_ROAM_AUTH_STATUS_CONNECTED 0x1 /** connected, but not authenticated */ #define WMI_ROAM_AUTH_STATUS_AUTHENTICATED 0x2 /** connected and authenticated */ @@ -11974,210 +13166,223 @@ enum { generated whenever firmware roamed to new AP silently and (a) If the host is awake, FW sends the event to the host immediately . (b) If host is in sleep then either - (1) FW waits until host sends WMI_PDEV_RESUME_CMDID or WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID + (1) FW waits until host sends WMI_PDEV_RESUME_CMDID or WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID command to FW (part of host wake up sequence from low power mode) before sending the event host. - (2) data/mgmt frame is received from roamed AP, which needs to return to host -*/ + (2) data/mgmt frame is received from roamed AP, which needs to return to host + */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material */ - A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material */ + A_UINT32 tlv_header; - A_UINT8 kck[GTK_OFFLOAD_KCK_BYTES]; /* EAPOL-Key Key Confirmation Key (KCK) */ - A_UINT8 kek[GTK_OFFLOAD_KEK_BYTES]; /* EAPOL-Key Key Encryption Key (KEK) */ - A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; + A_UINT8 kck[GTK_OFFLOAD_KCK_BYTES]; /* EAPOL-Key Key Confirmation Key (KCK) */ + A_UINT8 kek[GTK_OFFLOAD_KEK_BYTES]; /* EAPOL-Key Key Encryption Key (KEK) */ + A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; } wmi_key_material; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param */ - /** Unique id identifying the VDEV on which roaming is done by firmware */ - A_UINT32 vdev_id; - /** auth_status: connected or authorized */ - A_UINT32 auth_status; - /** roam_reason: - * bits 0-3 for roam reason see WMI_ROAM_REASON_XXX - * bits 4-5 for subnet status see WMI_ROAM_SUBNET_CHANGE_STATUS_XXX. - */ - A_UINT32 roam_reason; - /** associated AP's rssi calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI. not valid if roam_reason is BMISS */ - A_UINT32 rssi; - /** MAC address of roamed AP */ - wmi_mac_addr bssid; /* BSSID */ - /** whether the frame is beacon or probe rsp */ - A_UINT32 is_beacon; - /** the length of beacon/probe rsp */ - A_UINT32 bcn_probe_rsp_len; - /** the length of reassoc rsp */ - A_UINT32 reassoc_rsp_len; - /** the length of reassoc req */ - A_UINT32 reassoc_req_len; - /** - * TLV (tag length value) parameters follows roam_synch_event - * The TLV's are: - * A_UINT8 bcn_probe_rsp_frame[]; length identified by bcn_probe_rsp_len - * A_UINT8 reassoc_rsp_frame[]; length identified by reassoc_rsp_len - * wmi_channel chan; - * wmi_key_material key; - * A_UINT32 status; subnet changed status not being used currently. - * will pass the information using roam_status. - * A_UINT8 reassoc_req_frame[]; length identified by reassoc_req_len - * - **/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param */ + /** Unique id identifying the VDEV on which roaming is done by firmware */ + A_UINT32 vdev_id; + /** auth_status: connected or authorized */ + A_UINT32 auth_status; + /* + * roam_reason: + * bits 0-3 for roam reason see WMI_ROAM_REASON_XXX + * bits 4-5 for subnet status see WMI_ROAM_SUBNET_CHANGE_STATUS_XXX. + */ + A_UINT32 roam_reason; + /** associated AP's rssi calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI. not valid if roam_reason is BMISS */ + A_UINT32 rssi; + /** MAC address of roamed AP */ + wmi_mac_addr bssid; /* BSSID */ + /** whether the frame is beacon or probe rsp */ + A_UINT32 is_beacon; + /** the length of beacon/probe rsp */ + A_UINT32 bcn_probe_rsp_len; + /** the length of reassoc rsp */ + A_UINT32 reassoc_rsp_len; + /** the length of reassoc req */ + A_UINT32 reassoc_req_len; + /** + * TLV (tag length value ) parameters follows roam_synch_event + * The TLV's are: + * A_UINT8 bcn_probe_rsp_frame[]; length identified by bcn_probe_rsp_len + * A_UINT8 reassoc_rsp_frame[]; length identified by reassoc_rsp_len + * wmi_channel chan; + * wmi_key_material key; + * A_UINT32 status; subnet changed status not being used + * currently. will pass the information using roam_status. + * A_UINT8 reassoc_req_frame[]; length identified by reassoc_req_len + **/ } wmi_roam_synch_event_fixed_param; #define WMI_PEER_ESTIMATED_LINKSPEED_INVALID 0xFFFFFFFF typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_get_estimated_linkspeed_cmd_fixed_param */ - A_UINT32 tlv_header; - /** MAC address of the peer for which the estimated link speed is required. */ - wmi_mac_addr peer_macaddr; - /* Set to 1 only if vdev_id field is valid */ - A_UINT32 valid_vdev_id; - /* VDEV to which the peer belongs to */ - A_UINT32 vdev_id; + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_get_estimated_linkspeed_cmd_fixed_param */ + A_UINT32 tlv_header; + /** MAC address of the peer for which the estimated link speed is required. */ + wmi_mac_addr peer_macaddr; + /* Set to 1 only if vdev_id field is valid */ + A_UINT32 valid_vdev_id; + /* VDEV to which the peer belongs to */ + A_UINT32 vdev_id; } wmi_peer_get_estimated_linkspeed_cmd_fixed_param; typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_estimated_linkspeed_event_fixed_param */ - A_UINT32 tlv_header; - /** MAC address of the peer for which the estimated link speed is required. - */ - wmi_mac_addr peer_macaddr; - /* Estimated link speed in kbps. - * When est_linkspeed_kbps is not valid, the value is set to WMI_PEER_ESTIMATED_LINKSPEED_INVALID. - */ - A_UINT32 est_linkspeed_kbps; - /* Set to 1 only if vdev_id field is valid */ - A_UINT32 valid_vdev_id; - /* VDEV to which the peer belongs to */ - A_UINT32 vdev_id; + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_estimated_linkspeed_event_fixed_param */ + A_UINT32 tlv_header; + /** MAC address of the peer for which the estimated link speed is required. + */ + wmi_mac_addr peer_macaddr; + /* Estimated link speed in kbps. + * When est_linkspeed_kbps is not valid, the value is set to WMI_PEER_ESTIMATED_LINKSPEED_INVALID. + */ + A_UINT32 est_linkspeed_kbps; + /* Set to 1 only if vdev_id field is valid */ + A_UINT32 valid_vdev_id; + /* VDEV to which the peer belongs to */ + A_UINT32 vdev_id; } wmi_peer_estimated_linkspeed_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals */ - /* vdev ID */ - A_UINT32 vdev_id; - A_UINT32 data_len; /** length in byte of data[]. */ - /* This structure is used to send REQ binary blobs -* from application/service to firmware where Host drv is pass through . -* Following this structure is the TLV: -* A_UINT8 data[]; <-- length in byte given by field data_len. -*/ + A_UINT32 tlv_header; /* TLV tag and len; tag equals */ + /* vdev ID */ + A_UINT32 vdev_id; + A_UINT32 data_len; + /** length in byte of data[]. */ + /* This structure is used to send REQ binary blobs + * from application/service to firmware where Host drv is pass through . + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field data_len. + */ } wmi_req_stats_ext_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats1_event_fix_param */ - A_UINT32 vdev_id; /** vdev ID */ - A_UINT32 data_len; /** length in byte of data[]. */ - /* This structure is used to send REQ binary blobs - * from firmware to application/service where Host drv is pass through . - * Following this structure is the TLV: - * A_UINT8 data[]; <-- length in byte given by field data_len. - */ + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats1_event_fix_param */ + A_UINT32 vdev_id; + /** vdev ID */ + A_UINT32 data_len; + /** length in byte of data[]. */ + /* This structure is used to send REQ binary blobs + * from firmware to application/service where Host drv is pass through . + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field data_len. + */ } wmi_stats_ext_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** peer MAC address */ - wmi_mac_addr peer_macaddr; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param */ + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_peer_delete_resp_event_fixed_param; typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_state_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* vdev ID */ - /* MAC address of the peer for which the estimated link speed is required.*/ - wmi_mac_addr peer_macaddr; - A_UINT32 state; /* peer state */ + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_state_event_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; /* vdev ID */ + /* MAC address of the peer for which the estimated link speed is required. */ + wmi_mac_addr peer_macaddr; + A_UINT32 state; /* peer state */ } wmi_peer_state_event_fixed_param; typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param */ - A_UINT32 tlv_header; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* peer MAC address */ - wmi_mac_addr peer_macaddr; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param + */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* peer MAC address */ + wmi_mac_addr peer_macaddr; } wmi_peer_assoc_conf_event_fixed_param; enum { - WMI_2G4_HT40_OBSS_SCAN_PASSIVE = 0, /** scan_type: passive */ - WMI_2G4_HT40_OBSS_SCAN_ACTIVE, /** scan_type: active */ + WMI_2G4_HT40_OBSS_SCAN_PASSIVE = 0, + /** scan_type: passive */ + WMI_2G4_HT40_OBSS_SCAN_ACTIVE, + /** scan_type: active */ }; typedef struct { - /** - * TLV tag and len; - * tag equals WMITLV_TAG_STRUC_wmi_obss_scan_enalbe_cmd_fixed_param - */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /** - * active or passive. if active all the channels are actively scanned. - * if passive then all the channels are passively scanned - */ - A_UINT32 scan_type; - /** - * FW can perform multiple scans with in a OBSS scan interval. - * For each scan, - * if the scan is passive then obss_scan_passive_dwell is minimum dwell to be used for each channel , - * if the scan is active then obss_scan_active_dwell is minimum dwell to be used for each channel . - * The unit for these 2 parameters is TUs. - */ - A_UINT32 obss_scan_passive_dwell; - A_UINT32 obss_scan_active_dwell; - /** - * OBSS scan interval . FW needs to perform one or more OBSS scans within this interval and fulfill the - * both min and total per channel dwell time requirement - */ - A_UINT32 bss_channel_width_trigger_scan_interval; - /** - * FW can perform multiple scans with in a OBSS scan interval. - * For each scan, - * the total per channel dwell time across all scans with in OBSS scan interval should be - * atleast obss_scan_passive_total_per channel for passive scas and obss_scan_active_total_per channel - * for active scans and , - * The unit for these 2 parameters is TUs. - */ - A_UINT32 obss_scan_passive_total_per_channel; - A_UINT32 obss_scan_active_total_per_channel; - A_UINT32 bss_width_channel_transition_delay_factor; /** parameter to check exemption from scan */ - A_UINT32 obss_scan_activity_threshold; /** parameter to check exemption from scan */ - /** following two parameters used by FW to fill IEs when sending 20/40 coexistence action frame to AP */ - A_UINT32 forty_mhz_intolerant; /** STA 40M bandwidth intolerant capability */ - A_UINT32 current_operating_class; /** STA current operating class */ - /** length of 2.4GHz channel list to scan at, channel list in tlv->channels[] */ - A_UINT32 channel_len; - /** length of optional ie data to append to probe reqest when active scan, ie data in tlv->ie_field[] */ - A_UINT32 ie_len; + /** + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_obss_scan_enalbe_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /** + * active or passive. if active all the channels are actively scanned. + * if passive then all the channels are passively scanned + */ + A_UINT32 scan_type; + /** + * FW can perform multiple scans with in a OBSS scan interval. + * For each scan, + * if the scan is passive then obss_scan_passive_dwell is minimum dwell to be used for each channel , + * if the scan is active then obss_scan_active_dwell is minimum dwell to be used for each channel . + * The unit for these 2 parameters is TUs. + */ + A_UINT32 obss_scan_passive_dwell; + A_UINT32 obss_scan_active_dwell; + /** + * OBSS scan interval . FW needs to perform one or more OBSS scans within this interval and fulfill the + * both min and total per channel dwell time requirement + */ + A_UINT32 bss_channel_width_trigger_scan_interval; + /** + * FW can perform multiple scans with in a OBSS scan interval. + * For each scan, + * the total per channel dwell time across all scans with in OBSS scan interval should be + * atleast obss_scan_passive_total_per channel for passive scas and obss_scan_active_total_per channel + * for active scans and , + * The unit for these 2 parameters is TUs. + */ + A_UINT32 obss_scan_passive_total_per_channel; + A_UINT32 obss_scan_active_total_per_channel; + A_UINT32 bss_width_channel_transition_delay_factor; + /** parameter to check exemption from scan */ + A_UINT32 obss_scan_activity_threshold; + /** parameter to check exemption from scan */ + /** following two parameters used by FW to fill IEs when sending 20/40 coexistence action frame to AP */ + A_UINT32 forty_mhz_intolerant; + /** STA 40M bandwidth intolerant capability */ + A_UINT32 current_operating_class; + /** STA current operating class */ + /** length of 2.4GHz channel list to scan at, channel list in tlv->channels[] */ + A_UINT32 channel_len; + /** length of optional ie data to append to probe reqest when active scan, ie data in tlv->ie_field[] */ + A_UINT32 ie_len; } wmi_obss_scan_enable_cmd_fixed_param; typedef struct { - /** - * TLV tag and len; - * tag equals WMITLV_TAG_STRUC_wmi_obss_scan_disalbe_cmd_fixed_param - */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; + /** + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_obss_scan_disalbe_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; } wmi_obss_scan_disable_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_offload_prb_rsp_tx_status_event_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV */ - A_UINT32 vdev_id; - /** prb rsp tx status, values defined in enum WMI_FRAME_TX_STATUS */ - A_UINT32 tx_status; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_offload_prb_rsp_tx_status_event_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV */ + A_UINT32 vdev_id; + /** prb rsp tx status, values defined in enum WMI_FRAME_TX_STATUS */ + A_UINT32 tx_status; } wmi_offload_prb_rsp_tx_status_event_fixed_param; typedef enum { - WMI_FRAME_TX_OK, /* frame tx ok */ - WMI_FRAME_TX_XRETRY, /* excessivley retried */ - WMI_FRAME_TX_DROP, /* frame dropped by FW due to resources */ - WMI_FRAME_TX_FILTERED, /* frame filtered by hardware */ + WMI_FRAME_TX_OK, /* frame tx ok */ + WMI_FRAME_TX_XRETRY, /* excessivley retried */ + WMI_FRAME_TX_DROP, /* frame dropped by FW due to resources */ + WMI_FRAME_TX_FILTERED, /* frame filtered by hardware */ } WMI_FRAME_TX_STATUS; /** @@ -12193,211 +13398,221 @@ typedef enum { * avoidance information update. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_chan_avoid_update_cmd_param */ - A_UINT32 tlv_header; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_chan_avoid_update_cmd_param */ + A_UINT32 tlv_header; } wmi_chan_avoid_update_cmd_param; /* ExtScan operation mode */ typedef enum { - WMI_EXTSCAN_MODE_NONE = 0x0000, - WMI_EXTSCAN_MODE_START = 0x0001, /* ExtScan/TableMonitoring operation started */ - WMI_EXTSCAN_MODE_STOP = 0x0002, /* ExtScan/TableMonitoring operation stopped */ - WMI_EXTSCAN_MODE_IGNORED = 0x0003, /* ExtScan command ignored due to error */ + WMI_EXTSCAN_MODE_NONE = 0x0000, + WMI_EXTSCAN_MODE_START = 0x0001, /* ExtScan/TableMonitoring operation started */ + WMI_EXTSCAN_MODE_STOP = 0x0002, /* ExtScan/TableMonitoring operation stopped */ + WMI_EXTSCAN_MODE_IGNORED = 0x0003, /* ExtScan command ignored due to error */ } wmi_extscan_operation_mode; /* Channel Mask */ typedef enum { - WMI_CHANNEL_BAND_UNSPECIFIED = 0x0000, - WMI_CHANNEL_BAND_24 = 0x0001, /* 2.4 channel */ - WMI_CHANNEL_BAND_5_NON_DFS = 0x0002, /* 5G Channels (No DFS channels) */ - WMI_CHANNEL_BAND_DFS = 0x0004, /* DFS channels */ + WMI_CHANNEL_BAND_UNSPECIFIED = 0x0000, + WMI_CHANNEL_BAND_24 = 0x0001, /* 2.4 channel */ + WMI_CHANNEL_BAND_5_NON_DFS = 0x0002, /* 5G Channels (No DFS channels) */ + WMI_CHANNEL_BAND_DFS = 0x0004, /* DFS channels */ } wmi_channel_band_mask; typedef enum { - WMI_EXTSCAN_CYCLE_STARTED_EVENT = 0x0001, - WMI_EXTSCAN_CYCLE_COMPLETED_EVENT = 0x0002, - WMI_EXTSCAN_BUCKET_STARTED_EVENT = 0x0004, - WMI_EXTSCAN_BUCKET_COMPLETED_EVENT = 0x0008, - WMI_EXTSCAN_BUCKET_FAILED_EVENT = 0x0010, - WMI_EXTSCAN_BUCKET_OVERRUN_EVENT = 0x0020, - WMI_EXTSCAN_THRESHOLD_NUM_SCANS = 0x0040, - WMI_EXTSCAN_THRESHOLD_PERCENT = 0x0080, + WMI_EXTSCAN_CYCLE_STARTED_EVENT = 0x0001, + WMI_EXTSCAN_CYCLE_COMPLETED_EVENT = 0x0002, + WMI_EXTSCAN_BUCKET_STARTED_EVENT = 0x0004, + WMI_EXTSCAN_BUCKET_COMPLETED_EVENT = 0x0008, + WMI_EXTSCAN_BUCKET_FAILED_EVENT = 0x0010, + WMI_EXTSCAN_BUCKET_OVERRUN_EVENT = 0x0020, + WMI_EXTSCAN_THRESHOLD_NUM_SCANS = 0x0040, + WMI_EXTSCAN_THRESHOLD_PERCENT = 0x0080, - WMI_EXTSCAN_EVENT_MAX = 0x8000 + WMI_EXTSCAN_EVENT_MAX = 0x8000 } wmi_extscan_event_type; #define WMI_EXTSCAN_CYCLE_EVENTS_MASK (WMI_EXTSCAN_CYCLE_STARTED_EVENT | \ - WMI_EXTSCAN_CYCLE_COMPLETED_EVENT) + WMI_EXTSCAN_CYCLE_COMPLETED_EVENT) #define WMI_EXTSCAN_BUCKET_EVENTS_MASK (WMI_EXTSCAN_BUCKET_STARTED_EVENT | \ - WMI_EXTSCAN_BUCKET_COMPLETED_EVENT | \ - WMI_EXTSCAN_BUCKET_FAILED_EVENT | \ - WMI_EXTSCAN_BUCKET_OVERRUN_EVENT) + WMI_EXTSCAN_BUCKET_COMPLETED_EVENT | \ + WMI_EXTSCAN_BUCKET_FAILED_EVENT | \ + WMI_EXTSCAN_BUCKET_OVERRUN_EVENT) typedef enum { - WMI_EXTSCAN_NO_FORWARDING = 0x0000, - WMI_EXTSCAN_FORWARD_FRAME_TO_HOST = 0x0001 + WMI_EXTSCAN_NO_FORWARDING = 0x0000, + WMI_EXTSCAN_FORWARD_FRAME_TO_HOST = 0x0001 } wmi_extscan_forwarding_flags; typedef enum { - WMI_EXTSCAN_USE_MSD = 0x0001, /* Use Motion Sensor Detection */ - WMI_EXTSCAN_EXTENDED_BATCHING_EN = 0x0002, /* Extscan LPASS extended batching feature is supported and enabled */ + /* Use Motion Sensor Detection */ + WMI_EXTSCAN_USE_MSD = 0x0001, + /* Extscan LPASS extended batching feature is supported and enabled */ + WMI_EXTSCAN_EXTENDED_BATCHING_EN = 0x0002, } wmi_extscan_configuration_flags; - typedef enum { - WMI_EXTSCAN_BUCKET_CACHE_RESULTS = 0x0001, /* Cache the results of bucket whose configuration flags has this bit set */ - WMI_EXTSCAN_REPORT_EVENT_CONTEXT_HUB = 0x0002, /* Report ext scan results to context hub or not. */ + /* + * Cache the results of bucket whose + * configuration flags has this bit set + */ + WMI_EXTSCAN_BUCKET_CACHE_RESULTS = 0x0001, + /* Report ext scan results to context hub or not.*/ + WMI_EXTSCAN_REPORT_EVENT_CONTEXT_HUB = 0x0002, } wmi_extscan_bucket_configuration_flags; typedef enum { - WMI_EXTSCAN_STATUS_OK = 0, - WMI_EXTSCAN_STATUS_ERROR = 0x80000000, - WMI_EXTSCAN_STATUS_INVALID_PARAMETERS, - WMI_EXTSCAN_STATUS_INTERNAL_ERROR + WMI_EXTSCAN_STATUS_OK = 0, + WMI_EXTSCAN_STATUS_ERROR = 0x80000000, + WMI_EXTSCAN_STATUS_INVALID_PARAMETERS, + WMI_EXTSCAN_STATUS_INTERNAL_ERROR } wmi_extscan_start_stop_status; typedef struct { - /** Request ID - to identify command. Cannot be 0 */ - A_UINT32 request_id; - /** Requestor ID - client requesting ExtScan */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; + /** Request ID - to identify command. Cannot be 0 */ + A_UINT32 request_id; + /** Requestor ID - client requesting ExtScan */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; } wmi_extscan_command_id; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /** channel number */ - A_UINT32 channel; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /** channel number */ + A_UINT32 channel; - /** dwell time in msec - use defaults if 0 */ - A_UINT32 min_dwell_time; - A_UINT32 max_dwell_time; - - /** passive/active channel and other flags */ - A_UINT32 control_flags; /* 0 => active, 1 => passive scan; ignored for DFS */ + /** dwell time in msec - use defaults if 0 */ + A_UINT32 min_dwell_time; + A_UINT32 max_dwell_time; + /** passive/active channel and other flags */ + A_UINT32 control_flags; /* 0 => active, 1 => passive scan; ignored for DFS */ } wmi_extscan_bucket_channel; /* Scan Bucket specification */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /** Bucket ID - 0-based */ - A_UINT32 bucket_id; - /** ExtScan events subscription - events to be reported to client (see wmi_extscan_event_type) */ - A_UINT32 notify_extscan_events; - /** Options to forward scan results - see wmi_extscan_forwarding_flags */ - A_UINT32 forwarding_flags; - /** ExtScan configuration flags - wmi_extscan_bucket_configuration_flags */ - A_UINT32 configuration_flags; - /** DEPRECATED member: multiplier to be applied to the periodic scan's base period */ - A_UINT32 base_period_multiplier; - /** dwell time in msec on active channels - use defaults if 0 */ - A_UINT32 min_dwell_time_active; - A_UINT32 max_dwell_time_active; - /** dwell time in msec on passive channels - use defaults if 0 */ - A_UINT32 min_dwell_time_passive; - A_UINT32 max_dwell_time_passive; - /** see wmi_channel_band_mask; when equal to WMI_CHANNEL_UNSPECIFIED, use channel list */ - A_UINT32 channel_band; - /** number of channels (if channel_band is WMI_CHANNEL_UNSPECIFIED) */ - A_UINT32 num_channels; - /** scan period upon start or restart of the bucket - periodicity of the bucket to begin with */ - A_UINT32 min_period; - /** period above which exponent is not applied anymore */ - A_UINT32 max_period; - /** back off value to be applied to bucket's periodicity after exp_max_step_count scan cycles - * new_bucket_period = last_bucket_period + last_exponent_period * exp_backoff - */ - A_UINT32 exp_backoff; - /** number of scans performed at a given periodicity after which exponential back off value is - * applied to current periodicity to obtain a newer one - */ - A_UINT32 exp_max_step_count; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /** Bucket ID - 0-based */ + A_UINT32 bucket_id; + /** ExtScan events subscription - events to be reported to client (see wmi_extscan_event_type) */ + A_UINT32 notify_extscan_events; + /** Options to forward scan results - see wmi_extscan_forwarding_flags */ + A_UINT32 forwarding_flags; + /* + * ExtScan configuration flags - + * wmi_extscan__bucket_configuration_flags + */ + A_UINT32 configuration_flags; + /** DEPRECATED member:multiplier to be applied to the periodic scan's base period */ + A_UINT32 base_period_multiplier; + /** dwell time in msec on active channels - use defaults if 0 */ + A_UINT32 min_dwell_time_active; + A_UINT32 max_dwell_time_active; + /** dwell time in msec on passive channels - use defaults if 0 */ + A_UINT32 min_dwell_time_passive; + A_UINT32 max_dwell_time_passive; + /** see wmi_channel_band_mask; when equal to WMI_CHANNEL_UNSPECIFIED, use channel list */ + A_UINT32 channel_band; + /** number of channels (if channel_band is WMI_CHANNEL_UNSPECIFIED) */ + A_UINT32 num_channels; + /** scan period upon start or restart of the bucket - periodicity of the bucket to begin with */ + A_UINT32 min_period; + /** period above which exponent is not applied anymore */ + A_UINT32 max_period; + /** + * back off value to be applied to bucket's periodicity after exp_max_step_count scan cycles + * new_bucket_period = last_bucket_period + last_exponent_period exp_backoff + */ + A_UINT32 exp_backoff; + /** number of scans performed at a given periodicity after which exponential back off value is + * applied to current periodicity to obtain a newer one + */ + A_UINT32 exp_max_step_count; /** Followed by the variable length TLV chan_list: * wmi_extscan_bucket_channel chan_list[] */ } wmi_extscan_bucket; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_start_cmd_fixed_param */ - /** Request ID - to identify command. Cannot be 0 */ - A_UINT32 request_id; - /** Requestor ID - client requesting ExtScan */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous requests */ - A_UINT32 table_id; - /** Base period (milliseconds) used by scan buckets to define periodicity of the scans */ - A_UINT32 base_period; - /** Maximum number of iterations to run - one iteration is the scanning of the least frequent bucket */ - A_UINT32 max_iterations; - /** Options to forward scan results - see wmi_extscan_forwarding_flags */ - A_UINT32 forwarding_flags; - /** ExtScan configuration flags - wmi_extscan_configuration_flags */ - A_UINT32 configuration_flags; - /** ExtScan events subscription - bitmask indicating which events should be send to client (see wmi_extscan_event_type) */ - A_UINT32 notify_extscan_events; - /** Scan Priority, input to scan scheduler */ - A_UINT32 scan_priority; - /** Maximum number of BSSIDs to cache on each scan cycle */ - A_UINT32 max_bssids_per_scan_cycle; - /** Minimum RSSI value to report */ - A_UINT32 min_rssi; - /** Maximum table usage in percentage */ - A_UINT32 max_table_usage; - /** default dwell time in msec on active channels */ - A_UINT32 min_dwell_time_active; - A_UINT32 max_dwell_time_active; - /** default dwell time in msec on passive channels */ - A_UINT32 min_dwell_time_passive; - A_UINT32 max_dwell_time_passive; - /** min time in msec on the BSS channel,only valid if atleast one VDEV is active*/ - A_UINT32 min_rest_time; - /** max rest time in msec on the BSS channel,only valid if at least one VDEV is active*/ - /** the scanner will rest on the bss channel at least min_rest_time. after min_rest_time the scanner - * will start checking for tx/rx activity on all VDEVs. if there is no activity the scanner will - * switch to off channel. if there is activity the scanner will let the radio on the bss channel - * until max_rest_time expires.at max_rest_time scanner will switch to off channel - * irrespective of activity. activity is determined by the idle_time parameter. - */ - A_UINT32 max_rest_time; - /** time before sending next set of probe requests. - * The scanner keeps repeating probe requests transmission with period specified by repeat_probe_time. - * The number of probe requests specified depends on the ssid_list and bssid_list - */ - /** Max number of probes to be sent */ - A_UINT32 n_probes; - /** time in msec between 2 sets of probe requests. */ - A_UINT32 repeat_probe_time; - /** time in msec between 2 consequetive probe requests with in a set. */ - A_UINT32 probe_spacing_time; - /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity */ - A_UINT32 idle_time; - /** maximum time in msec allowed for scan */ - A_UINT32 max_scan_time; - /** delay in msec before sending first probe request after switching to a channel */ - A_UINT32 probe_delay; - /** Scan control flags */ - A_UINT32 scan_ctrl_flags; - /** Burst duration time in msec*/ - A_UINT32 burst_duration; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_start_cmd_fixed_param */ + /** Request ID - to identify command. Cannot be 0 */ + A_UINT32 request_id; + /** Requestor ID - client requesting ExtScan */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous requests */ + A_UINT32 table_id; + /** Base period (milliseconds) used by scan buckets to define periodicity of the scans */ + A_UINT32 base_period; + /** Maximum number of iterations to run - one iteration is the scanning of the least frequent bucket */ + A_UINT32 max_iterations; + /** Options to forward scan results - see wmi_extscan_forwarding_flags */ + A_UINT32 forwarding_flags; + /** ExtScan configuration flags - wmi_extscan_configuration_flags */ + A_UINT32 configuration_flags; + /** ExtScan events subscription - bitmask indicating which events should be send to client (see wmi_extscan_event_type) */ + A_UINT32 notify_extscan_events; + /** Scan Priority, input to scan scheduler */ + A_UINT32 scan_priority; + /** Maximum number of BSSIDs to cache on each scan cycle */ + A_UINT32 max_bssids_per_scan_cycle; + /** Minimum RSSI value to report */ + A_UINT32 min_rssi; + /** Maximum table usage in percentage */ + A_UINT32 max_table_usage; + /** default dwell time in msec on active channels */ + A_UINT32 min_dwell_time_active; + A_UINT32 max_dwell_time_active; + /** default dwell time in msec on passive channels */ + A_UINT32 min_dwell_time_passive; + A_UINT32 max_dwell_time_passive; + /** min time in msec on the BSS channel,only valid if atleast one VDEV is active*/ + A_UINT32 min_rest_time; + /** max rest time in msec on the BSS channel,only valid if at least one VDEV is active*/ + /** the scanner will rest on the bss channel at least min_rest_time. after min_rest_time the scanner + * will start checking for tx/rx activity on all VDEVs. if there is no activity the scanner will + * switch to off channel. if there is activity the scanner will let the radio on the bss channel + * until max_rest_time expires.at max_rest_time scanner will switch to off channel + * irrespective of activity. activity is determined by the idle_time parameter. + */ + A_UINT32 max_rest_time; + /** time before sending next set of probe requests. + * The scanner keeps repeating probe requests transmission with period specified by repeat_probe_time. + * The number of probe requests specified depends on the ssid_list and bssid_list + */ + /** Max number of probes to be sent */ + A_UINT32 n_probes; + /** time in msec between 2 sets of probe requests. */ + A_UINT32 repeat_probe_time; + /** time in msec between 2 consequetive probe requests with in a set. */ + A_UINT32 probe_spacing_time; + /** data inactivity time in msec on bss channel that will be used by scanner for measuring the inactivity */ + A_UINT32 idle_time; + /** maximum time in msec allowed for scan */ + A_UINT32 max_scan_time; + /** delay in msec before sending first probe request after switching to a channel */ + A_UINT32 probe_delay; + /** Scan control flags */ + A_UINT32 scan_ctrl_flags; + /** Burst duration time in msec*/ + A_UINT32 burst_duration; - /** number of bssids in the TLV bssid_list[] */ - A_UINT32 num_bssid; - /** number of ssid in the TLV ssid_list[] */ - A_UINT32 num_ssids; - /** number of bytes in TLV ie_data[] */ - A_UINT32 ie_len; - /** number of buckets in the TLV bucket_list[] */ - A_UINT32 num_buckets; - /** in number of scans, send notifications to host after these many scans */ - A_UINT32 report_threshold_num_scans; - /** number of channels in channel_list[] determined by the - sum of wmi_extscan_bucket.num_channels in array */ + /** number of bssids in the TLV bssid_list[] */ + A_UINT32 num_bssid; + /** number of ssid in the TLV ssid_list[] */ + A_UINT32 num_ssids; + /** number of bytes in TLV ie_data[] */ + A_UINT32 ie_len; + /** number of buckets in the TLV bucket_list[] */ + A_UINT32 num_buckets; + /** in number of scans, send notifications to host after these many scans */ + A_UINT32 report_threshold_num_scans; + + /** number of channels in channel_list[] determined by the + sum of wmi_extscan_bucket.num_channels in array */ /** - * TLV (tag length value) parameters follow the extscan_cmd + * TLV (tag length value ) parameters follow the extscan_cmd * structure. The TLV's are: * wmi_ssid ssid_list[]; * wmi_mac_addr bssid_list[]; @@ -12408,697 +13623,728 @@ typedef struct { } wmi_extscan_start_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_stop_cmd_fixed_param */ - /** Request ID - to match running command. 0 matches any request */ - A_UINT32 request_id; - /** Requestor ID - client requesting stop */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous requests */ - A_UINT32 table_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_stop_cmd_fixed_param */ + /** Request ID - to match running command. 0 matches any request */ + A_UINT32 request_id; + /** Requestor ID - client requesting stop */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous requests */ + A_UINT32 table_id; } wmi_extscan_stop_cmd_fixed_param; enum wmi_extscan_get_cached_results_flags { - WMI_EXTSCAN_GET_CACHED_RESULTS_FLAG_NONE = 0x0000, - WMI_EXTSCAN_GET_CACHED_RESULTS_FLAG_FLUSH_TABLE = 0x0001 + WMI_EXTSCAN_GET_CACHED_RESULTS_FLAG_NONE = 0x0000, + WMI_EXTSCAN_GET_CACHED_RESULTS_FLAG_FLUSH_TABLE = 0x0001 }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_get_cached_results_cmd_fixed_param */ - /** request ID - used to correlate command with events */ - A_UINT32 request_id; - /** Requestor ID - client that requested results */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous requests */ - A_UINT32 table_id; - /** maximum number of results to be returned */ - A_UINT32 max_results; - /** flush BSSID list - wmi_extscan_get_cached_results_flags */ - A_UINT32 control_flags; /* enum wmi_extscan_get_cached_results_flags */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_get_cached_results_cmd_fixed_param */ + /** request ID - used to correlate command with events */ + A_UINT32 request_id; + /** Requestor ID - client that requested results */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous requests */ + A_UINT32 table_id; + /** maximum number of results to be returned */ + A_UINT32 max_results; + /** flush BSSID list - wmi_extscan_get_cached_results_flags */ + A_UINT32 control_flags; /* enum wmi_extscan_get_cached_results_flags */ } wmi_extscan_get_cached_results_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_get_wlan_change_results_cmd_fixed_param */ - /** request ID - used to correlate command with events */ - A_UINT32 request_id; - /** Requestor ID - client that requested results */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous requests */ - A_UINT32 table_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_get_wlan_change_results_cmd_fixed_param */ + /** request ID - used to correlate command with events */ + A_UINT32 request_id; + /** Requestor ID - client that requested results */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous requests */ + A_UINT32 table_id; } wmi_extscan_get_wlan_change_results_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /**bssid */ - wmi_mac_addr bssid; - /**channel number */ - A_UINT32 channel; - /**upper RSSI limit */ - A_UINT32 upper_rssi_limit; - /**lower RSSI limit */ - A_UINT32 lower_rssi_limit; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /**bssid */ + wmi_mac_addr bssid; + /**channel number */ + A_UINT32 channel; + /**upper RSSI limit */ + A_UINT32 upper_rssi_limit; + /**lower RSSI limit */ + A_UINT32 lower_rssi_limit; } wmi_extscan_wlan_change_bssid_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param */ - /** Request ID - to identify command. Cannot be 0 */ - A_UINT32 request_id; - /** Requestor ID - client requesting wlan change monitoring */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /** operation mode: start/stop */ - A_UINT32 mode; /* wmi_extscan_operation_mode */ - /** number of rssi samples to store */ - A_UINT32 max_rssi_samples; - /** number of samples to use to calculate RSSI average */ - A_UINT32 rssi_averaging_samples; - /** number of scans to confirm loss of contact with RSSI */ - A_UINT32 lost_ap_scan_count; - /** number of out-of-range BSSIDs necessary to send event */ - A_UINT32 max_out_of_range_count; - - /** total number of bssid signal descriptors (in all pages) */ - A_UINT32 total_entries; - /** index of the first bssid entry found in the TLV wlan_change_descriptor_list*/ - A_UINT32 first_entry_index; - /** number of bssid signal descriptors in this page */ - A_UINT32 num_entries_in_page; -/* Following this structure is the TLV: - * wmi_extscan_wlan_change_bssid_param wlan_change_descriptor_list[]; - * (number of elements given by field num_page_entries) - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param */ + /** Request ID - to identify command. Cannot be 0 */ + A_UINT32 request_id; + /** Requestor ID - client requesting wlan change monitoring */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /** operation mode: start/stop */ + A_UINT32 mode; /* wmi_extscan_operation_mode */ + /** number of rssi samples to store */ + A_UINT32 max_rssi_samples; + /** number of samples to use to calculate RSSI average */ + A_UINT32 rssi_averaging_samples; + /** number of scans to confirm loss of contact with RSSI */ + A_UINT32 lost_ap_scan_count; + /** number of out-of-range BSSIDs necessary to send event */ + A_UINT32 max_out_of_range_count; + /** total number of bssid signal descriptors (in all pages) */ + A_UINT32 total_entries; + /** index of the first bssid entry found in the TLV wlan_change_descriptor_list*/ + A_UINT32 first_entry_index; + /** number of bssid signal descriptors in this page */ + A_UINT32 num_entries_in_page; + /* Following this structure is the TLV: + * wmi_extscan_wlan_change_bssid_param wlan_change_descriptor_list[]; // number of elements given by field num_page_entries. + */ } wmi_extscan_configure_wlan_change_monitor_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /**bssid */ - wmi_mac_addr bssid; - /**RSSI min threshold for reporting */ - A_UINT32 min_rssi; - /**Deprecated entry - channel number */ - A_UINT32 channel; - /** RSSI max threshold for reporting */ - A_UINT32 max_rssi; -} wmi_extscan_hotlist_entry; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_monitor_cmd_fixed_param */ - /** Request ID - to identify command. Cannot be 0 */ - A_UINT32 request_id; - /** Requestor ID - client requesting hotlist monitoring */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /** operation mode: start/stop */ - A_UINT32 mode; /* wmi_extscan_operation_mode */ - /** total number of bssids (in all pages) */ - A_UINT32 total_entries; - /** index of the first bssid entry found in the TLV wmi_extscan_hotlist_entry */ - A_UINT32 first_entry_index; - /** number of bssids in this page */ - A_UINT32 num_entries_in_page; - /** number of consecutive scans to confirm loss of contact with AP */ - A_UINT32 lost_ap_scan_count; -/* Following this structure is the TLV: - * wmi_extscan_hotlist_entry hotlist[]; <-- number of elements given by field num_page_entries. - */ -} wmi_extscan_configure_hotlist_monitor_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /**ssid */ - wmi_ssid ssid; - /**band */ - A_UINT32 band; - /**RSSI threshold for reporting */ - A_UINT32 min_rssi; - A_UINT32 max_rssi; + /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + A_UINT32 tlv_header; + /**ssid */ + wmi_ssid ssid; + /**band */ + A_UINT32 band; + /**RSSI threshold for reporting */ + A_UINT32 min_rssi; + A_UINT32 max_rssi; } wmi_extscan_hotlist_ssid_entry; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param */ - /** Request ID - to identify command. Cannot be 0 */ - A_UINT32 request_id; - /** Requestor ID - client requesting hotlist ssid monitoring */ - A_UINT32 requestor_id; - /** VDEV id(interface) that is requesting scan */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /** operation mode: start/stop */ - A_UINT32 mode; /* wmi_extscan_operation_mode */ - /**total number of ssids (in all pages) */ - A_UINT32 total_entries; - /**index of the first ssid entry found in the TLV wmi_extscan_hotlist_ssid_entry*/ - A_UINT32 first_entry_index; - /**number of ssids in this page */ - A_UINT32 num_entries_in_page; + /** + * TLV tag and len; tag equals + * MITLV_TAG_STRUC_wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** Request ID - to identify command. Cannot be 0 */ + A_UINT32 request_id; + /** Requestor ID - client requesting hotlist ssid monitoring */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /** operation mode: start/stop */ + A_UINT32 mode; /* wmi_extscan_operation_mode */ + /**total number of ssids (in all pages) */ + A_UINT32 total_entries; + /**index of the first ssid entry found in the TLV extscan_hotlist_ssid_entry*/ + A_UINT32 first_entry_index; + /**number of ssids in this page */ + A_UINT32 num_entries_in_page; /** number of consecutive scans to confirm loss of an ssid **/ A_UINT32 lost_ap_scan_count; - /* Following this structure is the TLV: - * wmi_extscan_hotlist_ssid_entry hotlist_ssid[]; <-- number of elements given by field num_page_entries. - */ + /* Following this structure is the TLV: + * wmi_extscan_hotlist_ssid_entry hotlist_ssid[]; + * number of element given by field num_page_entries. + */ } wmi_extscan_configure_hotlist_ssid_monitor_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /** size in bytes of scan cache entry */ - A_UINT32 scan_cache_entry_size; - /** maximum number of scan cache entries */ - A_UINT32 max_scan_cache_entries; - /** maximum number of buckets per extscan request */ - A_UINT32 max_buckets; - /** maximum number of BSSIDs that will be stored in each scan (best n/w as per RSSI) */ - A_UINT32 max_bssid_per_scan; - /** table usage level at which indication must be sent to host */ - A_UINT32 max_table_usage_threshold; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /**bssid */ + wmi_mac_addr bssid; + /**RSSI min threshold for reporting */ + A_UINT32 min_rssi; + /**Deprecated entry channel number */ + A_UINT32 channel; + /** RSSI max threshold for reporting */ + A_UINT32 max_rssi; +} wmi_extscan_hotlist_entry; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_configure_hotlist_monitor_cmd_fixed_param */ + /** Request ID - to identify command. Cannot be 0 */ + A_UINT32 request_id; + /** Requestor ID - client requesting hotlist monitoring */ + A_UINT32 requestor_id; + /** VDEV id(interface) that is requesting scan */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /** operation mode: start/stop */ + A_UINT32 mode; /* wmi_extscan_operation_mode */ + /**total number of bssids (in all pages) */ + A_UINT32 total_entries; + /**index of the first bssid entry found in the TLV wmi_extscan_hotlist_entry*/ + A_UINT32 first_entry_index; + /**number of bssids in this page */ + A_UINT32 num_entries_in_page; + /** number of consecutive scans to confirm loss of contact with AP */ + A_UINT32 lost_ap_scan_count; + /* Following this structure is the TLV: + * wmi_extscan_hotlist_entry hotlist[]; // number of elements given by field num_page_entries. + */ +} wmi_extscan_configure_hotlist_monitor_cmd_fixed_param; + + typedef struct { + /* TLV tag and len; tag equals + *WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param */ + A_UINT32 tlv_header; + /** Request ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID that configured the table */ + A_UINT32 config_request_id; + /** Requestor ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID + that configured the table */ + A_UINT32 config_requestor_id; + /** + * VDEV id(interface) of the + * WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID that configured the table + */ + A_UINT32 config_vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /**total number of ssids (in all pages) */ + A_UINT32 total_entries; + /**index of the first ssid entry found in the TLV wmi_extscan_wlan_descriptor*/ + A_UINT32 first_entry_index; + /**number of ssids in this page */ + A_UINT32 num_entries_in_page; + /* Following this structure is the TLV: + * wmi_extscan_wlan_descriptor hotlist_match[]; + * number of descriptors given by field num_entries_in_page + */ +} wmi_extscan_hotlist_ssid_match_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /** size in bytes of scan cache entry */ + A_UINT32 scan_cache_entry_size; + /** maximum number of scan cache entries */ + A_UINT32 max_scan_cache_entries; + /** maximum number of buckets per extscan request */ + A_UINT32 max_buckets; + /** maximum number of BSSIDs that will be stored in each scan (best n/w as per RSSI) */ + A_UINT32 max_bssid_per_scan; + /** table usage level at which indication must be sent to host */ + A_UINT32 max_table_usage_threshold; } wmi_extscan_cache_capabilities; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /** size in bytes of wlan change entry */ - A_UINT32 wlan_change_entry_size; - /** maximum number of entries in wlan change table */ - A_UINT32 max_wlan_change_entries; - /** number of RSSI samples used for averaging RSSI */ - A_UINT32 max_rssi_averaging_samples; - /** number of BSSID/RSSI entries (BSSID pointer, RSSI, timestamp) that device can hold */ - A_UINT32 max_rssi_history_entries; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /** size in bytes of wlan change entry */ + A_UINT32 wlan_change_entry_size; + /** maximum number of entries in wlan change table */ + A_UINT32 max_wlan_change_entries; + /** number of RSSI samples used for averaging RSSI */ + A_UINT32 max_rssi_averaging_samples; + /** number of BSSID/RSSI entries (BSSID pointer, RSSI, timestamp) that device can hold */ + A_UINT32 max_rssi_history_entries; } wmi_extscan_wlan_change_monitor_capabilities; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /** size in bytes of hotlist entry */ - A_UINT32 wlan_hotlist_entry_size; - /** maximum number of entries in wlan change table */ - A_UINT32 max_hotlist_entries; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /** size in bytes of hotlist entry */ + A_UINT32 wlan_hotlist_entry_size; + /** maximum number of entries in wlan change table */ + A_UINT32 max_hotlist_entries; } wmi_extscan_hotlist_monitor_capabilities; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_set_capabilities_cmd_fixed_param */ - /** Request ID - matches request ID used to start hot list monitoring */ - A_UINT32 request_id; - /** Requestor ID - client requesting stop */ - A_UINT32 requestor_id; - /** number of extscan caches */ - A_UINT32 num_extscan_cache_tables; - /** number of wlan change lists */ - A_UINT32 num_wlan_change_monitor_tables; - /** number of hotlists */ - A_UINT32 num_hotlist_monitor_tables; - /** if one sided rtt data collection is supported */ - A_UINT32 rtt_one_sided_supported; - /** if 11v data collection is supported */ - A_UINT32 rtt_11v_supported; - /** if 11mc data collection is supported */ - A_UINT32 rtt_ftm_supported; - /** number of extscan cache capabilities (one per table) */ - A_UINT32 num_extscan_cache_capabilities; - /** number of wlan change capabilities (one per table) */ - A_UINT32 num_extscan_wlan_change_capabilities; - /** number of extscan hotlist capabilities (one per table) */ - A_UINT32 num_extscan_hotlist_capabilities; -/* Following this structure is the TLV: - * wmi_extscan_cache_capabilities extscan_cache_capabilities; <-- number of capabilities given by num_extscan_caches - * wmi_extscan_wlan_change_monitor_capabilities wlan_change_capabilities; <-- number of capabilities given by num_wlan_change_monitor_tables - * wmi_extscan_hotlist_monitor_capabilities hotlist_capabilities; <-- number of capabilities given by num_hotlist_monitor_tables - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_set_capabilities_cmd_fixed_param */ + /** Request ID - matches request ID used to start hot list monitoring */ + A_UINT32 request_id; + /** Requestor ID - client requesting stop */ + A_UINT32 requestor_id; + /** number of extscan caches */ + A_UINT32 num_extscan_cache_tables; + /** number of wlan change lists */ + A_UINT32 num_wlan_change_monitor_tables; + /** number of hotlists */ + A_UINT32 num_hotlist_monitor_tables; + /** if one sided rtt data collection is supported */ + A_UINT32 rtt_one_sided_supported; + /** if 11v data collection is supported */ + A_UINT32 rtt_11v_supported; + /** if 11mc data collection is supported */ + A_UINT32 rtt_ftm_supported; + /** number of extscan cache capabilities (one per table) */ + A_UINT32 num_extscan_cache_capabilities; + /** number of wlan change capabilities (one per table) */ + A_UINT32 num_extscan_wlan_change_capabilities; + /** number of extscan hotlist capabilities (one per table) */ + A_UINT32 num_extscan_hotlist_capabilities; + /* Following this structure is the TLV: + * wmi_extscan_cache_capabilities extscan_cache_capabilities; // number of capabilities given by num_extscan_caches + * wmi_extscan_wlan_change_monitor_capabilities wlan_change_capabilities; // number of capabilities given by num_wlan_change_monitor_tables + * wmi_extscan_hotlist_monitor_capabilities hotlist_capabilities; // number of capabilities given by num_hotlist_monitor_tables + */ } wmi_extscan_set_capabilities_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_get_capabilities_cmd_fixed_param */ - /** Request ID - matches request ID used to start hot list monitoring */ - A_UINT32 request_id; - /** Requestor ID - client requesting capabilities */ - A_UINT32 requestor_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_get_capabilities_cmd_fixed_param */ + /** Request ID - matches request ID used to start hot list monitoring */ + A_UINT32 request_id; + /** Requestor ID - client requesting capabilities */ + A_UINT32 requestor_id; } wmi_extscan_get_capabilities_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_start_stop_event_fixed_param */ - /** Request ID of the operation that was started/stopped */ - A_UINT32 request_id; - /** Requestor ID of the operation that was started/stopped */ - A_UINT32 requestor_id; - /** VDEV id(interface) of the operation that was started/stopped */ - A_UINT32 vdev_id; - /** extscan WMI command */ - A_UINT32 command; - /** operation mode: start/stop */ - A_UINT32 mode; /* wmi_extscan_operation_mode */ - /**success/failure */ - A_UINT32 status; /* enum wmi_extscan_start_stop_status */ - /** table ID - to allow support for multiple simultaneous requests */ - A_UINT32 table_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_start_stop_event_fixed_param */ + /** Request ID of the operation that was started/stopped */ + A_UINT32 request_id; + /** Requestor ID of the operation that was started/stopped */ + A_UINT32 requestor_id; + /** VDEV id(interface) of the operation that was started/stopped */ + A_UINT32 vdev_id; + /** extscan WMI command */ + A_UINT32 command; + /** operation mode: start/stop */ + A_UINT32 mode; /* wmi_extscan_operation_mode */ + /**success/failure */ + A_UINT32 status; /* enum wmi_extscan_start_stop_status */ + /** table ID - to allow support for multiple simultaneous requests */ + A_UINT32 table_id; } wmi_extscan_start_stop_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_operation_event_fixed_param */ - /** Request ID of the extscan operation that is currently running */ - A_UINT32 request_id; - /** Requestor ID of the extscan operation that is currently running */ - A_UINT32 requestor_id; - /** VDEV id(interface) of the extscan operation that is currently running */ - A_UINT32 vdev_id; - /** scan event (wmi_scan_event_type) */ - A_UINT32 event; /* wmi_extscan_event_type */ - /** table ID - to allow support for multiple simultaneous requests */ - A_UINT32 table_id; - /**number of buckets */ - A_UINT32 num_buckets; - /* Following this structure is the TLV: - * A_UINT32 bucket_id[]; <-- number of elements given by field num_buckets. - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_operation_event_fixed_param */ + /** Request ID of the extscan operation that is currently running */ + A_UINT32 request_id; + /** Requestor ID of the extscan operation that is currently running */ + A_UINT32 requestor_id; + /** VDEV id(interface) of the extscan operation that is currently running */ + A_UINT32 vdev_id; + /** scan event (wmi_scan_event_type) */ + A_UINT32 event; /* wmi_extscan_event_type */ + /** table ID - to allow support for multiple simultaneous requests */ + A_UINT32 table_id; + /**number of buckets */ + A_UINT32 num_buckets; + /* Following this structure is the TLV: + * A_UINT32 bucket_id[]; // number of elements given by field num_buckets. + */ } wmi_extscan_operation_event_fixed_param; /* Types of extscan tables */ typedef enum { - EXTSCAN_TABLE_NONE = 0, - EXTSCAN_TABLE_BSSID = 1, - EXTSCAN_TABLE_RSSI = 2, + EXTSCAN_TABLE_NONE = 0, + EXTSCAN_TABLE_BSSID = 1, + EXTSCAN_TABLE_RSSI = 2, } wmi_extscan_table_type; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_table_usage_event_fixed_param */ - /** Request ID of the extscan operation that is currently running */ - A_UINT32 request_id; - /** Requestor ID of the extscan operation that is currently running */ - A_UINT32 requestor_id; - /** VDEV id(interface) of the extscan operation that is currently running */ - A_UINT32 vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /**see wmi_extscan_table_type for table reporting usage */ - A_UINT32 table_type; - /**number of entries in use */ - A_UINT32 entries_in_use; - /**maximum number of entries in table */ - A_UINT32 maximum_entries; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_table_usage_event_fixed_param */ + /** Request ID of the extscan operation that is currently running */ + A_UINT32 request_id; + /** Requestor ID of the extscan operation that is currently running */ + A_UINT32 requestor_id; + /** VDEV id(interface) of the extscan operation that is currently running */ + A_UINT32 vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /**see wmi_extscan_table_type for table reporting usage */ + A_UINT32 table_type; + /**number of entries in use */ + A_UINT32 entries_in_use; + /**maximum number of entries in table */ + A_UINT32 maximum_entries; } wmi_extscan_table_usage_event_fixed_param; typedef enum { - WMI_SCAN_STATUS_INTERRUPTED = 1 /* Indicates scan got interrupted i.e. aborted or pre-empted for a long time (> 1sec) - this can be used to discard scan results */ + /** + * Indicates scan got interrupted i.e. aborted or pre-empted for a long time (> 1sec) + * this can be used to discard scan results + */ + WMI_SCAN_STATUS_INTERRUPTED = 1 } wmi_scan_status_flags; + typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /** RSSI */ - A_UINT32 rssi; - /** time stamp in milliseconds */ - A_UINT32 tstamp; - /** Extscan cycle during which this entry was scanned */ - A_UINT32 scan_cycle_id; - /** flag to indicate if the given result was obtained as part of interrupted (aborted/large time gap preempted) scan */ - A_UINT32 flags; - /** Bitmask of buckets (i.e. sets of channels) scanned */ - A_UINT32 buckets_scanned; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /** RSSI */ + A_UINT32 rssi; + /** time stamp in milliseconds */ + A_UINT32 tstamp; + /** Extscan cycle during which this entry was scanned */ + A_UINT32 scan_cycle_id; + /** + * flag to indicate if the given result was obtained as part of + * interrupted (aborted/large time gap preempted) scan + */ + A_UINT32 flags; + /** Bitmask of buckets (i.e. sets of channels) scanned */ + A_UINT32 buckets_scanned; } wmi_extscan_rssi_info; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /**bssid */ - wmi_mac_addr bssid; - /**ssid */ - wmi_ssid ssid; - /**channel number */ - A_UINT32 channel; - /* capabilities */ - A_UINT32 capabilities; - /* beacon interval in TUs */ - A_UINT32 beacon_interval; - /**time stamp in milliseconds - time last seen */ - A_UINT32 tstamp; - /**flags - _tExtScanEntryFlags */ - A_UINT32 flags; - /**RTT in ns */ - A_UINT32 rtt; - /**rtt standard deviation */ - A_UINT32 rtt_sd; - /* rssi information */ - A_UINT32 number_rssi_samples; - /** IE length */ - A_UINT32 ie_length; /* length of IE data */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /**bssid */ + wmi_mac_addr bssid; + /**ssid */ + wmi_ssid ssid; + /**channel number */ + A_UINT32 channel; + /* capabilities */ + A_UINT32 capabilities; + /* beacon interval in TUs */ + A_UINT32 beacon_interval; + /**time stamp in milliseconds - time last seen */ + A_UINT32 tstamp; + /**flags - _tExtScanEntryFlags */ + A_UINT32 flags; + /**RTT in ns */ + A_UINT32 rtt; + /**rtt standard deviation */ + A_UINT32 rtt_sd; + /* rssi information */ + A_UINT32 number_rssi_samples; + /** IE length */ + A_UINT32 ie_length; /* length of IE data */ } wmi_extscan_wlan_descriptor; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_cached_results_event_fixed_param */ - /** Request ID of the WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID */ - A_UINT32 request_id; - /** Requestor ID of the WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID */ - A_UINT32 requestor_id; - /** VDEV id(interface) of the WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID */ - A_UINT32 vdev_id; - /** Request ID of the extscan operation that is currently running */ - A_UINT32 extscan_request_id; - /** Requestor ID of the extscan operation that is currently running */ - A_UINT32 extscan_requestor_id; - /** VDEV id(interface) of the extscan operation that is currently running */ - A_UINT32 extscan_vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /**current time stamp in seconds. Used to provide a baseline for the relative timestamps returned for each block and entry */ - A_UINT32 current_tstamp; - /**total number of bssids (in all pages) */ - A_UINT32 total_entries; - /**index of the first bssid entry found in the TLV wmi_extscan_wlan_descriptor*/ - A_UINT32 first_entry_index; - /**number of bssids in this page */ - A_UINT32 num_entries_in_page; - /** number of buckets scanned**/ - A_UINT32 buckets_scanned; - /* Followed by the variable length TLVs - * wmi_extscan_wlan_descriptor bssid_list[] - * wmi_extscan_rssi_info rssi_list[] - * A_UINT8 ie_list[] - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_cached_results_event_fixed_param */ + /** Request ID of the WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID */ + A_UINT32 request_id; + /** Requestor ID of the WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID */ + A_UINT32 requestor_id; + /** VDEV id(interface) of the WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID */ + A_UINT32 vdev_id; + /** Request ID of the extscan operation that is currently running */ + A_UINT32 extscan_request_id; + /** Requestor ID of the extscan operation that is currently running */ + A_UINT32 extscan_requestor_id; + /** VDEV id(interface) of the extscan operation that is currently running */ + A_UINT32 extscan_vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /**current time stamp in seconds. Used to provide a baseline for the relative timestamps returned for each block and entry */ + A_UINT32 current_tstamp; + /**total number of bssids (in all pages) */ + A_UINT32 total_entries; + /**index of the first bssid entry found in the TLV wmi_extscan_wlan_descriptor*/ + A_UINT32 first_entry_index; + /**number of bssids in this page */ + A_UINT32 num_entries_in_page; + /* number of buckets scanned */ + A_UINT32 buckets_scanned; + /* Followed by the variable length TLVs + * wmi_extscan_wlan_descriptor bssid_list[] + * wmi_extscan_rssi_info rssi_list[] + * A_UINT8 ie_list[] + */ } wmi_extscan_cached_results_event_fixed_param; typedef enum { - EXTSCAN_WLAN_CHANGE_FLAG_NONE = 0x00, - EXTSCAN_WLAN_CHANGE_FLAG_OUT_OF_RANGE = 0x01, - EXTSCAN_WLAN_CHANGE_FLAG_AP_LOST = 0x02, + EXTSCAN_WLAN_CHANGE_FLAG_NONE = 0x00, + EXTSCAN_WLAN_CHANGE_FLAG_OUT_OF_RANGE = 0x01, + EXTSCAN_WLAN_CHANGE_FLAG_AP_LOST = 0x02, } wmi_extscan_wlan_change_flags; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ - /**bssid */ - wmi_mac_addr bssid; - /**time stamp in milliseconds */ - A_UINT32 tstamp; - /**upper RSSI limit */ - A_UINT32 upper_rssi_limit; - /**lower RSSI limit */ - A_UINT32 lower_rssi_limit; - /** channel */ - A_UINT32 channel; /* in MHz */ - /**current RSSI average */ - A_UINT32 rssi_average; - /**flags - wmi_extscan_wlan_change_flags */ - A_UINT32 flags; - /**legnth of RSSI history to follow (number of values) */ - A_UINT32 num_rssi_samples; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */ + /**bssid */ + wmi_mac_addr bssid; + /**time stamp in milliseconds */ + A_UINT32 tstamp; + /**upper RSSI limit */ + A_UINT32 upper_rssi_limit; + /**lower RSSI limit */ + A_UINT32 lower_rssi_limit; + /** channel */ + A_UINT32 channel; /* in MHz */ + /**current RSSI average */ + A_UINT32 rssi_average; + /**flags - wmi_extscan_wlan_change_flags */ + A_UINT32 flags; + /**legnth of RSSI history to follow (number of values) */ + A_UINT32 num_rssi_samples; } wmi_extscan_wlan_change_result_bssid; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_wlan_change_results_event_fixed_param */ - /** Request ID of the WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID command that requested the results */ - A_UINT32 request_id; - /** Requestor ID of the WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID command that requested the results */ - A_UINT32 requestor_id; - /** VDEV id(interface) of the WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID command that requested the results */ - A_UINT32 vdev_id; - /** Request ID of the WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID command that configured the table */ - A_UINT32 config_request_id; - /** Requestor ID of the WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID command that configured the table */ - A_UINT32 config_requestor_id; - /** VDEV id(interface) of the WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID command that configured the table */ - A_UINT32 config_vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /**number of entries with RSSI out of range or BSSID not detected */ - A_UINT32 change_count; - /**total number of bssid signal descriptors (in all pages) */ - A_UINT32 total_entries; - /**index of the first bssid signal descriptor entry found in the TLV wmi_extscan_wlan_descriptor*/ - A_UINT32 first_entry_index; - /**number of bssids signal descriptors in this page */ - A_UINT32 num_entries_in_page; -/* Following this structure is the TLV: - * wmi_extscan_wlan_change_result_bssid bssid_signal_descriptor_list[]; - * (number of descriptors given by field num_entries_in_page) - * Following this structure is the list of RSSI values (each is an A_UINT8): - * A_UINT8 rssi_list[]; <-- last N RSSI values. - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_wlan_change_results_event_fixed_param */ + /** Request ID of the WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID command that requested the results */ + A_UINT32 request_id; + /** Requestor ID of the WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID command that requested the results */ + A_UINT32 requestor_id; + /** VDEV id(interface) of the WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID command that requested the results */ + A_UINT32 vdev_id; + /** Request ID of the WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID command that configured the table */ + A_UINT32 config_request_id; + /** Requestor ID of the WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID command that configured the table */ + A_UINT32 config_requestor_id; + /** VDEV id(interface) of the WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID command that configured the table */ + A_UINT32 config_vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /**number of entries with RSSI out of range or BSSID not detected */ + A_UINT32 change_count; + /**total number of bssid signal descriptors (in all pages) */ + A_UINT32 total_entries; + /**index of the first bssid signal descriptor entry found in the TLV wmi_extscan_wlan_descriptor*/ + A_UINT32 first_entry_index; + /**number of bssids signal descriptors in this page */ + A_UINT32 num_entries_in_page; + /* Following this structure is the TLV: + * wmi_extscan_wlan_change_result_bssid bssid_signal_descriptor_list[]; // number of descriptors given by field num_entries_in_page. + * Following this structure is the list of RSSI values (each is an A_UINT8): + * A_UINT8 rssi_list[]; // last N RSSI values. + */ } wmi_extscan_wlan_change_results_event_fixed_param; -enum _tExtScanEntryFlags -{ - WMI_HOTLIST_FLAG_NONE = 0x00, - WMI_HOTLIST_FLAG_PRESENCE = 0x01, - WMI_HOTLIST_FLAG_DUPLICATE_SSID = 0x80, +enum _tExtScanEntryFlags { + WMI_HOTLIST_FLAG_NONE = 0x00, + WMI_HOTLIST_FLAG_PRESENCE = 0x01, + WMI_HOTLIST_FLAG_DUPLICATE_SSID = 0x80, }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param */ - /** Request ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID that configured the table */ - A_UINT32 config_request_id; - /** Requestor ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID that configured the table */ - A_UINT32 config_requestor_id; - /** VDEV id(interface) of the WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID that configured the table */ - A_UINT32 config_vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /**total number of bssids (in all pages) */ - A_UINT32 total_entries; - /**index of the first bssid entry found in the TLV wmi_extscan_wlan_descriptor*/ - A_UINT32 first_entry_index; - /**number of bssids in this page */ - A_UINT32 num_entries_in_page; -/* Following this structure is the TLV: - * wmi_extscan_wlan_descriptor hotlist_match[]; <-- number of descriptors given by field num_entries_in_page. - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param */ + /** Request ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID that configured the table */ + A_UINT32 config_request_id; + /** Requestor ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID that configured the table */ + A_UINT32 config_requestor_id; + /** VDEV id(interface) of the WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID that configured the table */ + A_UINT32 config_vdev_id; + /** table ID - to allow support for multiple simultaneous tables */ + A_UINT32 table_id; + /**total number of bssids (in all pages) */ + A_UINT32 total_entries; + /**index of the first bssid entry found in the TLV wmi_extscan_wlan_descriptor*/ + A_UINT32 first_entry_index; + /**number of bssids in this page */ + A_UINT32 num_entries_in_page; + /* Following this structure is the TLV: + * wmi_extscan_wlan_descriptor hotlist_match[]; // number of descriptors given by field num_entries_in_page. + */ } wmi_extscan_hotlist_match_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_hotlist_match_event_fixed_param */ - /** Request ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID that configured the table */ - A_UINT32 config_request_id; - /** Requestor ID of the WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID that configured the table */ - A_UINT32 config_requestor_id; - /** VDEV id(interface) of the WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID that configured the table */ - A_UINT32 config_vdev_id; - /** table ID - to allow support for multiple simultaneous tables */ - A_UINT32 table_id; - /**total number of ssids (in all pages) */ - A_UINT32 total_entries; - /**index of the first ssid entry found in the TLV wmi_extscan_wlan_descriptor*/ - A_UINT32 first_entry_index; - /**number of ssids in this page */ - A_UINT32 num_entries_in_page; -/* Following this structure is the TLV: - * wmi_extscan_wlan_descriptor hotlist_match[]; <-- number of descriptors given by field num_entries_in_page. - */ -} wmi_extscan_hotlist_ssid_match_event_fixed_param; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_capabilities_event_fixed_param */ + /** Request ID of the WMI_EXTSCAN_GET_CAPABILITIES_CMDID */ + A_UINT32 request_id; + /** Requestor ID of the WMI_EXTSCAN_GET_CAPABILITIES_CMDID */ + A_UINT32 requestor_id; + /** VDEV id(interface) of the WMI_EXTSCAN_GET_CAPABILITIES_CMDID */ + A_UINT32 vdev_id; + /** number of extscan caches */ + A_UINT32 num_extscan_cache_tables; + /** number of wlan change lists */ + A_UINT32 num_wlan_change_monitor_tables; + /** number of hotlists */ + A_UINT32 num_hotlist_monitor_tables; + /** if one sided rtt data collection is supported */ + A_UINT32 rtt_one_sided_supported; + /** if 11v data collection is supported */ + A_UINT32 rtt_11v_supported; + /** if 11mc data collection is supported */ + A_UINT32 rtt_ftm_supported; + /** number of extscan cache capabilities (one per table) */ + A_UINT32 num_extscan_cache_capabilities; + /** number of wlan change capabilities (one per table) */ + A_UINT32 num_extscan_wlan_change_capabilities; + /** number of extscan hotlist capabilities (one per table) */ + A_UINT32 num_extscan_hotlist_capabilities; + /* max number of roaming ssid whitelist firmware can support */ + A_UINT32 num_roam_ssid_whitelist; + /* max number of blacklist bssid firmware can support */ + A_UINT32 num_roam_bssid_blacklist; + /* max number of preferred list firmware can support */ + A_UINT32 num_roam_bssid_preferred_list; + /* max number of hotlist ssids firmware can support */ + A_UINT32 num_extscan_hotlist_ssid; + /* max number of epno networks firmware can support */ + A_UINT32 num_epno_networks; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_extscan_capabilities_event_fixed_param */ - /** Request ID of the WMI_EXTSCAN_GET_CAPABILITIES_CMDID */ - A_UINT32 request_id; - /** Requestor ID of the WMI_EXTSCAN_GET_CAPABILITIES_CMDID */ - A_UINT32 requestor_id; - /** VDEV id(interface) of the WMI_EXTSCAN_GET_CAPABILITIES_CMDID */ - A_UINT32 vdev_id; - /** number of extscan caches */ - A_UINT32 num_extscan_cache_tables; - /** number of wlan change lists */ - A_UINT32 num_wlan_change_monitor_tables; - /** number of hotlists */ - A_UINT32 num_hotlist_monitor_tables; - /** if one sided rtt data collection is supported */ - A_UINT32 rtt_one_sided_supported; - /** if 11v data collection is supported */ - A_UINT32 rtt_11v_supported; - /** if 11mc data collection is supported */ - A_UINT32 rtt_ftm_supported; - /** number of extscan cache capabilities (one per table) */ - A_UINT32 num_extscan_cache_capabilities; - /** number of wlan change capabilities (one per table) */ - A_UINT32 num_extscan_wlan_change_capabilities; - /** number of extscan hotlist capabilities (one per table) */ - A_UINT32 num_extscan_hotlist_capabilities; - /* max number of roaming ssid whitelist firmware can support */ - A_UINT32 num_roam_ssid_whitelist; - /* max number of blacklist bssid firmware can support */ - A_UINT32 num_roam_bssid_blacklist; - /* max number of preferred list firmware can support */ - A_UINT32 num_roam_bssid_preferred_list; - /* max number of hotlist ssids firmware can support */ - A_UINT32 num_extscan_hotlist_ssid; - /* max number of epno networks firmware can support */ - A_UINT32 num_epno_networks; - -/* Following this structure are the TLVs describing the capabilities of of the various types of lists. The FW theoretically - * supports multiple lists of each type. - * - * wmi_extscan_cache_capabilities extscan_cache_capabilities[] <-- capabilities of extscan cache (BSSID/RSSI lists) - * wmi_extscan_wlan_change_monitor_capabilities wlan_change_capabilities[] <-- capabilities of wlan_change_monitor_tables - * wmi_extscan_hotlist_monitor_capabilities hotlist_capabilities[] <-- capabilities of hotlist_monitor_tables - */ + /* Following this structure are the TLVs describing the capabilities of of the various types of lists. The FW theoretically + * supports multiple lists of each type. + * + * wmi_extscan_cache_capabilities extscan_cache_capabilities[] // capabilities of extscan cache (BSSID/RSSI lists) + * wmi_extscan_wlan_change_monitor_capabilities wlan_change_capabilities[] // capabilities of wlan_change_monitor_tables + * wmi_extscan_hotlist_monitor_capabilities hotlist_capabilities[] // capabilities of hotlist_monitor_tables + */ } wmi_extscan_capabilities_event_fixed_param; /* WMI_D0_WOW_DISABLE_ACK_EVENTID */ -typedef struct{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param */ - A_UINT32 reserved0; /* for future need */ +typedef struct { + A_UINT32 tlv_header; + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param */ + A_UINT32 reserved0; /* for future need */ } wmi_d0_wow_disable_ack_event_fixed_param; /** WMI_PDEV_RESUME_EVENTID : generated in response to WMI_PDEV_RESUME_CMDID */ typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_resume_event_fixed_param; - - /** value representing all modules */ #define WMI_DEBUG_LOG_MODULE_ALL 0xffff /* param definitions */ /** - * Log level for a given module. Value contains both module id and log level. - * here is the bitmap definition for value. - * module Id : 16 - * Flags : reserved - * Level : 8 - * if odule Id is WMI_DEBUG_LOG_MODULE_ALL then log level is applied to all modules (global). - * WMI_DEBUG_LOG_MIDULE_ALL will overwrites per module level setting. - */ + * Log level for a given module. Value contains both module id and log level. + * here is the bitmap definition for value. + * module Id : 16 + * Flags : reserved + * Level : 8 + * if odule Id is WMI_DEBUG_LOG_MODULE_ALL then log level is applied to all modules (global). + * WMI_DEBUG_LOG_MIDULE_ALL will overwrites per module level setting. + */ #define WMI_DEBUG_LOG_PARAM_LOG_LEVEL 0x1 -#define WMI_DBGLOG_SET_LOG_LEVEL(val,lvl) do { \ - (val) |= (lvl & 0xff); \ - } while (0) +#define WMI_DBGLOG_SET_LOG_LEVEL(val, lvl) do { \ + (val) |= (lvl & 0xff); \ +} while (0) #define WMI_DBGLOG_GET_LOG_LEVEL(val) ((val) & 0xff) -#define WMI_DBGLOG_SET_MODULE_ID(val,mid) do { \ - (val) |= ((mid & 0xffff) << 16); \ - } while (0) +#define WMI_DBGLOG_SET_MODULE_ID(val, mid) do { \ + (val) |= ((mid & 0xffff) << 16); \ +} while (0) #define WMI_DBGLOG_GET_MODULE_ID(val) (((val) >> 16) & 0xffff) /** - * Enable the debug log for a given vdev. Value is vdev id - */ + * Enable the debug log for a given vdev. Value is vdev id + */ #define WMI_DEBUG_LOG_PARAM_VDEV_ENABLE 0x2 - /** - * Disable the debug log for a given vdev. Value is vdev id - * All the log level for a given VDEV is disabled except the ERROR log messages - */ + * Disable the debug log for a given vdev. Value is vdev id + * All the log level for a given VDEV is disabled except the ERROR log messages + */ #define WMI_DEBUG_LOG_PARAM_VDEV_DISABLE 0x3 /** - * set vdev enable bitmap. value is the vden enable bitmap - */ + * set vdev enable bitmap. value is the vden enable bitmap + */ #define WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP 0x4 /** - * set a given log level to all the modules specified in the module bitmap. - * and set the log levle for all other modules to DBGLOG_ERR. - * value: log levelt to be set. - * module_id_bitmap : identifies the modules for which the log level should be set and - * modules for which the log level should be reset to DBGLOG_ERR. - */ + * set a given log level to all the modules specified in the module bitmap. + * and set the log levle for all other modules to DBGLOG_ERR. + * value: log levelt to be set. + * module_id_bitmap : identifies the modules for which the log level should be set and + * modules for which the log level should be reset to DBGLOG_ERR. + */ #define WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP 0x5 #define NUM_MODULES_PER_ENTRY ((sizeof(A_UINT32)) << 3) -#define WMI_MODULE_ENABLE(pmid_bitmap,mod_id) \ - ((pmid_bitmap)[(mod_id)/NUM_MODULES_PER_ENTRY] |= \ - (1 << ((mod_id)%NUM_MODULES_PER_ENTRY))) +#define WMI_MODULE_ENABLE(pmid_bitmap, mod_id) \ + ((pmid_bitmap)[(mod_id)/NUM_MODULES_PER_ENTRY] |= \ + (1 << ((mod_id)%NUM_MODULES_PER_ENTRY))) -#define WMI_MODULE_DISABLE(pmid_bitmap,mod_id) \ - ((pmid_bitmap)[(mod_id)/NUM_MODULES_PER_ENTRY] &= \ - (~(1 << ((mod_id)%NUM_MODULES_PER_ENTRY)))) +#define WMI_MODULE_DISABLE(pmid_bitmap, mod_id) \ + ((pmid_bitmap)[(mod_id)/NUM_MODULES_PER_ENTRY] &= \ + (~(1 << ((mod_id)%NUM_MODULES_PER_ENTRY)))) -#define WMI_MODULE_IS_ENABLED(pmid_bitmap,mod_id) \ - (((pmid_bitmap)[(mod_id)/NUM_MODULES_PER_ENTRY] & \ - (1 << ((mod_id)%NUM_MODULES_PER_ENTRY))) != 0) +#define WMI_MODULE_IS_ENABLED(pmid_bitmap, mod_id) \ + (((pmid_bitmap)[(mod_id)/NUM_MODULES_PER_ENTRY] & \ + (1 << ((mod_id)%NUM_MODULES_PER_ENTRY))) != 0) -#define MAX_MODULE_ID_BITMAP_WORDS 16 /* 16*32=512 module ids. should be more than sufficient */ +#define MAX_MODULE_ID_BITMAP_WORDS 16 /* 16*32=512 module ids. should be more than sufficient */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_debug_log_config_cmd_fixed_param */ - A_UINT32 dbg_log_param; /** param types are defined above */ - A_UINT32 value; - /* The below array will follow this tlv ->fixed length module_id_bitmap[] - A_UINT32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS]; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_debug_log_config_cmd_fixed_param */ + A_UINT32 dbg_log_param; + /** param types are defined above */ + A_UINT32 value; + /* The below array will follow this tlv ->fixed length module_id_bitmap[] + A_UINT32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS]; + */ } wmi_debug_log_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_temperature_cmd_fixed_param */ - A_UINT32 param; /* Reserved for future use */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_temperature_cmd_fixed_param */ + A_UINT32 param; /* Reserved for future use */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_get_temperature_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_temperature_event_fixed_param */ - A_INT32 value; /* temprature value in Celcius degree */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_temperature_event_fixed_param */ + A_INT32 value; /* temprature value in Celcius degree */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_temperature_event_fixed_param; typedef enum { - ANTDIV_HW_CFG_STATUS, - ANTDIV_SW_CFG_STATUS, - ANTDIV_MAX_STATUS_TYPE_NUM + ANTDIV_HW_CFG_STATUS, + ANTDIV_SW_CFG_STATUS, + ANTDIV_MAX_STATUS_TYPE_NUM } ANTDIV_STATUS_TYPE; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_antdiv_status_cmd_fixed_param */ - A_UINT32 status_event_id; /* Status event ID - see ANTDIV_STATUS_TYPE */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_get_antdiv_status_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* Status event ID - see ANTDIV_STATUS_TYPE */ + A_UINT32 status_event_id; + /** + * pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_get_antdiv_status_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_antdiv_status_event_fixed_param */ - A_UINT32 support; /* ANT DIV feature enabled or not */ - A_UINT32 chain_num; /* how many chain supported */ - A_UINT32 ant_num; /* how many ANT supported, 32 max */ - /* - * Each entry is for a tx/rx chain, and contains a bitmap identifying - * the antennas attached to that tx/rx chain. - */ - A_UINT32 selectable_ant_mask[8]; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_antdiv_status_event_fixed_param + */ + A_UINT32 tlv_header; + /* ANT DIV feature enabled or not */ + A_UINT32 support; + A_UINT32 chain_num; /* how many chain supported */ + /* how many ANT supported, 32 max */ + A_UINT32 ant_num; + /** + * Each entry is for a tx/rx chain, and contains a bitmap + * identifying the antennas attached to that tx/rx chain. + */ + A_UINT32 selectable_ant_mask[8]; + /** + * pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_antdiv_status_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_dhcp_server_offload_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 enable; - A_UINT32 srv_ipv4; /* server IP */ - A_UINT32 start_lsb; /* starting address assigned to client */ - A_UINT32 num_client; /* number of clients we support */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_dhcp_server_offload_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 enable; + A_UINT32 srv_ipv4; /* server IP */ + A_UINT32 start_lsb; /* starting address assigned to client */ + A_UINT32 num_client; /* number of clients we support */ } wmi_set_dhcp_server_offload_cmd_fixed_param; typedef enum { - AP_RX_DATA_OFFLOAD = 0x00, - STA_RX_DATA_OFFLOAD = 0x01, + AP_RX_DATA_OFFLOAD = 0x00, + STA_RX_DATA_OFFLOAD = 0x01, } wmi_ipa_offload_types; /** @@ -13120,33 +14366,33 @@ typedef enum { * */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ipa_offload_enable_disable_cmd_fixed_param */ - A_UINT32 offload_type; /* wmi_ipa_offload_types enum values */ - A_UINT32 vdev_id; - A_UINT32 enable; /* 1 == enable, 0 == disable */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ipa_offload_enable_disable_cmd_fixed_param */ + A_UINT32 offload_type; /* wmi_ipa_offload_types enum values */ + A_UINT32 vdev_id; + A_UINT32 enable; /* 1 == enable, 0 == disable */ } wmi_ipa_offload_enable_disable_cmd_fixed_param; typedef enum { - WMI_LED_FLASHING_PATTERN_NOT_CONNECTED = 0, - WMI_LED_FLASHING_PATTERN_CONNECTED = 1, - WMI_LED_FLASHING_PATTERN_RESERVED = 2, + WMI_LED_FLASHING_PATTERN_NOT_CONNECTED = 0, + WMI_LED_FLASHING_PATTERN_CONNECTED = 1, + WMI_LED_FLASHING_PATTERN_RESERVED = 2, } wmi_set_led_flashing_type; /** -The state of the LED GPIO control is determined by two 32 bit values(X_0 and X_1) to produce a 64 bit value. -Each 32 bit value consists of 4 bytes, where each byte defines the number of 50ms intervals that the GPIO will -remain at a predetermined state. The 64 bit value provides 8 unique GPIO timing intervals. The pattern starts -with the MSB of X_0 and continues to the LSB of X_1. After executing the timer interval of the LSB of X_1, the -pattern returns to the MSB of X_0 and repeats. The GPIO state for each timing interval alternates from Low to -High and the first interval of the pattern represents the time when the GPIO is Low. When a timing interval of -Zero is reached, it is skipped and moves on to the next interval. -*/ -typedef struct{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_led_flashing_cmd_fixed_param */ - A_UINT32 pattern_id; /* pattern identifier */ - A_UINT32 led_x0; /* led flashing parameter0 */ - A_UINT32 led_x1; /* led flashing parameter1 */ - A_UINT32 gpio_num; /* GPIO number */ + The state of the LED GPIO control is determined by two 32 bit values(X_0 and X_1) to produce a 64 bit value. + Each 32 bit value consists of 4 bytes, where each byte defines the number of 50ms intervals that the GPIO will + remain at a predetermined state. The 64 bit value provides 8 unique GPIO timing intervals. The pattern starts + with the MSB of X_0 and continues to the LSB of X_1. After executing the timer interval of the LSB of X_1, the + pattern returns to the MSB of X_0 and repeats. The GPIO state for each timing interval alternates from Low to + High and the first interval of the pattern represents the time when the GPIO is Low. When a timing interval of + Zero is reached, it is skipped and moves on to the next interval. + */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_led_flashing_cmd_fixed_param */ + A_UINT32 pattern_id; /* pattern identifier */ + A_UINT32 led_x0; /* led flashing parameter0 */ + A_UINT32 led_x1; /* led flashing parameter1 */ + A_UINT32 gpio_num; /* GPIO number */ } wmi_set_led_flashing_cmd_fixed_param; /** @@ -13160,9 +14406,9 @@ typedef struct{ * Here, we provide the ability to advertise the available services by responding to mDNS queries. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_offload_cmd_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 enable; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_offload_cmd_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 enable; } wmi_mdns_offload_cmd_fixed_param; #define WMI_MAX_MDNS_FQDN_LEN 64 @@ -13171,51 +14417,51 @@ typedef struct { #define WMI_MDNS_FQDN_TYPE_UNIQUE 1 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_set_fqdn_cmd_fixed_param */ - A_UINT32 vdev_id; - /** type of fqdn, general or unique */ - A_UINT32 type; - /** length of fqdn */ - A_UINT32 fqdn_len; - /* Following this structure is the TLV byte stream of fqdn data of length fqdn_len - * A_UINT8 fqdn_data[]; <-- fully-qualified domain name to check if match with the received queries - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_set_fqdn_cmd_fixed_param */ + A_UINT32 vdev_id; + /** type of fqdn, general or unique */ + A_UINT32 type; + /** length of fqdn */ + A_UINT32 fqdn_len; + /* Following this structure is the TLV byte stream of fqdn data of length fqdn_len + * A_UINT8 fqdn_data[]; // fully-qualified domain name to check if match with the received queries + */ } wmi_mdns_set_fqdn_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_set_resp_cmd_fixed_param */ - A_UINT32 vdev_id; - /** Answer Resource Record count */ - A_UINT32 AR_count; - /** length of response */ - A_UINT32 resp_len; - /* Following this structure is the TLV byte stream of resp data of length resp_len - * A_UINT8 resp_data[]; <-- responses consisits of Resource Records - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_set_resp_cmd_fixed_param */ + A_UINT32 vdev_id; + /** Answer Resource Record count */ + A_UINT32 AR_count; + /** length of response */ + A_UINT32 resp_len; + /* Following this structure is the TLV byte stream of resp data of length resp_len + * A_UINT8 resp_data[]; // responses consisits of Resource Records + */ } wmi_mdns_set_resp_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_get_stats_cmd_fixed_param */ - A_UINT32 vdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_get_stats_cmd_fixed_param */ + A_UINT32 vdev_id; } wmi_mdns_get_stats_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_stats_event_fixed_param */ - A_UINT32 vdev_id; - /** curTimestamp in milliseconds */ - A_UINT32 curTimestamp; - /** last received Query in milliseconds */ - A_UINT32 lastQueryTimestamp; - /** last sent Response in milliseconds */ - A_UINT32 lastResponseTimestamp; - /** stats of received queries */ - A_UINT32 totalQueries; - /** stats of macth queries */ - A_UINT32 totalMatches; - /** stats of responses */ - A_UINT32 totalResponses; - /** indicate the current status of mDNS offload */ - A_UINT32 status; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mdns_stats_event_fixed_param */ + A_UINT32 vdev_id; + /** curTimestamp in milliseconds */ + A_UINT32 curTimestamp; + /** last received Query in milliseconds */ + A_UINT32 lastQueryTimestamp; + /** last sent Response in milliseconds */ + A_UINT32 lastResponseTimestamp; + /** stats of received queries */ + A_UINT32 totalQueries; + /** stats of macth queries */ + A_UINT32 totalMatches; + /** stats of responses */ + A_UINT32 totalResponses; + /** indicate the current status of mDNS offload */ + A_UINT32 status; } wmi_mdns_stats_event_fixed_param; /** @@ -13230,102 +14476,108 @@ typedef struct { */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_ofl_enable_cmd_fixed_param */ - /** VDEV id(interface) of the WMI_SAP_OFL_ENABLE_CMDID */ - A_UINT32 vdev_id; - /** enable/disable sap auth offload */ - A_UINT32 enable; - /** sap ssid */ - wmi_ssid ap_ssid; - /** authentication mode (defined above) */ - A_UINT32 rsn_authmode; - /** unicast cipher set */ - A_UINT32 rsn_ucastcipherset; - /** mcast/group cipher set */ - A_UINT32 rsn_mcastcipherset; - /** mcast/group management frames cipher set */ - A_UINT32 rsn_mcastmgmtcipherset; - /** sap channel */ - A_UINT32 channel; - /** length of psk */ - A_UINT32 psk_len; - /* Following this structure is the TLV byte stream of wpa passphrase data of length psk_len - * A_UINT8 psk[]; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_ofl_enable_cmd_fixed_param */ + /** VDEV id(interface) of the WMI_SAP_OFL_ENABLE_CMDID */ + A_UINT32 vdev_id; + /** enable/disable sap auth offload */ + A_UINT32 enable; + /** sap ssid */ + wmi_ssid ap_ssid; + /** authentication mode (defined above) */ + A_UINT32 rsn_authmode; + /** unicast cipher set */ + A_UINT32 rsn_ucastcipherset; + /** mcast/group cipher set */ + A_UINT32 rsn_mcastcipherset; + /** mcast/group management frames cipher set */ + A_UINT32 rsn_mcastmgmtcipherset; + /** sap channel */ + A_UINT32 channel; + /** length of psk */ + A_UINT32 psk_len; + /* Following this structure is the TLV byte stream of wpa passphrase data of length psk_len + * A_UINT8 psk[]; + */ } wmi_sap_ofl_enable_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param */ - /** VDEV id(interface) of the WMI_SAP_OFL_ADD_STA_EVENTID */ - A_UINT32 vdev_id; - /** aid (association id) of this station */ - A_UINT32 assoc_id; - /** peer station's mac addr */ - wmi_mac_addr peer_macaddr; - /** length of association request frame */ - A_UINT32 data_len; - /* Following this structure is the TLV byte stream of a whole association request frame of length data_len - * A_UINT8 bufp[]; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param */ + /** VDEV id(interface) of the WMI_SAP_OFL_ADD_STA_EVENTID */ + A_UINT32 vdev_id; + /** aid (association id) of this station */ + A_UINT32 assoc_id; + /** peer station's mac addr */ + wmi_mac_addr peer_macaddr; + /** length of association request frame */ + A_UINT32 data_len; + /* Following this structure is the TLV byte stream of a whole association request frame of length data_len + * A_UINT8 bufp[]; + */ } wmi_sap_ofl_add_sta_event_fixed_param; typedef enum { - SAP_OFL_DEL_STA_FLAG_NONE = 0x00, - SAP_OFL_DEL_STA_FLAG_RECONNECT = 0x01, + SAP_OFL_DEL_STA_FLAG_NONE = 0x00, + SAP_OFL_DEL_STA_FLAG_RECONNECT = 0x01, } wmi_sap_ofl_del_sta_flags; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_ofl_del_sta_event_fixed_param */ - /** VDEV id(interface) of the WMI_SAP_OFL_DEL_STA_EVENTID */ - A_UINT32 vdev_id; - /** aid (association id) of this station */ - A_UINT32 assoc_id; - /** peer station's mac addr */ - wmi_mac_addr peer_macaddr; - /** disassociation reason */ - A_UINT32 reason; - /** flags - wmi_sap_ofl_del_sta_flags */ - A_UINT32 flags; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_ofl_del_sta_event_fixed_param */ + /** VDEV id(interface) of the WMI_SAP_OFL_DEL_STA_EVENTID */ + A_UINT32 vdev_id; + /** aid (association id) of this station */ + A_UINT32 assoc_id; + /** peer station's mac addr */ + wmi_mac_addr peer_macaddr; + /** disassociation reason */ + A_UINT32 reason; + /** flags - wmi_sap_ofl_del_sta_flags */ + A_UINT32 flags; } wmi_sap_ofl_del_sta_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sap_set_blacklist_param_cmd_fixed_param */ - A_UINT32 vdev_id; - /* Number of client failure connection attempt */ - A_UINT32 num_retry; - /* Time in milliseconds to record the client's failure connection attempts */ - A_UINT32 retry_allow_time_ms; - /* Time in milliseconds to drop the connection request if client is blacklisted */ - A_UINT32 blackout_time_ms; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_sap_set_blacklist_param_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* Number of client failure connection attempt */ + A_UINT32 num_retry; + /*Time in milliseconds to record the client's failure connection attempts*/ + A_UINT32 retry_allow_time_ms; + /* + * Time in milliseconds to drop the connection request if + * client is blacklisted + */ + A_UINT32 blackout_time_ms; } wmi_sap_set_blacklist_param_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_apfind_cmd_param */ - A_UINT32 data_len; /** length in byte of data[]. */ - /** This structure is used to send REQ binary blobs - * from application/service to firmware where Host drv is pass through . - * Following this structure is the TLV: - * A_UINT8 data[]; <-- length in byte given by field data_len. - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_apfind_cmd_param */ + A_UINT32 data_len; /** length in byte of data[]. */ + /** This structure is used to send REQ binary blobs + * from application/service to firmware where Host drv is pass through . + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field data_len. + */ } wmi_apfind_cmd_param; typedef enum apfind_event_type_e { - APFIND_MATCH_EVENT = 0, - APFIND_WAKEUP_EVENT, + APFIND_MATCH_EVENT = 0, + APFIND_WAKEUP_EVENT, } APFIND_EVENT_TYPE; typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_apfind_event_hdr */ - A_UINT32 event_type; /** APFIND_EVENT_TYPE */ - A_UINT32 data_len; /** length in byte of data[]. */ - /** This structure is used to send event binary blobs - * from firmware to application/service and Host drv. - * Following this structure is the TLV: - * A_UINT8 data[]; <-- length in byte given by field data_len. - */ + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_apfind_event_hdr */ + A_UINT32 event_type; /** APFIND_EVENT_TYPE */ + A_UINT32 data_len; /** length in byte of data[]. */ + /** This structure is used to send event binary blobs + * from firmware to application/service and Host drv. + * Following this structure is the TLV: + * A_UINT8 data[]; // length in byte given by field data_len. + */ } wmi_apfind_event_hdr; - /** * OCB DCC types and structures. */ @@ -13358,26 +14610,27 @@ typedef struct { * cannot be changed without breaking WMI compatibility. * * NOTE: For each of the types, one additional bit is allocated. This - * leftmost bit is used to indicate that the value is invalid. */ -#define SIZE_NDLTYPE_ACPRIO (1 + 3) -#define SIZE_NDLTYPE_CONTROLLOOP (1 + 3) + * leftmost bit is used to indicate that the value is invalid. + */ +#define SIZE_NDLTYPE_ACPRIO (1 + 3) +#define SIZE_NDLTYPE_CONTROLLOOP (1 + 3) #define SIZE_NDLTYPE_ARRIVALRATE (1 + 13) #define SIZE_NDLTYPE_CHANNELLOAD (1 + 10) #define SIZE_NDLTYPE_CHANNELUSE (1 + 13) -#define SIZE_NDLTYPE_DATARATE (1 + 3) +#define SIZE_NDLTYPE_DATARATE (1 + 3) #define SIZE_NDLTYPE_DISTANCE (1 + 12) -#define SIZE_NDLTYPE_NUMBERELEMENTS (1 + 6) +#define SIZE_NDLTYPE_NUMBERELEMENTS (1 + 6) #define SIZE_NDLTYPE_PACKETDURATION (1 + 11) #define SIZE_NDLTYPE_PACKETINTERVAL (1 + 10) -#define SIZE_NDLTYPE_PATHLOSS (1 + 5) -#define SIZE_NDLTYPE_RXPOWER (1 + 7) -#define SIZE_NDLTYPE_SNR (1 + 7) +#define SIZE_NDLTYPE_PATHLOSS (1 + 5) +#define SIZE_NDLTYPE_RXPOWER (1 + 7) +#define SIZE_NDLTYPE_SNR (1 + 7) #define SIZE_NDLTYPE_TIMING (1 + 12) -#define SIZE_NDLTYPE_TXPOWER (1 + 7) -#define SIZE_NDLTYPE_RATIO (1 + 7) -#define SIZE_NDLTYPE_EXPONENT (1 + 7) -#define SIZE_NDLTYPE_QUEUESTATUS (1 + 1) -#define SIZE_NDLTYPE_DCCMECHANISM (1 + 6) +#define SIZE_NDLTYPE_TXPOWER (1 + 7) +#define SIZE_NDLTYPE_RATIO (1 + 7) +#define SIZE_NDLTYPE_EXPONENT (1 + 7) +#define SIZE_NDLTYPE_QUEUESTATUS (1 + 1) +#define SIZE_NDLTYPE_DCCMECHANISM (1 + 6) #define SIZE_BYTE (8) #define INVALID_ACPRIO ((1 << SIZE_NDLTYPE_ACPRIO) - 1) @@ -13400,774 +14653,770 @@ typedef struct { #define INVALID_QUEUESTATS ((1 << SIZE_NDLTYPE_QUEUESTATUS) - 1) #define INVALID_DCCMECHANISM ((1 << SIZE_NDLTYPE_DCCMECHANISM) - 1) -/** The MCS_COUNT macro cannot be modified without breaking - * WMI compatibility. */ +/** + * The MCS_COUNT macro cannot be modified without breaking + * WMI compatibility. + */ #define MCS_COUNT (8) -/** Flags for ndlType_dccMechanism. */ +/** + * Flags for ndlType_dccMechanism. + */ typedef enum { - DCC_MECHANISM_TPC = 1, - DCC_MECHANISM_TRC = 2, - DCC_MECHANISM_TDC = 4, - DCC_MECHANISM_DSC = 8, - DCC_MECHANISM_TAC = 16, - DCC_MECHANISM_RESERVED = 32, - DCC_MECHANISM_ALL = 0x3f, + DCC_MECHANISM_TPC = 1, + DCC_MECHANISM_TRC = 2, + DCC_MECHANISM_TDC = 4, + DCC_MECHANISM_DSC = 8, + DCC_MECHANISM_TAC = 16, + DCC_MECHANISM_RESERVED = 32, + DCC_MECHANISM_ALL = 0x3f, } wmi_dcc_ndl_type_dcc_mechanism; /** Values for ndlType_queueStatus. */ typedef enum { - DCC_QUEUE_CLOSED = 0, - DCC_QUEUE_OPEN = 1, + DCC_QUEUE_CLOSED = 0, + DCC_QUEUE_OPEN = 1, } wmi_dcc_ndl_type_queue_status; -/** For ndlType_acPrio, use the values in wmi_traffic_ac. */ - -/** Values for ndlType_datarate */ +/** + * For ndlType_acPrio, use the values in wmi_traffic_ac. + * Values for ndlType_datarate. + */ typedef enum { - DCC_DATARATE_3_MBPS = 0, - DCC_DATARATE_4_5_MBPS = 1, - DCC_DATARATE_6_MBPS = 2, - DCC_DATARATE_9_MBPS = 3, - DCC_DATARATE_12_MBPS = 4, - DCC_DATARATE_18_MBPS = 5, - DCC_DATARATE_24_MBPS = 6, - DCC_DATARATE_27_MBPS = 7, + DCC_DATARATE_3_MBPS = 0, + DCC_DATARATE_4_5_MBPS = 1, + DCC_DATARATE_6_MBPS = 2, + DCC_DATARATE_9_MBPS = 3, + DCC_DATARATE_12_MBPS = 4, + DCC_DATARATE_18_MBPS = 5, + DCC_DATARATE_24_MBPS = 6, + DCC_DATARATE_27_MBPS = 7, } wmi_dcc_ndl_type_datarate; /** Data structure for active state configuration. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_ndl_active_state_config */ - A_UINT32 tlv_header; - /** - * NDL_asStateId, ndlType_numberElements, 1+6 bits. - * NDL_asChanLoad, ndlType_channelLoad, 1+10 bits. - */ - A_UINT32 state_info; - /** - * NDL_asDcc(AC_BK), ndlType_dccMechanism, 1+6 bits. - * NDL_asDcc(AC_BE), ndlType_dccMechanism, 1+6 bits. - * NDL_asDcc(AC_VI), ndlType_dccMechanism, 1+6 bits. - * NDL_asDcc(AC_VO), ndlType_dccMechanism, 1+6 bits. - */ - A_UINT32 as_dcc[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_DCCMECHANISM)]; - - /** - * NDL_asTxPower(AC_BK), ndlType_txPower, 1+7 bits. - * NDL_asTxPower(AC_BE), ndlType_txPower, 1+7 bits. - * NDL_asTxPower(AC_VI), ndlType_txPower, 1+7 bits. - * NDL_asTxPower(AC_VO), ndlType_txPower, 1+7 bits. - */ - A_UINT32 as_tx_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_TXPOWER)]; - /** - * NDL_asPacketInterval(AC_BK), ndlType_packetInterval, 1+10 bits. - * NDL_asPacketInterval(AC_BE), ndlType_packetInterval, 1+10 bits. - * NDL_asPacketInterval(AC_VI), ndlType_packetInterval, 1+10 bits. - * NDL_asPacketInterval(AC_VO), ndlType_packetInterval, 1+10 bits. - */ - A_UINT32 as_packet_interval_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETINTERVAL)]; - /** - * NDL_asDatarate(AC_BK), ndlType_datarate, 1+3 bits. - * NDL_asDatarate(AC_BE), ndlType_datarate, 1+3 bits. - * NDL_asDatarate(AC_VI), ndlType_datarate, 1+3 bits. - * NDL_asDatarate(AC_VO), ndlType_datarate, 1+3 bits. - */ - A_UINT32 as_datarate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_DATARATE)]; - /** - * NDL_asCarrierSense(AC_BK), ndlType_rxPower, 1+7 bits. - * NDL_asCarrierSense(AC_BE), ndlType_rxPower, 1+7 bits. - * NDL_asCarrierSense(AC_VI), ndlType_rxPower, 1+7 bits. - * NDL_asCarrierSense(AC_VO), ndlType_rxPower, 1+7 bits. - */ - A_UINT32 as_carrier_sense_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_RXPOWER)]; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_ndl_active_state_config + */ + A_UINT32 tlv_header; + /** + * NDL_asStateId, ndlType_numberElements, 1+6 bits. + * NDL_asChanLoad, ndlType_channelLoad, 1+10 bits. + */ + A_UINT32 state_info; + /** + * NDL_asDcc(AC_BK), ndlType_dccMechanism, 1+6 bits. + * NDL_asDcc(AC_BE), ndlType_dccMechanism, 1+6 bits. + * NDL_asDcc(AC_VI), ndlType_dccMechanism, 1+6 bits. + * NDL_asDcc(AC_VO), ndlType_dccMechanism, 1+6 bits. + */ + A_UINT32 as_dcc[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_DCCMECHANISM)]; + /** + * NDL_asTxPower(AC_BK), ndlType_txPower, 1+7 bits. + * NDL_asTxPower(AC_BE), ndlType_txPower, 1+7 bits. + * NDL_asTxPower(AC_VI), ndlType_txPower, 1+7 bits. + * NDL_asTxPower(AC_VO), ndlType_txPower, 1+7 bits. + */ + A_UINT32 as_tx_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_TXPOWER)]; + /** + * NDL_asPacketInterval(AC_BK), ndlType_packetInterval, 1+10 bits. + * NDL_asPacketInterval(AC_BE), ndlType_packetInterval, 1+10 bits. + * NDL_asPacketInterval(AC_VI), ndlType_packetInterval, 1+10 bits. + * NDL_asPacketInterval(AC_VO), ndlType_packetInterval, 1+10 bits. + */ + A_UINT32 as_packet_interval_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETINTERVAL)]; + /** + * NDL_asDatarate(AC_BK), ndlType_datarate, 1+3 bits. + * NDL_asDatarate(AC_BE), ndlType_datarate, 1+3 bits. + * NDL_asDatarate(AC_VI), ndlType_datarate, 1+3 bits. + * NDL_asDatarate(AC_VO), ndlType_datarate, 1+3 bits. + */ + A_UINT32 as_datarate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_DATARATE)]; + /** + * NDL_asCarrierSense(AC_BK), ndlType_rxPower, 1+7 bits. + * NDL_asCarrierSense(AC_BE), ndlType_rxPower, 1+7 bits. + * NDL_asCarrierSense(AC_VI), ndlType_rxPower, 1+7 bits. + * NDL_asCarrierSense(AC_VO), ndlType_rxPower, 1+7 bits. + */ + A_UINT32 as_carrier_sense_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_RXPOWER)]; } wmi_dcc_ndl_active_state_config; #define WMI_NDL_AS_STATE_ID_GET(ptr) WMI_GET_BITS((ptr)->state_info, 0, 7) -#define WMI_NDL_AS_STATE_ID_SET(ptr,val) WMI_SET_BITS((ptr)->state_info, 0, 7, val) +#define WMI_NDL_AS_STATE_ID_SET(ptr, val) WMI_SET_BITS((ptr)->state_info, 0, 7, val) #define WMI_NDL_AS_CHAN_LOAD_GET(ptr) WMI_GET_BITS((ptr)->state_info, 7, 11) -#define WMI_NDL_AS_CHAN_LOAD_SET(ptr,val) WMI_SET_BITS((ptr)->state_info, 7, 11, val) -#define WMI_NDL_AS_DCC_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->as_dcc, acprio, SIZE_NDLTYPE_DCCMECHANISM) -#define WMI_NDL_AS_DCC_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->as_dcc, acprio, SIZE_NDLTYPE_DCCMECHANISM, val) -#define WMI_NDL_AS_TX_POWER_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->as_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) -#define WMI_NDL_AS_TX_POWER_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->as_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) -#define WMI_NDL_AS_PACKET_INTERVAL_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->as_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL) -#define WMI_NDL_AS_PACKET_INTERVAL_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->as_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL, val) -#define WMI_NDL_AS_DATARATE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->as_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE) -#define WMI_NDL_AS_DATARATE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->as_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE, val) -#define WMI_NDL_AS_CARRIER_SENSE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->as_carrier_sense_ac, acprio, SIZE_NDLTYPE_RXPOWER) -#define WMI_NDL_AS_CARRIER_SENSE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->as_carrier_sense_ac, acprio, SIZE_NDLTYPE_RXPOWER, val) +#define WMI_NDL_AS_CHAN_LOAD_SET(ptr, val) WMI_SET_BITS((ptr)->state_info, 7, 11, val) +#define WMI_NDL_AS_DCC_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->as_dcc, acprio, SIZE_NDLTYPE_DCCMECHANISM) +#define WMI_NDL_AS_DCC_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->as_dcc, acprio, SIZE_NDLTYPE_DCCMECHANISM, val) +#define WMI_NDL_AS_TX_POWER_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->as_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) +#define WMI_NDL_AS_TX_POWER_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->as_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) +#define WMI_NDL_AS_PACKET_INTERVAL_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->as_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL) +#define WMI_NDL_AS_PACKET_INTERVAL_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->as_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL, val) +#define WMI_NDL_AS_DATARATE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->as_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE) +#define WMI_NDL_AS_DATARATE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->as_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE, val) +#define WMI_NDL_AS_CARRIER_SENSE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->as_carrier_sense_ac, acprio, SIZE_NDLTYPE_RXPOWER) +#define WMI_NDL_AS_CARRIER_SENSE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->as_carrier_sense_ac, acprio, SIZE_NDLTYPE_RXPOWER, val) /** Data structure for EDCA/QOS parameters. */ -typedef struct -{ - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_qos_parameter */ - A_UINT32 tlv_header; - /** Arbitration Inter-Frame Spacing. Range: 2-15 */ - A_UINT32 aifsn; - /** Contention Window minimum. Range: 1 - 10 */ - A_UINT32 cwmin; - /** Contention Window maximum. Range: 1 - 10 */ - A_UINT32 cwmax; +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_qos_parameter */ + A_UINT32 tlv_header; + /** Arbitration Inter-Frame Spacing. Range: 2-15 */ + A_UINT32 aifsn; + /** Contention Window minimum. Range: 1 - 10 */ + A_UINT32 cwmin; + /** Contention Window maximum. Range: 1 - 10 */ + A_UINT32 cwmax; } wmi_qos_parameter; /** Data structure for information specific to a channel. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_channel */ - A_UINT32 tlv_header; - A_UINT32 bandwidth; /* MHz units */ - wmi_mac_addr mac_address; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_channel */ + A_UINT32 tlv_header; + A_UINT32 bandwidth; /* MHz units */ + wmi_mac_addr mac_address; } wmi_ocb_channel; /** Data structure for an element of the schedule array. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_schedule_element */ - A_UINT32 tlv_header; - A_UINT32 channel_freq; /* MHz units */ - A_UINT32 total_duration; /* ms units */ - A_UINT32 guard_interval; /* ms units */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_schedule_element */ + A_UINT32 tlv_header; + A_UINT32 channel_freq; /* MHz units */ + A_UINT32 total_duration; /* ms units */ + A_UINT32 guard_interval; /* ms units */ } wmi_ocb_schedule_element; /** Data structure for OCB configuration. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_set_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** VDEV id(interface) that is being configured */ - A_UINT32 vdev_id; - A_UINT32 channel_count; - A_UINT32 schedule_size; - A_UINT32 flags; - A_UINT32 ta_max_duration; /* Max duration of continuing multichannel operation without receiving a TA frame (units = seconds) */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_set_config_cmd_fixed_param */ + A_UINT32 tlv_header; + /** VDEV id(interface) that is being configured */ + A_UINT32 vdev_id; + A_UINT32 channel_count; + A_UINT32 schedule_size; + A_UINT32 flags; + /** + * Max duration of continuing multichannel operation without + * receiving a TA frame (units = seconds) + */ + A_UINT32 ta_max_duration; - /** This is followed by a TLV array of wmi_channel. */ - /** This is followed by a TLV array of wmi_ocb_channel. */ - /** This is followed by a TLV array of wmi_qos_parameter. */ - /** This is followed by a TLV array of wmi_dcc_ndl_chan. */ - /** This is followed by a TLV array of wmi_dcc_ndl_active_state_config. */ - /** This is followed by a TLV array of wmi_ocb_schedule_element. */ + /** This is followed by a TLV array of wmi_channel. + * This is followed by a TLV array of wmi_ocb_channel. + * This is followed by a TLV array of wmi_qos_parameter. + * This is followed by a TLV array of wmi_dcc_ndl_chan. + * This is followed by a TLV array of wmi_dcc_ndl_active_state_config. + * This is followed by a TLV array of wmi_ocb_schedule_element. + */ } wmi_ocb_set_config_cmd_fixed_param; -#define EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET 0 -#define EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK 1 -#define WMI_OCB_EXPIRY_TIME_IN_TSF(ptr) (((ptr)->flags & EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK) >> EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET) +#define EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET 0 +#define EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK 1 + +#define WMI_OCB_EXPIRY_TIME_IN_TSF(ptr) \ + (((ptr)->flags & EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK) >> EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET) /** Data structure for the response to the WMI_OCB_SET_CONFIG_CMDID command. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_set_config_resp_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - A_UINT32 status; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_set_config_resp_event_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV id(interface)*/ + A_UINT32 vdev_id; + A_UINT32 status; } wmi_ocb_set_config_resp_event_fixed_param; /* SIZE_UTC_TIME and SIZE_UTC_TIME_ERROR cannot be modified without breaking - WMI compatibility. */ -#define SIZE_UTC_TIME (10) /* The size of the utc time in bytes. */ -#define SIZE_UTC_TIME_ERROR (5) /* The size of the utc time error in bytes. */ + * WMI compatibility. + */ +/* The size of the utc time in bytes. */ +#define SIZE_UTC_TIME (10) +/* The size of the utc time error in bytes. */ +#define SIZE_UTC_TIME_ERROR (5) /** Data structure to set the UTC time. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_set_utc_time_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** 10 bytes of the utc time. */ - A_UINT32 utc_time[WMI_PACKED_ARR_SIZE(SIZE_UTC_TIME,SIZE_BYTE)]; - /** 5 bytes of the time error. */ - A_UINT32 time_error[WMI_PACKED_ARR_SIZE(SIZE_UTC_TIME_ERROR,SIZE_BYTE)]; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_set_utc_time_cmd_fixed_param */ + A_UINT32 tlv_header; + /*VDEV Identifier*/ + A_UINT32 vdev_id; + /** 10 bytes of the utc time. */ + A_UINT32 utc_time[WMI_PACKED_ARR_SIZE(SIZE_UTC_TIME, SIZE_BYTE)]; + /** 5 bytes of the time error. */ + A_UINT32 time_error[WMI_PACKED_ARR_SIZE(SIZE_UTC_TIME_ERROR, SIZE_BYTE)]; } wmi_ocb_set_utc_time_cmd_fixed_param; -#define WMI_UTC_TIME_GET(ptr,byte_index) wmi_packed_arr_get_bits((ptr)->utc_time, byte_index, SIZE_BYTE) -#define WMI_UTC_TIME_SET(ptr,byte_index,val) wmi_packed_arr_set_bits((ptr)->utc_time, byte_index, SIZE_BYTE, val) -#define WMI_TIME_ERROR_GET(ptr,byte_index) wmi_packed_arr_get_bits((ptr)->time_error, byte_index, SIZE_BYTE) -#define WMI_TIME_ERROR_SET(ptr,byte_index,val) wmi_packed_arr_set_bits((ptr)->time_error, byte_index, SIZE_BYTE, val) +#define WMI_UTC_TIME_GET(ptr, byte_index) wmi_packed_arr_get_bits((ptr)->utc_time, byte_index, SIZE_BYTE) +#define WMI_UTC_TIME_SET(ptr, byte_index, val) wmi_packed_arr_set_bits((ptr)->utc_time, byte_index, SIZE_BYTE, val) +#define WMI_TIME_ERROR_GET(ptr, byte_index) wmi_packed_arr_get_bits((ptr)->time_error, byte_index, SIZE_BYTE) +#define WMI_TIME_ERROR_SET(ptr, byte_index, val) wmi_packed_arr_set_bits((ptr)->time_error, byte_index, SIZE_BYTE, val) /** Data structure start the timing advertisement. The template for the * timing advertisement frame follows this structure in the WMI command. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_start_timing_advert_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** Number of times the TA is sent every 5 seconds. */ - A_UINT32 repeat_rate; - /** The frequency on which to transmit. */ - A_UINT32 channel_freq; /* MHz units */ - /** The offset into the template of the timestamp. */ - A_UINT32 timestamp_offset; - /** The offset into the template of the time value. */ - A_UINT32 time_value_offset; - /** The length of the timing advertisement template. The - * template is in the TLV data. */ - A_UINT32 timing_advert_template_length; - - /** This is followed by a binary array containing the TA template. */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_start_timing_advert_cmd_fixed_param */ + A_UINT32 tlv_header; + /*VDEV Identifier*/ + A_UINT32 vdev_id; + /** Number of times the TA is sent every 5 seconds. */ + A_UINT32 repeat_rate; + /** The frequency on which to transmit. */ + A_UINT32 channel_freq; /* MHz units */ + /** The offset into the template of the timestamp. */ + A_UINT32 timestamp_offset; + /** The offset into the template of the time value. */ + A_UINT32 time_value_offset; + /** The length of the timing advertisement template. The + * template is in the TLV data. */ + A_UINT32 timing_advert_template_length; + /** This is followed by a binary array containing the TA template. */ } wmi_ocb_start_timing_advert_cmd_fixed_param; /** Data structure to stop the timing advertisement. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_stop_timing_advert_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - A_UINT32 channel_freq; /* MHz units */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_stop_timing_advert_cmd_fixed_param */ + A_UINT32 tlv_header; + /*VDEV Identifier*/ + A_UINT32 vdev_id; + A_UINT32 channel_freq; /* MHz units */ } wmi_ocb_stop_timing_advert_cmd_fixed_param; /** Data structure for the request for WMI_OCB_GET_TSF_TIMER_CMDID. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - A_UINT32 reserved; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_cmd_fixed_param */ + A_UINT32 tlv_header; + /*VDEV Identifier*/ + A_UINT32 vdev_id; + A_UINT32 reserved; } wmi_ocb_get_tsf_timer_cmd_fixed_param; /** Data structure for the response to WMI_OCB_GET_TSF_TIMER_CMDID. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_resp_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - A_UINT32 tsf_timer_high; - A_UINT32 tsf_timer_low; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_get_tsf_timer_resp_event_fixed_param */ + A_UINT32 tlv_header; + /*VDEV Identifier*/ + A_UINT32 vdev_id; + A_UINT32 tsf_timer_high; + A_UINT32 tsf_timer_low; } wmi_ocb_get_tsf_timer_resp_event_fixed_param; /** Data structure for DCC stats configuration per channel. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_ndl_stats_per_channel */ - A_UINT32 tlv_header; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_ndl_stats_per_channel */ + A_UINT32 tlv_header; - /** The channel for which this applies, 16 bits. */ - /** The dcc_stats_bitmap, 8 bits. */ - A_UINT32 chan_info; + /*VDEV Identifier*/ + A_UINT32 vdev_id; - /** Demodulation model parameters. */ - /** - * NDL_snrBackoff(MCS0), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS1), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS2), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS3), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS4), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS5), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS6), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS7), ndlType_snr, 1+7 bits. - */ - A_UINT32 snr_backoff_mcs[WMI_PACKED_ARR_SIZE(MCS_COUNT,SIZE_NDLTYPE_SNR)]; + /** The channel for which this applies, 16 bits. + * The dcc_stats_bitmap, 8 bits. */ + A_UINT32 chan_info; - /** Communication ranges. */ - /** - * tx_power, ndlType_txPower, 1+7 bits. - * datarate, ndlType_datarate, 1+3 bits. - */ - A_UINT32 tx_power_datarate; - /** - * NDL_carrierSenseRange, ndlType_distance, 1+12 bits. - * NDL_estCommRange, ndlType_distance, 1+12 bits. - */ - A_UINT32 carrier_sense_est_comm_range; + /** Demodulation model parameters. + * + * NDL_snrBackoff(MCS0), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS1), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS2), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS3), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS4), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS5), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS6), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS7), ndlType_snr, 1+7 bits. + */ + A_UINT32 snr_backoff_mcs[WMI_PACKED_ARR_SIZE(MCS_COUNT, SIZE_NDLTYPE_SNR)]; - /** Channel load measures. */ - /** - * dccSensitivity, ndlType_rxPower, 1+7 bits. - * carrierSense, ndlType_rxPower, 1+7 bits. - * NDL_channelLoad, ndlType_channelLoad, 1+10 bits. - */ - A_UINT32 dcc_stats; - /** - * NDL_packetArrivalRate, ndlType_arrivalRate, 1+13 bits. - * NDL_packetAvgDuration, ndlType_packetDuration, 1+11 bits. - */ - A_UINT32 packet_stats; - /** - * NDL_channelBusyTime, ndlType_channelLoad, 1+10 bits. - */ - A_UINT32 channel_busy_time; + /** Communication ranges. + * + * tx_power, ndlType_txPower, 1+7 bits. + * datarate, ndlType_datarate, 1+3 bits. + */ + A_UINT32 tx_power_datarate; + /** + * NDL_carrierSenseRange, ndlType_distance, 1+12 bits. + * NDL_estCommRange, ndlType_distance, 1+12 bits. + */ + A_UINT32 carrier_sense_est_comm_range; - /** Transmit packet statistics. */ - /** - * NDL_txPacketArrivalRate(AC_BK), ndlType_arrivalRate, 1+13 bits. - * NDL_txPacketArrivalRate(AC_BE), ndlType_arrivalRate, 1+13 bits. - * NDL_txPacketArrivalRate(AC_VI), ndlType_arrivalRate, 1+13 bits. - * NDL_txPacketArrivalRate(AC_VO), ndlType_arrivalRate, 1+13 bits. - */ - A_UINT32 tx_packet_arrival_rate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_ARRIVALRATE)]; - /** - * NDL_txPacketAvgDuration(AC_BK), ndlType_packetDuration, 1+11 bits. - * NDL_txPacketAvgDuration(AC_BE), ndlType_packetDuration, 1+11 bits. - * NDL_txPacketAvgDuration(AC_VI), ndlType_packetDuration, 1+11 bits. - * NDL_txPacketAvgDuration(AC_VO), ndlType_packetDuration, 1+11 bits. - */ - A_UINT32 tx_packet_avg_duration_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_PACKETDURATION)]; - /** - * NDL_txChannelUse(AC_BK), ndlType_channelUse, 1+13 bits. - * NDL_txChannelUse(AC_BE), ndlType_channelUse, 1+13 bits. - * NDL_txChannelUse(AC_VI), ndlType_channelUse, 1+13 bits. - * NDL_txChannelUse(AC_VO), ndlType_channelUse, 1+13 bits. - */ - A_UINT32 tx_channel_use_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_CHANNELUSE)]; - /** - * NDL_txSignalAvgPower(AC_BK), ndlType_txPower, 1+7 bits. - * NDL_txSignalAvgPower(AC_BE), ndlType_txPower, 1+7 bits. - * NDL_txSignalAvgPower(AC_VI), ndlType_txPower, 1+7 bits. - * NDL_txSignalAvgPower(AC_VO), ndlType_txPower, 1+7 bits. - */ - A_UINT32 tx_signal_avg_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_TXPOWER)]; + /** Channel load measures. */ + /** + * dccSensitivity, ndlType_rxPower, 1+7 bits. + * carrierSense, ndlType_rxPower, 1+7 bits. + * NDL_channelLoad, ndlType_channelLoad, 1+10 bits. + */ + A_UINT32 dcc_stats; + /** + * NDL_packetArrivalRate, ndlType_arrivalRate, 1+13 bits. + * NDL_packetAvgDuration, ndlType_packetDuration, 1+11 bits. + */ + A_UINT32 packet_stats; + /** + * NDL_channelBusyTime, ndlType_channelLoad, 1+10 bits. + */ + A_UINT32 channel_busy_time; + /** + *Transmit packet statistics. + * NDL_txPacketArrivalRate(AC_BK), ndlType_arrivalRate, 1+13 bits. + * NDL_txPacketArrivalRate(AC_BE), ndlType_arrivalRate, 1+13 bits. + * NDL_txPacketArrivalRate(AC_VI), ndlType_arrivalRate, 1+13 bits. + * NDL_txPacketArrivalRate(AC_VO), ndlType_arrivalRate, 1+13 bits. + */ + A_UINT32 tx_packet_arrival_rate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_ARRIVALRATE)]; + /** + * NDL_txPacketAvgDuration(AC_BK), ndlType_packetDuration, 1+11 bits. + * NDL_txPacketAvgDuration(AC_BE), ndlType_packetDuration, 1+11 bits. + * NDL_txPacketAvgDuration(AC_VI), ndlType_packetDuration, 1+11 bits. + * NDL_txPacketAvgDuration(AC_VO), ndlType_packetDuration, 1+11 bits. + */ + A_UINT32 tx_packet_avg_duration_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETDURATION)]; + /** + * NDL_txChannelUse(AC_BK), ndlType_channelUse, 1+13 bits. + * NDL_txChannelUse(AC_BE), ndlType_channelUse, 1+13 bits. + * NDL_txChannelUse(AC_VI), ndlType_channelUse, 1+13 bits. + * NDL_txChannelUse(AC_VO), ndlType_channelUse, 1+13 bits. + */ + A_UINT32 tx_channel_use_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_CHANNELUSE)]; + /** + * NDL_txSignalAvgPower(AC_BK), ndlType_txPower, 1+7 bits. + * NDL_txSignalAvgPower(AC_BE), ndlType_txPower, 1+7 bits. + * NDL_txSignalAvgPower(AC_VI), ndlType_txPower, 1+7 bits. + * NDL_txSignalAvgPower(AC_VO), ndlType_txPower, 1+7 bits. + */ + A_UINT32 tx_signal_avg_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_TXPOWER)]; } wmi_dcc_ndl_stats_per_channel; -#define WMI_NDL_STATS_SNR_BACKOFF_GET(ptr,mcs) wmi_packed_arr_get_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR) -#define WMI_NDL_STATS_SNR_BACKOFF_SET(ptr,mcs,val) wmi_packed_arr_set_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR, val) - -#define WMI_NDL_STATS_CHAN_FREQ_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 0, 16) -#define WMI_NDL_STATS_CHAN_FREQ_SET(ptr,val) WMI_SET_BITS((ptr)->chan_info, 0, 16, val) -#define WMI_NDL_STATS_DCC_STATS_BITMAP_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 16, 8) -#define WMI_NDL_STATS_DCC_STATS_BITMAP_SET(ptr,val) WMI_SET_BITS((ptr)->chan_info, 16, 8, val) - -#define WMI_NDL_STATS_SNR_BACKOFF_GET(ptr,mcs) wmi_packed_arr_get_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR) -#define WMI_NDL_STATS_SNR_BACKOFF_SET(ptr,mcs,val) wmi_packed_arr_set_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR, val) - -#define WMI_TX_POWER_GET(ptr) WMI_GET_BITS((ptr)->tx_power_datarate, 0, 8) -#define WMI_TX_POWER_SET(ptr,val) WMI_SET_BITS((ptr)->tx_power_datarate, 0, 8, val) -#define WMI_TX_DATARATE_GET(ptr) WMI_GET_BITS((ptr)->tx_power_datarate, 0, 4) -#define WMI_TX_DATARATE_SET(ptr,val) WMI_SET_BITS((ptr)->tx_power_datarate, 0, 4, val) -#define WMI_NDL_CARRIER_SENSE_RANGE_GET(ptr) WMI_GET_BITS((ptr)->carrier_sense_est_comm_range, 0, 13) -#define WMI_NDL_CARRIER_SENSE_RANGE_SET(ptr,val) WMI_SET_BITS((ptr)->carrier_sense_est_comm_range, 0, 13, val) -#define WMI_NDL_EST_COMM_RANGE_GET(ptr) WMI_GET_BITS((ptr)->carrier_sense_est_comm_range, 13, 13) -#define WMI_NDL_EST_COMM_RANGE_SET(ptr,val) WMI_SET_BITS((ptr)->carrier_sense_est_comm_range, 13, 13, val) - -#define WMI_DCC_SENSITIVITY_GET(ptr) WMI_GET_BITS((ptr)->dcc_stats, 0, 8) -#define WMI_DCC_SENSITIVITY_SET(ptr,val) WMI_SET_BITS((ptr)->dcc_stats, 0, 8, val) -#define WMI_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->dcc_stats, 8, 8) -#define WMI_CARRIER_SENSE_SET(ptr,val) WMI_SET_BITS((ptr)->dcc_stats, 8, 8, val) +#define WMI_NDL_STATS_SNR_BACKOFF_GET(ptr, mcs) wmi_packed_arr_get_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR) +#define WMI_NDL_STATS_SNR_BACKOFF_SET(ptr, mcs, val) wmi_packed_arr_set_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR, val) +#define WMI_NDL_STATS_CHAN_FREQ_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 0, 16) +#define WMI_NDL_STATS_CHAN_FREQ_SET(ptr, val) WMI_SET_BITS((ptr)->chan_info, 0, 16, val) +#define WMI_NDL_STATS_DCC_STATS_BITMAP_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 16, 8) +#define WMI_NDL_STATS_DCC_STATS_BITMAP_SET(ptr, val) WMI_SET_BITS((ptr)->chan_info, 16, 8, val) +#define WMI_NDL_STATS_SNR_BACKOFF_GET(ptr, mcs) wmi_packed_arr_get_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR) +#define WMI_NDL_STATS_SNR_BACKOFF_SET(ptr, mcs, val) wmi_packed_arr_set_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR, val) +#define WMI_TX_POWER_GET(ptr) WMI_GET_BITS((ptr)->tx_power_datarate, 0, 8) +#define WMI_TX_POWER_SET(ptr, val) WMI_SET_BITS((ptr)->tx_power_datarate, 0, 8, val) +#define WMI_TX_DATARATE_GET(ptr) WMI_GET_BITS((ptr)->tx_power_datarate, 0, 4) +#define WMI_TX_DATARATE_SET(ptr, val) WMI_SET_BITS((ptr)->tx_power_datarate, 0, 4, val) +#define WMI_NDL_CARRIER_SENSE_RANGE_GET(ptr) WMI_GET_BITS((ptr)->carrier_sense_est_comm_range, 0, 13) +#define WMI_NDL_CARRIER_SENSE_RANGE_SET(ptr, val) WMI_SET_BITS((ptr)->carrier_sense_est_comm_range, 0, 13, val) +#define WMI_NDL_EST_COMM_RANGE_GET(ptr) WMI_GET_BITS((ptr)->carrier_sense_est_comm_range, 13, 13) +#define WMI_NDL_EST_COMM_RANGE_SET(ptr, val) WMI_SET_BITS((ptr)->carrier_sense_est_comm_range, 13, 13, val) +#define WMI_DCC_SENSITIVITY_GET(ptr) WMI_GET_BITS((ptr)->dcc_stats, 0, 8) +#define WMI_DCC_SENSITIVITY_SET(ptr, val) WMI_SET_BITS((ptr)->dcc_stats, 0, 8, val) +#define WMI_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->dcc_stats, 8, 8) +#define WMI_CARRIER_SENSE_SET(ptr, val) WMI_SET_BITS((ptr)->dcc_stats, 8, 8, val) #define WMI_NDL_CHANNEL_LOAD_GET(ptr) WMI_GET_BITS((ptr)->dcc_stats, 16, 11) -#define WMI_NDL_CHANNEL_LOAD_SET(ptr,val) WMI_SET_BITS((ptr)->dcc_stats, 16, 11, val) +#define WMI_NDL_CHANNEL_LOAD_SET(ptr, val) WMI_SET_BITS((ptr)->dcc_stats, 16, 11, val) #define WMI_NDL_PACKET_ARRIVAL_RATE_GET(ptr) WMI_GET_BITS((ptr)->packet_stats, 0, 14) -#define WMI_NDL_PACKET_ARRIVAL_RATE_SET(ptr,val) WMI_SET_BITS((ptr)->packet_stats, 0, 14, val) +#define WMI_NDL_PACKET_ARRIVAL_RATE_SET(ptr, val) WMI_SET_BITS((ptr)->packet_stats, 0, 14, val) #define WMI_NDL_PACKET_AVG_DURATION_GET(ptr) WMI_GET_BITS((ptr)->packet_stats, 14, 12) -#define WMI_NDL_PACKET_AVG_DURATION_SET(ptr,val) WMI_SET_BITS((ptr)->packet_stats, 14, 12, val) +#define WMI_NDL_PACKET_AVG_DURATION_SET(ptr, val) WMI_SET_BITS((ptr)->packet_stats, 14, 12, val) #define WMI_NDL_CHANNEL_BUSY_TIME_GET(ptr) WMI_GET_BITS((ptr)->channel_busy_time, 0, 11) -#define WMI_NDL_CHANNEL_BUSY_TIME_SET(ptr,val) WMI_SET_BITS((ptr)->channel_busy_time, 0, 11, val) +#define WMI_NDL_CHANNEL_BUSY_TIME_SET(ptr, val) WMI_SET_BITS((ptr)->channel_busy_time, 0, 11, val) -#define WMI_NDL_TX_PACKET_ARRIVAL_RATE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tx_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE) -#define WMI_NDL_TX_PACKET_ARRIVAL_RATE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tx_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE, val) -#define WMI_NDL_TX_PACKET_AVG_DURATION_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tx_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION) -#define WMI_NDL_TX_PACKET_AVG_DURATION_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tx_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION, val) -#define WMI_NDL_TX_CHANNEL_USE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tx_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE) -#define WMI_NDL_TX_CHANNEL_USE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tx_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE, val) -#define WMI_NDL_TX_SIGNAL_AVG_POWER_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tx_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) -#define WMI_NDL_TX_SIGNAL_AVG_POWER_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tx_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) +#define WMI_NDL_TX_PACKET_ARRIVAL_RATE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tx_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE) +#define WMI_NDL_TX_PACKET_ARRIVAL_RATE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tx_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE, val) +#define WMI_NDL_TX_PACKET_AVG_DURATION_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tx_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION) +#define WMI_NDL_TX_PACKET_AVG_DURATION_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tx_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION, val) +#define WMI_NDL_TX_CHANNEL_USE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tx_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE) +#define WMI_NDL_TX_CHANNEL_USE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tx_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE, val) +#define WMI_NDL_TX_SIGNAL_AVG_POWER_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tx_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) +#define WMI_NDL_TX_SIGNAL_AVG_POWER_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tx_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) /** Bitmap for DCC stats. */ typedef enum { - DCC_STATS_DEMODULATION_MODEL = 1, - DCC_STATS_COMMUNICATION_RANGES = 2, - DCC_STATS_CHANNEL_LOAD_MEASURES = 4, - DCC_STATS_TRANSMIT_PACKET_STATS = 8, - DCC_STATS_TRANSMIT_MODEL_PARAMETER = 16, - DCC_STATS_ALL = 0xff, + DCC_STATS_DEMODULATION_MODEL = 1, + DCC_STATS_COMMUNICATION_RANGES = 2, + DCC_STATS_CHANNEL_LOAD_MEASURES = 4, + DCC_STATS_TRANSMIT_PACKET_STATS = 8, + DCC_STATS_TRANSMIT_MODEL_PARAMETER = 16, + DCC_STATS_ALL = 0xff, } wmi_dcc_stats_bitmap; /** Data structure for getting the DCC stats. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_get_stats_cmd_fixed_param */ - A_UINT32 tlv_header; - - /* VDEV identifier */ - A_UINT32 vdev_id; - - /** The number of channels for which stats are being requested. */ - A_UINT32 num_channels; - - /** This is followed by a TLV array of wmi_dcc_channel_stats_request. */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_get_stats_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /**The number of channels for which stats are being requested. */ + A_UINT32 num_channels; + /** This is followed by a TLV array of wmi_dcc_channel_stats_request. */ } wmi_dcc_get_stats_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_channel_stats_request */ - A_UINT32 tlv_header; - - /** The channel for which this applies. */ - A_UINT32 chan_freq; /* MHz units */ - - /** The DCC stats being requested. */ - A_UINT32 dcc_stats_bitmap; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_channel_stats_request. + */ + A_UINT32 tlv_header; + /** The channel for which this applies. */ + A_UINT32 chan_freq; /* MHz units */ + /** The DCC stats being requested. */ + A_UINT32 dcc_stats_bitmap; } wmi_dcc_channel_stats_request; /** Data structure for the response with the DCC stats. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_get_stats_resp_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** Number of channels in the response. */ - A_UINT32 num_channels; - /** This is followed by a TLV array of wmi_dcc_ndl_stats_per_channel. */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_get_stats_resp_event_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** Number of channels in the response. */ + A_UINT32 num_channels; + /** This is followed by a TLV array of wmi_dcc_ndl_stats_per_channel. */ } wmi_dcc_get_stats_resp_event_fixed_param; /** Data structure for clearing the DCC stats. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_clear_stats_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - A_UINT32 dcc_stats_bitmap; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_clear_stats_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + A_UINT32 dcc_stats_bitmap; } wmi_dcc_clear_stats_cmd_fixed_param; /** Data structure for the pushed DCC stats */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_stats_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** The number of channels in the response. */ - A_UINT32 num_channels; - - /** This is followed by a TLV array of wmi_dcc_ndl_stats_per_channel. */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_stats_event_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** The number of channels in the response. */ + A_UINT32 num_channels; + /** This is followed by a TLV array of wmi_dcc_ndl_stats_per_channel. */ } wmi_dcc_stats_event_fixed_param; /** Data structure for updating NDL per channel. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_ndl_chan */ - A_UINT32 tlv_header; - - /** - * Channel frequency, 16 bits - * NDL_numActiveState, ndlType_numberElements, 1+6 bits - */ - A_UINT32 chan_info; - - /** - * NDL_minDccSampling, 10 bits. - * Maximum time interval between subsequent checks of the DCC rules. - */ - A_UINT32 ndl_min_dcc_sampling; - - /** - * dcc_enable, 1 bit. - * dcc_stats_enable, 1 bit. - * dcc_stats_interval, 16 bits. - */ - A_UINT32 dcc_flags; - - /** General DCC configuration. */ - /** - * NDL_timeUp, ndlType_timing, 1+12 bits. - * NDL_timeDown, ndlType_timing, 1+12 bits. - */ - A_UINT32 general_config; - - /** Transmit power thresholds. */ - /** - * NDL_minTxPower, ndlType_txPower, 1+7 bits. - * NDL_maxTxPower, ndlType_txPower, 1+7 bits. - */ - A_UINT32 min_max_tx_power; /* see "ETSI TS 102 687" table above for units */ - /** - * NDL_defTxPower(AC_BK), ndlType_txPower, 1+7 bits. - * NDL_defTxPower(AC_BE), ndlType_txPower, 1+7 bits. - * NDL_defTxPower(AC_VI), ndlType_txPower, 1+7 bits. - * NDL_defTxPower(AC_VO), ndlType_txPower, 1+7 bits. - */ + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_ndl_chan + */ + A_UINT32 tlv_header; + /** + * Channel frequency, 16 bits + * NDL_numActiveState, ndlType_numberElements, 1+6 bits + */ + A_UINT32 chan_info; + /** + * NDL_minDccSampling, 10 bits. + * Maximum time interval between subsequent checks of the DCC rules. + */ + A_UINT32 ndl_min_dcc_sampling; + /** + * dcc_enable, 1 bit. + * dcc_stats_enable, 1 bit. + * dcc_stats_interval, 16 bits. + */ + A_UINT32 dcc_flags; + /** General DCC configuration. + * NDL_timeUp, ndlType_timing, 1+12 bits. + * NDL_timeDown, ndlType_timing, 1+12 bits. + */ + A_UINT32 general_config; + /** Transmit power thresholds. + * NDL_minTxPower, ndlType_txPower, 1+7 bits. + * NDL_maxTxPower, ndlType_txPower, 1+7 bits. + */ + /* see "ETSI TS 102 687" table above for units */ + A_UINT32 min_max_tx_power; + /** + * NDL_defTxPower(AC_BK), ndlType_txPower, 1+7 bits. + * NDL_defTxPower(AC_BE), ndlType_txPower, 1+7 bits. + * NDL_defTxPower(AC_VI), ndlType_txPower, 1+7 bits. + * NDL_defTxPower(AC_VO), ndlType_txPower, 1+7 bits. + */ /* see "ETSI TS 102 687" table above for units */ - A_UINT32 def_tx_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_TXPOWER)]; + A_UINT32 def_tx_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_TXPOWER)]; + /** Packet timing thresholds. + * NDL_maxPacketDuration(AC_BK), ndlType_packetDuration, 1+11 bits. + * NDL_maxPacketDuration(AC_BE), ndlType_packetDuration, 1+11 bits. + * NDL_maxPacketDuration(AC_VI), ndlType_packetDuration, 1+11 bits. + * NDL_maxPacketDuration(AC_VO), ndlType_packetDuration, 1+11 bits. + */ + A_UINT32 max_packet_duration_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETDURATION)]; + /** + * NDL_minPacketInterval, ndlType_packetInterval, 1+10 bits. + * NDL_maxPacketInterval, ndlType_packetInterval, 1+10 bits. + */ + A_UINT32 min_max_packet_interval; + /** + * NDL_defPacketInterval(AC_BK), ndlType_packetInterval, 1+10 bits. + * NDL_defPacketInterval(AC_BE), ndlType_packetInterval, 1+10 bits. + * NDL_defPacketInterval(AC_VI), ndlType_packetInterval, 1+10 bits. + * NDL_defPacketInterval(AC_VO), ndlType_packetInterval, 1+10 bits + */ + A_UINT32 def_packet_interval_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETINTERVAL)]; + /** Packet datarate thresholds. + * NDL_minDatarate, ndlType_datarate, 1+3 bits. + * NDL_maxDatarate, ndlType_datarate, 1+3 bits. + */ + A_UINT32 min_max_datarate; + /** + * NDL_defDatarate(AC_BK), ndlType_datarate, 1+3 bits. + * NDL_defDatarate(AC_BE), ndlType_datarate, 1+3 bits. + * NDL_defDatarate(AC_VI), ndlType_datarate, 1+3 bits. + * NDL_defDatarate(AC_VO), ndlType_datarate, 1+3 bits. + */ + A_UINT32 def_datarate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_DATARATE)]; + /** Receive signal thresholds. + * NDL_minCarrierSense, ndlType_rxPower, 1+7 bits. + * NDL_maxCarrierSense, ndlType_rxPower, 1+7 bits. + * NDL_defCarrierSense, ndlType_rxPower, 1+7 bits. + */ + A_UINT32 min_max_def_carrier_sense; - /** Packet timing thresholds. */ - /** - * NDL_maxPacketDuration(AC_BK), ndlType_packetDuration, 1+11 bits. - * NDL_maxPacketDuration(AC_BE), ndlType_packetDuration, 1+11 bits. - * NDL_maxPacketDuration(AC_VI), ndlType_packetDuration, 1+11 bits. - * NDL_maxPacketDuration(AC_VO), ndlType_packetDuration, 1+11 bits. - */ - A_UINT32 max_packet_duration_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_PACKETDURATION)]; - /** - * NDL_minPacketInterval, ndlType_packetInterval, 1+10 bits. - * NDL_maxPacketInterval, ndlType_packetInterval, 1+10 bits. - */ - A_UINT32 min_max_packet_interval; - /** - * NDL_defPacketInterval(AC_BK), ndlType_packetInterval, 1+10 bits. - * NDL_defPacketInterval(AC_BE), ndlType_packetInterval, 1+10 bits. - * NDL_defPacketInterval(AC_VI), ndlType_packetInterval, 1+10 bits. - * NDL_defPacketInterval(AC_VO), ndlType_packetInterval, 1+10 bits. - */ - A_UINT32 def_packet_interval_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_PACKETINTERVAL)]; + /** Receive model parameter. + * NDL_defDccSensitivity, ndlType_rxPower, 1+7 bits. + * NDL_maxCsRange, ndlType_distance, 1+12 bits. + * NDL_refPathLoss, ndlType_pathloss, 1+5 bits. + */ + A_UINT32 receive_model_parameter; - /** Packet datarate thresholds. */ - /** - * NDL_minDatarate, ndlType_datarate, 1+3 bits. - * NDL_maxDatarate, ndlType_datarate, 1+3 bits. - */ - A_UINT32 min_max_datarate; - /** - * NDL_defDatarate(AC_BK), ndlType_datarate, 1+3 bits. - * NDL_defDatarate(AC_BE), ndlType_datarate, 1+3 bits. - * NDL_defDatarate(AC_VI), ndlType_datarate, 1+3 bits. - * NDL_defDatarate(AC_VO), ndlType_datarate, 1+3 bits. - */ - A_UINT32 def_datarate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC,SIZE_NDLTYPE_DATARATE)]; + /** + * NDL_minSNR, ndlType_snr, 1+7 bits. + */ + A_UINT32 receive_model_parameter_2; - /** Receive signal thresholds. */ - /** - * NDL_minCarrierSense, ndlType_rxPower, 1+7 bits. - * NDL_maxCarrierSense, ndlType_rxPower, 1+7 bits. - * NDL_defCarrierSense, ndlType_rxPower, 1+7 bits. - */ - A_UINT32 min_max_def_carrier_sense; - - /** Receive model parameter. */ - /** - * NDL_defDccSensitivity, ndlType_rxPower, 1+7 bits. - * NDL_maxCsRange, ndlType_distance, 1+12 bits. - * NDL_refPathLoss, ndlType_pathloss, 1+5 bits. - */ - A_UINT32 receive_model_parameter; - - /** - * NDL_minSNR, ndlType_snr, 1+7 bits. - */ - A_UINT32 receive_model_parameter_2; - - /** Demodulation model parameters. */ - /** - * NDL_snrBackoff(MCS0), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS1), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS2), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS3), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS4), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS5), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS6), ndlType_snr, 1+7 bits. - * NDL_snrBackoff(MCS7), ndlType_snr, 1+7 bits. - */ - A_UINT32 snr_backoff_mcs[WMI_PACKED_ARR_SIZE(MCS_COUNT,SIZE_NDLTYPE_SNR)]; - - /** Transmit model parameters. */ - /** - * NDL_tmPacketArrivalRate(AC_BK), ndlType_arrivalRate, 1+13 bits. - * NDL_tmPacketArrivalRate(AC_BE), ndlType_arrivalRate, 1+13 bits. - * NDL_tmPacketArrivalRate(AC_VI), ndlType_arrivalRate, 1+13 bits. - * NDL_tmPacketArrivalRate(AC_VO), ndlType_arrivalRate, 1+13 bits. - */ - A_UINT32 tm_packet_arrival_rate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_ARRIVALRATE)]; - /** - * NDL_tmPacketAvgDuration(AC_BK), ndlType_packetDuration, 1+11 bits. - * NDL_tmPacketAvgDuration(AC_BE), ndlType_packetDuration, 1+11 bits. - * NDL_tmPacketAvgDuration(AC_VI), ndlType_packetDuration, 1+11 bits. - * NDL_tmPacketAvgDuration(AC_VO), ndlType_packetDuration, 1+11 bits. - */ - A_UINT32 tm_packet_avg_duration_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETDURATION)]; - /** - * NDL_tmSignalAvgPower(AC_BK), ndlType_txPower, 1+7 bits. - * NDL_tmSignalAvgPower(AC_BE), ndlType_txPower, 1+7 bits. - * NDL_tmSignalAvgPower(AC_VI), ndlType_txPower, 1+7 bits. - * NDL_tmSignalAvgPower(AC_VO), ndlType_txPower, 1+7 bits. - */ - A_UINT32 tm_signal_avg_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_TXPOWER)]; - /** - * NDL_tmMaxChannelUse, ndlType_channelUse, 1+13 bits. - */ - A_UINT32 tm_max_channel_use; + /** Demodulation model parameters. + * NDL_snrBackoff(MCS0), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS1), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS2), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS3), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS4), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS5), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS6), ndlType_snr, 1+7 bits. + * NDL_snrBackoff(MCS7), ndlType_snr, 1+7 bits. + */ + A_UINT32 snr_backoff_mcs[WMI_PACKED_ARR_SIZE(MCS_COUNT, SIZE_NDLTYPE_SNR)]; + /** Transmit model parameters. + * NDL_tmPacketArrivalRate(AC_BK), ndlType_arrivalRate, 1+13 bits. + * NDL_tmPacketArrivalRate(AC_BE), ndlType_arrivalRate, 1+13 bits. + * NDL_tmPacketArrivalRate(AC_VI), ndlType_arrivalRate, 1+13 bits. + * NDL_tmPacketArrivalRate(AC_VO), ndlType_arrivalRate, 1+13 bits. + */ + A_UINT32 tm_packet_arrival_rate_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_ARRIVALRATE)]; + /** + * NDL_tmPacketAvgDuration(AC_BK), ndlType_packetDuration, 1+11 bits. + * NDL_tmPacketAvgDuration(AC_BE), ndlType_packetDuration, 1+11 bits. + * NDL_tmPacketAvgDuration(AC_VI), ndlType_packetDuration, 1+11 bits. + * NDL_tmPacketAvgDuration(AC_VO), ndlType_packetDuration, 1+11 bits. + */ + A_UINT32 tm_packet_avg_duration_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_PACKETDURATION)]; + /** + * NDL_tmSignalAvgPower(AC_BK), ndlType_txPower, 1+7 bits. + * NDL_tmSignalAvgPower(AC_BE), ndlType_txPower, 1+7 bits. + * NDL_tmSignalAvgPower(AC_VI), ndlType_txPower, 1+7 bits. + * NDL_tmSignalAvgPower(AC_VO), ndlType_txPower, 1+7 bits. + */ + A_UINT32 tm_signal_avg_power_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_TXPOWER)]; + /* NDL_tmMaxChannelUse, ndlType_channelUse, 1+13 bits. */ + A_UINT32 tm_max_channel_use; /** * NDL_tmChannelUse(AC_BK), ndlType_channelUse, 1+13 bits. * NDL_tmChannelUse(AC_BE), ndlType_channelUse, 1+13 bits. * NDL_tmChannelUse(AC_VI), ndlType_channelUse, 1+13 bits. * NDL_tmChannelUse(AC_VO), ndlType_channelUse, 1+13 bits. */ - A_UINT32 tm_channel_use_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_CHANNELUSE)]; - - /** Channel load thresholds. */ - /** - * NDL_minChannelLoad, ndlType_channelLoad, 1+10 bits. - * NDL_maxChannelLoad, ndlType_channelLoad, 1+10 bits. - */ - A_UINT32 min_max_channel_load; - - /** Transmit queue parameters. */ - /** - * NDL_numQueue, ndlType_acPrio, 1+3 bits. - * NDL_refQueueStatus(AC_BK), ndlType_queueStatus, 1+1 bit. - * NDL_refQueueStatus(AC_BE), ndlType_queueStatus, 1+1 bit. - * NDL_refQueueStatus(AC_VI), ndlType_queueStatus, 1+1 bit. - * NDL_refQueueStatus(AC_VO), ndlType_queueStatus, 1+1 bit. - */ - A_UINT32 transmit_queue_parameters; - - /** - * NDL_refQueueLen(AC_BK), ndlType_numberElements, 1+6 bits. - * NDL_refQueueLen(AC_BE), ndlType_numberElements, 1+6 bits. - * NDL_refQueueLen(AC_VI), ndlType_numberElements, 1+6 bits. - * NDL_refQueueLen(AC_VO), ndlType_numberElements, 1+6 bits. - */ - A_UINT32 numberElements[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_NUMBERELEMENTS)]; - + A_UINT32 tm_channel_use_ac[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_CHANNELUSE)]; + /** Channel load thresholds. + * NDL_minChannelLoad, ndlType_channelLoad, 1+10 bits. + * NDL_maxChannelLoad, ndlType_channelLoad, 1+10 bits. + */ + A_UINT32 min_max_channel_load; + /** Transmit queue parameters. + * NDL_numQueue, ndlType_acPrio, 1+3 bits. + * NDL_refQueueStatus(AC_BK), ndlType_queueStatus, 1+1 bit. + * NDL_refQueueStatus(AC_BE), ndlType_queueStatus, 1+1 bit. + * NDL_refQueueStatus(AC_VI), ndlType_queueStatus, 1+1 bit. + * NDL_refQueueStatus(AC_VO), ndlType_queueStatus, 1+1 bit. + */ + A_UINT32 transmit_queue_parameters; + /** + * NDL_refQueueLen(AC_BK), ndlType_numberElements, 1+6 bits. + * NDL_refQueueLen(AC_BE), ndlType_numberElements, 1+6 bits. + * NDL_refQueueLen(AC_VI), ndlType_numberElements, 1+6 bits. + * NDL_refQueueLen(AC_VO), ndlType_numberElements, 1+6 bits. + */ + A_UINT32 numberElements[WMI_PACKED_ARR_SIZE(WLAN_MAX_AC, SIZE_NDLTYPE_NUMBERELEMENTS)]; } wmi_dcc_ndl_chan; -#define WMI_CHAN_FREQ_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 0, 16) -#define WMI_CHAN_FREQ_SET(ptr,val) WMI_SET_BITS((ptr)->chan_info, 0, 16, val) -#define WMI_NDL_NUM_ACTIVE_STATE_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 16, 7) -#define WMI_NDL_NUM_ACTIVE_STATE_SET(ptr,val) WMI_SET_BITS((ptr)->chan_info, 16, 7, val) +#define WMI_CHAN_FREQ_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 0, 16) +#define WMI_CHAN_FREQ_SET(ptr, val) WMI_SET_BITS((ptr)->chan_info, 0, 16, val) +#define WMI_NDL_NUM_ACTIVE_STATE_GET(ptr) WMI_GET_BITS((ptr)->chan_info, 16, 7) +#define WMI_NDL_NUM_ACTIVE_STATE_SET(ptr, val) WMI_SET_BITS((ptr)->chan_info, 16, 7, val) -#define WMI_NDL_MIN_DCC_SAMPLING_GET(ptr) WMI_GET_BITS((ptr)->ndl_min_dcc_sampling, 0, 10) -#define WMI_NDL_MIN_DCC_SAMPLING_SET(ptr,val) WMI_SET_BITS((ptr)->ndl_min_dcc_sampling, 0, 10, val) -#define WMI_NDL_MEASURE_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->ndl_min_dcc_sampling, 10, 16) -#define WMI_NDL_MEASURE_INTERVAL_SET(ptr,val) WMI_SET_BITS((ptr)->ndl_min_dcc_sampling, 10, 16, val) +#define WMI_NDL_MIN_DCC_SAMPLING_GET(ptr) WMI_GET_BITS((ptr)->ndl_min_dcc_sampling, 0, 10) +#define WMI_NDL_MIN_DCC_SAMPLING_SET(ptr, val) WMI_SET_BITS((ptr)->ndl_min_dcc_sampling, 0, 10, val) -#define WMI_NDL_DCC_ENABLE_GET(ptr) WMI_GET_BITS((ptr)->dcc_flags, 0, 1) -#define WMI_NDL_DCC_ENABLE_SET(ptr,val) WMI_SET_BITS((ptr)->dcc_flags, 0, 1, val) -#define WMI_NDL_DCC_STATS_ENABLE_GET(ptr) WMI_GET_BITS((ptr)->dcc_flags, 1, 1) -#define WMI_NDL_DCC_STATS_ENABLE_SET(ptr,val) WMI_SET_BITS((ptr)->dcc_flags, 1, 1, val) -#define WMI_NDL_DCC_STATS_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->dcc_flags, 2, 16) -#define WMI_NDL_DCC_STATS_INTERVAL_SET(ptr,val) WMI_SET_BITS((ptr)->dcc_flags, 2, 16, val) +#define WMI_NDL_MEASURE_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->ndl_min_dcc_sampling, 10, 16) +#define WMI_NDL_MEASURE_INTERVAL_SET(ptr, val) WMI_SET_BITS((ptr)->ndl_min_dcc_sampling, 10, 16, val) -#define WMI_NDL_TIME_UP_GET(ptr) WMI_GET_BITS((ptr)->general_config, 0, 13) -#define WMI_NDL_TIME_UP_SET(ptr,val) WMI_SET_BITS((ptr)->general_config, 0, 13, val) -#define WMI_NDL_TIME_DOWN_GET(ptr) WMI_GET_BITS((ptr)->general_config, 13, 13) -#define WMI_NDL_TIME_DOWN_SET(ptr,val) WMI_SET_BITS((ptr)->general_config, 13, 13, val) -#define WMI_NDL_MIN_TX_POWER_GET(ptr) WMI_GET_BITS((ptr)->min_max_tx_power, 0, 8) -#define WMI_NDL_MIN_TX_POWER_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_tx_power, 0, 8, val) -#define WMI_NDL_MAX_TX_POWER_GET(ptr) WMI_GET_BITS((ptr)->min_max_tx_power, 8, 8) -#define WMI_NDL_MAX_TX_POWER_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_tx_power, 8, 8, val) +#define WMI_NDL_DCC_ENABLE_GET(ptr) WMI_GET_BITS((ptr)->dcc_flags, 0, 1) +#define WMI_NDL_DCC_ENABLE_SET(ptr, val) WMI_SET_BITS((ptr)->dcc_flags, 0, 1, val) +#define WMI_NDL_DCC_STATS_ENABLE_GET(ptr) WMI_GET_BITS((ptr)->dcc_flags, 1, 1) +#define WMI_NDL_DCC_STATS_ENABLE_SET(ptr, val) WMI_SET_BITS((ptr)->dcc_flags, 1, 1, val) +#define WMI_NDL_DCC_STATS_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->dcc_flags, 2, 16) +#define WMI_NDL_DCC_STATS_INTERVAL_SET(ptr, val) WMI_SET_BITS((ptr)->dcc_flags, 2, 16, val) -#define WMI_NDL_DEF_TX_POWER_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->def_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) -#define WMI_NDL_DEF_TX_POWER_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->def_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) +#define WMI_NDL_TIME_UP_GET(ptr) WMI_GET_BITS((ptr)->general_config, 0, 13) +#define WMI_NDL_TIME_UP_SET(ptr, val) WMI_SET_BITS((ptr)->general_config, 0, 13, val) +#define WMI_NDL_TIME_DOWN_GET(ptr) WMI_GET_BITS((ptr)->general_config, 13, 13) +#define WMI_NDL_TIME_DOWN_SET(ptr, val) WMI_SET_BITS((ptr)->general_config, 13, 13, val) -#define WMI_NDL_MAX_PACKET_DURATION_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->max_packet_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION) -#define WMI_NDL_MAX_PACKET_DURATION_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->max_packet_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION, val) -#define WMI_NDL_MIN_PACKET_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->min_max_packet_interval, 0, 11) -#define WMI_NDL_MIN_PACKET_INTERVAL_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_packet_interval, 0, 11, val) -#define WMI_NDL_MAX_PACKET_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->min_max_packet_interval, 11, 11) -#define WMI_NDL_MAX_PACKET_INTERVAL_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_packet_interval, 11, 11, val) -#define WMI_NDL_DEF_PACKET_INTERVAL_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->def_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL) -#define WMI_NDL_DEF_PACKET_INTERVAL_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->def_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL, val) +#define WMI_NDL_MIN_TX_POWER_GET(ptr) WMI_GET_BITS((ptr)->min_max_tx_power, 0, 8) +#define WMI_NDL_MIN_TX_POWER_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_tx_power, 0, 8, val) +#define WMI_NDL_MAX_TX_POWER_GET(ptr) WMI_GET_BITS((ptr)->min_max_tx_power, 8, 8) +#define WMI_NDL_MAX_TX_POWER_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_tx_power, 8, 8, val) -#define WMI_NDL_MIN_DATARATE_GET(ptr) WMI_GET_BITS((ptr)->min_max_datarate, 0, 4) -#define WMI_NDL_MIN_DATARATE_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_datarate, 0, 4, val) -#define WMI_NDL_MAX_DATARATE_GET(ptr) WMI_GET_BITS((ptr)->min_max_datarate, 4, 4) -#define WMI_NDL_MAX_DATARATE_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_datarate, 4, 4, val) -#define WMI_NDL_DEF_DATARATE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->def_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE) -#define WMI_NDL_DEF_DATARATE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->def_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE, val) +#define WMI_NDL_DEF_TX_POWER_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->def_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) +#define WMI_NDL_DEF_TX_POWER_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->def_tx_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) -#define WMI_NDL_MIN_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->min_max_def_carrier_sense, 0, 8) -#define WMI_NDL_MIN_CARRIER_SENSE_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_def_carrier_sense, 0, 8, val) -#define WMI_NDL_MAX_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->min_max_def_carrier_sense, 8, 8) -#define WMI_NDL_MAX_CARRIER_SENSE_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_def_carrier_sense, 8, 8, val) -#define WMI_NDL_DEF_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->min_max_def_carrier_sense, 16, 8) -#define WMI_NDL_DEF_CARRIER_SENSE_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_def_carrier_sense, 16, 8, val) +#define WMI_NDL_MAX_PACKET_DURATION_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->max_packet_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION) +#define WMI_NDL_MAX_PACKET_DURATION_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->max_packet_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION, val) +#define WMI_NDL_MIN_PACKET_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->min_max_packet_interval, 0, 11) +#define WMI_NDL_MIN_PACKET_INTERVAL_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_packet_interval, 0, 11, val) +#define WMI_NDL_MAX_PACKET_INTERVAL_GET(ptr) WMI_GET_BITS((ptr)->min_max_packet_interval, 11, 11) +#define WMI_NDL_MAX_PACKET_INTERVAL_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_packet_interval, 11, 11, val) +#define WMI_NDL_DEF_PACKET_INTERVAL_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->def_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL) +#define WMI_NDL_DEF_PACKET_INTERVAL_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->def_packet_interval_ac, acprio, SIZE_NDLTYPE_PACKETINTERVAL, val) + +#define WMI_NDL_MIN_DATARATE_GET(ptr) WMI_GET_BITS((ptr)->min_max_datarate, 0, 4) +#define WMI_NDL_MIN_DATARATE_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_datarate, 0, 4, val) +#define WMI_NDL_MAX_DATARATE_GET(ptr) WMI_GET_BITS((ptr)->min_max_datarate, 4, 4) +#define WMI_NDL_MAX_DATARATE_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_datarate, 4, 4, val) +#define WMI_NDL_DEF_DATARATE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->def_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE) +#define WMI_NDL_DEF_DATARATE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->def_datarate_ac, acprio, SIZE_NDLTYPE_DATARATE, val) + +#define WMI_NDL_MIN_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->min_max_def_carrier_sense, 0, 8) +#define WMI_NDL_MIN_CARRIER_SENSE_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_def_carrier_sense, 0, 8, val) +#define WMI_NDL_MAX_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->min_max_def_carrier_sense, 8, 8) +#define WMI_NDL_MAX_CARRIER_SENSE_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_def_carrier_sense, 8, 8, val) +#define WMI_NDL_DEF_CARRIER_SENSE_GET(ptr) WMI_GET_BITS((ptr)->min_max_def_carrier_sense, 16, 8) +#define WMI_NDL_DEF_CARRIER_SENSE_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_def_carrier_sense, 16, 8, val) #define WMI_NDL_DEF_DCC_SENSITIVITY_GET(ptr) WMI_GET_BITS((ptr)->receive_model_parameter, 0, 8) -#define WMI_NDL_DEF_DCC_SENSITIVITY_SET(ptr,val) WMI_SET_BITS((ptr)->receive_model_parameter, 0, 8, val) +#define WMI_NDL_DEF_DCC_SENSITIVITY_SET(ptr, val) WMI_SET_BITS((ptr)->receive_model_parameter, 0, 8, val) #define WMI_NDL_MAX_CS_RANGE_GET(ptr) WMI_GET_BITS((ptr)->receive_model_parameter, 8, 13) -#define WMI_NDL_MAX_CS_RANGE_SET(ptr,val) WMI_SET_BITS((ptr)->receive_model_parameter, 8, 13, val) +#define WMI_NDL_MAX_CS_RANGE_SET(ptr, val) WMI_SET_BITS((ptr)->receive_model_parameter, 8, 13, val) #define WMI_NDL_REF_PATH_LOSS_GET(ptr) WMI_GET_BITS((ptr)->receive_model_parameter, 21, 6) -#define WMI_NDL_REF_PATH_LOSS_SET(ptr,val) WMI_SET_BITS((ptr)->receive_model_parameter, 21, 6, val) +#define WMI_NDL_REF_PATH_LOSS_SET(ptr, val) WMI_SET_BITS((ptr)->receive_model_parameter, 21, 6, val) #define WMI_NDL_MIN_SNR_GET(ptr) WMI_GET_BITS((ptr)->receive_model_parameter_2, 0, 8) -#define WMI_NDL_MIN_SNR_SET(ptr,val) WMI_SET_BITS((ptr)->receive_model_parameter_2, 0, 8, val) +#define WMI_NDL_MIN_SNR_SET(ptr, val) WMI_SET_BITS((ptr)->receive_model_parameter_2, 0, 8, val) -#define WMI_NDL_SNR_BACKOFF_GET(ptr,mcs) wmi_packed_arr_get_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR) -#define WMI_NDL_SNR_BACKOFF_SET(ptr,mcs,val) wmi_packed_arr_set_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR, val) +#define WMI_NDL_SNR_BACKOFF_GET(ptr, mcs) wmi_packed_arr_get_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR) +#define WMI_NDL_SNR_BACKOFF_SET(ptr, mcs, val) wmi_packed_arr_set_bits((ptr)->snr_backoff_mcs, mcs, SIZE_NDLTYPE_SNR, val) -#define WMI_NDL_TM_PACKET_ARRIVAL_RATE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tm_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE) -#define WMI_NDL_TM_PACKET_ARRIVAL_RATE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tm_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE, val) -#define WMI_NDL_TM_PACKET_AVG_DURATION_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tm_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION) -#define WMI_NDL_TM_PACKET_AVG_DURATION_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tm_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION, val) -#define WMI_NDL_TM_SIGNAL_AVG_POWER_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tm_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) -#define WMI_NDL_TM_SIGNAL_AVG_POWER_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tm_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) -#define WMI_NDL_TM_MAX_CHANNEL_USE_GET(ptr) WMI_GET_BITS((ptr)->tm_max_channel_use, 0, 14) -#define WMI_NDL_TM_MAX_CHANNEL_USE_SET(ptr,val) WMI_SET_BITS((ptr)->tm_max_channel_use, 0, 14, val) -#define WMI_NDL_TM_CHANNEL_USE_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->tm_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE) -#define WMI_NDL_TM_CHANNEL_USE_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->tm_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE, val) +#define WMI_NDL_TM_PACKET_ARRIVAL_RATE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tm_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE) +#define WMI_NDL_TM_PACKET_ARRIVAL_RATE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tm_packet_arrival_rate_ac, acprio, SIZE_NDLTYPE_ARRIVALRATE, val) +#define WMI_NDL_TM_PACKET_AVG_DURATION_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tm_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION) +#define WMI_NDL_TM_PACKET_AVG_DURATION_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tm_packet_avg_duration_ac, acprio, SIZE_NDLTYPE_PACKETDURATION, val) +#define WMI_NDL_TM_SIGNAL_AVG_POWER_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tm_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER) +#define WMI_NDL_TM_SIGNAL_AVG_POWER_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tm_signal_avg_power_ac, acprio, SIZE_NDLTYPE_TXPOWER, val) +#define WMI_NDL_TM_MAX_CHANNEL_USE_GET(ptr) WMI_GET_BITS((ptr)->tm_max_channel_use, 0, 14) +#define WMI_NDL_TM_MAX_CHANNEL_USE_SET(ptr, val) WMI_SET_BITS((ptr)->tm_max_channel_use, 0, 14, val) +#define WMI_NDL_TM_CHANNEL_USE_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->tm_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE) +#define WMI_NDL_TM_CHANNEL_USE_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->tm_channel_use_ac, acprio, SIZE_NDLTYPE_CHANNELUSE, val) -#define WMI_NDL_MIN_CHANNEL_LOAD_GET(ptr) WMI_GET_BITS((ptr)->min_max_channel_load, 0, 11) -#define WMI_NDL_MIN_CHANNEL_LOAD_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_channel_load, 0, 11, val) -#define WMI_NDL_MAX_CHANNEL_LOAD_GET(ptr) WMI_GET_BITS((ptr)->min_max_channel_load, 11, 11) -#define WMI_NDL_MAX_CHANNEL_LOAD_SET(ptr,val) WMI_SET_BITS((ptr)->min_max_channel_load, 11, 11, val) +#define WMI_NDL_MIN_CHANNEL_LOAD_GET(ptr) WMI_GET_BITS((ptr)->min_max_channel_load, 0, 11) +#define WMI_NDL_MIN_CHANNEL_LOAD_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_channel_load, 0, 11, val) +#define WMI_NDL_MAX_CHANNEL_LOAD_GET(ptr) WMI_GET_BITS((ptr)->min_max_channel_load, 11, 11) +#define WMI_NDL_MAX_CHANNEL_LOAD_SET(ptr, val) WMI_SET_BITS((ptr)->min_max_channel_load, 11, 11, val) -#define WMI_NDL_NUM_QUEUE_GET(ptr) WMI_GET_BITS((ptr)->transmit_queue_parameters, 0, 4) -#define WMI_NDL_NUM_QUEUE_SET(ptr,val) WMI_SET_BITS((ptr)->transmit_queue_parameters, 0, 4, val) -#define WMI_NDL_REF_QUEUE_STATUS_GET(ptr,acprio) WMI_GET_BITS((ptr)->transmit_queue_parameters, (4 + (acprio * 2)), 2) -#define WMI_NDL_REF_QUEUE_STATUS_SET(ptr,acprio,val) WMI_SET_BITS((ptr)->transmit_queue_parameters, (4 + (acprio * 2)), 2, val) -#define WMI_NDL_REF_QUEUE_LEN_GET(ptr,acprio) wmi_packed_arr_get_bits((ptr)->numberElements, acprio, SIZE_NDLTYPE_NUMBERELEMENTS) -#define WMI_NDL_REF_QUEUE_LEN_SET(ptr,acprio,val) wmi_packed_arr_set_bits((ptr)->numberElements, acprio, SIZE_NDLTYPE_NUMBERELEMENTS, val) +#define WMI_NDL_NUM_QUEUE_GET(ptr) WMI_GET_BITS((ptr)->transmit_queue_parameters, 0, 4) +#define WMI_NDL_NUM_QUEUE_SET(ptr, val) WMI_SET_BITS((ptr)->transmit_queue_parameters, 0, 4, val) +#define WMI_NDL_REF_QUEUE_STATUS_GET(ptr, acprio) WMI_GET_BITS((ptr)->transmit_queue_parameters, (4 + (acprio * 2)), 2) +#define WMI_NDL_REF_QUEUE_STATUS_SET(ptr, acprio, val) WMI_SET_BITS((ptr)->transmit_queue_parameters, (4 + (acprio * 2)), 2, val) +#define WMI_NDL_REF_QUEUE_LEN_GET(ptr, acprio) wmi_packed_arr_get_bits((ptr)->numberElements, acprio, SIZE_NDLTYPE_NUMBERELEMENTS) +#define WMI_NDL_REF_QUEUE_LEN_SET(ptr, acprio, val) wmi_packed_arr_set_bits((ptr)->numberElements, acprio, SIZE_NDLTYPE_NUMBERELEMENTS, val) /** Data structure for updating the NDL. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_update_ndl_cmd_fixed_param */ - A_UINT32 tlv_header; - - /* VDEV identifier */ - A_UINT32 vdev_id; - - /** The number of channels in the request. */ - A_UINT32 num_channel; - - /** This is followed by a TLV array of wmi_dcc_ndl_chan. */ - /** This is followed by a TLV array of wmi_dcc_ndl_active_state_config. */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_update_ndl_cmd_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** The number of channels in the request. */ + A_UINT32 num_channel; + /** This is followed by a TLV array of wmi_dcc_ndl_chan. */ + /** This is followed by a TLV array of wmi_dcc_ndl_active_state_config. */ } wmi_dcc_update_ndl_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_dcc_update_ndl_resp_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - A_UINT32 status; + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_dcc_update_ndl_resp_event_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + A_UINT32 status; } wmi_dcc_update_ndl_resp_event_fixed_param; /* Actions for TSF timestamp */ typedef enum { - TSF_TSTAMP_CAPTURE_REQ = 1, - TSF_TSTAMP_CAPTURE_RESET = 2, - TSF_TSTAMP_READ_VALUE = 3, - TSF_TSTAMP_QTIMER_CAPTURE_REQ = 4, + TSF_TSTAMP_CAPTURE_REQ = 1, + TSF_TSTAMP_CAPTURE_RESET = 2, + TSF_TSTAMP_READ_VALUE = 3, + TSF_TSTAMP_QTIMER_CAPTURE_REQ = 4, } wmi_tsf_tstamp_action; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_tsf_tstamp_action_cmd_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* action type, refer to wmi_tsf_tstamp_action */ - A_UINT32 tsf_action; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_tsf_tstamp_action_cmd_fixed_param */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* action type, refer to wmi_tsf_tstamp_action */ + A_UINT32 tsf_action; } wmi_vdev_tsf_tstamp_action_cmd_fixed_param; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_tsf_report_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /* low 32bit of tsf */ - A_UINT32 tsf_low; - /* high 32 bit of tsf */ - A_UINT32 tsf_high; - /* low 32 bits of qtimer */ - A_UINT32 qtimer_low; - /* high 32 bits of qtimer */ - A_UINT32 qtimer_high; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_tsf_report_event_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /* low 32bit of tsf */ + A_UINT32 tsf_low; + /* high 32 bit of tsf */ + A_UINT32 tsf_high; + /* low 32 bits of qtimer */ + A_UINT32 qtimer_low; + /* high 32 bits of qtimer */ + A_UINT32 qtimer_high; } wmi_vdev_tsf_report_event_fixed_param; -/* ie_id values: +/** + * ie_id values: * 0 to 255 are used for individual IEEE802.11 Information Element types */ #define WMI_SET_VDEV_IE_ID_SCAN_SET_DEFAULT_IE 256 @@ -14177,295 +15426,426 @@ typedef struct { /* band values: */ typedef enum { - WMI_SET_VDEV_IE_BAND_ALL = 0, - WMI_SET_VDEV_IE_BAND_2_4GHZ, - WMI_SET_VDEV_IE_BAND_5GHZ, + WMI_SET_VDEV_IE_BAND_ALL = 0, + WMI_SET_VDEV_IE_BAND_2_4GHZ, + WMI_SET_VDEV_IE_BAND_5GHZ, } wmi_set_vdev_ie_band; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_ie_cmd_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** unique id to identify the ie_data as defined by ieee 802.11 spec */ - A_UINT32 ie_id; - /** ie_len corresponds to num of bytes in ie_data[] */ - A_UINT32 ie_len; - /** source of this command */ - A_UINT32 ie_source; /* see WMI_SET_VDEV_IE_SOURCE_ defs */ - /** band for this IE - se wmi_set_vdev_ie_band enum */ - A_UINT32 band; - /** - * Following this structure is the TLV byte stream of ie data of length ie_buf_len: - * A_UINT8 ie_data[]; - * - */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_set_ie_cmd_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* unique id to identify the ie_data as defined by ieee 802.11 spec */ + A_UINT32 ie_id; + /* ie_len corresponds to num of bytes in ie_data[] */ + A_UINT32 ie_len; + /** source of this command */ + A_UINT32 ie_source; /* see WMI_SET_VDEV_IE_SOURCE_ defs */ + /** band for this IE - se wmi_set_vdev_ie_band enum */ + A_UINT32 band; + /* + * Following this structure is the TLV byte stream of ie data of length + * buf_len: + * A_UINT8 ie_data[]; + */ } wmi_vdev_set_ie_cmd_fixed_param; +/* DISA feature related data structures */ +#define MAX_MAC_HEADER_LEN 32 +typedef enum { + WMI_ENCRYPT_DECRYPT_FLAG_INVALID, + WMI_ENCRYPT = 1, + WMI_DECRYPT = 2, +} WMI_ENCRYPT_DECRYPT_FLAG; + +typedef struct { + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_encrypt_decrypt_data_req_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + A_UINT32 key_flag; /* WMI_ENCRYPT_DECRYPT_FLAG */ + A_UINT32 key_idx; + A_UINT32 key_cipher; + A_UINT32 key_len; /* units = bytes */ + A_UINT32 key_txmic_len; /* units = bytes */ + A_UINT32 key_rxmic_len; /* units = bytes */ + /** Key: This array needs to be provided in little-endian order */ + A_UINT8 key_data[WMI_MAX_KEY_LEN]; + /** + * Packet number: This array needs to be provided in little-endian + * order. + * If the PN is less than 8 bytes, the PN data shall be placed into this + * pn[] array starting at byte 0, leaving the MSBs empty. + */ + A_UINT8 pn[8]; + /** + * 802.11 MAC header to be typecast to struct ieee80211_qosframe_addr4 + * This array needs to be provided in little-endian order. + */ + A_UINT8 mac_hdr[MAX_MAC_HEADER_LEN]; + A_UINT32 data_len; /** Payload length, units = bytes */ + /** + * Following this struct are this TLV: + * A_UINT8 data[]; <-- actual data to be encrypted, + * needs to be provided in little-endian order + */ +} wmi_vdev_encrypt_decrypt_data_req_cmd_fixed_param; + +/** + * This event is generated in response to + * WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID from HOST. + * On receiving WMI command WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID from + * HOST with DISA test vectors, DISA frame will prepared and submitted to HW, + * then on receiving the tx completion for the DISA frame this WMI event + * will be delivered to HOST with the encrypted frame. + */ +typedef struct { + /** + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_encrypt_decrypt_data_resp_event_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + A_INT32 status; /* 0: success, -1: Failure, */ + /* 802.11 header length + encrypted payload length (units = bytes) */ + A_UINT32 data_length; + /** + * Following this struct is this TLV: + * A_UINT8 enc80211_frame[]; <-- Encrypted 802.11 frame; + * 802.11 header + encrypted payload, + * provided in little-endian order + */ +} wmi_vdev_encrypt_decrypt_data_resp_event_fixed_param; + /* DEPRECATED - use wmi_pdev_set_pcl_cmd_fixed_param instead */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_pcl_cmd_fixed_param */ - /** Set Preferred Channel List **/ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_soc_set_pcl_cmd_fixed_param + * Set Preferred Channel List + */ + A_UINT32 tlv_header; - /** # of channels to scan */ - A_UINT32 num_chan; -/** - * TLV (tag length value) parameters follow the wmi_soc_set_pcl_cmd - * structure. The TLV's are: - * A_UINT32 channel_list[]; - **/ + /* # of channels to scan */ + A_UINT32 num_chan; + /* + * TLV (tag length value ) parameters follow the wmi_soc_set_pcl_cmd + * structure. The TLV's are: + * A_UINT32 channel_list[]; + */ } wmi_soc_set_pcl_cmd_fixed_param; /* Values for channel_weight */ typedef enum { - WMI_PCL_WEIGHT_DISALLOW = 0, - WMI_PCL_WEIGHT_LOW = 1, - WMI_PCL_WEIGHT_MEDIUM = 2, - WMI_PCL_WEIGHT_HIGH = 3, - WMI_PCL_WEIGHT_VERY_HIGH = 4, + WMI_PCL_WEIGHT_DISALLOW = 0, + WMI_PCL_WEIGHT_LOW = 1, + WMI_PCL_WEIGHT_MEDIUM = 2, + WMI_PCL_WEIGHT_HIGH = 3, + WMI_PCL_WEIGHT_VERY_HIGH = 4, } wmi_pcl_chan_weight; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_pcl_cmd_fixed_param */ - /** Set Preferred Channel List **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_pcl_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** Set Preferred Channel List **/ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - /** # of channels to scan */ - A_UINT32 num_chan; -/** - * TLV (tag length value) parameters follow the wmi_soc_set_pcl_cmd - 12930 * structure. The TLV's are: - * A_UINT32 channel_weight[]; channel order & size will be as per the list provided in WMI_SCAN_CHAN_LIST_CMDID - **/ + /** # of channels to scan */ + A_UINT32 num_chan; + /** + * TLV (tag length value ) parameters follow the wmi_soc_set_pcl_cmd + * structure. The TLV's are: + * A_UINT32 channel_weight[]; + * channel order & size will be as per the list provided + * in WMI_SCAN_CHAN_LIST_CMDID + **/ } wmi_pdev_set_pcl_cmd_fixed_param; /* DEPRECATED - use wmi_pdev_set_hw_mode_cmd_fixed_param instead */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_cmd_fixed_param */ - /** Set Hardware Mode **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_cmd_fixed_param + * Set Hardware Mode */ + A_UINT32 tlv_header; - /* Hardware Mode Index */ - A_UINT32 hw_mode_index; + /* Hardware Mode Index */ + A_UINT32 hw_mode_index; } wmi_soc_set_hw_mode_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param */ - /** Set Hardware Mode **/ + /* TLV tag and len tag equals WMITLV_TAG_STRUC_wmi_pdev_band_to_mac */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* start frequency in MHz */ + A_UINT32 start_freq; + /* end frequency in MHz */ + A_UINT32 end_freq; +} wmi_pdev_band_to_mac; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** Set Hardware Mode **/ - /* Hardware Mode Index */ - A_UINT32 hw_mode_index; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + + /* Hardware Mode Index */ + A_UINT32 hw_mode_index; + + /* Number of band to mac TLVs */ + A_UINT32 num_band_to_mac; + + /* Followed by TLVs of type + * num_band_to_mac * wmi_pdev_band_to_mac. + */ } wmi_pdev_set_hw_mode_cmd_fixed_param; -/* DEPRECATED - use wmi_pdev_set_dual_mac_config_cmd_fixed_param instead */ +/* DEPRECATED - use wmi_pdev_set_mac_config_cmd_fixed_param instead */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_cmd_fixed_param */ - /** Set Dual MAC Firmware Configuration **/ + /* + * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_cmd_fixed_param + * Set Dual MAC Firmware Configuration + */ + A_UINT32 tlv_header; - /* Concurrent scan configuration bits */ - A_UINT32 concurrent_scan_config_bits; - /* Firmware mode configuration bits */ - A_UINT32 fw_mode_config_bits; + /* Concurrent scan configuration bits */ + A_UINT32 concurrent_scan_config_bits; + /* Firmware mode configuration bits */ + A_UINT32 fw_mode_config_bits; } wmi_soc_set_dual_mac_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_cmd_fixed_param */ - /** Set Dual MAC Firmware Configuration **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** Set Dual MAC Firmware Configuration **/ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - /* Concurrent scan configuration bits */ - A_UINT32 concurrent_scan_config_bits; - /* Firmware mode configuration bits */ - A_UINT32 fw_mode_config_bits; + /* Concurrent scan configuration bits */ + A_UINT32 concurrent_scan_config_bits; + /* Firmware mode configuration bits */ + A_UINT32 fw_mode_config_bits; } wmi_pdev_set_mac_config_cmd_fixed_param; typedef struct { /* DEPRECATED */ - A_UINT32 num_tx_chains; - A_UINT32 num_rx_chains; - A_UINT32 reserved[2]; + A_UINT32 num_tx_chains; + A_UINT32 num_rx_chains; + A_UINT32 reserved[2]; } soc_num_tx_rx_chains; typedef struct { - A_UINT32 num_tx_chains_2g; - A_UINT32 num_rx_chains_2g; - A_UINT32 num_tx_chains_5g; - A_UINT32 num_rx_chains_5g; + A_UINT32 num_tx_chains_2g; + A_UINT32 num_rx_chains_2g; + A_UINT32 num_tx_chains_5g; + A_UINT32 num_rx_chains_5g; } band_num_tx_rx_chains; -typedef union { /* DEPRECATED */ - soc_num_tx_rx_chains soc_txrx_chain_setting; - band_num_tx_rx_chains band_txrx_chain_setting; +typedef union { + soc_num_tx_rx_chains soc_txrx_chain_setting; + band_num_tx_rx_chains band_txrx_chain_setting; } antenna_num_tx_rx_chains; typedef enum { - ANTENNA_MODE_DISABLED = 0x0, - ANTENNA_MODE_LOW_POWER_LOCATION_SCAN = 0x01, - /* reserved */ + ANTENNA_MODE_DISABLED = 0x0, + ANTENNA_MODE_LOW_POWER_LOCATION_SCAN = 0x01, + /* reserved */ } antenna_mode_reason; /* DEPRECATED - use wmi_pdev_set_antenna_mode_cmd_fixed_param instead */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_antenna_mode_cmd_fixed_param */ + /* + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_soc_set_antenna_mode_cmd_fixed_param + */ + A_UINT32 tlv_header; - /* the reason for setting antenna mode, refer antenna_mode_reason */ - A_UINT32 reason; + /* the reason for setting antenna mode, refer antenna_mode_reason */ + A_UINT32 reason; - /* - * The above reason parameter will select whether the following union - * is soc_num_tx_rx_chains or band_num_tx_rx_chains. - */ - antenna_num_tx_rx_chains num_txrx_chains_setting; + /* + * The above reason parameter will select whether the following union + * is soc_num_tx_rx_chains or band_num_tx_rx_chains. + */ + antenna_num_tx_rx_chains num_txrx_chains_setting; } wmi_soc_set_antenna_mode_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_antenna_mode_cmd_fixed_param */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_antenna_mode_cmd_fixed_param + */ + A_UINT32 tlv_header; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - /* Bits 0-15 is the number of RX chains and 16-31 is the number of TX chains */ - A_UINT32 num_txrx_chains; + /* Bits 0-15 is the number of RX chains and + * 16-31 is the number of TX chains + */ + A_UINT32 num_txrx_chains; } wmi_pdev_set_antenna_mode_cmd_fixed_param; /** Data structure for information specific to a VDEV to MAC mapping. */ /* DEPRECATED - use wmi_pdev_set_hw_mode_response_vdev_mac_entry instead */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_vdev_mac_entry */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* VDEV ID */ - A_UINT32 mac_id; /* MAC ID */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_vdev_mac_entry */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; /* VDEV ID */ + A_UINT32 mac_id; /* MAC ID */ } wmi_soc_set_hw_mode_response_vdev_mac_entry; /** Data structure for information specific to a VDEV to MAC mapping. */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_vdev_mac_entry */ - A_UINT32 tlv_header; + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_vdev_mac_entry */ + A_UINT32 tlv_header; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - A_UINT32 vdev_id; + A_UINT32 vdev_id; } wmi_pdev_set_hw_mode_response_vdev_mac_entry; /* DEPRECATED - use wmi_pdev_set_hw_mode_response_event_fixed_param instead */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_event_fixed_param */ - /** Set Hardware Mode Response Event **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_soc_set_hw_mode_response_event_fixed_param + * Set Hardware Mode Response Event **/ + A_UINT32 tlv_header; - /* Status of set_hw_mode command */ - /* - * Values for Status: - * 0 - OK; command successful - * 1 - EINVAL; Requested invalid hw_mode - * 2 - ECANCELED; HW mode change canceled - * 3 - ENOTSUP; HW mode not supported - * 4 - EHARDWARE; HW mode change prevented by hardware - * 5 - EPENDING; HW mode change is pending - * 6 - ECOEX; HW mode change conflict with Coex - */ - A_UINT32 status; - /* Configured Hardware Mode */ - A_UINT32 cfgd_hw_mode_index; - /* Number of Vdev to Mac entries */ - A_UINT32 num_vdev_mac_entries; - -/** - * TLV (tag length value) parameters follow the soc_set_hw_mode_response_event - * structure. The TLV's are: - * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; - */ + /* Status of set_hw_mode command + * Values for Status: + * 0 - OK; command successful + * 1 - EINVAL; Requested invalid hw_mode + * 2 - ECANCELED; HW mode change canceled + * 3 - ENOTSUP; HW mode not supported + * 4 - EHARDWARE; HW mode change prevented by hardware + * 5 - EPENDING; HW mode change is pending + * 6 - ECOEX; HW mode change conflict with Coex + */ + A_UINT32 status; + /* Configured Hardware Mode */ + A_UINT32 cfgd_hw_mode_index; + /* Number of Vdev to Mac entries */ + A_UINT32 num_vdev_mac_entries; + /* + * TLV (tag length value ) parameters follow the soc_set_hw_mode_response_event + * structure. The TLV's are: + * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; + */ } wmi_soc_set_hw_mode_response_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_event_fixed_param */ - /** Set Hardware Mode Response Event **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_hw_mode_response_event_fixed_param + */ + A_UINT32 tlv_header; + /** Set Hardware Mode Response Event **/ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - /* Status of set_hw_mode command */ - /* - * Values for Status: - * 0 - OK; command successful - * 1 - EINVAL; Requested invalid hw_mode - * 2 - ECANCELED; HW mode change canceled - * 3 - ENOTSUP; HW mode not supported - * 4 - EHARDWARE; HW mode change prevented by hardware - * 5 - EPENDING; HW mode change is pending - * 6 - ECOEX; HW mode change conflict with Coex - */ - A_UINT32 status; - /* Configured Hardware Mode */ - A_UINT32 cfgd_hw_mode_index; - /* Number of Vdev to Mac entries */ - A_UINT32 num_vdev_mac_entries; -/** - * TLV (tag length value) parameters follow the soc_set_hw_mode_response_event - * structure. The TLV's are: - * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; - */ + /* Status of set_hw_mode command */ + /* + * Values for Status: + * 0 - OK; command successful + * 1 - EINVAL; Requested invalid hw_mode + * 2 - ECANCELED; HW mode change canceled + * 3 - ENOTSUP; HW mode not supported + * 4 - EHARDWARE; HW mode change prevented by hardware + * 5 - EPENDING; HW mode change is pending + * 6 - ECOEX; HW mode change conflict with Coex + */ + A_UINT32 status; + /* Configured Hardware Mode */ + A_UINT32 cfgd_hw_mode_index; + /* Number of Vdev to Mac entries */ + A_UINT32 num_vdev_mac_entries; + /** + * TLV (tag length value ) parameters follow the + * soc_set_hw_mode_response_event structure. The TLV's are: + * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; + */ } wmi_pdev_set_hw_mode_response_event_fixed_param; /* DEPRECATED - use wmi_pdev_hw_mode_transition_event_fixed_param instead */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_hw_mode_transition_event_fixed_param */ - /** Hardware Mode Transition Event **/ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_soc_hw_mode_transition_event_fixed_param + * Hardware Mode Transition Event + */ + A_UINT32 tlv_header; + /* Original or old Hardware mode */ + A_UINT32 old_hw_mode_index; + /* New Hardware Mode */ + A_UINT32 new_hw_mode_index; + /* Number of Vdev to Mac entries */ + A_UINT32 num_vdev_mac_entries; - /* Original or old Hardware mode */ - A_UINT32 old_hw_mode_index; - /* New Hardware Mode */ - A_UINT32 new_hw_mode_index; - /* Number of Vdev to Mac entries */ - A_UINT32 num_vdev_mac_entries; - -/** - * TLV (tag length value) parameters follow the soc_set_hw_mode_response_event - * structure. The TLV's are: - * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; - */ + /** + * TLV (tag length value ) parameters follow the soc_set_hw_mode_response_event + * structure. The TLV's are: + * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; + */ } wmi_soc_hw_mode_transition_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_hw_mode_transition_event_fixed_param */ - /** Hardware Mode Transition Event **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_hw_mode_transition_event_fixed_param + */ + A_UINT32 tlv_header; + /** Hardware Mode Transition Event **/ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - /* Original or old Hardware mode */ - A_UINT32 old_hw_mode_index; - /* New Hardware Mode */ - A_UINT32 new_hw_mode_index; - /* Number of Vdev to Mac entries */ - A_UINT32 num_vdev_mac_entries; + /* Original or old Hardware mode */ + A_UINT32 old_hw_mode_index; + /* New Hardware Mode */ + A_UINT32 new_hw_mode_index; + /* Number of Vdev to Mac entries */ + A_UINT32 num_vdev_mac_entries; -/** - * TLV (tag length value) parameters follow the soc_set_hw_mode_response_event - * structure. The TLV's are: - * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; - */ + /** + * TLV (tag length value ) parameters follow the + * soc_set_hw_mode_response_event structure. The TLV's are: + * A_UINT32 wmi_soc_set_hw_mode_response_vdev_mac_entry[]; + */ } wmi_pdev_hw_mode_transition_event_fixed_param; /** @@ -14473,24 +15853,33 @@ typedef struct { * plugging in reorder queue desc to lithium hw. * * Example: plug-in queue desc for TID 5 - * host->target: WMI_PEER_REORDER_QUEUE_SETUP_CMDID, - * (vdev_id = PEER vdev id, - * peer_macaddr = PEER mac addr, - * tid = 5, - * queue_ptr_lo = queue desc addr lower 32 bits, - * queue_ptr_hi = queue desc addr higher 32 bits, - * queue_no = 16-bit number assigned by host for queue, + * host->target: WMI_PEER_REORDER_QUEUE_SETUP_CMDID, + * (vdev_id = PEER vdev id, + * peer_macaddr = PEER mac addr, + * tid = 5, + * queue_ptr_lo = queue desc addr lower 32 bits, + * queue_ptr_hi = queue desc addr higher 32 bits, + * queue_no = 16-bit number assigned by host for queue, * stored in bits 15:0 of queue_no field) */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_reorder_queue_setup_cmd_fixed_param */ - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; /* peer mac address */ - A_UINT32 tid; /* 0 to 15 = QoS TIDs, 16 = non-qos TID */ - A_UINT32 queue_ptr_lo; /* lower 32 bits of queue desc adddress */ - A_UINT32 queue_ptr_hi; /* upper 32 bits of queue desc adddress */ - A_UINT32 queue_no; /* 16-bit number assigned by host for queue, - stored in bits 15:0 of queue_no field */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_reorder_queue_setup_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* peer mac address */ + wmi_mac_addr peer_macaddr; + /* 0 to 15 = QoS TIDs, 16 = non-qos TID */ + A_UINT32 tid; + /* lower 32 bits of queue desc adddress */ + A_UINT32 queue_ptr_lo; + /* upper 32 bits of queue desc adddress */ + A_UINT32 queue_ptr_hi; + /* 16-bit number assigned by host for queue, + * stored in bits 15:0 of queue_no field + */ + A_UINT32 queue_no; } wmi_peer_reorder_queue_setup_cmd_fixed_param; /** @@ -14498,564 +15887,626 @@ typedef struct { * removing one or more reorder queue desc to lithium hw. * * Example: remove queue desc for all TIDs - * host->target: WMI_PEER_REORDER_REMOVE_CMDID, - * (vdev_id = PEER vdev id, - * peer_macaddr = PEER mac addr, - * tid = 0x1FFFF, + * host->target: WMI_PEER_REORDER_REMOVE_CMDID, + * (vdev_id = PEER vdev id, + * peer_macaddr = PEER mac addr, + * tid = 0x1FFFF, */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param */ - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; /* peer mac address */ - A_UINT32 tid_mask; /* bits 0 to 15 = QoS TIDs, bit 16 = non-qos TID */ + /* TLV tag and len; + * tag equals + * WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* peer mac address */ + wmi_mac_addr peer_macaddr; + /* bits 0 to 15 = QoS TIDs, bit 16 = non-qos TID */ + A_UINT32 tid_mask; } wmi_peer_reorder_queue_remove_cmd_fixed_param; -/* DEPRECATED - use wmi_pdev_set_mac_config_response_event_fixed_param instead */ +/* DEPRECATED - use wmi_pdev_set_mac_config_response_event_fixed_param + * instead + */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_response_event_fixed_param */ - /** Set Dual MAC Config Response Event **/ - - /* Status for set_dual_mac_config command */ - /* - * Values for Status: - * 0 - OK; command successful - * 1 - EINVAL; Requested invalid hw_mode - * 3 - ENOTSUP; HW mode not supported - * 4 - EHARDWARE; HW mode change prevented by hardware - * 6 - ECOEX; HW mode change conflict with Coex - */ - A_UINT32 status; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_soc_set_dual_mac_config_response_event_fixed_param + * Set Dual MAC Config Response Event + */ + A_UINT32 tlv_header; + /* Status for set_dual_mac_config command */ + /* + * Values for Status: + * 0 - OK; command successful + * 1 - EINVAL; Requested invalid hw_mode + * 3 - ENOTSUP; HW mode not supported + * 4 - EHARDWARE; HW mode change prevented by hardware + * 6 - ECOEX; HW mode change conflict with Coex + */ + A_UINT32 status; } wmi_soc_set_dual_mac_config_response_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_response_event_fixed_param */ - /** Set Dual MAC Config Response Event **/ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_mac_config_response_event_fixed_param + */ + A_UINT32 tlv_header; + /** Set Dual MAC Config Response Event **/ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; - /* Status for set_dual_mac_config command */ - /* - * Values for Status: - * 0 - OK; command successful - * 1 - EINVAL; Requested invalid hw_mode - * 3 - ENOTSUP; HW mode not supported - * 4 - EHARDWARE; HW mode change prevented by hardware - * 6 - ECOEX; HW mode change conflict with Coex - */ - A_UINT32 status; + /* Status for set_dual_mac_config command */ + /* + * Values for Status: + * 0 - OK; command successful + * 1 - EINVAL; Requested invalid hw_mode + * 3 - ENOTSUP; HW mode not supported + * 4 - EHARDWARE; HW mode change prevented by hardware + * 6 - ECOEX; HW mode change conflict with Coex + */ + A_UINT32 status; } wmi_pdev_set_mac_config_response_event_fixed_param; typedef enum { - MAWC_MOTION_STATE_UNKNOWN, - MAWC_MOTION_STATE_STATIONARY, - MAWC_MOTION_STATE_WALK, - MAWC_MOTION_STATE_TRANSIT, + MAWC_MOTION_STATE_UNKNOWN, + MAWC_MOTION_STATE_STATIONARY, + MAWC_MOTION_STATE_WALK, + MAWC_MOTION_STATE_TRANSIT, } MAWC_MOTION_STATE; typedef enum { - MAWC_SENSOR_STATUS_OK, - MAWC_SENSOR_STATUS_FAILED_TO_ENABLE, - MAWC_SENSOR_STATUS_SHUTDOWN, + MAWC_SENSOR_STATUS_OK, + MAWC_SENSOR_STATUS_FAILED_TO_ENABLE, + MAWC_SENSOR_STATUS_SHUTDOWN, } MAWC_SENSOR_STATUS; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mawc_sensor_report_ind_cmd_fixed_param */ - A_UINT32 tlv_header; - /** new motion state, MAWC_MOTION_STATE */ - A_UINT32 motion_state; - /** status code of sensor, MAWC_SENSOR_STATUS */ - A_UINT32 sensor_status; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mawc_sensor_report_ind_cmd_fixed_param */ + A_UINT32 tlv_header; + /** new motion state, MAWC_MOTION_STATE */ + A_UINT32 motion_state; + /** status code of sensor, MAWC_SENSOR_STATUS */ + A_UINT32 sensor_status; } wmi_mawc_sensor_report_ind_cmd_fixed_param; /* MBO flag field definition */ -/* Bit 0: 0 - Allow to connect to both MBO and non-MBO AP +/* + * Bit 0: 0 - Allow to connect to both MBO and non-MBO AP * 1 - Allow to connect to MBO AP only * Bit 1-31 : reserved. */ #define WMI_ROAM_MBO_FLAG_MBO_ONLY_MODE (1<<0) /* DEPRECATED */ typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_roam_set_mbo_fixed_param */ - A_UINT32 tlv_header; - /** vdev id */ - A_UINT32 vdev_id; - /** enable or disable MBO */ - A_UINT32 enable; - /** MBO flags, refer to definition of MBO flags*/ - A_UINT32 flags; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_roam_set_mbo_fixed_param + */ + A_UINT32 tlv_header; + /** vdev id */ + A_UINT32 vdev_id; + /** enable or disable MBO */ + A_UINT32 enable; + /** MBO flags, refer to definition of MBO flags*/ + A_UINT32 flags; } wmi_roam_set_mbo_fixed_param; /* DEPRECATED */ typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_ARRAY_STRUC */ - A_UINT32 tlv_header; - /** Current operating class number */ - A_UINT32 cur_op_class; - /** Country string of current reg domain, - * the expected value should be same as country str defined - * in country IE. - * 3 octets (COUNTRY_STR) + 1 octet (always 0) - * The ordering of this array must be maintained, - * even when a big-endian host's WMI messages undergo - * automatic byte reordering for conversion to the - * little-endian ordering required by the target. - * On big-endian hosts, this array may need to be byte-swapped - * by the host, so the subsequent automatic byte-swap - * will result in the correct final byte order. - * global operating class: set country_str[0]=0 - */ - A_UINT8 country_str[4]; - /** Supported operating class number in current regdomain */ - A_UINT32 supp_op_class_num; - /* The TLVs will follow. */ - /* A_UINT32 supp_op_class_list[] */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_ARRAY_STRUC + */ + A_UINT32 tlv_header; + /** Current operating class number */ + A_UINT32 cur_op_class; + /* + * Country string of current reg domain, + * the expected value should be same as country str defined + * in country IE. + * 3 octets (COUNTRY_STR) + 1 octet (always 0) + * The ordering of this array must be maintained, + * even when a big-endian host's WMI messages undergo + * automatic byte reordering for conversion to the + * little-endian ordering required by the target. + * On big-endian hosts, this array may need to be byte-swapped + * by the host, so the subsequent automatic byte-swap + * will result in the correct final byte order. + * global operating class: set country_str[0]=0 + */ + A_UINT8 country_str[4]; + /** Supported operating class number in current regdomain */ + A_UINT32 supp_op_class_num; + /* The TLVs will follow. */ + /* A_UINT32 supp_op_class_list[] */ } wmi_supported_operating_class_param; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_ARRAY_STRUC */ - A_UINT32 tlv_header; - /** non preferred channel attribute length */ - A_UINT32 non_prefer_ch_attr_len; - /* The TLVs will follow. */ - /** A_UINT8 non_prefer_ch_attr[];*/ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_ARRAY_STRUC + */ + A_UINT32 tlv_header; + /** non preferred channel attribute length */ + A_UINT32 non_prefer_ch_attr_len; + /* The TLVs will follow. */ + /** A_UINT8 non_prefer_ch_attr[];*/ } wmi_mbo_non_preferred_channel_report_param; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_mawc_enable_sensor_event_fixed_param */ - A_UINT32 tlv_header; - /* enable(1) or disable(0) */ - A_UINT32 enable; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_mawc_enable_sensor_event_fixed_param */ + A_UINT32 tlv_header; + /* enable(1) or disable(0) */ + A_UINT32 enable; } wmi_mawc_enable_sensor_event_fixed_param; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_extscan_configure_mawc_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /* enable(1) or disable(0) MAWC */ - A_UINT32 enable; - /* ratio of skipping suppressing scan, skip one out of x */ - A_UINT32 suppress_ratio; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_extscan_configure_mawc_cmd_fixed_param */ + A_UINT32 tlv_header; + /* Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /* enable(1) or disable(0) MAWC */ + A_UINT32 enable; + /* ratio of skipping suppressing scan, skip one out of x */ + A_UINT32 suppress_ratio; } wmi_extscan_configure_mawc_cmd_fixed_param; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_nlo_configure_mawc_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /* enable(1) or disable(0) MAWC */ - A_UINT32 enable; - /* ratio of exponential backoff, next = current + current*ratio/100 */ - A_UINT32 exp_backoff_ratio; - /* initial scan interval(msec) */ - A_UINT32 init_scan_interval; - /* max scan interval(msec) */ - A_UINT32 max_scan_interval; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_nlo_configure_mawc_cmd_fixed_param */ + A_UINT32 tlv_header; + /* Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /* enable(1) or disable(0) MAWC */ + A_UINT32 enable; + /* ratio of exponential backoff, next = current + current*ratio/100 */ + A_UINT32 exp_backoff_ratio; + /* initial scan interval(msec) */ + A_UINT32 init_scan_interval; + /* max scan interval(msec) */ + A_UINT32 max_scan_interval; } wmi_nlo_configure_mawc_cmd_fixed_param; typedef struct { - /* TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_roam_configure_mawc_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /* enable(1) or disable(0) MAWC */ - A_UINT32 enable; - /* data traffic load (kBps) to register CMC */ - A_UINT32 traffic_load_threshold; - /* RSSI threshold (dBm) to scan for Best AP */ - A_UINT32 best_ap_rssi_threshold; - /* high RSSI threshold adjustment in Stationary to suppress scan */ - A_UINT32 rssi_stationary_high_adjust; - /* low RSSI threshold adjustment in Stationary to suppress scan */ - A_UINT32 rssi_stationary_low_adjust; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_roam_configure_mawc_cmd_fixed_param */ + A_UINT32 tlv_header; + /* Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /* enable(1) or disable(0) MAWC */ + A_UINT32 enable; + /* data traffic load (kBps) to register CMC */ + A_UINT32 traffic_load_threshold; + /* RSSI threshold (dBm) to scan for Best AP */ + A_UINT32 best_ap_rssi_threshold; + /* high RSSI threshold adjustment in Stationary to suppress scan */ + A_UINT32 rssi_stationary_high_adjust; + /* low RSSI threshold adjustment in Stationary to suppress scan */ + A_UINT32 rssi_stationary_low_adjust; } wmi_roam_configure_mawc_cmd_fixed_param; #define WMI_PACKET_FILTER_COMPARE_DATA_LEN_DWORD 2 #define WMI_PACKET_FILTER_MAX_CMP_PER_PACKET_FILTER 5 typedef enum { - PACKET_FILTER_TYPE_INVALID = 0, - PACKET_FILTER_TYPE_FILTER_PKT, - PACKET_FILTER_TYPE_RESERVE_PKT, /* not used */ - PACKET_FILTER_TYPE_MAX_ENUM_SIZE + PACKET_FILTER_TYPE_INVALID = 0, + PACKET_FILTER_TYPE_FILTER_PKT, + PACKET_FILTER_TYPE_RESERVE_PKT, /* not used */ + PACKET_FILTER_TYPE_MAX_ENUM_SIZE } WMI_PACKET_FILTER_FILTER_TYPE; typedef enum { - PACKET_FILTER_PROTO_TYPE_INVALID = 0, + PACKET_FILTER_PROTO_TYPE_INVALID = 0, - /* L2 header */ - PACKET_FILTER_PROTO_TYPE_MAC, - PACKET_FILTER_PROTO_TYPE_SNAP, + /* L2 header */ + PACKET_FILTER_PROTO_TYPE_MAC, + PACKET_FILTER_PROTO_TYPE_SNAP, - /* L3 header (EtherType) */ - PACKET_FILTER_PROTO_TYPE_IPV4, - PACKET_FILTER_PROTO_TYPE_IPV6, + /* L3 header (EtherType) */ + PACKET_FILTER_PROTO_TYPE_IPV4, + PACKET_FILTER_PROTO_TYPE_IPV6, - /* L4 header (IP protocol) */ - PACKET_FILTER_PROTO_TYPE_UDP, - PACKET_FILTER_PROTO_TYPE_TCP, - PACKET_FILTER_PROTO_TYPE_ICMPV6, + /* L4 header (IP protocol) */ + PACKET_FILTER_PROTO_TYPE_UDP, + PACKET_FILTER_PROTO_TYPE_TCP, + PACKET_FILTER_PROTO_TYPE_ICMPV6, - PACKET_FILTER_PROTO_TYPE_MAX + PACKET_FILTER_PROTO_TYPE_MAX } WMI_PACKET_FILTER_PROTO_TYPE; typedef enum { - PACKET_FILTER_CMP_TYPE_INVALID = 0, - PACKET_FILTER_CMP_TYPE_EQUAL, - PACKET_FILTER_CMP_TYPE_MASK_EQUAL, - PACKET_FILTER_CMP_TYPE_NOT_EQUAL, - PACKET_FILTER_CMP_TYPE_MASK_NOT_EQUAL, - PACKET_FILTER_CMP_TYPE_ADDRTYPE, - PACKET_FILTER_CMP_TYPE_MAX + PACKET_FILTER_CMP_TYPE_INVALID = 0, + PACKET_FILTER_CMP_TYPE_EQUAL, + PACKET_FILTER_CMP_TYPE_MASK_EQUAL, + PACKET_FILTER_CMP_TYPE_NOT_EQUAL, + PACKET_FILTER_CMP_TYPE_MASK_NOT_EQUAL, + PACKET_FILTER_CMP_TYPE_ADDRTYPE, + PACKET_FILTER_CMP_TYPE_MAX } WMI_PACKET_FILTER_CMP_TYPE; typedef enum { - PACKET_FILTER_SET_INACTIVE = 0, - PACKET_FILTER_SET_ACTIVE + PACKET_FILTER_SET_INACTIVE = 0, + PACKET_FILTER_SET_ACTIVE } WMI_PACKET_FILTER_ACTION; typedef enum { - PACKET_FILTER_SET_DISABLE = 0, - PACKET_FILTER_SET_ENABLE + PACKET_FILTER_SET_DISABLE = 0, + PACKET_FILTER_SET_ENABLE } WMI_PACKET_FILTER_RUNTIME_ENABLE; typedef struct { - A_UINT32 proto_type; - A_UINT32 cmp_type; - A_UINT32 data_length; /* Length of the data to compare (units = bytes) */ - A_UINT32 data_offset; /* from start of the respective frame header (units = bytes) */ - A_UINT32 compareData[WMI_PACKET_FILTER_COMPARE_DATA_LEN_DWORD]; /* Data to compare, little-endian order */ - A_UINT32 dataMask[WMI_PACKET_FILTER_COMPARE_DATA_LEN_DWORD]; /* Mask to be applied on rcvd packet data before compare, little-endian order */ + A_UINT32 proto_type; + A_UINT32 cmp_type; + A_UINT32 data_length; /* Length of the data to compare (units = bytes) */ + /* + * from start of the respective frame header ( + * units = bytes) + */ + A_UINT32 data_offset; + /* Data to compare, little-endian order */ + A_UINT32 compareData[WMI_PACKET_FILTER_COMPARE_DATA_LEN_DWORD]; + /* Mask to be applied on rcvd packet data before compare, little-endian order */ + A_UINT32 dataMask[WMI_PACKET_FILTER_COMPARE_DATA_LEN_DWORD]; } WMI_PACKET_FILTER_PARAMS_TYPE; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 filter_id; - A_UINT32 filter_action; /* WMI_PACKET_FILTER_ACTION */ - A_UINT32 filter_type; - A_UINT32 num_params; /* how many entries in paramsData are valid */ - A_UINT32 coalesce_time; /* not currently used - fill with 0x0 */ - WMI_PACKET_FILTER_PARAMS_TYPE paramsData[WMI_PACKET_FILTER_MAX_CMP_PER_PACKET_FILTER]; - /* deprecated0: - * This field simply provides filler space to retain the original message - * format while reducing WMI_PACKET_FILTER_MAX_CMP_PER_PACKET_FILTER - * from 10 to 5. - */ - WMI_PACKET_FILTER_PARAMS_TYPE deprecated0[5]; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 filter_id; + A_UINT32 filter_action; /* WMI_PACKET_FILTER_ACTION */ + A_UINT32 filter_type; + A_UINT32 num_params; /* how many entries in paramsData are valid */ + A_UINT32 coalesce_time; /* not currently used - fill with 0x0 */ + WMI_PACKET_FILTER_PARAMS_TYPE paramsData[WMI_PACKET_FILTER_MAX_CMP_PER_PACKET_FILTER]; + /* + * deprecated0: + * This field simply provides filler space to retain the + * original message format while reducing + * WMI_PACKET_FILTER_MAX_CMP_PER_PACKET_FILTER from 10 to 5. + */ + WMI_PACKET_FILTER_PARAMS_TYPE deprecated0[5]; } WMI_PACKET_FILTER_CONFIG_CMD_fixed_param; /* enable / disable all filters within the specified vdev */ typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 enable; /* WMI_PACKET_FILTER_RUNTIME_ENABLE */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 enable; /* WMI_PACKET_FILTER_RUNTIME_ENABLE */ } WMI_PACKET_FILTER_ENABLE_CMD_fixed_param; + #define WMI_LRO_INFO_TCP_FLAG_VALS_BITPOS 0 #define WMI_LRO_INFO_TCP_FLAG_VALS_NUMBITS 9 #define WMI_LRO_INFO_TCP_FLAG_VALS_SET(tcp_flag_u32, tcp_flag_values) \ - WMI_SET_BITS(tcp_flag_u32, \ - WMI_LRO_INFO_TCP_FLAG_VALS_BITPOS, \ - WMI_LRO_INFO_TCP_FLAG_VALS_NUMBITS, \ - tcp_flag_values) + WMI_SET_BITS(tcp_flag_u32, \ + WMI_LRO_INFO_TCP_FLAG_VALS_BITPOS, \ + WMI_LRO_INFO_TCP_FLAG_VALS_NUMBITS, \ + tcp_flag_values) #define WMI_LRO_INFO_TCP_FLAG_VALS_GET(tcp_flag_u32) \ - WMI_GET_BITS(tcp_flag_u32, \ - WMI_LRO_INFO_TCP_FLAG_VALS_BITPOS, \ - WMI_LRO_INFO_TCP_FLAG_VALS_NUMBITS) + WMI_GET_BITS(tcp_flag_u32, \ + WMI_LRO_INFO_TCP_FLAG_VALS_BITPOS, \ + WMI_LRO_INFO_TCP_FLAG_VALS_NUMBITS) #define WMI_LRO_INFO_TCP_FLAGS_MASK_BITPOS 9 #define WMI_LRO_INFO_TCP_FLAGS_MASK_NUMBITS 9 #define WMI_LRO_INFO_TCP_FLAGS_MASK_SET(tcp_flag_u32, tcp_flags_mask) \ - WMI_SET_BITS(tcp_flag_u32, \ - WMI_LRO_INFO_TCP_FLAGS_MASK_BITPOS, \ - WMI_LRO_INFO_TCP_FLAGS_MASK_NUMBITS, \ - tcp_flags_mask) + WMI_SET_BITS(tcp_flag_u32, \ + WMI_LRO_INFO_TCP_FLAGS_MASK_BITPOS, \ + WMI_LRO_INFO_TCP_FLAGS_MASK_NUMBITS, \ + tcp_flags_mask) #define WMI_LRO_INFO_TCP_FLAGS_MASK_GET(tcp_flag_u32) \ - WMI_GET_BITS(tcp_flag_u32, \ - WMI_LRO_INFO_TCP_FLAGS_MASK_BITPOS, \ - WMI_LRO_INFO_TCP_FLAGS_MASK_NUMBITS) + WMI_GET_BITS(tcp_flag_u32, \ + WMI_LRO_INFO_TCP_FLAGS_MASK_BITPOS, \ + WMI_LRO_INFO_TCP_FLAGS_MASK_NUMBITS) typedef struct { - A_UINT32 tlv_header; - /** - * @brief lro_enable - indicates whether lro is enabled - * [0] LRO Enable - */ - A_UINT32 lro_enable; - /** - * @brief tcp_flag_u32 - mask of which TCP flags to check and - * values to check for - * [8:0] TCP flag values - If the TCP flags from the packet do not match - * the values in this field after masking with TCP flags mask below, - * LRO eligible will not be set - * [17:9] TCP flags mask - Mask field for comparing the TCP values - * provided above with the TCP flags field in the received packet - * Use WMI_LRO_INFO_TCP_FLAG_VALS and WMI_LRO_INFO_TCP_FLAGS_MASK - * macros to isolate the mask field and values field that are packed - * into this u32 "word". - */ - A_UINT32 tcp_flag_u32; - /** - * @brief toeplitz_hash_ipv4 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains - * bytes 0 to 3 - * - * In this and all the below toeplitz_hash fields, the bytes are - * specified in little-endian order. For example: - * toeplitz_hash_ipv4_0_3 bits 7:0 holds seed byte 0 - * toeplitz_hash_ipv4_0_3 bits 15:8 holds seed byte 1 - * toeplitz_hash_ipv4_0_3 bits 23:16 holds seed byte 2 - * toeplitz_hash_ipv4_0_3 bits 31:24 holds seed byte 3 - */ - A_UINT32 toeplitz_hash_ipv4_0_3; + A_UINT32 tlv_header; + /** + * @brief lro_enable - indicates whether lro is enabled + * [0] LRO Enable + */ + A_UINT32 lro_enable; + /** + * @brief tcp_flag_u32 - mask of which TCP flags to check and + * values to check for + * [8:0] TCP flag values - If the TCP flags from the packet do not match + * the values in this field after masking with TCP flags mask + * below,LRO eligible will not be set + * [17:9] TCP flags mask - Mask field for comparing the TCP values + * provided above with the TCP flags field in the received packet + * Use WMI_LRO_INFO_TCP_FLAG_VALS and WMI_LRO_INFO_TCP_FLAGS_MASK + * macros to isolate the mask field and values field that are packed + * into this u32 "word". + */ + A_UINT32 tcp_flag_u32; + /** + * @brief toeplitz_hash_ipv4 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains + * bytes 0 to 3 + * + * In this and all the below toeplitz_hash fields, the bytes are + * specified in little-endian order. For example: + * toeplitz_hash_ipv4_0_3 bits 7:0 holds seed byte 0 + * toeplitz_hash_ipv4_0_3 bits 15:8 holds seed byte 1 + * toeplitz_hash_ipv4_0_3 bits 23:16 holds seed byte 2 + * toeplitz_hash_ipv4_0_3 bits 31:24 holds seed byte 3 + */ + A_UINT32 toeplitz_hash_ipv4_0_3; - /** - * @brief toeplitz_hash_ipv4 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains - * bytes 4 to 7 - */ - A_UINT32 toeplitz_hash_ipv4_4_7; + /** + * @brief toeplitz_hash_ipv4 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains + * bytes 4 to 7 + */ + A_UINT32 toeplitz_hash_ipv4_4_7; - /** - * @brief toeplitz_hash_ipv4 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains - * bytes 8 to 11 - */ - A_UINT32 toeplitz_hash_ipv4_8_11; + /** + * @brief toeplitz_hash_ipv4 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains + * bytes 8 to 11 + */ + A_UINT32 toeplitz_hash_ipv4_8_11; - /** - * @brief toeplitz_hash_ipv4 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains - * bytes 12 to 15 - */ - A_UINT32 toeplitz_hash_ipv4_12_15; + /** + * @brief toeplitz_hash_ipv4 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains + * bytes 12 to 15 + */ + A_UINT32 toeplitz_hash_ipv4_12_15; - /** - * @brief toeplitz_hash_ipv4 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains - * byte 16 - */ - A_UINT32 toeplitz_hash_ipv4_16; + /** + * @brief toeplitz_hash_ipv4 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv4 packets. Contains + * byte 16 + */ + A_UINT32 toeplitz_hash_ipv4_16; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 0 to 3 - */ - A_UINT32 toeplitz_hash_ipv6_0_3; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 0 to 3 + */ + A_UINT32 toeplitz_hash_ipv6_0_3; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 4 to 7 - */ - A_UINT32 toeplitz_hash_ipv6_4_7; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 4 to 7 + */ + A_UINT32 toeplitz_hash_ipv6_4_7; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 8 to 11 - */ - A_UINT32 toeplitz_hash_ipv6_8_11; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 8 to 11 + */ + A_UINT32 toeplitz_hash_ipv6_8_11; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 12 to 15 - */ - A_UINT32 toeplitz_hash_ipv6_12_15; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 12 to 15 + */ + A_UINT32 toeplitz_hash_ipv6_12_15; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 16 to 19 - */ - A_UINT32 toeplitz_hash_ipv6_16_19; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 16 to 19 + */ + A_UINT32 toeplitz_hash_ipv6_16_19; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 20 to 22 - */ - A_UINT32 toeplitz_hash_ipv6_20_23; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 20 to 22 + */ + A_UINT32 toeplitz_hash_ipv6_20_23; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 24 to 27 - */ - A_UINT32 toeplitz_hash_ipv6_24_27; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 24 to 27 + */ + A_UINT32 toeplitz_hash_ipv6_24_27; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 28 to 31 - */ - A_UINT32 toeplitz_hash_ipv6_28_31; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 28 to 31 + */ + A_UINT32 toeplitz_hash_ipv6_28_31; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 32 to 35 - */ - A_UINT32 toeplitz_hash_ipv6_32_35; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 32 to 35 + */ + A_UINT32 toeplitz_hash_ipv6_32_35; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * bytes 36 to 39 - */ - A_UINT32 toeplitz_hash_ipv6_36_39; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * bytes 36 to 39 + */ + A_UINT32 toeplitz_hash_ipv6_36_39; - /** - * @brief toeplitz_hash_ipv6 - contains seed needed to compute - * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains - * byte 40 - */ - A_UINT32 toeplitz_hash_ipv6_40; + /** + * @brief toeplitz_hash_ipv6 - contains seed needed to compute + * the flow id 5-tuple toeplitz hash for IPv6 packets. Contains + * byte 40 + */ + A_UINT32 toeplitz_hash_ipv6_40; } wmi_lro_info_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param */ - A_UINT32 offset; /* flash offset to write, starting from 0 */ - A_UINT32 length; /* vaild data length in buffer, unit: byte */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* flash offset to write, starting from 0 */ + A_UINT32 offset; + /* vaild data length in buffer, unit: byte */ + A_UINT32 length; } wmi_transfer_data_to_flash_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_complete_event_fixed_param */ - /** Return status. 0 for success, non-zero otherwise */ - A_UINT32 status; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_transfer_data_to_flash_complete_event_fixed_param + */ + A_UINT32 tlv_header; + /* Return status. 0 for success, non-zero otherwise */ + A_UINT32 status; } wmi_transfer_data_to_flash_complete_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_read_data_from_flash_cmd_fixed_param */ - A_UINT32 offset; /* flash offset to read, starting from 0 */ - A_UINT32 length; /* data length to read, unit: byte */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_read_data_from_flash_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 offset; /* flash offset to read, starting from 0 */ + A_UINT32 length; /* data length to read, unit: byte */ } wmi_read_data_from_flash_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_read_data_from_flash_event_fixed_param */ - A_UINT32 status; /* Return status. 0 for success, non-zero otherwise */ - A_UINT32 offset; /* flash offset reading from, starting from 0 */ - A_UINT32 length; /* length of data being reported, unit: byte */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_read_data_from_flash_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 status; /* Return status. 0 for success, non-zero otherwise */ + A_UINT32 offset; /* flash offset reading from, starting from 0 */ + A_UINT32 length; /* length of data being reported, unit: byte */ } wmi_read_data_from_flash_event_fixed_param; typedef enum { - ENHANCED_MCAST_FILTER_DISABLED, - ENHANCED_MCAST_FILTER_ENABLED + ENHANCED_MCAST_FILTER_DISABLED, + ENHANCED_MCAST_FILTER_ENABLED } ENHANCED_MCAST_FILTER_CONFIG; /* * Command to enable/disable filtering of multicast IP with unicast mac */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_config_enhanced_mcast_filter_fixed_param */ - /* Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /* 1 = enable 0 = disable (see ENHANCED_MCAST_FILTER_CONFIG) */ - A_UINT32 enable; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_config_enhanced_mcast_filter_fixed_param + */ + A_UINT32 tlv_header; + /* Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /* 1 = enable 0 = disable (see ENHANCED_MCAST_FILTER_CONFIG) */ + A_UINT32 enable; } wmi_config_enhanced_mcast_filter_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_wisa_cmd_fixed_param */ - A_UINT32 tlv_header; - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /** WISA enable / disable mode */ - A_UINT32 wisa_mode; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_wisa_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* WISA enable / disable mode */ + A_UINT32 wisa_mode; } wmi_vdev_wisa_cmd_fixed_param; /* * This structure is used to report SMPS force mode set complete to host. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_complete_event_fixed_param */ - /* Unique id identifying the VDEV */ - A_UINT32 vdev_id; - /* Return status. 0 for success, non-zero otherwise */ - A_UINT32 status; + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_sta_smps_force_mode_complete_event_fixed_param + */ + A_UINT32 tlv_header; + /* Unique id identifying the VDEV */ + A_UINT32 vdev_id; + /* Return status. 0 for success, non-zero otherwise */ + A_UINT32 status; } wmi_sta_smps_force_mode_complete_event_fixed_param; /* * This structure is used to report SCPC calibrated data to host. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scpc_event_fixed_param */ - /** number of BDF patches. Each patch contains offset, length and data */ - A_UINT32 num_patch; -/* This TLV is followed by another TLV of array of bytes - * A_UINT8 data[]; - * This data array contains, for example - * patch1 offset(byte3~0), patch1 data length(byte7~4), patch1 data(byte11~8) - * patch2 offset(byte15~12), patch2 data length(byte19~16), patch2 data(byte47~20) - * - */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_scpc_event_fixed_param + */ + A_UINT32 tlv_header; + /* number of BDF patches. Each patch contains offset, length and data */ + A_UINT32 num_patch; + /* This TLV is followed by another TLV of array of bytes + * A_UINT8 data[]; + * This data array contains, for example + * patch1 offset(byte3~0), patch1 data length(byte7~4), + * patch1 data(byte11~8) + * patch2 offset(byte15~12), patch2 data length(byte19~16), + * patch2 data(byte47~20) + */ } wmi_scpc_event_fixed_param; /* bpf interface structure */ typedef struct wmi_bpf_get_capability_cmd_s { - A_UINT32 tlv_header; - A_UINT32 reserved; /* reserved for future use - must be filled with 0x0 */ + A_UINT32 tlv_header; + A_UINT32 reserved; /* reserved for future use - must be filled with 0x0 */ } wmi_bpf_get_capability_cmd_fixed_param; typedef struct wmi_bpf_capability_info_evt_s { - A_UINT32 tlv_header; - A_UINT32 bpf_version; /* fw's implement version */ - A_UINT32 max_bpf_filters; /* max filters that fw supports */ - A_UINT32 max_bytes_for_bpf_inst; /* the maximum bytes that can be used as bpf instructions */ + A_UINT32 tlv_header; + A_UINT32 bpf_version; /* fw's implement version */ + A_UINT32 max_bpf_filters; /* max filters that fw supports */ + A_UINT32 max_bytes_for_bpf_inst; /* the maximum bytes that can be used as bpf instructions */ } wmi_bpf_capability_info_evt_fixed_param; /* bit 0 of flags: report counters */ #define WMI_BPF_GET_VDEV_STATS_FLAG_CTR_S 0 #define WMI_BPF_GET_VDEV_STATS_FLAG_CTR_M 0x1 typedef struct wmi_bpf_get_vdev_stats_cmd_s { - A_UINT32 tlv_header; - A_UINT32 flags; - A_UINT32 vdev_id; + A_UINT32 tlv_header; + A_UINT32 flags; + A_UINT32 vdev_id; } wmi_bpf_get_vdev_stats_cmd_fixed_param; typedef struct wmi_bpf_vdev_stats_info_evt_s { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 num_filters; - A_UINT32 num_checked_pkts; - A_UINT32 num_dropped_pkts; -} wmi_bpf_vdev_stats_info_evt_fixed_param; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 num_filters; + A_UINT32 num_checked_pkts; + A_UINT32 num_dropped_pkts; + } wmi_bpf_vdev_stats_info_evt_fixed_param; typedef struct wmi_bpf_set_vdev_instructions_cmd_s { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 filter_id; - A_UINT32 bpf_version; /* host bpf version */ - A_UINT32 total_length; - A_UINT32 current_offset; - A_UINT32 current_length; -/* - * The TLV follows: - * A_UINT8 buf_inst[]; <-- Variable length buffer for the instuctions - */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 filter_id; + A_UINT32 bpf_version; /* host bpf version */ + A_UINT32 total_length; + A_UINT32 current_offset; + A_UINT32 current_length; + /* + * The TLV follows: + * A_UINT8 buf_inst[]; //Variable length buffer for the instuctions + */ } wmi_bpf_set_vdev_instructions_cmd_fixed_param; #define BPF_FILTER_ID_ALL 0xFFFFFFFF typedef struct wmi_bpf_del_vdev_instructions_cmd_s { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 filter_id; /* BPF_FILTER_ID_ALL means delete all */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 filter_id; /* BPF_FILTER_ID_ALL means delete all */ } wmi_bpf_del_vdev_instructions_cmd_fixed_param; #define AES_BLOCK_LEN 16 /* in bytes */ @@ -15069,564 +16520,758 @@ typedef struct wmi_bpf_del_vdev_instructions_cmd_s { /* WMI_PDEV_FIPS_CMDID */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_fips_cmd_fixed_param */ - - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - - A_UINT32 fips_cmd; /* FIPS_ENCRYPT or FIPS_DECRYPT */ - A_UINT32 mode; /* FIPS_ENGINE_AES_CTR or FIPS_ENGINE_AES_MIC */ - A_UINT32 key_len; /* FIPS_KEY_LENGTH_128 or FIPS_KEY_LENGTH_256 (units = bytes) */ - A_UINT8 key[WMI_MAX_KEY_LEN]; /* Key */ - A_UINT32 data_len; /* data length */ -/* - * Following this structure is the TLV: - * A_UINT32 data[1]; <-- In Data (keep this in the end) - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_fips_cmd_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + A_UINT32 fips_cmd; /* FIPS_ENCRYPT or FIPS_DECRYPT */ + /* FIPS_ENGINE_AES_CTR or FIPS_ENGINE_AES_MIC */ + A_UINT32 mode; + /* FIPS_KEY_LENGTH_128 or FIPS_KEY_LENGTH_256 (units = bytes) */ + A_UINT32 key_len; + A_UINT8 key[WMI_MAX_KEY_LEN]; /* Key */ + A_UINT32 data_len; /* data length */ + /* + * Following this structure is the TLV: + * A_UINT32 data[1]; - In Data (keep this in the end) + */ } wmi_pdev_fips_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 enable; /* 1:enable, 0:disable */ - A_UINT32 mode; /* 1:GPIO parallel mode, 0:GPIO serial mode */ - A_UINT32 rx_antenna; /* rx antenna */ - A_UINT32 tx_default_antenna; /* tx default antenna */ - /* - * Following this structure is the TLV: - * wmi_pdev_smart_ant_gpio_handle - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + A_UINT32 enable; /* 1:enable, 0:disable */ + /* 1:GPIO parallel mode, 0:GPIO serial mode */ + A_UINT32 mode; + A_UINT32 rx_antenna; /* rx antenna */ + A_UINT32 tx_default_antenna; /* tx default antenna */ + /* + * Following this structure is the TLV: + * wmi_pdev_smart_ant_gpio_handle + */ } wmi_pdev_smart_ant_enable_cmd_fixed_param; /** GPIO pins/function values to control antennas */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle */ - A_UINT32 gpio_pin; /* For serial: index 0-strobe index 1-data, For Parallel: per stream */ - A_UINT32 gpio_func; /* GPIO function values for Smart Antenna */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle + */ + A_UINT32 tlv_header; + /* For serial: index 0-strobe index 1-data, For Parallel: per stream */ + A_UINT32 gpio_pin; + A_UINT32 gpio_func; /* GPIO function values for Smart Antenna */ + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_smart_ant_gpio_handle; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 rx_antenna; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + A_UINT32 rx_antenna; } wmi_pdev_smart_ant_set_rx_antenna_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param */ - /** unique id identifying the vdev, generated by the caller */ - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /* - * Following this structure is the TLV: - * wmi_peer_smart_ant_set_tx_antenna_series - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** unique id identifying the vdev, generated by the caller */ + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /* + * Following this structure is the TLV: + * wmi_peer_smart_ant_set_tx_antenna_series + */ } wmi_peer_smart_ant_set_tx_antenna_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_series */ - /* antenna array */ - A_UINT32 antenna_series; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_tx_antenna_series + */ + A_UINT32 tlv_header; + /* antenna array */ + A_UINT32 antenna_series; } wmi_peer_smart_ant_set_tx_antenna_series; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */ - /* rate array */ - A_UINT32 train_rate_series; - /* antenna array */ - A_UINT32 train_antenna_series; - /* Rate flags */ - /* TODO: For future use? */ - A_UINT32 rc_flags; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param + */ + A_UINT32 tlv_header; + /* rate array */ + A_UINT32 train_rate_series; + /* antenna array */ + A_UINT32 train_antenna_series; + /* Rate flags */ + /* TODO: For future use? */ + A_UINT32 rc_flags; } wmi_peer_smart_ant_set_train_antenna_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /* num packets; 0-stop training */ - A_UINT32 num_pkts; - /* - * Following this structure is the TLV: - * wmi_peer_smart_ant_set_train_antenna_param - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /* num packets; 0-stop training */ + A_UINT32 num_pkts; + /* + * Following this structure is the TLV: + * wmi_peer_smart_ant_set_train_antenna_param + */ } wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param */ - /** unique id identifying the vdev, generated by the caller */ - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ - /** peer MAC address */ - wmi_mac_addr peer_macaddr; - /* command id*/ - A_UINT32 cmd_id; - /* number of arguments passed */ - A_UINT32 args_count; -/* - * Following this structure is the TLV: - * A_UINT32 args[]; <-- argument list - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** unique id identifying the vdev, generated by the caller */ + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /* command id*/ + A_UINT32 cmd_id; + /* number of arguments passed */ + A_UINT32 args_count; + /* + * Following this structure is the TLV: + * A_UINT32 args[]; // argument list + */ } wmi_peer_smart_ant_set_node_config_ops_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_ant_ctrl_chain */ - A_UINT32 antCtrlChain; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_ant_ctrl_chain + */ + A_UINT32 tlv_header; + A_UINT32 antCtrlChain; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_set_ant_ctrl_chain; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_ant_switch_tbl_cmd_fixed_param */ - A_UINT32 mac_id; /* MAC ID */ - A_UINT32 antCtrlCommon1; - A_UINT32 antCtrlCommon2; - /* - * Following this structure is the TLV: - * wmi_pdev_set_ant_ctrl_chain - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_ant_switch_tbl_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 mac_id; /* MAC ID */ + A_UINT32 antCtrlCommon1; + A_UINT32 antCtrlCommon2; + /* + * Following this structure is the TLV: + * wmi_pdev_set_ant_ctrl_chain + */ } wmi_pdev_set_ant_switch_tbl_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_ctl_table_cmd_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - /** len of CTL info */ - A_UINT32 ctl_len; - /* ctl array (len adjusted to number of words). - * Following this structure is the TLV: - * A_UINT32 ctl_info[1]; - */ + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_ctl_table_cmd_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + /** len of CTL info */ + A_UINT32 ctl_len; + /* ctl array (len adjusted to number of words) + * Following this structure is the TLV: + * A_UINT32 ctl_info[1]; + */ } wmi_pdev_set_ctl_table_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 mimogain_info; /* see WMI_MIMOGAIN macros */ - /* - * Bit 7:0 len of array gain table - * Bit 8 bypass multi chain gain or not - */ - /* array gain table(s) (len adjusted to number of words). - * Following this structure is the TLV: - * A_UINT32 arraygain_tbl[1]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_mimogain_table_cmd_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + A_UINT32 mimogain_info; /* see WMI_MIMOGAIN macros */ + /* + * Bit 7:0 len of array gain table + * Bit 8 bypass multi chain gain or not + */ + /* + * array gain table(s) (len adjusted to number of words). + * Following this structure is the TLV: + * A_UINT32 arraygain_tbl[1]; + */ } wmi_pdev_set_mimogain_table_cmd_fixed_param; #define WMI_MIMOGAIN_ARRAY_GAIN_LEN_S 0 #define WMI_MIMOGAIN_ARRAY_GAIN_LEN (0xff << WMI_MIMOGAIN_ARRAY_GAIN_LEN_S) -#define WMI_MIMOGAIN_ARRAY_GAIN_LEN_GET(x) WMI_F_MS(x,WMI_MIMOGAIN_ARRAY_GAIN_LEN) -#define WMI_MIMOGAIN_ARRAY_GAIN_LEN_SET(x,z) WMI_F_RMW(x,z,WMI_MIMOGAIN_ARRAY_GAIN_LEN) +#define WMI_MIMOGAIN_ARRAY_GAIN_LEN_GET(x) WMI_F_MS(x, WMI_MIMOGAIN_ARRAY_GAIN_LEN) +#define WMI_MIMOGAIN_ARRAY_GAIN_LEN_SET(x, z) WMI_F_RMW(x, z, WMI_MIMOGAIN_ARRAY_GAIN_LEN) #define WMI_MIMOGAIN_MULTI_CHAIN_BYPASS_S 8 #define WMI_MIMOGAIN_MULTI_CHAIN_BYPASS (0x1 << WMI_MIMOGAIN_MULTI_CHAIN_BYPASS_S) -#define WMI_MIMOGAIN_MULTI_CHAIN_BYPASS_GET(x) WMI_F_MS(x,WMI_MIMOGAIN_MULTI_CHAIN_BYPASS) -#define WMI_MIMOGAIN_MULTI_CHAIN_BYPASS_SET(x,z) WMI_F_RMW(x,z,WMI_MIMOGAIN_MULTI_CHAIN_BYPASS) +#define WMI_MIMOGAIN_MULTI_CHAIN_BYPASS_GET(x) WMI_F_MS(x, WMI_MIMOGAIN_MULTI_CHAIN_BYPASS) +#define WMI_MIMOGAIN_MULTI_CHAIN_BYPASS_SET(x, z) WMI_F_RMW(x, z, WMI_MIMOGAIN_MULTI_CHAIN_BYPASS) typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_fwtest_set_param_cmd_fixed_param */ - /** parameter id */ - A_UINT32 param_id; - /** parameter value */ - A_UINT32 param_value; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_fwtest_set_param_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** parameter id */ + A_UINT32 param_id; + /** parameter value */ + A_UINT32 param_value; } wmi_fwtest_set_param_cmd_fixed_param; -#define WMI_ATF_DENOMINATION 1000 /* Expressed in 1 part in 1000 (permille) */ +/* Expressed in 1 part in 1000 (permille) */ +#define WMI_ATF_DENOMINATION 1000 -#define WMI_ATF_SSID_FAIR_SCHED 0 /** fair ATF scheduling for vdev */ -#define WMI_ATF_SSID_STRICT_SCHED 1 /** strict ATF scheduling for vdev */ +#define WMI_ATF_SSID_FAIR_SCHED 0 /** Fair ATF scheduling for vdev */ +#define WMI_ATF_SSID_STRICT_SCHED 1 /** Strict ATF scheduling for vdev */ typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_atf_peer_info */ - A_UINT32 tlv_header; - wmi_mac_addr peer_macaddr; - A_UINT32 atf_units; /* Based on 1 part in 1000 (per mille) */ - A_UINT32 atf_groupid; /* Group Id of the peers for ATF SSID grouping */ - A_UINT32 atf_units_reserved; /* Peer congestion threshold for future use */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_atf_peer_info + */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + A_UINT32 atf_units; /* Based on 1 part in 1000 (per mille) */ + A_UINT32 atf_groupid; /* Group Id of the peers for ATF SSID grouping */ + /* Peer congestion threshold for future use */ + A_UINT32 atf_units_reserved; } wmi_atf_peer_info; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param */ - A_UINT32 num_peers; - /* - * Following this structure is the TLV: - * struct wmi_atf_peer_info peer_info[num_peers]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 num_peers; + /* + * Following this structure is the TLV: + * struct wmi_atf_peer_info peer_info[num_peers]; + */ } wmi_peer_atf_request_fixed_param; /* Structure for Bandwidth Fairness peer information */ typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bwf_peer_info */ - A_UINT32 tlv_header; - wmi_mac_addr peer_macaddr; - A_UINT32 bwf_guaranteed_bandwidth; /* BWF guaranteed_bandwidth for the peers in mbps */ - A_UINT32 bwf_max_airtime; /* BWF Maximum airtime percentage that can be allocated to the peer to meet the guaranteed_bandwidth */ - A_UINT32 bwf_peer_priority; /* BWF priority of the peer to allocate the tokens dynamically */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_bwf_peer_info + */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + /* BWF guaranteed_bandwidth for the peers in mbps */ + A_UINT32 bwf_guaranteed_bandwidth; + /* + * BWF Maximum airtime percentage that can be allocated + * to the peer to meet the guaranteed_bandwidth + */ + A_UINT32 bwf_max_airtime; + /* BWF priority of the peer to allocate the tokens dynamically */ + A_UINT32 bwf_peer_priority; } wmi_bwf_peer_info; /* Structure for Bandwidth Fairness peer request */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_bwf_request_fixed_param */ - A_UINT32 num_peers; - /* - * Following this structure is the TLV: - * struct wmi_bwf_peer_info peer_info[num_peers]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_bwf_request_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 num_peers; + /* + * Following this structure is the TLV: + * struct wmi_bwf_peer_info peer_info[num_peers]; + */ } wmi_peer_bwf_request_fixed_param; + /* Equal distribution of ATF air time within an VDEV. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_atf_request_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 peer_atf_units; /* Per peer ATF units (per mille). */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_atf_request_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 peer_atf_units; /* Per peer ATF units (per mille). */ } wmi_vdev_atf_request_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /** parameter */ - A_UINT32 param; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_get_ani_cck_config_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /** parameter */ + A_UINT32 param; } wmi_pdev_get_ani_cck_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_ani_ofdm_config_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /** parameter */ - A_UINT32 param; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_get_ani_ofdm_config_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /** parameter */ + A_UINT32 param; } wmi_pdev_get_ani_ofdm_config_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_QBOOST_CFG_CMD_fixed_param */ - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ - A_UINT32 qb_enable; - wmi_mac_addr peer_macaddr; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_QBOOST_CFG_CMD_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + A_UINT32 qb_enable; + wmi_mac_addr peer_macaddr; } WMI_QBOOST_CFG_CMD_fixed_param; #define WMI_INST_STATS_INVALID_RSSI 0 typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_inst_rssi_stats_resp_fixed_param */ - A_UINT32 iRSSI; /* dBm above the noise floor */ - /* peer MAC address */ - wmi_mac_addr peer_macaddr; - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_inst_rssi_stats_resp_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 iRSSI; /* dBm above the noise floor */ + /* peer MAC address */ + wmi_mac_addr peer_macaddr; + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ } wmi_inst_rssi_stats_resp_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_cck_ofdm_rate_info */ - A_UINT32 ratecode_legacy; /* Rate code for CCK OFDM */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_cck_ofdm_rate_info + */ + A_UINT32 tlv_header; + A_UINT32 ratecode_legacy; /* Rate code for CCK OFDM */ } wmi_peer_cck_ofdm_rate_info; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info */ - A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ - A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ - A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info + */ + A_UINT32 tlv_header; + A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ + A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ + A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ } wmi_peer_mcs_rate_info; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_ratecode_list_event_fixed_param */ - wmi_mac_addr peer_macaddr; - A_UINT32 ratecount; /* Max Rate count for each mode */ - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ - /* - * Following this structure are the TLV: - * struct wmi_peer_cck_ofdm_rate_info; - * struct wmi_peer_mcs_rate_info; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_ratecode_list_event_fixed_param + */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + A_UINT32 ratecount; /* Max Rate count for each mode */ + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + /* + * Following this structure are the TLV + * struct wmi_peer_cck_ofdm_rate_info; + * struct wmi_peer_mcs_rate_info; + */ } wmi_peer_ratecode_list_event_fixed_param; typedef struct wmi_wds_addr_event { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wds_addr_event_fixed_param */ - A_UINT32 event_type[4]; - wmi_mac_addr peer_mac; - wmi_mac_addr dest_mac; - A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_wds_addr_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 event_type[4]; + wmi_mac_addr peer_mac; + wmi_mac_addr dest_mac; + A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ } wmi_wds_addr_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_sta_ps_statechange_event_fixed_param */ - wmi_mac_addr peer_macaddr; - A_UINT32 peer_ps_state; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_sta_ps_statechange_event_fixed_param + */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + A_UINT32 peer_ps_state; } wmi_peer_sta_ps_statechange_event_fixed_param; /* WMI_PDEV_FIPS_EVENTID */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 error_status; /* Error status: 0 (no err), 1, or OPER_TIMEOUT */ - A_UINT32 data_len; /* Data length */ -/* - * Following this structure is the TLV: - * A_UINT32 data[1]; <-- Out Data (keep this in the end) - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param + */ + A_UINT32 tlv_header; + union { + /* OBSOLETE - will be removed once all refs are gone */ + A_UINT32 mac_id; + /** pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + }; + /* Error status: 0 (no err), 1, or OPER_TIMEOUT */ + A_UINT32 error_status; + A_UINT32 data_len; /* Data length */ + /* + * Following this structure is the TLV: + * A_UINT32 data[1]; // Out Data (keep this in the end) + */ } wmi_pdev_fips_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - /* Noise threshold iterations with high values */ - A_UINT32 noise_floor_report_iter; - /* Total noise threshold iterations */ - A_UINT32 noise_floor_total_iter; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_channel_hopping_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 mac_id; /* MAC ID */ + /* Noise threshold iterations with high values */ + A_UINT32 noise_floor_report_iter; + /* Total noise threshold iterations */ + A_UINT32 noise_floor_total_iter; } wmi_pdev_channel_hopping_event_fixed_param; enum { - WMI_PDEV_RESERVE_AST_ENTRY_OK, - WMI_PDEV_RESERVE_AST_ENTRY_HASH_COLLISION, - WMI_PDEV_RESERVE_AST_ENTRY_CROSSING_AXI_BOUNDARY, + WMI_PDEV_RESERVE_AST_ENTRY_OK, + WMI_PDEV_RESERVE_AST_ENTRY_HASH_COLLISION, + WMI_PDEV_RESERVE_AST_ENTRY_CROSSING_AXI_BOUNDARY, }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_tpc_cmd_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 rate_flags; - /** - * FLAG_ONE_CHAIN 0x001 - one chain mask - * FLAG_TWO_CHAIN 0x005 - two chain mask - * FLAG_THREE_CHAIN 0x007 - three chain mask - * FLAG_FOUR_CHAIN 0x00F - four chain mask - * FLAG_STBC 0x010 - STBC is set - * FLAG_40MHZ 0x020 - * FLAG_80MHZ 0x040 - * FLAG_160MHZ 0x080 - * FLAG_TXBF 0x0100 - Tx Bf enabled - * FLAG_RTSENA 0x0200 - RTS enabled - * FLAG_CTSENA 0x0400 - CTS enabled - * FLAG_LDPC 0x0800 - LDPC set - * FLAG_SERIES1 0x1000 - - * FLAG_SGI 0x2000 - Short gaurd interval - * FLAG_MU2 0x4000 - MU2 data - * FLAG_MU3 0x8000 - MU3 data - * */ - A_UINT32 nss; - /** - * NSS 0x0 - 0x3 - * */ - A_UINT32 preamble; - /** - * PREAM_OFDM - 0x0 - * PREAM_CCK - 0x1 - * PREAM_HT - 0x2 - * PREAM_VHT - 0x3 - * */ - A_UINT32 hw_rate; - /** - * *** HW_OFDM_RATE *** - * OFDM_48_MBPS - 0x0 - * OFDM_24_MBPS - 0x1 - * OFDM_12_MBPS - 0x2 - * OFDM_6_MBPS - 0x3 - * OFDM_54_MBPS - 0x4 - * OFDM_36_MBPS - 0x5 - * OFDM_18_MBPS - 0x6 - * OFDM_9_MBPS - 0x7 - * - * *** HW_CCK_RATE *** - * CCK_11_LONG_MBPS - 0x0 - * CCK_5_5_LONG_MBPS - 0x1 - * CCK_2_LONG_MBPS - 0x2 - * CCK_1_LONG_MBPS - 0x3 - * CCK_11_SHORT_MBPS - 0x4 - * CCK_5_5_SHORT_MBPS - 0x5 - * CCK_2_SHORT_MBPS - 0x6 - * - * *** HW_HT / VHT_RATE *** - * MCS 0x0 - 0x9 - * */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_get_tpc_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 mac_id; /* MAC ID */ + A_UINT32 rate_flags; + /** + * FLAG_ONE_CHAIN 0x001 - one chain mask + * FLAG_TWO_CHAIN 0x005 - two chain mask + * FLAG_THREE_CHAIN 0x007 - three chain mask + * FLAG_FOUR_CHAIN 0x00F - four chain mask + * FLAG_STBC 0x010 - STBC is set + * FLAG_40MHZ 0x020 + * FLAG_80MHZ 0x040 + * FLAG_160MHZ 0x080 + * FLAG_TXBF 0x0100 - Tx Bf enabled + * FLAG_RTSENA 0x0200 - RTS enabled + * FLAG_CTSENA 0x0400 - CTS enabled + * FLAG_LDPC 0x0800 - LDPC set + * FLAG_SERIES1 0x1000 - + * FLAG_SGI 0x2000 - Short gaurd interval + * FLAG_MU2 0x4000 - MU2 data + * FLAG_MU3 0x8000 - MU3 data + * */ + A_UINT32 nss; + /** + * NSS 0x0 - 0x3 + * */ + A_UINT32 preamble; + /** + * PREAM_OFDM - 0x0 + * PREAM_CCK - 0x1 + * PREAM_HT - 0x2 + * PREAM_VHT - 0x3 + * */ + A_UINT32 hw_rate; + /** + * *** HW_OFDM_RATE *** + * OFDM_48_MBPS - 0x0 + * OFDM_24_MBPS - 0x1 + * OFDM_12_MBPS - 0x2 + * OFDM_6_MBPS - 0x3 + * OFDM_54_MBPS - 0x4 + * OFDM_36_MBPS - 0x5 + * OFDM_18_MBPS - 0x6 + * OFDM_9_MBPS - 0x7 + * + * *** HW_CCK_RATE *** + * CCK_11_LONG_MBPS - 0x0 + * CCK_5_5_LONG_MBPS - 0x1 + * CCK_2_LONG_MBPS - 0x2 + * CCK_1_LONG_MBPS - 0x3 + * CCK_11_SHORT_MBPS - 0x4 + * CCK_5_5_SHORT_MBPS - 0x5 + * CCK_2_SHORT_MBPS - 0x6 + * + * *** HW_HT / VHT_RATE *** + * MCS 0x0 - 0x9 + * */ } wmi_pdev_get_tpc_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_chip_power_stats_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals + WMITLV_TAG_STRUC_wmi_pdev_get_chip_power_stats_cmd_fixed_param */ + /** + * pdev_id for identifying the MAC See macros + * starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; } wmi_pdev_get_chip_power_stats_cmd_fixed_param; + typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /* - * Following this structure is the TLV: - * A_UINT32 tpc[1]; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 reserved0; /* for future need */ + /* + * Following this structure is the TLV: + * A_UINT32 tpc[1]; + */ } wmi_pdev_tpc_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param */ - union { - A_UINT32 mac_id; /* OBSOLETE - will be removed once all refs are gone */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - }; - A_UINT32 nfdBr_len; - A_UINT32 nfdBm_len; - A_UINT32 freqNum_len; - /* - * Following this structure is the TLV: - * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBr; - * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBm; - * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_freqNum; - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 mac_id; /* MAC ID */ + A_UINT32 nfdBr_len; + A_UINT32 nfdBm_len; + A_UINT32 freqNum_len; + /* + * Following this structure is the TLV: + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBr; + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBm; + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_freqNum; + */ } wmi_pdev_nfcal_power_all_channels_event_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBr */ - A_UINT32 nfdBr; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBr + */ + A_UINT32 tlv_header; + A_UINT32 nfdBr; } wmi_pdev_nfcal_power_all_channels_nfdBr; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBm */ - A_UINT32 nfdBm; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_nfdBm + */ + A_UINT32 tlv_header; + A_UINT32 nfdBm; } wmi_pdev_nfcal_power_all_channels_nfdBm; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_freqNum */ - A_UINT32 freqNum; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_freqNum + */ + A_UINT32 tlv_header; + A_UINT32 freqNum; } wmi_pdev_nfcal_power_all_channels_freqNum; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ani_cck_event_fixed_param */ - A_UINT32 cck_level; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ani_cck_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 cck_level; } wmi_ani_cck_event_fixed_param; typedef enum wmi_power_debug_reg_fmt_type { - /* WMI_POWER_DEBUG_REG_FMT_TYPE_ROME -> Dumps following 12 Registers - * SOC_SYSTEM_SLEEP - * WLAN_SYSTEM_SLEEP - * RTC_SYNC_FORCE_WAKE - * MAC_DMA_ISR - * MAC_DMA_TXRX_ISR - * MAC_DMA_ISR_S1 - * MAC_DMA_ISR_S2 - * MAC_DMA_ISR_S3 - * MAC_DMA_ISR_S4 - * MAC_DMA_ISR_S5 - * MAC_DMA_ISR_S6 - * MAC_DMA_ISR_S7 - */ - WMI_POWER_DEBUG_REG_FMT_TYPE_ROME, - - WMI_POWER_DEBUG_REG_FMT_TYPE_MAX = 0xf, + /* WMI_POWER_DEBUG_REG_FMT_TYPE_ROME -> Dumps following 12 Registers + * SOC_SYSTEM_SLEEP + * WLAN_SYSTEM_SLEEP + * RTC_SYNC_FORCE_WAKE + * MAC_DMA_ISR + * MAC_DMA_TXRX_ISR + * MAC_DMA_ISR_S1 + * MAC_DMA_ISR_S2 + * MAC_DMA_ISR_S3 + * MAC_DMA_ISR_S4 + * MAC_DMA_ISR_S5 + * MAC_DMA_ISR_S6 + * MAC_DMA_ISR_S7 + */ + WMI_POWER_DEBUG_REG_FMT_TYPE_ROME, + WMI_POWER_DEBUG_REG_FMT_TYPE_MAX = 0xf, } WMI_POWER_DEBUG_REG_FMT_TYPE; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chip_power_stats_event_fixed_param */ - A_UINT32 cumulative_sleep_time_ms; /* maximum range is 35 hours, due to conversion from internal 0.03215 ms units to ms */ - A_UINT32 cumulative_total_on_time_ms; /* maximum range is 35 hours, due to conversion from internal 0.03215 ms units to ms */ - A_UINT32 deep_sleep_enter_counter; /* count of number of times chip enterred deep sleep */ - A_UINT32 last_deep_sleep_enter_tstamp_ms; /* Last Timestamp when Chip went to deep sleep */ - A_UINT32 debug_register_fmt; /* WMI_POWER_DEBUG_REG_FMT_TYPE enum, describes debug registers being dumped as part of the event */ - A_UINT32 num_debug_register; /* number of debug registers being sent to host */ - /* - * Following this structure is the TLV: - * A_UINT32 debug_registers[num_debug_registers]; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals + WMITLV_TAG_STRUC_wmi_chip_power_stats_event_fixed_param */ + /* + * maximum range is 35 hours, due to conversion from internal + * 0.03215 ms units to ms + */ + A_UINT32 cumulative_sleep_time_ms; + /* + * maximum range is 35 hours, due to conversion from internal + * 0.03215 ms units to ms + */ + A_UINT32 cumulative_total_on_time_ms; + /* count of number of times chip enterred deep sleep */ + A_UINT32 deep_sleep_enter_counter; + /* Last Timestamp when Chip went to deep sleep */ + A_UINT32 last_deep_sleep_enter_tstamp_ms; + /* + * WMI_POWER_DEBUG_REG_FMT_TYPE enum, describes debug registers + * being dumped as part of the event + */ + A_UINT32 debug_register_fmt; + /* number of debug registers being sent to host */ + A_UINT32 num_debug_register; + /* + * Following this structure is the TLV: + * A_UINT32 debug_registers[num_debug_registers]; + */ } wmi_pdev_chip_power_stats_event_fixed_param; + typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param */ - A_UINT32 ofdm_level; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 ofdm_level; } wmi_ani_ofdm_event_fixed_param; typedef enum wmi_coex_config_type { - WMI_COEX_CONFIG_PAGE_P2P_TDM = 1, /* config interval (arg1 BT, arg2 WLAN) for P2P + PAGE */ - WMI_COEX_CONFIG_PAGE_STA_TDM = 2, /* config interval (arg1 BT, arg2 WLAN) for STA + PAGE */ - WMI_COEX_CONFIG_PAGE_SAP_TDM = 3, /* config interval (arg1 BT, arg2 WLAN) for SAP + PAGE */ - WMI_COEX_CONFIG_DURING_WLAN_CONN = 4, /* config during WLAN connection */ - WMI_COEX_CONFIG_BTC_ENABLE = 5, /* config to enable/disable BTC */ + /* config interval (arg1 BT, arg2 WLAN) for P2P + PAGE */ + WMI_COEX_CONFIG_PAGE_P2P_TDM = 1, + /* config interval (arg1 BT, arg2 WLAN) for STA + PAGE */ + WMI_COEX_CONFIG_PAGE_STA_TDM = 2, + /* config interval (arg1 BT, arg2 WLAN) for SAP + PAGE */ + WMI_COEX_CONFIG_PAGE_SAP_TDM = 3, + /* config during WLAN connection */ + WMI_COEX_CONFIG_DURING_WLAN_CONN = 4, + /* config to enable/disable BTC */ + WMI_COEX_CONFIG_BTC_ENABLE = 5, + /* config of COEX debug setting */ + WMI_COEX_CONFIG_COEX_DBG = 6, + /* + * config interval (ms units) (arg1 BT, arg2 WLAN) + * for P2P + STA + PAGE + */ + WMI_COEX_CONFIG_PAGE_P2P_STA_TDM = 7, + /* config interval (ms units) (arg1 BT, arg2 WLAN) for P2P + INQUIRY */ + WMI_COEX_CONFIG_INQUIRY_P2P_TDM = 8, + /* config interval (ms units) (arg1 BT, arg2 WLAN) for STA + INQUIRY */ + WMI_COEX_CONFIG_INQUIRY_STA_TDM = 9, + /* config interval (ms units) (arg1 BT, arg2 WLAN) for SAP + INQUIRY */ + WMI_COEX_CONFIG_INQUIRY_SAP_TDM = 10, + /* + * config interval (ms units) (arg1 BT, arg2 WLAN) for P2P + STA + + * INQUIRY + */ + WMI_COEX_CONFIG_INQUIRY_P2P_STA_TDM = 11, + /* config wlan total tx power when bt coex (arg1 is wlan_tx_power_limit, in 0.5dbm units) */ + WMI_COEX_CONFIG_TX_POWER = 12, } WMI_COEX_CONFIG_TYPE; typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 config_type; /* wmi_coex_config_type enum */ - A_UINT32 config_arg1; - A_UINT32 config_arg2; + A_UINT32 tlv_header; + A_UINT32 vdev_id; + /* wmi_coex_config_type enum */ + A_UINT32 config_type; + A_UINT32 config_arg1; + A_UINT32 config_arg2; } WMI_COEX_CONFIG_CMD_fixed_param; /** * This command is sent from WLAN host driver to firmware to * request firmware to enable/disable channel avoidance report * to host. - * */ enum { - WMI_MWSCOEX_CHAN_AVD_RPT_DISALLOW = 0, - WMI_MWSCOEX_CHAN_AVD_RPT_ALLOW = 1 + WMI_MWSCOEX_CHAN_AVD_RPT_DISALLOW = 0, + WMI_MWSCOEX_CHAN_AVD_RPT_ALLOW = 1 }; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param */ - /** Allow/disallow flag - see WMI_MWSCOEX_CHAN_AVD_RPT enum */ - A_UINT32 rpt_allow; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param + */ + A_UINT32 tlv_header; + /* Allow/disallow flag - see WMI_MWSCOEX_CHAN_AVD_RPT enum */ + A_UINT32 rpt_allow; } WMI_CHAN_AVOID_RPT_ALLOW_CMD_fixed_param; /* @@ -15634,23 +17279,32 @@ typedef struct { * WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param */ - /** 1 = enable, 0 = disable */ - A_UINT32 enable; - /** periodic stats duration (units are milliseconds) */ - A_UINT32 stats_period; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param + */ + A_UINT32 tlv_header; + /** 1 = enable, 0 = disable */ + A_UINT32 enable; + /** periodic stats duration (units are milliseconds) */ + A_UINT32 stats_period; } wmi_set_periodic_channel_stats_config_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_wal_power_debug_cmd_fixed_param */ - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - /* Identify the wlan module */ - A_UINT32 module_id; - /* Num of elements in the following args[] array */ - A_UINT32 num_args; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_wal_power_debug_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* + * pdev_id for identifying the MAC + * See macros starting with WMI_PDEV_ID_ for values. + */ + A_UINT32 pdev_id; + /* Identify the wlan module */ + A_UINT32 module_id; + /* Num of elements in the following args[] array */ + A_UINT32 num_args; /** * Following this structure are the TLVs: * A_UINT32 args[]; @@ -15658,20 +17312,27 @@ typedef struct { } wmi_pdev_wal_power_debug_cmd_fixed_param; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_reorder_timeout_val_cmd_fixed_param */ - /** - * @brief rx_timeout_pri - what rx reorder timeout (ms) to use for the AC - * @details - * Each WMM access category (voice, video, best-effort, background) - * will have its own timeout value to dictate how long to wait for - * missing rx MPDUs to arrive before releasing subsequent MPDUs that - * have already been received. - * This parameter specifies the timeout in milliseconds for each - * access category. - * The array elements are indexed by the WMI_AC enum to identify - * which array element corresponds to which AC / traffic type. - */ - A_UINT32 rx_timeout_pri[WMI_AC_MAX]; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_set_reorder_timeout_val_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** + * @brief rx_timeout_pri - what rx reorder timeout (ms) to use + * for the AC + * @details + * Each WMM access category (voice, video, best-effort, + * background) will have its own timeout value to dictate + * how long to wait for missing rx MPDUs to arrive before + * releasing subsequent MPDUs that have already been + * received. + * This parameter specifies the timeout in milliseconds + * for each access category. + * The array elements are indexed by the WMI_AC enum to + * identify which array element corresponds to which AC / + * traffic type. + */ + A_UINT32 rx_timeout_pri[WMI_AC_MAX]; } wmi_pdev_set_reorder_timeout_val_cmd_fixed_param; /** @@ -15692,92 +17353,81 @@ typedef struct { * FW will generate and send out a wlan stats event immediately. */ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param */ - /** Indicate if threshold mechnism is enabled or disabled. - * It is disabled by default. - * Host can enable and disable it dynamically. - */ - A_UINT32 enable_thresh; - /** use_thresh_bitmap equals 0 means gbl_thresh is used. - * when use_thresh_bitmap equals 1, ignore gbl_thresh and use stats bitmap indicated thresholds. - */ - A_UINT32 use_thresh_bitmap; - /** global threshold, valid when use_thresh_bitmap equals 0. - * It takes effect for all counters. - * If use_thresh_bitmap ==0 && gbl_thresh == 0, disable threshold mechanism. - */ - A_UINT32 gbl_thresh; - /** Enable/disable bitmap for threshold mechanism of CCA stats */ - A_UINT32 cca_thresh_bitmap; - /** Enable/disable bitmap for threshold mechanism of signal stats */ - A_UINT32 signal_thresh_bitmap; - /** Enable/disable bitmap for threshold mechanism of TX stats */ - A_UINT32 tx_thresh_bitmap; - /** Enable/disable bitmap for threshold mechanism of RX stats */ - A_UINT32 rx_thresh_bitmap; - /* This TLV is followed by TLVs below: - * wmi_chan_cca_stats_thresh cca_thresh; - * wmi_peer_signal_stats_thresh signal_thresh; - * wmi_tx_stats_thresh tx_thresh; - * wmi_rx_stats_thresh rx_thresh; - */ + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param */ + /** Indicate if threshold mechnism is enabled or disabled. + * It is disabled by default. + * Host can enable and disable it dynamically. + */ + A_UINT32 enable_thresh; + /** use_thresh_bitmap equals 0 means gbl_thresh is used. + * when use_thresh_bitmap equals 1, ignore gbl_thresh and use stats bitmap indicated thresholds. + */ + A_UINT32 use_thresh_bitmap; + /** global threshold, valid when use_thresh_bitmap equals 0. + * It takes effect for all counters. + * If use_thresh_bitmap ==0 && gbl_thresh == 0, disable threshold mechanism. + */ + A_UINT32 gbl_thresh; + /** Enable/disable bitmap for threshold mechanism of CCA stats */ + A_UINT32 cca_thresh_enable_bitmap; + /** Enable/disable bitmap for threshold mechanism of signal stats */ + A_UINT32 signal_thresh_enable_bitmap; + /** Enable/disable bitmap for threshold mechanism of TX stats */ + A_UINT32 tx_thresh_enable_bitmap; + /** Enable/disable bitmap for threshold mechanism of RX stats */ + A_UINT32 rx_thresh_enable_bitmap; + /* This TLV is followed by TLVs below: + * wmi_chan_cca_stats_thresh cca_thresh; + * wmi_peer_signal_stats_thresh signal_thresh; + * wmi_tx_stats_thresh tx_thresh; + * wmi_rx_stats_thresh rx_thresh; + */ } wmi_pdev_set_stats_threshold_cmd_fixed_param; typedef enum { - WMI_REQUEST_WLAN_TX_STAT = 0x01, - WMI_REQUEST_WLAN_RX_STAT = 0x02, - WMI_REQUEST_WLAN_CCA_STAT = 0x04, - WMI_REQUEST_WLAN_SIGNAL_STAT = 0x08, + WMI_REQUEST_WLAN_TX_STAT = 0x01, + WMI_REQUEST_WLAN_RX_STAT = 0x02, + WMI_REQUEST_WLAN_CCA_STAT = 0x04, + WMI_REQUEST_WLAN_SIGNAL_STAT = 0x08, } wmi_wlan_stats_id; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param */ - wmi_wlan_stats_id stats_id; + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param */ + wmi_wlan_stats_id stats_id; } wmi_request_wlan_stats_cmd_fixed_param; -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_rmc_set_leader_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /* Leader's mac address */ - wmi_mac_addr leader_mac_addr; -} wmi_rmc_set_leader_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_rmc_manual_leader_event_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /* 0: success - * 1: selected leader not found in network, able to find using auto selection - * -1: error - * non zero value should be return to userspace in case of failure */ - A_INT32 status; - /* bssid of new leader */ - wmi_mac_addr leader_mac_addr; -} wmi_rmc_manual_leader_event_fixed_param; - typedef enum { - WLAN_2G_CAPABILITY = 0x1, - WLAN_5G_CAPABILITY = 0x2, + WLAN_2G_CAPABILITY = 0x1, + WLAN_5G_CAPABILITY = 0x2, } WLAN_BAND_CAPABILITY; typedef enum wmi_hw_mode_config_type { - WMI_HW_MODE_SINGLE = 0, /* Only one PHY is active. */ - WMI_HW_MODE_DBS = 1, /* Both PHYs are active in different bands, one in 2G and another in 5G. */ - WMI_HW_MODE_SBS_PASSIVE = 2, /* Both PHYs are in passive mode (only rx) in same band; no tx allowed. */ - WMI_HW_MODE_SBS = 3, /* Both PHYs are active in the same band. - * Support for both PHYs within one band is planned for 5G only - * (as indicated in WMI_MAC_PHY_CAPABILITIES), - * but could be extended to other bands in the future. - * The separation of the band between the two PHYs needs to be communicated separately. - */ - WMI_HW_MODE_DBS_SBS = 4, /* 3 PHYs, with 2 on the same band doing SBS - * as in WMI_HW_MODE_SBS, and 3rd on the other band - */ + /* Only one PHY is active. */ + WMI_HW_MODE_SINGLE = 0, + /** + * Both PHYs are active in different bands, one in 2G + * and another in 5G. + */ + WMI_HW_MODE_DBS = 1, + /** + * Both PHYs are in passive mode (only rx) in same band; + * no tx allowed. + */ + WMI_HW_MODE_SBS_PASSIVE = 2, + /** + * Both PHYs are active in the same band. + * Support for both PHYs within one band is planned for 5G only + * (as indicated in WMI_MAC_PHY_CAPABILITIES), + * but could be extended to other bands in the future. + * The separation of the band between the two PHYs needs to be + * communicated separately. + */ + WMI_HW_MODE_SBS = 3, + /** + * 3 PHYs, with 2 on the same band doing SBS + * as in WMI_HW_MODE_SBS, and 3rd on the other band + */ + WMI_HW_MODE_DBS_SBS = 4, } WMI_HW_MODE_CONFIG_TYPE; #define WMI_SUPPORT_11B_GET(flags) WMI_GET_BITS(flags, 0, 1) @@ -15802,252 +17452,313 @@ typedef enum wmi_hw_mode_config_type { #define WMI_MAX_MUBFEE_SET(flags, value) WMI_SET_BITS(flags, 28, 4, value) typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */ - /* hw_mode_id - identify a particular set of HW characteristics, as specified - * by the subsequent fields. WMI_MAC_PHY_CAPABILITIES element must be mapped - * to its parent WMI_HW_MODE_CAPABILITIES element using hw_mode_id. - * No particular ordering of WMI_MAC_PHY_CAPABILITIES elements should be assumed, - * though in practice the elements may always be ordered by hw_mode_id */ - A_UINT32 hw_mode_id; - /* pdev_id starts with 1. pdev_id 1 => phy_id 0, pdev_id 2 => phy_id 1 */ - A_UINT32 pdev_id; - /* phy id. Starts with 0 */ - A_UINT32 phy_id; - /* supported modulations and number of MU beamformees */ - union { - struct { - A_UINT32 supports_11b:1, - supports_11g:1, - supports_11a:1, - supports_11n:1, - supports_11ac:1, - supports_11ax:1, + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES + */ + A_UINT32 tlv_header; + /* + * hw_mode_id - identify a particular set of HW characteristics, as + * specified by the subsequent fields. WMI_MAC_PHY_CAPABILITIES element + * must be mapped to its parent WMI_HW_MODE_CAPABILITIES element using + * hw_mode_id. No particular ordering of WMI_MAC_PHY_CAPABILITIES + * elements should be assumed, though in practice the elements may + * always be ordered by hw_mode_id + */ + A_UINT32 hw_mode_id; + /* + * pdev_id starts with 1. pdev_id 1 => phy_id 0, + * pdev_id 2 => phy_id 1 + */ + A_UINT32 pdev_id; + /* phy id. Starts with 0 */ + A_UINT32 phy_id; + /* supported modulations and number of MU beamformees */ + union { + struct { + A_UINT32 supports_11b:1, + supports_11g:1, + supports_11a:1, + supports_11n:1, + supports_11ac:1, + supports_11ax:1, - unused: 22, + unused:22, - max_mubfee: 4; /* max MU beamformees supported per MAC */ - }; - A_UINT32 supported_flags; - }; - /* supported bands, enum WLAN_BAND_CAPABILITY */ - A_UINT32 supported_bands; - /* ampdu density 0 for no restriction, 1 for 1/4 us, 2 for 1/2 us, - * 3 for 1 us,4 for 2 us, 5 for 4 us, 6 for 8 us,7 for 16 us */ - A_UINT32 ampdu_density; - /* max bw supported 2G, enum wmi_channel_width */ - A_UINT32 max_bw_supported_2G; - /* WMI HT Capability, WMI_HT_CAP defines */ - A_UINT32 ht_cap_info_2G; - /* VHT capability info field of 802.11ac, WMI_VHT_CAP defines */ - A_UINT32 vht_cap_info_2G; - /* VHT Supported MCS Set field Rx/Tx same - * The max VHT-MCS for n SS subfield (where n = 1,...,8) is encoded as follows - * - 0 indicates support for VHT-MCS 0-7 for n spatial streams - * - 1 indicates support for VHT-MCS 0-8 for n spatial streams - * - 2 indicates support for VHT-MCS 0-9 for n spatial streams - * - 3 indicates that n spatial streams is not supported */ - A_UINT32 vht_supp_mcs_2G; - /*HE capability info field of 802.11ax, WMI_HE_CAP defines */ - A_UINT32 he_cap_info_2G; - /* HE Supported MCS Set field Rx/Tx same */ - A_UINT32 he_supp_mcs_2G; - /* Valid Transmit chain mask */ - A_UINT32 tx_chain_mask_2G; - /* Valid Receive chain mask */ - A_UINT32 rx_chain_mask_2G; - /* max bw supported 5G, enum wmi_channel_width */ - A_UINT32 max_bw_supported_5G; - /* WMI HT Capability, WMI_HT_CAP defines */ - A_UINT32 ht_cap_info_5G; - /* VHT capability info field of 802.11ac, WMI_VHT_CAP defines */ - A_UINT32 vht_cap_info_5G; - /* VHT Supported MCS Set field Rx/Tx same - * The max VHT-MCS for n SS subfield (where n = 1,...,8) is encoded as follows - * - 0 indicates support for VHT-MCS 0-7 for n spatial streams - * - 1 indicates support for VHT-MCS 0-8 for n spatial streams - * - 2 indicates support for VHT-MCS 0-9 for n spatial streams - * - 3 indicates that n spatial streams is not supported */ - A_UINT32 vht_supp_mcs_5G; - /*HE capability info field of 802.11ax, WMI_HE_CAP defines */ - A_UINT32 he_cap_info_5G; - /* HE Supported MCS Set field Rx/Tx same */ - A_UINT32 he_supp_mcs_5G; - /* Valid Transmit chain mask */ - A_UINT32 tx_chain_mask_5G; - /* Valid Receive chain mask */ - A_UINT32 rx_chain_mask_5G; + /* max MU beamformees supported per MAC */ + max_mubfee:4; + }; + A_UINT32 supported_flags; + }; + /* supported bands, enum WLAN_BAND_CAPABILITY */ + A_UINT32 supported_bands; + /* + * ampdu density 0 for no restriction, 1 for 1/4 us, 2 for 1/2 us, + * 3 for 1 us,4 for 2 us, 5 for 4 us, 6 for 8 us,7 for 16 us + */ + A_UINT32 ampdu_density; + /* max bw supported 2G, enum wmi_channel_width */ + A_UINT32 max_bw_supported_2G; + /* WMI HT Capability, WMI_HT_CAP defines */ + A_UINT32 ht_cap_info_2G; + /* VHT capability info field of 802.11ac, WMI_VHT_CAP defines */ + A_UINT32 vht_cap_info_2G; + /* + * VHT Supported MCS Set field Rx/Tx same + * The max VHT-MCS for n SS subfield (where n = 1,...,8) is encoded as + * follows + * - 0 indicates support for VHT-MCS 0-7 for n spatial streams + * - 1 indicates support for VHT-MCS 0-8 for n spatial streams + * - 2 indicates support for VHT-MCS 0-9 for n spatial streams + * - 3 indicates that n spatial streams is not supported + */ + A_UINT32 vht_supp_mcs_2G; + /* HE capability info field of 802.11ax, WMI_HE_CAP defines */ + A_UINT32 he_cap_info_2G; + /* HE Supported MCS Set field Rx/Tx same */ + A_UINT32 he_supp_mcs_2G; + /* Valid Transmit chain mask */ + A_UINT32 tx_chain_mask_2G; + /* Valid Receive chain mask */ + A_UINT32 rx_chain_mask_2G; + /* max bw supported 5G, enum wmi_channel_width */ + A_UINT32 max_bw_supported_5G; + /* WMI HT Capability, WMI_HT_CAP defines */ + A_UINT32 ht_cap_info_5G; + /* VHT capability info field of 802.11ac, WMI_VHT_CAP defines */ + A_UINT32 vht_cap_info_5G; + /* + * VHT Supported MCS Set field Rx/Tx same + * The max VHT-MCS for n SS subfield (where n = 1,...,8) is encoded as + * follows + * - 0 indicates support for VHT-MCS 0-7 for n spatial streams + * - 1 indicates support for VHT-MCS 0-8 for n spatial streams + * - 2 indicates support for VHT-MCS 0-9 for n spatial streams + * - 3 indicates that n spatial streams is not supported + */ + A_UINT32 vht_supp_mcs_5G; + /* HE capability info field of 802.11ax, WMI_HE_CAP defines */ + A_UINT32 he_cap_info_5G; + /* HE Supported MCS Set field Rx/Tx same */ + A_UINT32 he_supp_mcs_5G; + /* Valid Transmit chain mask */ + A_UINT32 tx_chain_mask_5G; + /* Valid Receive chain mask */ + A_UINT32 rx_chain_mask_5G; + /* HE capability phy field of 802.11ax, WMI_HE_CAP defines */ + A_UINT32 he_cap_phy_info_2G[WMI_MAX_HECAP_PHY_SIZE]; + A_UINT32 he_cap_phy_info_5G[WMI_MAX_HECAP_PHY_SIZE]; + wmi_ppe_threshold he_ppet2G; + wmi_ppe_threshold he_ppet5G; } WMI_MAC_PHY_CAPABILITIES; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES */ - /* hw_mode_id - identify a particular set of HW characteristics, - * as specified by the subsequent fields */ - A_UINT32 hw_mode_id; - /* BIT0 represents phy_id 0, BIT1 represent phy_id 1 and so on - * number of bits set in phy_id_map represents number of WMI_MAC_PHY_CAPABILITIES TLV's - * one for each active PHY for current HW mode identified by hw_mode_id. For example for - * DBS/SBS mode there will be 2 WMI_MAC_PHY_CAPABILITIES TLVs and for single MAC modes it - * will be 1 WMI_MAC_PHY_CAPABILITIES TLVs */ - A_UINT32 phy_id_map; - /* hw_mode_config_type - * Identify a particular type of HW mode such as SBS, DBS etc. - * Refer to WMI_HW_MODE_CONFIG_TYPE values. - */ - A_UINT32 hw_mode_config_type; + /* + * TLV tag and len; tag equal + * WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES + */ + A_UINT32 tlv_header; + /* + * hw_mode_id - identify a particular set of HW characteristics, + * as specified by the subsequent fields + */ + A_UINT32 hw_mode_id; + /** + * BIT0 represents phy_id 0, BIT1 represent phy_id 1 and so on. + * Number of bits set in phy_id_map represents number of + * WMI_MAC_PHY_CAPABILITIES TLV's + * one for each active PHY for current HW mode + * identified by hw_mode_id. For example for + * DBS/SBS mode there will be 2 + * WMI_MAC_PHY_CAPABILITIES TLVs and for + * single MAC modes it + * will be 1 WMI_MAC_PHY_CAPABILITIES + * TLVs + */ + A_UINT32 phy_id_map; + /** + * hw_mode_config_type + * Identify a particular type of HW mode such as SBS, DBS etc. + * Refer to WMI_HW_MODE_CONFIG_TYPE values. + */ + A_UINT32 hw_mode_config_type; } WMI_HW_MODE_CAPABILITIES; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SOC_MAC_PHY_HW_MODE_CAPS */ - /* num HW modes */ - A_UINT32 num_hw_modes; - /* num_hw_modes WMI_HW_MODE_CAPABILITIES TLV's */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_SOC_MAC_PHY_HW_MODE_CAPS + */ + A_UINT32 tlv_header; + /* num HW modes */ + A_UINT32 num_hw_modes; + /* num_hw_modes WMI_HW_MODE_CAPABILITIES TLV's */ } WMI_SOC_MAC_PHY_HW_MODE_CAPS; /*Below are Reg caps per PHY. Please note PHY ID starts with 0.*/ typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_HAL_REG_CAPABILITIES_EXT */ - /* phy id */ - A_UINT32 phy_id; - /* regdomain value specified in EEPROM */ - A_UINT32 eeprom_reg_domain; - /* regdomain */ - A_UINT32 eeprom_reg_domain_ext; - /* CAP1 capabilities bit map, see REGDMN_CAP1_ defines */ - A_UINT32 regcap1; - /* REGDMN EEPROM CAP, see REGDMN_EEPROM_EEREGCAP_ defines */ - A_UINT32 regcap2; - /* REGDMN MODE, see REGDMN_MODE_ enum */ - A_UINT32 wireless_modes; - A_UINT32 low_2ghz_chan; - A_UINT32 high_2ghz_chan; - A_UINT32 low_5ghz_chan; - A_UINT32 high_5ghz_chan; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_HAL_REG_CAPABILITIES_EXT + */ + A_UINT32 tlv_header; + /* phy id */ + A_UINT32 phy_id; + /* regdomain value specified in EEPROM */ + A_UINT32 eeprom_reg_domain; + /* regdomain */ + A_UINT32 eeprom_reg_domain_ext; + /* + * CAP1 capabilities bit map, see REGDMN_CAP1_ + * defines + */ + A_UINT32 regcap1; + /* + * REGDMN EEPROM CAP, see + * REGDMN_EEPROM_EEREGCAP_ defines + */ + A_UINT32 regcap2; + /* REGDMN MODE, see REGDMN_MODE_ enum */ + A_UINT32 wireless_modes; + A_UINT32 low_2ghz_chan; + A_UINT32 high_2ghz_chan; + A_UINT32 low_5ghz_chan; + A_UINT32 high_5ghz_chan; } WMI_HAL_REG_CAPABILITIES_EXT; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES */ - A_UINT32 num_phy; - /* num_phy WMI_HAL_REG_CAPABILITIES_EXT TLV's */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES + */ + A_UINT32 tlv_header; + /* num_phy WMI_HAL_REG_CAPABILITIES_EXT TLV's */ + A_UINT32 num_phy; } WMI_SOC_HAL_REG_CAPABILITIES; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_parameters_tlv */ - /** global default adaptive dwell mode, used when WMI_SCAN_DWELL_MODE_DEFAULT */ - A_UINT32 default_adaptive_dwell_mode; - /** the weight to calculate the average low pass filter for channel congestion. 0-100 */ - A_UINT32 adapative_lpf_weight; - /** interval to monitor passive scan in msec */ - A_UINT32 passive_monitor_interval_ms; - /** % of wifi activity to switch from passive to active 0-100 */ - A_UINT32 wifi_activity_threshold_pct; + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_parameters_tlv + */ + A_UINT32 tlv_header; + /* + * global default adaptive dwell mode, + * used when WMI_SCAN_DWELL_MODE_DEFAULT + */ + A_UINT32 default_adaptive_dwell_mode; + /* + * the weight to calculate the average low pass filter for + * channel congestion. 0-100 + */ + A_UINT32 adapative_lpf_weight; + /* interval to monitor passive scan in msec */ + A_UINT32 passive_monitor_interval_ms; + /* % of wifi activity to switch from passive to active 0-100 */ + A_UINT32 wifi_activity_threshold_pct; } wmi_scan_adaptive_dwell_parameters_tlv; typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_config_fixed_param */ - /* globally enable/disable adaptive dwell */ - A_UINT32 enable; -/** - * followed by TLV (tag length value) parameters array - * The TLV's are: - * wmi_scan_adaptive_dwell_parameters_tlv param[]; (0 or 1 elements) - */ + /* + * TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_scan_adaptive_dwell_config_fixed_param + */ + A_UINT32 tlv_header; + /* globally enable/disable adaptive dwell */ + A_UINT32 enable; + /* + * followed by TLV (tag length value) parameters array + * The TLV's are: + * wmi_scan_adaptive_dwell_parameters_tlv param[]; (0 or 1 elements) + */ } wmi_scan_adaptive_dwell_config_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_coex_get_antenna_isolation_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Currently there are no parameters for this message. */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_coex_get_antenna_isolation_cmd_fixed_param */ + A_UINT32 tlv_header; + /* Currently there are no parameters for this message. */ } wmi_coex_get_antenna_isolation_cmd_fixed_param; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param */ - A_UINT32 tlv_header; - /** Antenna isolation value in dB units, none zero value is valid while 0 means failed to do isolation measurement or corresponding chain is not active. - * Currently the HW descriptor only supports 4 chains at most. - * Further isolation_chainX elements can be added in the future - * for additional chains, if needed. - */ - A_UINT32 isolation_chain0:8, /* [7:0], isolation value for chain 0 */ - isolation_chain1:8, /* [15:8], isolation value for chain 1 */ - isolation_chain2:8, /* [23:16], isolation value for chain 2 */ - isolation_chain3:8; /* [31:24], isolation value for chain 3 */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param */ + A_UINT32 tlv_header; + /** Antenna isolation value in dB units, none zero value is valid while 0 means failed to do isolation measurement or corresponding chain is not active. + * Currently the HW descriptor only supports 4 chains at most. + * Further isolation_chainX elements can be added in the future + * for additional chains, if needed. + */ + A_UINT32 isolation_chain0:8, /* [7:0], isolation value for chain 0 */ + isolation_chain1:8, /* [15:8], isolation value for chain 1 */ + isolation_chain2:8, /* [23:16], isolation value for chain 2 */ + isolation_chain3:8; /* [31:24], isolation value for chain 3 */ } wmi_coex_report_isolation_event_fixed_param; - /* ADD NEW DEFS HERE */ - /***************************************************************************** * The following structures are deprecated. DO NOT USE THEM! */ + /** Max number of channels in the schedule. */ #define OCB_CHANNEL_MAX (5) /* NOTE: Make sure these data structures are identical to those 9235 * defined in sirApi.h */ -typedef struct -{ - /** Arbitration Inter-Frame Spacing. Range: 2-15 */ - A_UINT32 aifsn; - /** Contention Window minimum. Range: 1 - 10 */ - A_UINT32 cwmin; - /** Contention Window maximum. Range: 1 - 10 */ - A_UINT32 cwmax; +typedef struct { + /** Arbitration Inter-Frame Spacing. Range: 2-15 */ + A_UINT32 aifsn; + /** Contention Window minimum. Range: 1 - 10 */ + A_UINT32 cwmin; + /** Contention Window maximum. Range: 1 - 10 */ + A_UINT32 cwmax; } wmi_qos_params_t; -typedef struct -{ - /** Channel frequency in MHz */ - A_UINT32 chan_freq; - /** Channel duration in ms */ - A_UINT32 duration; - /** Start guard interval in ms */ - A_UINT32 start_guard_interval; - /** End guard interval in ms */ - A_UINT32 end_guard_interval; - /** Transmit power in dBm, range 0 - 23 */ - A_UINT32 tx_power; - /** Transmit datarate in Mbps */ - A_UINT32 tx_rate; - /** QoS parameters for each AC */ - wmi_qos_params_t qos_params[WLAN_MAX_AC]; - /** 1 to enable RX stats for this channel, 0 otherwise */ - A_UINT32 rx_stats; +typedef struct { + /** Channel frequency in MHz */ + A_UINT32 chan_freq; + /** Channel duration in ms */ + A_UINT32 duration; + /** Start guard interval in ms */ + A_UINT32 start_guard_interval; + /** End guard interval in ms */ + A_UINT32 end_guard_interval; + /** Transmit power in dBm, range 0 - 23 */ + A_UINT32 tx_power; + /** Transmit datarate in Mbps */ + A_UINT32 tx_rate; + /** QoS parameters for each AC */ + wmi_qos_params_t qos_params[WLAN_MAX_AC]; + /** 1 to enable RX stats for this channel, 0 otherwise */ + A_UINT32 rx_stats; } wmi_ocb_channel_t; typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_ocb_set_sched_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** Number of valid channels in the channels array */ - A_UINT32 num_channels; - /** The array of channels */ - wmi_ocb_channel_t channels[OCB_CHANNEL_MAX]; - /** 1 to allow off-channel tx, 0 otherwise */ - A_UINT32 off_channel_tx; /* Not supported */ + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ocb_set_sched_cmd_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** Number of valid channels in the channels array */ + A_UINT32 num_channels; + /** The array of channels */ + wmi_ocb_channel_t channels[OCB_CHANNEL_MAX]; + /** 1 to allow off-channel tx, 0 otherwise */ + A_UINT32 off_channel_tx; /* Not supported */ } wmi_ocb_set_sched_cmd_fixed_param; typedef struct { - /** Return status. 0 for success, non-zero otherwise */ - A_UINT32 status; + /** Return status. 0 for success, non-zero otherwise */ + A_UINT32 status; } wmi_ocb_set_sched_event_fixed_param; -/***************************************************************************** - * END DEPRECATED - */ - -/* ADD NEW DEFS ABOVE THIS DEPRECATED SECTION */ - - +/** +* END DEPRECATED +*/ #ifdef __cplusplus } #endif - #endif /*_WMI_UNIFIED_H_*/ - /**@}*/ diff --git a/fw/wmi_version.h b/fw/wmi_version.h old mode 100755 new mode 100644 index b946241095cc..9bfb9364e4c0 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -35,8 +35,8 @@ * compatibility. */ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a - * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 290 + * change that may or may not break compatibility */ +#define __WMI_REVISION_ 309 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work @@ -78,4 +78,3 @@ #define WMI_ABI_VERSION_NS_1 __NAMESPACE_1_ #define WMI_ABI_VERSION_NS_2 __NAMESPACE_2_ #define WMI_ABI_VERSION_NS_3 __NAMESPACE_3_ - diff --git a/fw/wmix.h b/fw/wmix.h old mode 100755 new mode 100644 index aaabb91ddff9..e7c7934b6739 --- a/fw/wmix.h +++ b/fw/wmix.h @@ -53,29 +53,29 @@ extern "C" { * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. */ typedef struct { - A_UINT32 commandId; + A_UINT32 commandId; } POSTPACK WMIX_CMD_HDR; typedef enum { - WMIX_DSETOPEN_REPLY_CMDID = 0x2001, - WMIX_DSETDATA_REPLY_CMDID, - WMIX_HB_CHALLENGE_RESP_CMDID, - WMIX_DBGLOG_CFG_MODULE_CMDID, - WMIX_PROF_CFG_CMDID, /* 0x200a */ - WMIX_PROF_ADDR_SET_CMDID, - WMIX_PROF_START_CMDID, - WMIX_PROF_STOP_CMDID, - WMIX_PROF_COUNT_GET_CMDID, + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, /* 0x200a */ + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, } WMIX_COMMAND_ID; typedef enum { - WMIX_DSETOPENREQ_EVENTID = 0x3001, - WMIX_DSETCLOSE_EVENTID, - WMIX_DSETDATAREQ_EVENTID, - WMIX_HB_CHALLENGE_RESP_EVENTID, - WMIX_DBGLOG_EVENTID, - WMIX_PROF_COUNT_EVENTID, - WMIX_PKTLOG_EVENTID, + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, + WMIX_PKTLOG_EVENTID, } WMIX_EVENT_ID; /* @@ -87,10 +87,10 @@ typedef enum { * DataSet Open Request Event */ typedef struct { - A_UINT32 dset_id; - A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ - A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ - A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ } POSTPACK WMIX_DSETOPENREQ_EVENT; /* @@ -98,7 +98,7 @@ typedef struct { * DataSet Close Event */ typedef struct { - A_UINT32 access_cookie; + A_UINT32 access_cookie; } POSTPACK WMIX_DSETCLOSE_EVENT; /* @@ -106,33 +106,32 @@ typedef struct { * DataSet Data Request Event */ typedef struct { - A_UINT32 access_cookie; - A_UINT32 offset; - A_UINT32 length; - A_UINT32 targ_buf; /* echo'ed, not used by Host, */ - A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ - A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ } WMIX_DSETDATAREQ_EVENT; typedef struct { - A_UINT32 status; - A_UINT32 targ_dset_handle; - A_UINT32 targ_reply_fn; - A_UINT32 targ_reply_arg; - A_UINT32 access_cookie; - A_UINT32 size; - A_UINT32 version; -} WMIX_DSETOPEN_REPLY_CMD; + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} WMIX_DSETOPEN_REPLY_CMD; typedef struct { - A_UINT32 status; - A_UINT32 targ_buf; - A_UINT32 targ_reply_fn; - A_UINT32 targ_reply_arg; - A_UINT32 length; - A_UINT8 buf[1]; -} WMIX_DSETDATA_REPLY_CMD; - + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} WMIX_DSETDATA_REPLY_CMD; /* * =============Error Detection support================= @@ -143,9 +142,9 @@ typedef struct { * Heartbeat Challenge Response command */ typedef struct { - A_UINT32 cookie; - A_UINT32 source; -} WMIX_HB_CHALLENGE_RESP_CMD; + A_UINT32 cookie; + A_UINT32 source; +} WMIX_HB_CHALLENGE_RESP_CMD; /* * WMIX_HB_CHALLENGE_RESP_EVENTID @@ -158,13 +157,13 @@ typedef struct { */ typedef struct { - A_UINT32 period; /* Time (in 30.5us ticks) between samples */ - A_UINT32 nbins; -} WMIX_PROF_CFG_CMD; + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} WMIX_PROF_CFG_CMD; typedef struct { - A_UINT32 addr; -} WMIX_PROF_ADDR_SET_CMD; + A_UINT32 addr; +} WMIX_PROF_ADDR_SET_CMD; /* * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request @@ -173,13 +172,11 @@ typedef struct { * count set to the corresponding count */ typedef struct { - A_UINT32 addr; - A_UINT32 count; -} WMIX_PROF_COUNT_EVENT; - + A_UINT32 addr; + A_UINT32 count; +} WMIX_PROF_COUNT_EVENT; #ifdef __cplusplus } #endif - #endif /* _WMIX_H_ */ diff --git a/hw/qca6290/v1/HALcomdef.h b/hw/qca6290/v1/HALcomdef.h new file mode 100644 index 000000000000..cc351b126107 --- /dev/null +++ b/hw/qca6290/v1/HALcomdef.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H +/* +============================================================================== + +FILE: HALcomdef.h + +DESCRIPTION: + +============================================================================== + + Edit History + +$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $ + +when who what, where, why +-------- --- ----------------------------------------------------------- +06/17/10 sc Included com_dtypes.h and cleaned up typedefs +05/15/08 gfr Added HAL_ENUM_32BITS macro. +02/14/08 gfr Added bool32 type. +11/13/07 gfr Removed dependency on comdef.h +01/08/07 hxw Created + +*/ + + +/* + * Assembly wrapper + */ +#ifndef _ARM_ASM_ + +/* + * C++ wrapper + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +/* ----------------------------------------------------------------------- +** Types +** ----------------------------------------------------------------------- */ + +/* + * Standard integer types. + * + * bool32 - boolean, 32 bit (TRUE or FALSE) + */ +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +/* + * Macro to allow forcing an enum to 32 bits. The argument should be + * an identifier in the namespace of the enumeration in question, i.e. + * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx). + */ +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + +/*=========================================================================== + +FUNCTION inp, outp, inpw, outpw, inpdw, outpdw + +DESCRIPTION + IN/OUT port macros for byte and word ports, typically inlined by compilers + which support these routines + +PARAMETERS + inp( xx_addr ) + inpw( xx_addr ) + inpdw( xx_addr ) + outp( xx_addr, xx_byte_val ) + outpw( xx_addr, xx_word_val ) + outpdw( xx_addr, xx_dword_val ) + xx_addr - Address of port to read or write (may be memory mapped) + xx_byte_val - 8 bit value to write + xx_word_val - 16 bit value to write + xx_dword_val - 32 bit value to write + +DEPENDENCIES + None + +RETURN VALUE + inp/inpw/inpdw: the byte, word or dword read from the given address + outp/outpw/outpdw: the byte, word or dword written to the given address + +SIDE EFFECTS + None. + +===========================================================================*/ + + /* ARM based targets use memory mapped i/o, so the inp/outp calls are + ** macroized to access memory directly + */ + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif /* !_ARM_ASM_ */ + +#endif /* HAL_COMDEF_H */ + diff --git a/hw/qca6290/v1/HALhwio.h b/hw/qca6290/v1/HALhwio.h new file mode 100644 index 000000000000..4e51df01439f --- /dev/null +++ b/hw/qca6290/v1/HALhwio.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H +/* +=========================================================================== +*/ +/** + @file HALhwio.h + + Public interface include file for accessing the HWIO HAL definitions. + + The HALhwio.h file is the public API interface to the HW I/O (HWIO) + register access definitions. +*/ + +/*========================================================================= + Include Files +==========================================================================*/ + + +/* + * Common types. + */ +#include "HALcomdef.h" + + + +/* ----------------------------------------------------------------------- +** Macros +** ----------------------------------------------------------------------- */ + +/** + @addtogroup macros + @{ +*/ + +/** + * Map a base name to the pointer to access the base. + * + * This macro maps a base name to the pointer to access the base. + * This is generally just used internally. + * + */ +#define HWIO_BASE_PTR(base) base##_BASE_PTR + + +/** + * Declare a HWIO base pointer. + * + * This macro will declare a HWIO base pointer data structure. The pointer + * will always be declared as a weak symbol so multiple declarations will + * resolve correctly to the same data at link-time. + */ +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +/** + @} +*/ + + +/** + @addtogroup hwio_macros + @{ +*/ + +/** + * @name Address Macros + * + * Macros for getting register addresses. + * These macros are used for retrieving the address of a register. + * HWIO_ADDR* will return the directly accessible address (virtual or physical based + * on environment), HWIO_PHYS* will always return the physical address. + * The offset from the base region can be retrieved using HWIO_OFFS*. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * @{ + */ +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) +/** @} */ + +/** + * @name Input Macros + * + * These macros are used for reading from a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the input will be masked with the supplied mask. The HWIO_INF* + * macros take a field name and will do the appropriate masking and shifting + * to return just the value of that field. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing). + * + * @{ + */ +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Output Macros + * + * These macros are used for writing to a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the output will be masked with the supplied mask (meaning these + * macros do a read first, mask in the supplied data, then write it back). + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * The HWIO_OUTF* macros take a field name and will do the appropriate masking + * and shifting to output just the value of that field. + * HWIO_OUTV* registers take a named value instead of a numeric value and + * do the same masking/shifting as HWIO_OUTF. + * + * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing). + * + * @{ + */ +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Shift and Mask Macros + * + * Macros for getting shift and mask values for fields and registers. + * HWIO_RMSK: The mask value for accessing an entire register. For example: + * @code + * HWIO_RMSK(REG) -> 0xFFFFFFFF + * @endcode + * HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n + * HWIO_SHFT: The right-shift value for accessing a field in a register. For example: + * @code + * HWIO_SHFT(REG, FLD) -> 8 + * @endcode + * HWIO_FMSK: The mask value for accessing a field in a register. For example: + * @code + * HWIO_FMSK(REG, FLD) -> 0xFF00 + * @endcode + * HWIO_VAL: The value for a field in a register. For example: + * @code + * HWIO_VAL(REG, FLD, ON) -> 0x1 + * @endcode + * HWIO_FVAL: This macro takes a numerical value and will shift and mask it into + * the given field position. For example: + * @code + * HWIO_FVAL(REG, FLD, 0x1) -> 0x100 + * @endcode + * HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it + * into the given field position. For example: + * @code + * HWIO_FVALV(REG, FLD, ON) -> 0x100 + * @endcode + * + * @{ + */ +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +/** @} */ + +/** + * @name Shadow Register Macros + * + * These macros are used for directly reading the value stored in a + * shadow register. + * Shadow registers are defined for write-only registers. Generally these + * macros should not be necessary as HWIO_OUTM* macros will automatically use + * the shadow values internally. + * + * @{ + */ +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) +/** @} */ + +/** + @} +*/ /* end_group */ + + +/** @cond */ + +/* + * Map to final symbols. This remapping is done to allow register + * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN + * then remappings like "#define xreg xregnew" do not work as expected. + */ +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + + +/* + * HWIO_INTLOCK + * + * Macro used by autogenerated code for mutual exclusion around + * read-mask-write operations. This is not supported in HAL + * code but can be overridden by non-HAL code. + */ +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + + +/* + * Input/output port macros for memory mapped IO. + */ +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + + +#ifdef HAL_HWIO_EXTERNAL + +/* + * Replace macros with externally supplied functions. + */ +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif /* HAL_HWIO_EXTERNAL */ + + +/* + * Base 8-bit byte accessing macros. + */ +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 16-bit word accessing macros. + */ +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 32-bit double-word accessing macros. + */ +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +/** @endcond */ + +#endif /* HAL_HWIO_H */ + diff --git a/hw/qca6290/v1/buffer_addr_info.h b/hw/qca6290/v1/buffer_addr_info.h new file mode 100644 index 000000000000..433fc6b2be7d --- /dev/null +++ b/hw/qca6290/v1/buffer_addr_info.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 buffer_addr_31_0[31:0] +// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { + uint32_t buffer_addr_31_0 : 32; //[31:0] + uint32_t buffer_addr_39_32 : 8, //[7:0] + return_buffer_manager : 3, //[10:8] + sw_buffer_cookie : 21; //[31:11] +}; + +/* + +buffer_addr_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + + +buffer_addr_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + + +return_buffer_manager + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + + + + +sw_buffer_cookie + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The two most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + +*/ + + +/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + + + +*/ +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The two most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + +*/ +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _BUFFER_ADDR_INFO_H_ diff --git a/hw/qca6290/v1/ce_src_desc.h b/hw/qca6290/v1/ce_src_desc.h new file mode 100644 index 000000000000..8dd6bc39c9d2 --- /dev/null +++ b/hw/qca6290/v1/ce_src_desc.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 src_buffer_low[31:0] +// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16] +// 2 fw_metadata[15:0], ce_res_1[31:16] +// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { + uint32_t src_buffer_low : 32; //[31:0] + uint32_t src_buffer_high : 8, //[7:0] + toeplitz_en : 1, //[8] + src_swap : 1, //[9] + dest_swap : 1, //[10] + gather : 1, //[11] + ce_res_0 : 4, //[15:12] + length : 16; //[31:16] + uint32_t fw_metadata : 16, //[15:0] + ce_res_1 : 16; //[31:16] + uint32_t ce_res_2 : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +src_buffer_low + + LSB 32 bits of the 40 Bit Pointer to the source buffer + + + +src_buffer_high + + MSB 8 bits of the 40 Bit Pointer to the source buffer + + + +toeplitz_en + + Enable generation of 32-bit Toeplitz-LFSR hash for the + data transfer + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +src_swap + + Treats source memory organization as big-endian. For + each dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +dest_swap + + Treats destination memory organization as big-endian. + For each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +gather + + Enables gather of multiple copy engine source + descriptors to one destination. + + + +ce_res_0 + + Reserved + + + +length + + Length of the buffer in units of octets of the current + descriptor + + + +fw_metadata + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +ce_res_1 + + Reserved + + + +ce_res_2 + + Reserved + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW + + LSB 32 bits of the 40 Bit Pointer to the source buffer + + +*/ +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff + +/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH + + MSB 8 bits of the 40 Bit Pointer to the source buffer + + +*/ +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff + +/* Description CE_SRC_DESC_1_TOEPLITZ_EN + + Enable generation of 32-bit Toeplitz-LFSR hash for the + data transfer + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100 + +/* Description CE_SRC_DESC_1_SRC_SWAP + + Treats source memory organization as big-endian. For + each dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200 + +/* Description CE_SRC_DESC_1_DEST_SWAP + + Treats destination memory organization as big-endian. + For each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400 + +/* Description CE_SRC_DESC_1_GATHER + + Enables gather of multiple copy engine source + descriptors to one destination. + + +*/ +#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_1_GATHER_LSB 11 +#define CE_SRC_DESC_1_GATHER_MASK 0x00000800 + +/* Description CE_SRC_DESC_1_CE_RES_0 + + Reserved + + +*/ +#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_1_CE_RES_0_LSB 12 +#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000 + +/* Description CE_SRC_DESC_1_LENGTH + + Length of the buffer in units of octets of the current + descriptor + + +*/ +#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_LENGTH_LSB 16 +#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000 + +/* Description CE_SRC_DESC_2_FW_METADATA + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_2_FW_METADATA_LSB 0 +#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff + +/* Description CE_SRC_DESC_2_CE_RES_1 + + Reserved + + +*/ +#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008 +#define CE_SRC_DESC_2_CE_RES_1_LSB 16 +#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000 + +/* Description CE_SRC_DESC_3_CE_RES_2 + + Reserved + + +*/ +#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c +#define CE_SRC_DESC_3_CE_RES_2_LSB 0 +#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff + +/* Description CE_SRC_DESC_3_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_3_RING_ID_LSB 20 +#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000 + +/* Description CE_SRC_DESC_3_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _CE_SRC_DESC_H_ diff --git a/hw/qca6290/v1/ce_stat_desc.h b/hw/qca6290/v1/ce_stat_desc.h new file mode 100644 index 000000000000..4667d1447546 --- /dev/null +++ b/hw/qca6290/v1/ce_stat_desc.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16] +// 1 toeplitz_hash_0[31:0] +// 2 toeplitz_hash_1[31:0] +// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { + uint32_t ce_res_5 : 8, //[7:0] + toeplitz_en : 1, //[8] + src_swap : 1, //[9] + dest_swap : 1, //[10] + gather : 1, //[11] + ce_res_6 : 4, //[15:12] + length : 16; //[31:16] + uint32_t toeplitz_hash_0 : 32; //[31:0] + uint32_t toeplitz_hash_1 : 32; //[31:0] + uint32_t fw_metadata : 16, //[15:0] + ce_res_7 : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +ce_res_5 + + Reserved + + + +toeplitz_en + + + + +src_swap + + Source memory buffer swapped + + + +dest_swap + + Destination memory buffer swapped + + + +gather + + Gather of multiple copy engine source descriptors to one + destination enabled + + + +ce_res_6 + + Reserved + + + +length + + Sum of all the Lengths of the source descriptor in the + gather chain + + + +toeplitz_hash_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + + + +toeplitz_hash_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + + + +fw_metadata + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +ce_res_7 + + Reserved + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description CE_STAT_DESC_0_CE_RES_5 + + Reserved + + +*/ +#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_5_LSB 0 +#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff + +/* Description CE_STAT_DESC_0_TOEPLITZ_EN + + + +*/ +#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100 + +/* Description CE_STAT_DESC_0_SRC_SWAP + + Source memory buffer swapped + + +*/ +#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200 + +/* Description CE_STAT_DESC_0_DEST_SWAP + + Destination memory buffer swapped + + +*/ +#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400 + +/* Description CE_STAT_DESC_0_GATHER + + Gather of multiple copy engine source descriptors to one + destination enabled + + +*/ +#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_0_GATHER_LSB 11 +#define CE_STAT_DESC_0_GATHER_MASK 0x00000800 + +/* Description CE_STAT_DESC_0_CE_RES_6 + + Reserved + + +*/ +#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_6_LSB 12 +#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000 + +/* Description CE_STAT_DESC_0_LENGTH + + Sum of all the Lengths of the source descriptor in the + gather chain + + +*/ +#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_0_LENGTH_LSB 16 +#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000 + +/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + + +*/ +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff + +/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + + +*/ +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff + +/* Description CE_STAT_DESC_3_FW_METADATA + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_3_FW_METADATA_LSB 0 +#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff + +/* Description CE_STAT_DESC_3_CE_RES_7 + + Reserved + + +*/ +#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_3_CE_RES_7_LSB 16 +#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000 + +/* Description CE_STAT_DESC_3_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_3_RING_ID_LSB 20 +#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000 + +/* Description CE_STAT_DESC_3_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _CE_STAT_DESC_H_ diff --git a/hw/qca6290/v1/com_dtypes.h b/hw/qca6290/v1/com_dtypes.h new file mode 100644 index 000000000000..a1c0edccc566 --- /dev/null +++ b/hw/qca6290/v1/com_dtypes.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +/** + @file com_dtypes.h + @brief This header file contains general data types that are of use to all + modules. + +*/ +/*=========================================================================== +NOTE: The @brief description and any detailed descriptions above do not appear + in the PDF. + + The Utility_Services_API_mainpage.dox file contains all file/group + descriptions that are in the output PDF generated using Doxygen and + Latex. To edit or update any of the file/group text in the PDF, edit + the Utility_Services_API_mainpage.dox file or contact Tech Pubs. + + The above description for this file is part of the "utils_services" + group description in the Utility_Services_API_mainpage.dox file. +===========================================================================*/ +/*=========================================================================== + + S T A N D A R D D E C L A R A T I O N S + +DESCRIPTION + This header file contains general data types that are of use to all modules. + The values or definitions are dependent on the specified + target. T_WINNT specifies Windows NT based targets, otherwise the + default is for ARM targets. + + T_WINNT Software is hosted on an NT platforn, triggers macro and + type definitions, unlike definition above which triggers + actual OS calls + +===========================================================================*/ + + +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $ + +when who what, where, why +-------- --- ---------------------------------------------------------- +03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup. +11/09/10 EBR Doxygenated file. +09/15/09 pc Created file. +===========================================================================*/ + + +/*=========================================================================== + + Data Declarations + +===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* For NT apps we want to use the Win32 definitions and/or those + supplied by the Win32 compiler for things like NULL, MAX, MIN + abs, labs, etc. +*/ +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +/* ------------------------------------------------------------------------ +** Constants +** ------------------------------------------------------------------------ */ + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +/** @addtogroup utils_services +@{ */ + +/** @name Macros for Common Data Types +@{ */ +#define TRUE 1 /**< Boolean TRUE value. */ +#define FALSE 0 /**< Boolean FALSE value. */ + +#define ON 1 /**< ON value. */ +#define OFF 0 /**< OFF value. */ + +#ifndef NULL + #define NULL 0 /**< NULL value. */ +#endif +/** @} */ /* end_name_group Macros for Common Data Types */ + +/* ----------------------------------------------------------------------- +** Standard Types +** ----------------------------------------------------------------------- */ + +/** @} */ /* end_addtogroup utils_services */ + +/* The following definitions are the same across platforms. This first + group are the sanctioned types. +*/ +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +/** @addtogroup utils_services +@{ */ +/** Boolean value type. +*/ +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +/** @cond +*/ +#if defined(DALSTDDEF_H) /* guards against a known re-definer */ +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif /* #if !defined(DALSTDDEF_H) */ +/** @endcond */ + +#ifndef _UINT32_DEFINED +/** Unsigned 32-bit value. +*/ +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED +/** Unsigned 16-bit value. +*/ +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED +/** Unsigned 8-bit value. +*/ +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED +/** Signed 32-bit value. +*/ +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED +/** Signed 16-bit value. +*/ +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED +/** Signed 8-bit value. +*/ +typedef signed char int8; +#define _INT8_DEFINED +#endif + +/** @cond +*/ +/* This group are the deprecated types. Their use should be +** discontinued and new code should use the types above +*/ +#ifndef _BYTE_DEFINED +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +/** DEPRECATED: Unsinged 16 bit value type. +*/ +typedef unsigned short word; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long dword; + +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char uint1; +/** DEPRECATED: Unsigned 16 bit value type. +*/ +typedef unsigned short uint2; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long uint4; + +/** DEPRECATED: Signed 8 bit value type. +*/ +typedef signed char int1; +/** DEPRECATED: Signed 16 bit value type. +*/ +typedef signed short int2; +/** DEPRECATED: Signed 32 bit value type. +*/ +typedef long int int4; + +/** DEPRECATED: Signed 32 bit value. +*/ +typedef signed long sint31; +/** DEPRECATED: Signed 16 bit value. +*/ +typedef signed short sint15; +/** DEPRECATED: Signed 8 bit value. +*/ +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; +/** @endcond */ + +#if (! defined T_WINNT) && (! defined __GNUC__) + /* Non WinNT Targets */ + #ifndef _INT64_DEFINED + /** Signed 64-bit value. + */ + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + /** Unsigned 64-bit value. + */ + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */ + /* WINNT or SOLARIS based targets */ + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; /* Signed 64-bit value */ + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; /* Unsigned 64-bit value */ + #define _UINT64_DEFINED + #endif + #endif +#endif /* T_WINNT */ + +#endif /* _ARM_ASM_ */ + +#ifdef __cplusplus +} +#endif + +/** @} */ /* end_addtogroup utils_services */ +#endif /* COM_DTYPES_H */ diff --git a/hw/qca6290/v1/lithium_top_reg.h b/hw/qca6290/v1/lithium_top_reg.h new file mode 100644 index 000000000000..87e1b3d2514e --- /dev/null +++ b/hw/qca6290/v1/lithium_top_reg.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +////////////////////////////////////////////////////////////////////////////// +// lithium_top_reg.h generated by: GenArmCHeader.pl +////////////////////////////////////////////////////////////////////////////// +// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!! +////////////////////////////////////////////////////////////////////////////// +// RCS File : -USE CVS LOG- +// Revision : -USE CVS LOG- +// Last Check In : -USE CVS LOG- +////////////////////////////////////////////////////////////////////////////// +// Description : Constants related to Hardware Registers +// +// Byte Addresses are used for all BASES and ADDRESSES +////////////////////////////////////////////////////////////////////////////// +#ifndef LITHIUM_TOP_REG_H +#define LITHIUM_TOP_REG_H + +#define UMAC_CE_COMMON_CE_HOST_IE_0 (0x00A18034) +#define UMAC_CE_COMMON_CE_HOST_IE_1 (0x00A18038) + +#endif diff --git a/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h b/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h new file mode 100644 index 000000000000..a845897e8938 --- /dev/null +++ b/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __MAC_TCL_REG_SEQ_BASE_H__ +#define __MAC_TCL_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h b/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h new file mode 100644 index 000000000000..73f4cc2b369a --- /dev/null +++ b/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h @@ -0,0 +1,6821 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __MAC_TCL_REG_SEQ_REG_H__ +#define __MAC_TCL_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "mac_tcl_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block MAC_TCL_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register TCL_R0_SW2TCL1_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CTRL //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00000007 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_CTRL //// + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_CTRL //// + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_CTRL //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_CTRL //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_GEN_CTRL //// + +#define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) +#define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7e1d +#define HWIO_TCL_R0_GEN_CTRL_SHFT 0 +#define HWIO_TCL_R0_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) +#define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 + +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe + +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd + +#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 +#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc + +#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK 0x00000e00 +#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT 0x9 + +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 + +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 + +#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_BMSK 0x00000004 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_SHFT 0x2 + +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_0 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x) (x+0x0000002c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_PHYS(x) (x+0x0000002c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_1 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x) (x+0x00000030) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_PHYS(x) (x+0x00000030) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_2 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x) (x+0x00000034) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_PHYS(x) (x+0x00000034) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_3 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x) (x+0x00000038) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_PHYS(x) (x+0x00000038) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_4 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x) (x+0x0000003c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_PHYS(x) (x+0x0000003c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_5 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x) (x+0x00000040) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_PHYS(x) (x+0x00000040) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_6 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x) (x+0x00000044) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_PHYS(x) (x+0x00000044) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK 0x00000fff +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_0 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x) (x+0x00000048) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_PHYS(x) (x+0x00000048) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_1 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x) (x+0x0000004c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_PHYS(x) (x+0x0000004c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_2 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x) (x+0x00000050) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_PHYS(x) (x+0x00000050) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_3 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x) (x+0x00000054) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_PHYS(x) (x+0x00000054) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_4 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x) (x+0x00000058) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_PHYS(x) (x+0x00000058) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_5 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x) (x+0x0000005c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_PHYS(x) (x+0x0000005c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_6 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x) (x+0x00000060) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_PHYS(x) (x+0x00000060) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK 0x00000fff +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_SHFT 0x0 + +//// Register TCL_R0_PCP_TID_MAP //// + +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x00000064) +#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x00000064) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff +#define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 +#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) +#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) +#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) +#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_31_0 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x00000068) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x00000068) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_63_32 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x0000006c) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x0000006c) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_64 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x00000070) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x00000070) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_31_0 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x) (x+0x00000074) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x) (x+0x00000074) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_63_32 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x) (x+0x00000078) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x) (x+0x00000078) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_95_64 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x) (x+0x0000007c) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x) (x+0x0000007c) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_127_96 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x) (x+0x00000080) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x) (x+0x00000080) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_159_128 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x) (x+0x00000084) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x) (x+0x00000084) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_191_160 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x) (x+0x00000088) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x) (x+0x00000088) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_223_192 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x) (x+0x0000008c) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x) (x+0x0000008c) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_255_224 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x) (x+0x00000090) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x) (x+0x00000090) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_287_256 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x) (x+0x00000094) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x) (x+0x00000094) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_314_288 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x) (x+0x00000098) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x) (x+0x00000098) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK 0x07ffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 + +//// Register TCL_R0_CONFIG_SEARCH_QUEUE //// + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x0000009c) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x0000009c) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00003dfc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 + +//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a0) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a0) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000a4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000a4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a8) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a8) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000ac) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000ac) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_CONFIG_SEARCH_METADATA //// + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000000b0) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000000b0) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 + +//// Register TCL_R0_TID_MAP_PRTY //// + +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000000b4) +#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000000b4) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef +#define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 +#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) +#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 + +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 + +//// Register TCL_R0_INVALID_APB_ACC_ADDR //// + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000000b8) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000000b8) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ + out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 + +//// Register TCL_R0_WATCHDOG //// + +#define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000000bc) +#define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000000bc) +#define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) +#define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x000000c0) +#define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x000000c0) +#define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000000c4) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000000c4) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000000c8) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000000c8) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000000cc) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000000cc) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000000d0) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000000d0) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000000d4) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000000d4) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000e0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000e0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000e4) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000e4) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000f4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000f4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000f8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000f8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000fc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000fc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000100) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000100) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000104) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000104) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000108) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000108) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000010c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000010c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000110) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000110) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000114) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000114) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000118) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000118) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x0000011c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x0000011c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x00000120) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x00000120) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000124) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000124) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000128) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000128) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x0000012c) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x0000012c) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000138) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000138) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000013c) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000013c) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000014c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000014c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000150) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000150) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000154) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000154) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000158) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000158) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000015c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000015c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000160) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000160) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000164) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000164) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000168) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000168) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000016c) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000016c) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000170) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000170) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000174) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000174) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000178) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000178) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000017c) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000017c) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000180) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000180) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000184) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000184) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000190) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000190) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000194) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000194) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001a4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001a4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001a8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001a8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001ac) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001ac) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b0) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b0) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001b8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001b8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001bc) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001bc) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001c0) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001c0) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x000001c4) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x000001c4) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001c8) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001c8) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x000001cc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x000001cc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x000001d0) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x000001d0) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x000001d4) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x000001d4) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x000001d8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x000001d8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x000001dc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x000001dc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001e8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001e8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001ec) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001ec) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001fc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001fc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000200) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000200) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000204) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000204) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000208) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000208) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000020c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000020c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000210) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000210) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000214) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000214) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000218) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000218) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x0000021c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x0000021c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000220) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000220) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000224) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000224) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000228) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000228) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_ID //// + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x0000022c) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x0000022c) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000230) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000230) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MISC //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000234) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000234) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000240) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000240) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000244) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000244) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000254) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000254) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000258) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000258) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000025c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000025c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000260) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000260) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000264) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000264) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000268) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000268) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000026c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000026c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000270) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000270) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000274) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000274) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000278) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000278) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000027c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000027c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000280) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000280) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_ID //// + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000284) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000284) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_STATUS //// + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000288) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000288) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_MISC //// + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000028c) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000028c) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000290) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000290) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000294) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000294) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002a0) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002a0) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002a4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002a4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002a8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002a8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d0) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d0) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000002d4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000002d4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000002d8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000002d8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_ID //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000002dc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000002dc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000002e0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000002e0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MISC //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000002e4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000002e4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002f8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002f8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002fc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002fc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000300) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000300) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000031c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000031c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000320) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000320) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x00000324) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x00000324) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000328) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000328) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x0000032c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x0000032c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000330) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000330) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_ID //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000334) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000334) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000338) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000338) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MISC //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000033c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000033c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000340) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000340) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000344) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000344) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000350) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000350) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000354) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000354) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000358) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000358) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000374) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000374) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000378) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000378) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000037c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000037c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000380) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000380) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000384) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000384) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000388) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000388) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_ID //// + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000038c) +#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000038c) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_STATUS //// + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000390) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000390) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_MISC //// + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000394) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000394) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000398) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000398) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000039c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000039c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003a8) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003a8) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003ac) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003ac) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b0) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b0) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003d8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003d8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000003dc) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000003dc) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000003e0) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000003e0) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000003e4) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000003e4) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register TCL_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000003e8) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000003e8) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000003ec) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000003ec) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000003f0) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000003f0) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000003f4) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000003f4) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000003f8) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000003f8) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000003fc) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000003fc) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000400) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000400) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000404) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000404) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x0000040c) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x0000040c) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000410) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000410) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000414) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000414) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_SIZE //// + +#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000418) +#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000418) +#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff +#define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) +#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_SEARCH_CTRL //// + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x0000041c) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x0000041c) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff03ff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 + +//// Register TCL_R0_ASE_WATCHDOG //// + +#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000420) +#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000420) +#define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) +#define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_ASE_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000424) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000424) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_WRITE_BACK_PENDING //// + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000428) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000428) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 + +//// Register TCL_R0_FSE_GST_BASE_ADDR_LOW //// + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x0000042c) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x0000042c) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT 0 +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH //// + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000430) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000430) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT 0 +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_GST_SIZE //// + +#define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x) (x+0x00000434) +#define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x) (x+0x00000434) +#define HWIO_TCL_R0_FSE_GST_SIZE_RMSK 0x000fffff +#define HWIO_TCL_R0_FSE_GST_SIZE_SHFT 0 +#define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) +#define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) +#define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff +#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_SEARCH_CTRL //// + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x) (x+0x00000438) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x) (x+0x00000438) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK 0xffff03ff +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT 0 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 + +//// Register TCL_R0_FSE_WATCHDOG //// + +#define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x) (x+0x0000043c) +#define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x) (x+0x0000043c) +#define HWIO_TCL_R0_FSE_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) +#define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_FSE_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x) (x+0x00000440) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x) (x+0x00000440) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_WRITE_BACK_PENDING //// + +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000444) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000444) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK 0x00000001 +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT 0 +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 + +//// Register TCL_R1_SM_STATES_IX_0 //// + +#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) +#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) +#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff +#define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) +#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 + +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 + +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 + +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc + +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 + +//// Register TCL_R1_SM_STATES_IX_1 //// + +#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) +#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) +#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x00007fff +#define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) +#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_CTRL_0 //// + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x1fffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f +#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_LOW //// + +#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) +#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_HIGH //// + +#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) +#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_0 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) +#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) +#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_1 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_2 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_3 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 + +//// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register TCL_R1_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_ASE_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 + +//// Register TCL_R1_ASE_SM_STATES //// + +#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff +#define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 +#define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) +#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) +#define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 + +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 + +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 + +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 + +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 + +//// Register TCL_R1_FSE_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x) (x+0x000010d0) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x) (x+0x000010d0) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS //// + +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x000010d4) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x000010d4) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x000010d8) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x000010d8) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x000010dc) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x000010dc) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x000010e0) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x000010e0) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa + +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x000010e4) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x000010e4) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 + +//// Register TCL_R1_FSE_SM_STATES //// + +#define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x) (x+0x000010e8) +#define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x) (x+0x000010e8) +#define HWIO_TCL_R1_FSE_SM_STATES_RMSK 0x003fffff +#define HWIO_TCL_R1_FSE_SM_STATES_SHFT 0 +#define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) +#define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) +#define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 +#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 + +#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 +#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 + +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 + +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 + +#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f +#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 + +//// Register TCL_R1_FSE_CACHE_DEBUG //// + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x) (x+0x000010ec) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x) (x+0x000010ec) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK 0x000003ff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT 0 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 + +//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS //// + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x000010f0) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x000010f0) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 + +//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n //// + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x10F4+0x4*n) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x10F4+0x4*n) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT 0 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 + +//// Register TCL_R2_SW2TCL1_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL1_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL2_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL2_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL3_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL3_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL_CMD_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL_CMD_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_FW2TCL1_RING_HP //// + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_FW2TCL1_RING_TP //// + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2TQM_RING_HP //// + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2TQM_RING_TP //// + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS1_RING_HP //// + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS1_RING_TP //// + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS2_RING_HP //// + +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS2_RING_TP //// + +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2FW_RING_HP //// + +#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) +#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) +#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2FW_RING_TP //// + +#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) +#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) +#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/hw/qca6290/v1/msmhwio.h b/hw/qca6290/v1/msmhwio.h new file mode 100644 index 000000000000..23223cfdc9a1 --- /dev/null +++ b/hw/qca6290/v1/msmhwio.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef MSMHWIO_H +#define MSMHWIO_H +/* +=========================================================================== +*/ +/** + @file msmhwio.h + + Deprecated public interface include file for accessing the HWIO macro + definitions. + + The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO) + register access definitions. See HALhwio.h and DDIHWIO.h for the new + interfaces. +*/ +/* + ==================================================================== + $Header: //components/rel/core.mpss/3.9.2/api/systemdrivers/msmhwio.h#1 $ $DateTime: 2016/01/19 23:36:58 $ $Author: pwbldsvc $ + ==================================================================== +*/ + +/*========================================================================= + Include Files +==========================================================================*/ + +/* + * Include main HWIO macros. + */ +#include "HALhwio.h" + + +#endif /* MSMHWIO_H */ + diff --git a/hw/qca6290/v1/reo_destination_ring.h b/hw/qca6290/v1/reo_destination_ring.h new file mode 100644 index 000000000000..fd6900d858a0 --- /dev/null +++ b/hw/qca6290/v1/reo_destination_ring.h @@ -0,0 +1,730 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_msdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; +// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +// 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; +// 6 rx_reo_queue_desc_addr_31_0[31:0] +// 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] +// 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_DESTINATION_RING 16 + +struct reo_destination_ring { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + reo_dest_buffer_type : 1, //[8] + reo_push_reason : 2, //[10:9] + reo_error_code : 5, //[15:11] + receive_queue_number : 16; //[31:16] + uint32_t soft_reorder_info_valid : 1, //[0] + reorder_opcode : 4, //[4:1] + reorder_slot_index : 8, //[12:5] + reserved_8a : 19; //[31:13] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15 : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info buf_or_link_desc_addr_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Details of the physical address of the a buffer or MSDU + link descriptor + +struct rx_mpdu_desc_info rx_mpdu_desc_info_details + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + General information related to the MPDU that is passed + on from REO entrance ring to the REO destination ring + +struct rx_msdu_desc_info rx_msdu_desc_info_details + + General information related to the MSDU that is passed + on from RXDMA all the way to to the REO destination ring. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + + +reo_dest_buffer_type + + Indicates the type of address provided in the + 'Buf_or_link_desc_addr_info' + + + + The address of an MSDU buffer + + The address of the MSDU + link descriptor. + + + + + +reo_push_reason + + Indicates why REO pushed the frame to this exit ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + + + +reo_error_code + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + + +receive_queue_number + + This field indicates the REO MPDU reorder queue ID from + which this frame originated. This field is populated from a + field with the same name in the RX_REO_QUEUE descriptor. + + + +soft_reorder_info_valid + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes + + + +reorder_opcode + + Field is valid when 'Soft_reorder_info_valid' is set. + This field is always valid for debug purpose as well. + + Details are in the MLD. + + + + + + + + + + + + + + + + + + + + + + the error reason code is in + reo_error_code field. + + + + + + + + + + + + + + + + + +reorder_slot_index + + Field only valid when 'Soft_reorder_info_valid' is set. + + + + TODO: add description + + + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15 + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 +#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 +#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 +#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + +*/ +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + +*/ +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE + + Indicates the type of address provided in the + 'Buf_or_link_desc_addr_info' + + + + The address of an MSDU buffer + + The address of the MSDU + link descriptor. + + + + +*/ +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 + +/* Description REO_DESTINATION_RING_7_REO_PUSH_REASON + + Indicates why REO pushed the frame to this exit ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + + +*/ +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 + +/* Description REO_DESTINATION_RING_7_REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + +*/ +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 + +/* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER + + This field indicates the REO MPDU reorder queue ID from + which this frame originated. This field is populated from a + field with the same name in the RX_REO_QUEUE descriptor. + + +*/ +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + +/* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes + + +*/ +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 + +/* Description REO_DESTINATION_RING_8_REORDER_OPCODE + + Field is valid when 'Soft_reorder_info_valid' is set. + This field is always valid for debug purpose as well. + + Details are in the MLD. + + + + + + + + + + + + + + + + + + + + + + the error reason code is in + reo_error_code field. + + + + + + + + + + + + + + + + +*/ +#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e + +/* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX + + Field only valid when 'Soft_reorder_info_valid' is set. + + + + TODO: add description + + + + +*/ +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 + +/* Description REO_DESTINATION_RING_8_RESERVED_8A + + +*/ +#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 13 +#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffffe000 + +/* Description REO_DESTINATION_RING_9_RESERVED_9A + + +*/ +#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0 +#define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_10_RESERVED_10A + + +*/ +#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 +#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_11_RESERVED_11A + + +*/ +#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 +#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_12_RESERVED_12A + + +*/ +#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 +#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_13_RESERVED_13A + + +*/ +#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 +#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_14_RESERVED_14A + + +*/ +#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 +#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_15_RESERVED_15 + + +*/ +#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 +#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff + +/* Description REO_DESTINATION_RING_15_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RING_ID_LSB 20 +#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 + +/* Description REO_DESTINATION_RING_15_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_DESTINATION_RING_H_ diff --git a/hw/qca6290/v1/reo_entrance_ring.h b/hw/qca6290/v1/reo_entrance_ring.h new file mode 100644 index 000000000000..8b3f4e9fccc9 --- /dev/null +++ b/hw/qca6290/v1/reo_entrance_ring.h @@ -0,0 +1,722 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; +// 4 rx_reo_queue_desc_addr_31_0[31:0] +// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] +// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7] +// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + rounded_mpdu_byte_count : 14, //[21:8] + reo_destination_indication : 5, //[26:22] + frameless_bar : 1, //[27] + reserved_5a : 4; //[31:28] + uint32_t rxdma_push_reason : 2, //[1:0] + rxdma_error_code : 5, //[6:2] + reserved_6a : 25; //[31:7] + uint32_t reserved_7a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct rx_mpdu_details reo_level_mpdu_frame_info + + Consumer: REO + + Producer: RXDMA + + + + Details related to the MPDU being pushed into the REO + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + + +rounded_mpdu_byte_count + + An approximation of the number of bytes received in this + MPDU. + + Used to keeps stats on the amount of data flowing + through a queue. + + + +reo_destination_indication + + RXDMA copy the MPDU's first MSDU's destination + indication field here. This is used for REO to be able to + re-route the packet to a different SW destination ring if + the packet is detected as error in REO. + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +frameless_bar + + When set, this REO entrance ring struct contains BAR + info from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is set are: + + Rx_reo_queue_desc_addr_31_0 + + RX_reo_queue_desc_addr_39_32 + + + + And within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0 + + + + + +reserved_5a + + + +rxdma_push_reason + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + This field is ignored by REO. + + + +rxdma_error_code + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + This field is ignored by REO. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + +reserved_6a + + + +reserved_7a + + + +ring_id + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff +#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff +#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff +#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + +*/ +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + +*/ +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT + + An approximation of the number of bytes received in this + MPDU. + + Used to keeps stats on the amount of data flowing + through a queue. + + +*/ +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION + + RXDMA copy the MPDU's first MSDU's destination + indication field here. This is used for REO to be able to + re-route the packet to a different SW destination ring if + the packet is detected as error in REO. + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR + + When set, this REO entrance ring struct contains BAR + info from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is set are: + + Rx_reo_queue_desc_addr_31_0 + + RX_reo_queue_desc_addr_39_32 + + + + And within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0 + + + + +*/ +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 + +/* Description REO_ENTRANCE_RING_5_RESERVED_5A + + +*/ +#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 + +/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + This field is ignored by REO. + + +*/ +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + This field is ignored by REO. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request +*/ +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +/* Description REO_ENTRANCE_RING_6_RESERVED_6A + + +*/ +#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 7 +#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xffffff80 + +/* Description REO_ENTRANCE_RING_7_RESERVED_7A + + +*/ +#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0 +#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff + +/* Description REO_ENTRANCE_RING_7_RING_ID + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_ENTRANCE_RING_H_ diff --git a/hw/qca6290/v1/reo_get_queue_stats.h b/hw/qca6290/v1/reo_get_queue_stats.h new file mode 100644 index 000000000000..6cc4b0728ea8 --- /dev/null +++ b/hw/qca6290/v1/reo_get_queue_stats.h @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 rx_reo_queue_desc_addr_31_0[31:0] +// 2 rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + clear_stats : 1, //[8] + reserved_2a : 23; //[31:9] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + + +clear_stats + + Clear stat settings.... + + + + Do NOT clear the stats after + generating the status + + Clear the stats after + generating the status. + + + + The stats actually cleared are: + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + +#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 +#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + +*/ +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + +*/ +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_GET_QUEUE_STATS_2_CLEAR_STATS + + Clear stat settings.... + + + + Do NOT clear the stats after + generating the status + + Clear the stats after + generating the status. + + + + The stats actually cleared are: + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + +*/ +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 + +/* Description REO_GET_QUEUE_STATS_2_RESERVED_2A + + +*/ +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 + +/* Description REO_GET_QUEUE_STATS_3_RESERVED_3A + + +*/ +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_4_RESERVED_4A + + +*/ +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_5_RESERVED_5A + + +*/ +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_6_RESERVED_6A + + +*/ +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_7_RESERVED_7A + + +*/ +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_8_RESERVED_8A + + +*/ +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_GET_QUEUE_STATS_H_ diff --git a/hw/qca6290/v1/reo_get_queue_stats_status.h b/hw/qca6290/v1/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..cf89d0d4d64a --- /dev/null +++ b/hw/qca6290/v1/reo_get_queue_stats_status.h @@ -0,0 +1,868 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 ssn[11:0], current_index[19:12], reserved_2[31:20] +// 3 pn_31_0[31:0] +// 4 pn_63_32[31:0] +// 5 pn_95_64[31:0] +// 6 pn_127_96[31:0] +// 7 last_rx_enqueue_timestamp[31:0] +// 8 last_rx_dequeue_timestamp[31:0] +// 9 rx_bitmap_31_0[31:0] +// 10 rx_bitmap_63_32[31:0] +// 11 rx_bitmap_95_64[31:0] +// 12 rx_bitmap_127_96[31:0] +// 13 rx_bitmap_159_128[31:0] +// 14 rx_bitmap_191_160[31:0] +// 15 rx_bitmap_223_192[31:0] +// 16 rx_bitmap_255_224[31:0] +// 17 current_mpdu_count[6:0], current_msdu_count[31:7] +// 18 reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] +// 19 frames_in_order_count[23:0], bar_received_count[31:24] +// 20 mpdu_frames_processed_count[31:0] +// 21 msdu_frames_processed_count[31:0] +// 22 total_processed_byte_count[31:0] +// 23 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25 + +struct reo_get_queue_stats_status { + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, //[11:0] + current_index : 8, //[19:12] + reserved_2 : 12; //[31:20] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t last_rx_enqueue_timestamp : 32; //[31:0] + uint32_t last_rx_dequeue_timestamp : 32; //[31:0] + uint32_t rx_bitmap_31_0 : 32; //[31:0] + uint32_t rx_bitmap_63_32 : 32; //[31:0] + uint32_t rx_bitmap_95_64 : 32; //[31:0] + uint32_t rx_bitmap_127_96 : 32; //[31:0] + uint32_t rx_bitmap_159_128 : 32; //[31:0] + uint32_t rx_bitmap_191_160 : 32; //[31:0] + uint32_t rx_bitmap_223_192 : 32; //[31:0] + uint32_t rx_bitmap_255_224 : 32; //[31:0] + uint32_t current_mpdu_count : 7, //[6:0] + current_msdu_count : 25; //[31:7] + uint32_t reserved_18 : 4, //[3:0] + timeout_count : 6, //[9:4] + forward_due_to_bar_count : 6, //[15:10] + duplicate_count : 16; //[31:16] + uint32_t frames_in_order_count : 24, //[23:0] + bar_received_count : 8; //[31:24] + uint32_t mpdu_frames_processed_count : 32; //[31:0] + uint32_t msdu_frames_processed_count : 32; //[31:0] + uint32_t total_processed_byte_count : 32; //[31:0] + uint32_t late_receive_mpdu_count : 12, //[11:0] + window_jump_2k : 4, //[15:12] + hole_count : 16; //[31:16] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +ssn + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + + +current_index + + Points to last forwarded packet + + + +reserved_2 + + + +pn_31_0 + + + + +pn_63_32 + + Bits [63:32] of the PN number. + + + +pn_95_64 + + Bits [95:64] of the PN number. + + + +pn_127_96 + + Bits [127:96] of the PN number. + + + +last_rx_enqueue_timestamp + + Timestamp of arrival of the last MPDU for this queue + + + +last_rx_dequeue_timestamp + + Timestamp of forwarding an MPDU + + + + If the queue is empty when a frame gets received, this + time shall be initialized to the 'enqueue' timestamp + + + + Used for aging + + + +rx_bitmap_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + + +rx_bitmap_63_32 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_95_64 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_127_96 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_159_128 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_191_160 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_223_192 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_255_224 + + See Rx_bitmap_31_0 description + + + +current_mpdu_count + + The number of MPDUs in the queue. + + + + + +current_msdu_count + + The number of MSDUs in the queue. + + + +reserved_18 + + + +timeout_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + + +forward_due_to_bar_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + + +duplicate_count + + The number of duplicate frames that have been detected + + + +frames_in_order_count + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + + +bar_received_count + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + + +mpdu_frames_processed_count + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + + + + +msdu_frames_processed_count + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + + + + +total_processed_byte_count + + An approximation of the number of bytes received for + this queue. + + + + In 64 byte units + + + +late_receive_mpdu_count + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + + +window_jump_2k + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + + +hole_count + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff +#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_2_SSN + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff + +/* Description REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX + + Points to last forwarded packet + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000 + +/* Description REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2 + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000 + +/* Description REO_GET_QUEUE_STATS_STATUS_3_PN_31_0 + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_4_PN_63_32 + + Bits [63:32] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_5_PN_95_64 + + Bits [95:64] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_6_PN_127_96 + + Bits [127:96] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP + + Timestamp of arrival of the last MPDU for this queue + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP + + Timestamp of forwarding an MPDU + + + + If the queue is empty when a frame gets received, this + time shall be initialized to the 'enqueue' timestamp + + + + Used for aging + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f + +/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18 + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f + +/* Description REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT + + The number of duplicate frames that have been detected + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000 + +/* Description REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes received for + this queue. + + + + In 64 byte units + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +/* Description REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000 + +/* Description REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_GET_QUEUE_STATS_STATUS_H_ diff --git a/hw/qca6290/v1/reo_reg_seq_hwiobase.h b/hw/qca6290/v1/reo_reg_seq_hwiobase.h new file mode 100644 index 000000000000..2120cf611a2e --- /dev/null +++ b/hw/qca6290/v1/reo_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __REO_REG_SEQ_BASE_H__ +#define __REO_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/hw/qca6290/v1/reo_reg_seq_hwioreg.h b/hw/qca6290/v1/reo_reg_seq_hwioreg.h new file mode 100644 index 000000000000..263123e3a540 --- /dev/null +++ b/hw/qca6290/v1/reo_reg_seq_hwioreg.h @@ -0,0 +1,8639 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __REO_REG_SEQ_REG_H__ +#define __REO_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "reo_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block REO_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register REO_R0_GENERAL_ENABLE //// + +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) +#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) +#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0x1fffffff +#define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 +#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) +#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) +#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ + out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) +#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x10000000 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1c + +#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x0e000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x19 + +#define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK 0x01c00000 +#define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_SHFT 0x16 + +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00200000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x15 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00100000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x14 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00080000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x13 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00040000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x12 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00020000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x11 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00010000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x10 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00008000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0xf + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00004000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xe + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00002000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xd + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00001000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xc + +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000800 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xb + +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000700 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000080 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x7 + +#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 +#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 + +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 + +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x8 + +//// Register REO_R0_TIMESTAMP //// + +#define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) +#define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) +#define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_SHFT 0 +#define HWIO_REO_R0_TIMESTAMP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) +#define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) +#define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ + out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) +#define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 + +//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x3fffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT 0x1b + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_BMSK 0x07000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_SHFT 0x18 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x00e00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x15 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x001c0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x12 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00038000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0xf + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00007000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0xc + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00000e00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0x9 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x000001c0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x6 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000038 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x3 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 + +//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x0003ffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0xf + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x00007000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0xc + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00000e00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x9 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000001c0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x6 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00000038 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0x3 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000007 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x0 + +//// Register REO_R0_IDLE_REQ_CTRL //// + +#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) +#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) +#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 +#define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) +#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 + +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x) (x+0x0000008c) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_PHYS(x) (x+0x0000008c) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000090) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000090) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x) (x+0x00000098) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_PHYS(x) (x+0x00000098) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x) (x+0x0000009c) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_PHYS(x) (x+0x0000009c) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x) (x+0x000000e4) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_PHYS(x) (x+0x000000e4) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x) (x+0x000000e8) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_PHYS(x) (x+0x000000e8) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x) (x+0x000000f0) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_PHYS(x) (x+0x000000f0) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x) (x+0x000000f4) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_PHYS(x) (x+0x000000f4) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x) (x+0x00000134) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_PHYS(x) (x+0x00000134) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000013c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000013c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000140) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000140) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_ID //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000148) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000148) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_MISC //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000014c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000014c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000194) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000194) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000198) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000198) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_ID //// + +#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) +#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000001a0) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000001a0) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MISC //// + +#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000001a4) +#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000001a4) +#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x000001ec) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x000001ec) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x000001f0) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x000001f0) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_ID //// + +#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) +#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) +#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x000001f8) +#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x000001f8) +#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MISC //// + +#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x000001fc) +#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x000001fc) +#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_DATA //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x00000244) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x00000244) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x00000248) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x00000248) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_ID //// + +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x0000024c) +#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x0000024c) +#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x00000250) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x00000250) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MISC //// + +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x00000254) +#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x00000254) +#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x00000294) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x00000294) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x0000029c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x0000029c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x000002a0) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x000002a0) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_ID //// + +#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x000002a4) +#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x000002a4) +#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x000002a8) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x000002a8) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MISC //// + +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x000002ac) +#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x000002ac) +#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x000002f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x000002f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002f8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002f8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_ID //// + +#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002fc) +#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002fc) +#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x00000300) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x00000300) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MISC //// + +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x00000304) +#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x00000304) +#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x00000344) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x00000344) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x0000034c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x0000034c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x00000350) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x00000350) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_ID //// + +#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x00000354) +#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x00000354) +#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000358) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000358) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MISC //// + +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x0000035c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x0000035c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003a4) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003a4) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x000003a8) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x000003a8) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_ID //// + +#define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x000003ac) +#define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x000003ac) +#define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_STATUS //// + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x000003b0) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x000003b0) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MISC //// + +#define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x000003b4) +#define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x000003b4) +#define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x000003fc) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x000003fc) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000400) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000400) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_ID //// + +#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x00000404) +#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x00000404) +#define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) +#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_STATUS //// + +#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MISC //// + +#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x0000040c) +#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x0000040c) +#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000454) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000454) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000458) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000458) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_ID //// + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x0000045c) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x0000045c) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_STATUS //// + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x00000460) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x00000460) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_MISC //// + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x00000464) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x00000464) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x000004ac) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x000004ac) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x000004b0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x000004b0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_ID //// + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x000004b4) +#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x000004b4) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_STATUS //// + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x000004b8) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x000004b8) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MISC //// + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x000004bc) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x000004bc) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_WATCHDOG_TIMEOUT //// + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x00000504) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x00000504) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x0fff0fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ + out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_BMSK 0x0fff0000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_SHFT 0x10 + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 + +//// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000508) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000508) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_0 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x0000050c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x0000050c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_1 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000510) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000510) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_2 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x00000514) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x00000514) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_3 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000518) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000518) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x0000051c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x0000051c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000520) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000520) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x00000524) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x00000524) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000528) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000528) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x0000052c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x0000052c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000530) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000530) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x00000534) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x00000534) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000538) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000538) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x0000053c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x0000053c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000540) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000540) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x00000544) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x00000544) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x00000548) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x00000548) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x0000054c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x0000054c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x00000550) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x00000550) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x00000554) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x00000554) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x00000558) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x00000558) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x0000055c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x0000055c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x00000560) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x00000560) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x00000564) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x00000564) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x00000568) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x00000568) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_0 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x0000056c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x0000056c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_1 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x00000570) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x00000570) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_2 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x00000574) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x00000574) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_3 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x00000578) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x00000578) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_CONTROL //// + +#define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x0000057c) +#define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x0000057c) +#define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f +#define HWIO_REO_R0_AGING_CONTROL_SHFT 0 +#define HWIO_REO_R0_AGING_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) +#define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_HIGH_MEMORY_THRESHOLD //// + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x00000580) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x00000580) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ + out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_0 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x00000584) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x00000584) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_1 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x00000588) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x00000588) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_2 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x0000058c) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x0000058c) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_3 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x00000590) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x00000590) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x00000594) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x00000594) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x00000598) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x00000598) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x0000059c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x0000059c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005a0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005a0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x000005a4) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x000005a4) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x000005a8) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x000005a8) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x000005ac) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x000005ac) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x000005b0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x000005b0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x000005b4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x000005b4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x000005b8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x000005b8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x000005bc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x000005bc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x000005c0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x000005c0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x000005c4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x000005c4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x000005c8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x000005c8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x000005cc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x000005cc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x000005d0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x000005d0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x000005d4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x000005d4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 + +//// Register REO_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000005d8) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000005d8) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000005dc) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000005dc) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000005e0) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000005e0) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register REO_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000005e4) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000005e4) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000005e8) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000005e8) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000005ec) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000005ec) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000005f0) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000005f0) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000005f4) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000005f4) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000005f8) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000005f8) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000005fc) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000005fc) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000600) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000600) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000604) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000604) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000608) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000608) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONFIG //// + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x0000060c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x0000060c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0x003f7fff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00200000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x15 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00100000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x14 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00080000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x13 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00040000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x12 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00020000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x11 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00010000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x10 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x00007f00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x8 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000000ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONTROL //// + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x00000610) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x00000610) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000001 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 + +//// Register REO_R0_CLK_GATE_CTRL //// + +#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000614) +#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000614) +#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff +#define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 +#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) +#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_BMSK 0x00001000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_SHFT 0xc + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_BMSK 0x00000800 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_SHFT 0xb + +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_0 //// + +#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x00000618) +#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x00000618) +#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_1 //// + +#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x0000061c) +#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x0000061c) +#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_2 //// + +#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x00000620) +#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x00000620) +#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_3 //// + +#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x00000624) +#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x00000624) +#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 + +//// Register REO_R1_MISC_DEBUG_CTRL //// + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0x3fffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 + +//// Register REO_R1_MISC_PERF_DEBUG_CTRL //// + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000200 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0x9 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000100 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0x8 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000080 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x7 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x0000007f +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0x03ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0x03ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_STM //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_BMSK 0xff000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_SHFT 0x18 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_BMSK 0x00ff0000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_SHFT 0x10 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0000ff00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0x8 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000000ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x00002024) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x00002024) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R1_END_OF_TEST_CHECK //// + +#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002028) +#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002028) +#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R1_SM_ALL_IDLE //// + +#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x0000202c) +#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x0000202c) +#define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 +#define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 +#define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) +#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) +#define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) +#define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 + +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 + +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 + +//// Register REO_R1_TESTBUS_CTRL //// + +#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002030) +#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002030) +#define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f +#define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) +#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 + +//// Register REO_R1_TESTBUS_LOWER //// + +#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002034) +#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002034) +#define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 +#define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) +#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register REO_R1_TESTBUS_HIGHER //// + +#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002038) +#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002038) +#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff +#define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 +#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) +#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_0 //// + +#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x0000203c) +#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x0000203c) +#define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_1 //// + +#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002040) +#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002040) +#define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_2 //// + +#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x00002044) +#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x00002044) +#define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_3 //// + +#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002048) +#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002048) +#define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_4 //// + +#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x0000204c) +#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x0000204c) +#define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_5 //// + +#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002050) +#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002050) +#define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_6 //// + +#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 + +//// Register REO_R1_IDLE_STATES_IX_0 //// + +#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002058) +#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002058) +#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 +#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) +#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 + +//// Register REO_R1_INVALID_APB_ACCESS //// + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x0000205c) +#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x0000205c) +#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 +#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) +#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ + out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO0_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO0_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO1_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x) (x+0x00003008) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_PHYS(x) (x+0x00003008) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO1_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x) (x+0x0000300c) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_PHYS(x) (x+0x0000300c) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO2_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x) (x+0x00003010) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_PHYS(x) (x+0x00003010) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO2_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x) (x+0x00003014) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_PHYS(x) (x+0x00003014) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_WBM2REO_LINK_RING_HP //// + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_WBM2REO_LINK_RING_TP //// + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_CMD_RING_HP //// + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003020) +#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003020) +#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) +#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_CMD_RING_TP //// + +#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003024) +#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003024) +#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) +#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO_RING_HP //// + +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003028) +#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003028) +#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 +#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) +#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO_RING_TP //// + +#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000302c) +#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000302c) +#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 +#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) +#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW1_RING_HP //// + +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003030) +#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003030) +#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW1_RING_TP //// + +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x00003034) +#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x00003034) +#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW2_RING_HP //// + +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003038) +#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003038) +#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW2_RING_TP //// + +#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x0000303c) +#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x0000303c) +#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW3_RING_HP //// + +#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003040) +#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003040) +#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW3_RING_TP //// + +#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x00003044) +#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x00003044) +#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW4_RING_HP //// + +#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003048) +#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003048) +#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW4_RING_TP //// + +#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x0000304c) +#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x0000304c) +#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2TCL_RING_HP //// + +#define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003050) +#define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003050) +#define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) +#define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2TCL_RING_TP //// + +#define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x00003054) +#define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x00003054) +#define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) +#define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2FW_RING_HP //// + +#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003058) +#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003058) +#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) +#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2FW_RING_TP //// + +#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x0000305c) +#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x0000305c) +#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) +#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_RELEASE_RING_HP //// + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003060) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003060) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_RELEASE_RING_TP //// + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003064) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003064) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_STATUS_RING_HP //// + +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003068) +#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003068) +#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) +#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_STATUS_RING_TP //// + +#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x0000306c) +#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x0000306c) +#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) +#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/hw/qca6290/v1/rx_attention.h b/hw/qca6290/v1/rx_attention.h new file mode 100644 index 000000000000..bc5f09901acd --- /dev/null +++ b/hw/qca6290/v1/rx_attention.h @@ -0,0 +1,1168 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31] +// 2 flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t first_mpdu : 1, //[0] + reserved_1a : 1, //[1] + mcast_bcast : 1, //[2] + ast_index_not_found : 1, //[3] + ast_index_timeout : 1, //[4] + power_mgmt : 1, //[5] + non_qos : 1, //[6] + null_data : 1, //[7] + mgmt_type : 1, //[8] + ctrl_type : 1, //[9] + more_data : 1, //[10] + eosp : 1, //[11] + a_msdu_error : 1, //[12] + fragment_flag : 1, //[13] + order : 1, //[14] + cce_match : 1, //[15] + overflow_err : 1, //[16] + msdu_length_err : 1, //[17] + tcp_udp_chksum_fail : 1, //[18] + ip_chksum_fail : 1, //[19] + sa_idx_invalid : 1, //[20] + da_idx_invalid : 1, //[21] + reserved_1b : 1, //[22] + rx_in_tx_decrypt_byp : 1, //[23] + encrypt_required : 1, //[24] + directed : 1, //[25] + buffer_fragment : 1, //[26] + mpdu_length_err : 1, //[27] + tkip_mic_err : 1, //[28] + decrypt_err : 1, //[29] + unencrypted_frame_err : 1, //[30] + fcs_err : 1; //[31] + uint32_t flow_idx_timeout : 1, //[0] + flow_idx_invalid : 1, //[1] + wifi_parser_error : 1, //[2] + amsdu_parser_error : 1, //[3] + sa_idx_timeout : 1, //[4] + da_idx_timeout : 1, //[5] + msdu_limit_error : 1, //[6] + da_is_valid : 1, //[7] + da_is_mcbc : 1, //[8] + sa_is_valid : 1, //[9] + decrypt_status_code : 3, //[12:10] + rx_bitmap_not_updated : 1, //[13] + reserved_2 : 17, //[30:14] + msdu_done : 1; //[31] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +first_mpdu + + Indicates the first MSDU of the PPDU. If both + first_mpdu and last_mpdu are set in the MSDU then this is a + not an A-MPDU frame but a stand alone MPDU. Interior MPDU + in an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. + +reserved_1a + + + +mcast_bcast + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when + first_msdu is set. + +ast_index_not_found + + Only valid when first_msdu is set. + + + + Indicates no AST matching entries within the the max + search count. + +ast_index_timeout + + Only valid when first_msdu is set. + + + + Indicates an unsuccessful search in the address seach + table due to timeout. + +power_mgmt + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. + +non_qos + + Set if packet is not a non-QoS data frame. Only set + when first_msdu is set. + +null_data + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. + +mgmt_type + + Set if packet is a management packet. Only set when + first_msdu is set. + +ctrl_type + + Set if packet is a control packet. Only set when + first_msdu is set. + +more_data + + Set if more bit in frame control is set. Only set when + first_msdu is set. + +eosp + + Set if the EOSP (end of service period) bit in the QoS + control field is set. Only set when first_msdu is set. + +a_msdu_error + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this MPDU + without decapsulation. + +fragment_flag + + Indicates that this is an 802.11 fragment frame. This + is set when either the more_frag bit is set in the frame + control or the fragment number is not zero. Only set when + first_msdu is set. + +order + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. + +cce_match + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. + +overflow_err + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time + +msdu_length_err + + Indicates that the MSDU length from the 802.3 + encapsulated length field extends beyond the MPDU boundary + or if the length is less than 14 bytes. + + Merged with original other_msdu_err: Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated but + will be DMA'ed in RAW format as a single MSDU buffer + +tcp_udp_chksum_fail + + Indicates that the computed checksum (tcp_udp_chksum) + did not match the checksum in the TCP/UDP header. + +ip_chksum_fail + + Indicates that the computed checksum did not match the + checksum in the IP header. + +sa_idx_invalid + + Indicates no matching entry was found in the address + search table for the source MAC address. + +da_idx_invalid + + Indicates no matching entry was found in the address + search table for the destination MAC address. + +reserved_1b + + +rx_in_tx_decrypt_byp + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. + +encrypt_required + + Indicates that this data type frame is not encrypted + even if the policy for this MPDU requires encryption as + indicated in the peer entry key type. + +directed + + MPDU is a directed packet which means that the RA + matched our STA addresses. In proxySTA it means that the TA + matched an entry in our address search table with the + corresponding no_ack bit is the address search entry + cleared. + +buffer_fragment + + Indicates that at least one of the rx buffers has been + fragmented. If set the FW should look at the rx_frag_info + descriptor described below. + +mpdu_length_err + + Indicates that the MPDU was pre-maturely terminated + resulting in a truncated MPDU. Don't trust the MPDU length + field. + +tkip_mic_err + + Indicates that the MPDU Michael integrity check failed + +decrypt_err + + Indicates that the MPDU decrypt integrity check failed + +unencrypted_frame_err + + Copied here by RX OLE from the RX_MPDU_END TLV + +fcs_err + + Indicates that the MPDU FCS check failed + +flow_idx_timeout + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + + +flow_idx_invalid + + flow id is not valid + + + +wifi_parser_error + + TODO: add details to the description + + + +amsdu_parser_error + + A-MSDU could not be properly de-agregated. + + + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. + +msdu_limit_error + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decasulated but will be DMA'ed in RAW format as a single + MSDU buffer + +da_is_valid + + Indicates that OLE found a valid DA entry + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. + +sa_is_valid + + Indicates that OLE found a valid SA entry + +decrypt_status_code + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + + +rx_bitmap_not_updated + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + + +reserved_2 + + + +msdu_done + + If set indicates that the RX packet data, RX header + data, RX PPDU start descriptor, RX MPDU start/end + descriptor, RX MSDU start/end descriptors and RX Attention + descriptor are all valid. This bit must be in the last + octet of the descriptor. +*/ + + +/* Description RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_ATTENTION_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_ATTENTION_0_RESERVED_0 + + +*/ +#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_0_RESERVED_0_LSB 9 +#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_ATTENTION_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_ATTENTION_1_FIRST_MPDU + + Indicates the first MSDU of the PPDU. If both + first_mpdu and last_mpdu are set in the MSDU then this is a + not an A-MPDU frame but a stand alone MPDU. Interior MPDU + in an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. +*/ +#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_1_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 + +/* Description RX_ATTENTION_1_RESERVED_1A + + +*/ +#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1A_LSB 1 +#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 + +/* Description RX_ATTENTION_1_MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_1_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 + +/* Description RX_ATTENTION_1_AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + + + Indicates no AST matching entries within the the max + search count. +*/ +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +/* Description RX_ATTENTION_1_AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + + + Indicates an unsuccessful search in the address seach + table due to timeout. +*/ +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 + +/* Description RX_ATTENTION_1_POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ +#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_1_POWER_MGMT_LSB 5 +#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 + +/* Description RX_ATTENTION_1_NON_QOS + + Set if packet is not a non-QoS data frame. Only set + when first_msdu is set. +*/ +#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_1_NON_QOS_LSB 6 +#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 + +/* Description RX_ATTENTION_1_NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ +#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_NULL_DATA_LSB 7 +#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 + +/* Description RX_ATTENTION_1_MGMT_TYPE + + Set if packet is a management packet. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 + +/* Description RX_ATTENTION_1_CTRL_TYPE + + Set if packet is a control packet. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 + +/* Description RX_ATTENTION_1_MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_MORE_DATA_LSB 10 +#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 + +/* Description RX_ATTENTION_1_EOSP + + Set if the EOSP (end of service period) bit in the QoS + control field is set. Only set when first_msdu is set. +*/ +#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_1_EOSP_LSB 11 +#define RX_ATTENTION_1_EOSP_MASK 0x00000800 + +/* Description RX_ATTENTION_1_A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this MPDU + without decapsulation. +*/ +#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 + +/* Description RX_ATTENTION_1_FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This + is set when either the more_frag bit is set in the frame + control or the fragment number is not zero. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 + +/* Description RX_ATTENTION_1_ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ +#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_1_ORDER_LSB 14 +#define RX_ATTENTION_1_ORDER_MASK 0x00004000 + +/* Description RX_ATTENTION_1_CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ +#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_1_CCE_MATCH_LSB 15 +#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 + +/* Description RX_ATTENTION_1_OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time +*/ +#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 + +/* Description RX_ATTENTION_1_MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 + encapsulated length field extends beyond the MPDU boundary + or if the length is less than 14 bytes. + + Merged with original other_msdu_err: Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated but + will be DMA'ed in RAW format as a single MSDU buffer +*/ +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 + +/* Description RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum) + did not match the checksum in the TCP/UDP header. +*/ +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +/* Description RX_ATTENTION_1_IP_CHKSUM_FAIL + + Indicates that the computed checksum did not match the + checksum in the IP header. +*/ +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 + +/* Description RX_ATTENTION_1_SA_IDX_INVALID + + Indicates no matching entry was found in the address + search table for the source MAC address. +*/ +#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 + +/* Description RX_ATTENTION_1_DA_IDX_INVALID + + Indicates no matching entry was found in the address + search table for the destination MAC address. +*/ +#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 + +/* Description RX_ATTENTION_1_RESERVED_1B + +*/ +#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1B_LSB 22 +#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 + +/* Description RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. +*/ +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +/* Description RX_ATTENTION_1_ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted + even if the policy for this MPDU requires encryption as + indicated in the peer entry key type. +*/ +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 + +/* Description RX_ATTENTION_1_DIRECTED + + MPDU is a directed packet which means that the RA + matched our STA addresses. In proxySTA it means that the TA + matched an entry in our address search table with the + corresponding no_ack bit is the address search entry + cleared. +*/ +#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_1_DIRECTED_LSB 25 +#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 + +/* Description RX_ATTENTION_1_BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been + fragmented. If set the FW should look at the rx_frag_info + descriptor described below. +*/ +#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 + +/* Description RX_ATTENTION_1_MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated + resulting in a truncated MPDU. Don't trust the MPDU length + field. +*/ +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 + +/* Description RX_ATTENTION_1_TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ +#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 + +/* Description RX_ATTENTION_1_DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed +*/ +#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 + +/* Description RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +/* Description RX_ATTENTION_1_FCS_ERR + + Indicates that the MPDU FCS check failed +*/ +#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_FCS_ERR_LSB 31 +#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 + +/* Description RX_ATTENTION_2_FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + +*/ +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +/* Description RX_ATTENTION_2_FLOW_IDX_INVALID + + flow id is not valid + + +*/ +#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 + +/* Description RX_ATTENTION_2_WIFI_PARSER_ERROR + + TODO: add details to the description + + +*/ +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 + +/* Description RX_ATTENTION_2_AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + + +*/ +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 + +/* Description RX_ATTENTION_2_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 + +/* Description RX_ATTENTION_2_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 + +/* Description RX_ATTENTION_2_MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decasulated but will be DMA'ed in RAW format as a single + MSDU buffer +*/ +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 + +/* Description RX_ATTENTION_2_DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ +#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 + +/* Description RX_ATTENTION_2_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. +*/ +#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 + +/* Description RX_ATTENTION_2_SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ +#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 + +/* Description RX_ATTENTION_2_DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + +*/ +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +/* Description RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + +*/ +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +/* Description RX_ATTENTION_2_RESERVED_2 + + +*/ +#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_2_RESERVED_2_LSB 14 +#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 + +/* Description RX_ATTENTION_2_MSDU_DONE + + If set indicates that the RX packet data, RX header + data, RX PPDU start descriptor, RX MPDU start/end + descriptor, RX MSDU start/end descriptors and RX Attention + descriptor are all valid. This bit must be in the last + octet of the descriptor. +*/ +#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_DONE_LSB 31 +#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 + + +#endif // _RX_ATTENTION_H_ diff --git a/hw/qca6290/v1/rx_mpdu_desc_info.h b/hw/qca6290/v1/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..bb9cfdeee1fc --- /dev/null +++ b/hw/qca6290/v1/rx_mpdu_desc_info.h @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], reserved[31] +// 1 peer_meta_data[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { + uint32_t msdu_count : 8, //[7:0] + mpdu_sequence_number : 12, //[19:8] + fragment_flag : 1, //[20] + mpdu_retry_bit : 1, //[21] + ampdu_flag : 1, //[22] + bar_frame : 1, //[23] + pn_fields_contain_valid_info : 1, //[24] + sa_is_valid : 1, //[25] + sa_idx_timeout : 1, //[26] + da_is_valid : 1, //[27] + da_is_mcbc : 1, //[28] + da_idx_timeout : 1, //[29] + raw_mpdu : 1, //[30] + reserved : 1; //[31] + uint32_t peer_meta_data : 32; //[31:0] +}; + +/* + +msdu_count + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + + +mpdu_sequence_number + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + + +fragment_flag + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + + +mpdu_retry_bit + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + + +ampdu_flag + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + + +bar_frame + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + + +pn_fields_contain_valid_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check + +sa_is_valid + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + + +sa_idx_timeout + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + + +da_is_valid + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + + +da_idx_timeout + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + + +raw_mpdu + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + + +reserved + + + +peer_meta_data + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ + + +/* Description RX_MPDU_DESC_INFO_0_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff + +/* Description RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description RX_MPDU_DESC_INFO_0_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000 + +/* Description RX_MPDU_DESC_INFO_0_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000 + +/* Description RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description RX_MPDU_DESC_INFO_0_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000 + +/* Description RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description RX_MPDU_DESC_INFO_0_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000 + +/* Description RX_MPDU_DESC_INFO_0_RESERVED + + +*/ +#define RX_MPDU_DESC_INFO_0_RESERVED_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RESERVED_LSB 31 +#define RX_MPDU_DESC_INFO_0_RESERVED_MASK 0x80000000 + +/* Description RX_MPDU_DESC_INFO_1_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff + + +#endif // _RX_MPDU_DESC_INFO_H_ diff --git a/hw/qca6290/v1/rx_mpdu_details.h b/hw/qca6290/v1/rx_mpdu_details.h new file mode 100644 index 000000000000..279420a43f1c --- /dev/null +++ b/hw/qca6290/v1/rx_mpdu_details.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info msdu_link_desc_addr_info; +// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +}; + +/* + +struct buffer_addr_info msdu_link_desc_addr_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Details of the physical address of the MSDU link + descriptor that contains pointers to MSDUs related to this + MPDU + +struct rx_mpdu_desc_info rx_mpdu_desc_info_details + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + General information related to the MPDU that should be +*/ + +#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff + + +#endif // _RX_MPDU_DETAILS_H_ diff --git a/hw/qca6290/v1/rx_mpdu_end.h b/hw/qca6290/v1/rx_mpdu_end.h new file mode 100644 index 000000000000..924c06be2680 --- /dev/null +++ b/hw/qca6290/v1/rx_mpdu_end.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t reserved_1a : 11, //[10:0] + unsup_ktype_short_frame : 1, //[11] + rx_in_tx_decrypt_byp : 1, //[12] + overflow_err : 1, //[13] + mpdu_length_err : 1, //[14] + tkip_mic_err : 1, //[15] + decrypt_err : 1, //[16] + unencrypted_frame_err : 1, //[17] + pn_fields_contain_valid_info : 1, //[18] + fcs_err : 1, //[19] + msdu_length_err : 1, //[20] + rxdma0_destination_ring : 2, //[22:21] + rxdma1_destination_ring : 2, //[24:23] + decrypt_status_code : 3, //[27:25] + rx_bitmap_not_updated : 1, //[28] + reserved_1b : 3; //[31:29] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +reserved_1a + + + +unsup_ktype_short_frame + + This bit will be '1' when WEP or TKIP or WAPI key type + is received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. + +rx_in_tx_decrypt_byp + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. + +overflow_err + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time + +mpdu_length_err + + Set by RXPCU if the expected MPDU length does not + correspond with the actually received number of bytes in the + MPDU. + +tkip_mic_err + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error + for this MPDU + +decrypt_err + + Set by RX CRYPTO when CRYPTO detected a decrypt error + for this MPDU. + +unencrypted_frame_err + + Set by RX CRYPTO when CRYPTO detected an unencrypted + frame while in the peer entry field + 'All_frames_shall_be_encrypted' is set. + +pn_fields_contain_valid_info + + Set by RX CRYPTO to indicate that there is a valid PN + field present in this MPDU + +fcs_err + + Set by RXPCU when there is an FCS error detected for + this MPDU + +msdu_length_err + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU + +rxdma0_destination_ring + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + + + RXDMA0 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA0 shall push the frame to + the FW ring + + + + RXDMA0 shall push the frame to + the SW ring + + + + RXDMA0 shall push the frame + to the REO entrance ring + + + + + +rxdma1_destination_ring + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + + + RXDMA1 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA1 shall push the frame to + the FW ring + + + + RXDMA1 shall push the frame to + the SW ring + + + + RXDMA1 shall push the frame + to the REO entrance ring + + + + + +decrypt_status_code + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + + +rx_bitmap_not_updated + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + + +reserved_1b + + +*/ + + +/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_END_0_RESERVED_0 + + +*/ +#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_0_RESERVED_0_LSB 9 +#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MPDU_END_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_END_1_RESERVED_1A + + +*/ +#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1A_LSB 0 +#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff + +/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME + + This bit will be '1' when WEP or TKIP or WAPI key type + is received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. +*/ +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. +*/ +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +/* Description RX_MPDU_END_1_OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time +*/ +#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 + +/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR + + Set by RXPCU if the expected MPDU length does not + correspond with the actually received number of bytes in the + MPDU. +*/ +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 + +/* Description RX_MPDU_END_1_TKIP_MIC_ERR + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error + for this MPDU +*/ +#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 + +/* Description RX_MPDU_END_1_DECRYPT_ERR + + Set by RX CRYPTO when CRYPTO detected a decrypt error + for this MPDU. +*/ +#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 + +/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR + + Set by RX CRYPTO when CRYPTO detected an unencrypted + frame while in the peer entry field + 'All_frames_shall_be_encrypted' is set. +*/ +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO + + Set by RX CRYPTO to indicate that there is a valid PN + field present in this MPDU +*/ +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +/* Description RX_MPDU_END_1_FCS_ERR + + Set by RXPCU when there is an FCS error detected for + this MPDU +*/ +#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_FCS_ERR_LSB 19 +#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 + +/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU +*/ +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 + +/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + + + RXDMA0 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA0 shall push the frame to + the FW ring + + + + RXDMA0 shall push the frame to + the SW ring + + + + RXDMA0 shall push the frame + to the REO entrance ring + + + + +*/ +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 + +/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + + + RXDMA1 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA1 shall push the frame to + the FW ring + + + + RXDMA1 shall push the frame to + the SW ring + + + + RXDMA1 shall push the frame + to the REO entrance ring + + + + +*/ +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 + +/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + +*/ +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 + +/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + +*/ +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 + +/* Description RX_MPDU_END_1_RESERVED_1B + + +*/ +#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1B_LSB 29 +#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 + + +#endif // _RX_MPDU_END_H_ diff --git a/hw/qca6290/v1/rx_mpdu_info.h b/hw/qca6290/v1/rx_mpdu_info.h new file mode 100644 index 000000000000..de155604a27c --- /dev/null +++ b/hw/qca6290/v1/rx_mpdu_info.h @@ -0,0 +1,2871 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] +// 1 ast_index[15:0], sw_peer_id[31:16] +// 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] +// 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], mesh_sta[6], bssid_hit[7], bssid_number[11:8], tid[15:12], reserved_3a[31:16] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8 peer_meta_data[31:0] +// 9 struct rxpt_classify_info rxpt_classify_info_details; +// 10 rx_reo_queue_desc_addr_31_0[31:0] +// 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] +// 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] +// 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30] +// 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] +// 15 mac_addr_ad1_31_0[31:0] +// 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] +// 17 mac_addr_ad2_47_16[31:0] +// 18 mac_addr_ad3_31_0[31:0] +// 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] +// 20 mac_addr_ad4_31_0[31:0] +// 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] +// 22 mpdu_ht_control_field[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_INFO 23 + +struct rx_mpdu_info { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + ndp_frame : 1, //[9] + phy_err : 1, //[10] + phy_err_during_mpdu_header : 1, //[11] + protocol_version_err : 1, //[12] + ast_based_lookup_valid : 1, //[13] + reserved_0a : 2, //[15:14] + phy_ppdu_id : 16; //[31:16] + uint32_t ast_index : 16, //[15:0] + sw_peer_id : 16; //[31:16] + uint32_t mpdu_frame_control_valid : 1, //[0] + mpdu_duration_valid : 1, //[1] + mac_addr_ad1_valid : 1, //[2] + mac_addr_ad2_valid : 1, //[3] + mac_addr_ad3_valid : 1, //[4] + mac_addr_ad4_valid : 1, //[5] + mpdu_sequence_control_valid : 1, //[6] + mpdu_qos_control_valid : 1, //[7] + mpdu_ht_control_valid : 1, //[8] + frame_encryption_info_valid : 1, //[9] + reserved_2a : 6, //[15:10] + fr_ds : 1, //[16] + to_ds : 1, //[17] + encrypted : 1, //[18] + mpdu_retry : 1, //[19] + mpdu_sequence_number : 12; //[31:20] + uint32_t epd_en : 1, //[0] + all_frames_shall_be_encrypted : 1, //[1] + encrypt_type : 4, //[5:2] + mesh_sta : 1, //[6] + bssid_hit : 1, //[7] + bssid_number : 4, //[11:8] + tid : 4, //[15:12] + reserved_3a : 16; //[31:16] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t peer_meta_data : 32; //[31:0] + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + receive_queue_number : 16, //[23:8] + pre_delim_err_warning : 1, //[24] + first_delim_err : 1, //[25] + reserved_11 : 6; //[31:26] + uint32_t key_id_octet : 8, //[7:0] + new_peer_entry : 1, //[8] + decrypt_needed : 1, //[9] + decap_type : 2, //[11:10] + rx_insert_vlan_c_tag_padding : 1, //[12] + rx_insert_vlan_s_tag_padding : 1, //[13] + strip_vlan_c_tag_decap : 1, //[14] + strip_vlan_s_tag_decap : 1, //[15] + pre_delim_count : 12, //[27:16] + ampdu_flag : 1, //[28] + bar_frame : 1, //[29] + reserved_12 : 2; //[31:30] + uint32_t mpdu_length : 14, //[13:0] + first_mpdu : 1, //[14] + mcast_bcast : 1, //[15] + ast_index_not_found : 1, //[16] + ast_index_timeout : 1, //[17] + power_mgmt : 1, //[18] + non_qos : 1, //[19] + null_data : 1, //[20] + mgmt_type : 1, //[21] + ctrl_type : 1, //[22] + more_data : 1, //[23] + eosp : 1, //[24] + fragment_flag : 1, //[25] + order : 1, //[26] + u_apsd_trigger : 1, //[27] + encrypt_required : 1, //[28] + directed : 1, //[29] + reserved_13 : 2; //[31:30] + uint32_t mpdu_frame_control_field : 16, //[15:0] + mpdu_duration_field : 16; //[31:16] + uint32_t mac_addr_ad1_31_0 : 32; //[31:0] + uint32_t mac_addr_ad1_47_32 : 16, //[15:0] + mac_addr_ad2_15_0 : 16; //[31:16] + uint32_t mac_addr_ad2_47_16 : 32; //[31:0] + uint32_t mac_addr_ad3_31_0 : 32; //[31:0] + uint32_t mac_addr_ad3_47_32 : 16, //[15:0] + mpdu_sequence_control_field : 16; //[31:16] + uint32_t mac_addr_ad4_31_0 : 32; //[31:0] + uint32_t mac_addr_ad4_47_32 : 16, //[15:0] + mpdu_qos_control_field : 16; //[31:16] + uint32_t mpdu_ht_control_field : 32; //[31:0] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + + +ndp_frame + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + + +phy_err + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + + +phy_err_during_mpdu_header + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + + +protocol_version_err + + Set when RXPCU detected a version error in the Frame + control field + + + +ast_based_lookup_valid + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + + +reserved_0a + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +ast_index + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + + +sw_peer_id + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + + +mpdu_frame_control_valid + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + + +mpdu_duration_valid + + When set, the field Mpdu_duration_field has valid + information + + + + + + +mac_addr_ad1_valid + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + + +mac_addr_ad2_valid + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + + +mac_addr_ad3_valid + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + + +mac_addr_ad4_valid + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + + +mpdu_sequence_control_valid + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + + +mpdu_qos_control_valid + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + + +mpdu_ht_control_valid + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + + +frame_encryption_info_valid + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + + +reserved_2a + + + +fr_ds + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + + +to_ds + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + + +encrypted + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + + +mpdu_retry + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + + +mpdu_sequence_number + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + + +epd_en + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + + +all_frames_shall_be_encrypted + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + + +encrypt_type + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + + + +mesh_sta + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA + + + +bssid_hit + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + + +bssid_number + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + + +tid + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + + +reserved_3a + + + +pn_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + + +pn_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + + +pn_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + + +pn_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + + +peer_meta_data + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + + +struct rxpt_classify_info rxpt_classify_info_details + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + RXOLE related classification info + + + +rx_reo_queue_desc_addr_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + + +receive_queue_number + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + + +pre_delim_err_warning + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + + +first_delim_err + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + + +reserved_11 + + + +key_id_octet + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + +new_peer_entry + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + + +decrypt_needed + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + + +decap_type + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or + 802.3 (uses SNAP/LLC) + + + +rx_insert_vlan_c_tag_padding + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + + +rx_insert_vlan_s_tag_padding + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + + +strip_vlan_c_tag_decap + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + + +strip_vlan_s_tag_decap + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + + +pre_delim_count + + The number of delimiters before this MPDU. + + + + In case of ndp or phy_err, this field will be set to 0 + +ampdu_flag + + When set, received frame was part of an A-MPDU. + + + + + + +bar_frame + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + + +reserved_12 + + . + +mpdu_length + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + + +first_mpdu + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + + +mcast_bcast + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ast_index_not_found + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ast_index_timeout + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +power_mgmt + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +non_qos + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + + +null_data + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +mgmt_type + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ctrl_type + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +more_data + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +eosp + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +fragment_flag + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +order + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + + +u_apsd_trigger + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +encrypt_required + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +directed + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +reserved_13 + + + +mpdu_frame_control_field + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + + +mpdu_duration_field + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + + +mac_addr_ad1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + + +mac_addr_ad1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + + +mac_addr_ad2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + + +mac_addr_ad2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + + +mac_addr_ad3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + + +mac_addr_ad3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + + +mpdu_sequence_control_field + + + + + The sequence control field of the MPDU + + + +mac_addr_ad4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + + +mac_addr_ad4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + + +mpdu_qos_control_field + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + + +mpdu_ht_control_field + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ + + +/* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + +*/ +#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + +*/ +#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_INFO_0_NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + +*/ +#define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 + +/* Description RX_MPDU_INFO_0_PHY_ERR + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + +*/ +#define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 + +/* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + +*/ +#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +/* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame + control field + + +*/ +#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +/* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + +*/ +#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +/* Description RX_MPDU_INFO_0_RESERVED_0A + + +*/ +#define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 +#define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 + +/* Description RX_MPDU_INFO_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_1_AST_INDEX + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + +*/ +#define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_1_SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + +*/ +#define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +/* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid + information + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +/* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +/* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +/* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +/* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +/* Description RX_MPDU_INFO_2_RESERVED_2A + + +*/ +#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RESERVED_2A_LSB 10 +#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x0000fc00 + +/* Description RX_MPDU_INFO_2_FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + +*/ +#define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FR_DS_LSB 16 +#define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 + +/* Description RX_MPDU_INFO_2_TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + +*/ +#define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_TO_DS_LSB 17 +#define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 + +/* Description RX_MPDU_INFO_2_ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + +*/ +#define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 + +/* Description RX_MPDU_INFO_2_MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + +*/ +#define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 + +/* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + +*/ +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +/* Description RX_MPDU_INFO_3_EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + +*/ +#define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_EPD_EN_LSB 0 +#define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 + +/* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + +*/ +#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +/* Description RX_MPDU_INFO_3_ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + + +*/ +#define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c + +/* Description RX_MPDU_INFO_3_MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA + + +*/ +#define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_MESH_STA_LSB 6 +#define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000040 + +/* Description RX_MPDU_INFO_3_BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + +*/ +#define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_BSSID_HIT_LSB 7 +#define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000080 + +/* Description RX_MPDU_INFO_3_BSSID_NUMBER + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + +*/ +#define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 8 +#define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00000f00 + +/* Description RX_MPDU_INFO_3_TID + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + +*/ +#define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_TID_LSB 12 +#define RX_MPDU_INFO_3_TID_MASK 0x0000f000 + +/* Description RX_MPDU_INFO_3_RESERVED_3A + + +*/ +#define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_RESERVED_3A_LSB 16 +#define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_4_PN_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + +*/ +#define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_INFO_4_PN_31_0_LSB 0 +#define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_5_PN_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_INFO_5_PN_63_32_LSB 0 +#define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff + +/* Description RX_MPDU_INFO_6_PN_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_INFO_6_PN_95_64_LSB 0 +#define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff + +/* Description RX_MPDU_INFO_7_PN_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_PN_127_96_LSB 0 +#define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff + +/* Description RX_MPDU_INFO_8_PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff +#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 +#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff + +/* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (lower 32 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +/* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + +*/ +#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +/* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + +*/ +#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 + +/* Description RX_MPDU_INFO_11_RESERVED_11 + + +*/ +#define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RESERVED_11_LSB 26 +#define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 + +/* Description RX_MPDU_INFO_12_KEY_ID_OCTET + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + +*/ +#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + +*/ +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 + +/* Description RX_MPDU_INFO_12_DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + +*/ +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 + +/* Description RX_MPDU_INFO_12_DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or + 802.3 (uses SNAP/LLC) + + +*/ +#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 + +/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + +*/ +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + +*/ +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +/* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + +*/ +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +/* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + +*/ +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +/* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + + + In case of ndp or phy_err, this field will be set to 0 +*/ +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 + +/* Description RX_MPDU_INFO_12_AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + + + + +*/ +#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 + +/* Description RX_MPDU_INFO_12_BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + +*/ +#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 + +/* Description RX_MPDU_INFO_12_RESERVED_12 + + . +*/ +#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RESERVED_12_LSB 30 +#define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 + +/* Description RX_MPDU_INFO_13_MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + +*/ +#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff + +/* Description RX_MPDU_INFO_13_FIRST_MPDU + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + +*/ +#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 + +/* Description RX_MPDU_INFO_13_MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 + +/* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +/* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MPDU_INFO_13_POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 + +/* Description RX_MPDU_INFO_13_NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NON_QOS_LSB 19 +#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 + +/* Description RX_MPDU_INFO_13_NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 + +/* Description RX_MPDU_INFO_13_MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 + +/* Description RX_MPDU_INFO_13_CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 + +/* Description RX_MPDU_INFO_13_MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 + +/* Description RX_MPDU_INFO_13_EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_EOSP_LSB 24 +#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 + +/* Description RX_MPDU_INFO_13_FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 + +/* Description RX_MPDU_INFO_13_ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + +*/ +#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ORDER_LSB 26 +#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 + +/* Description RX_MPDU_INFO_13_U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 + +/* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 + +/* Description RX_MPDU_INFO_13_DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_DIRECTED_LSB 29 +#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 + +/* Description RX_MPDU_INFO_13_RESERVED_13 + + +*/ +#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_RESERVED_13_LSB 30 +#define RX_MPDU_INFO_13_RESERVED_13_MASK 0xc0000000 + +/* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + +*/ +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + +*/ +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +/* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD + + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + +#endif // _RX_MPDU_INFO_H_ diff --git a/hw/qca6290/v1/rx_mpdu_link_ptr.h b/hw/qca6290/v1/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..afd9d7bfeb0d --- /dev/null +++ b/hw/qca6290/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info mpdu_link_desc_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { + struct buffer_addr_info mpdu_link_desc_addr_info; +}; + +/* + +struct buffer_addr_info mpdu_link_desc_addr_info + + Details of the physical address of an MPDU link + descriptor +*/ + +#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff + + +#endif // _RX_MPDU_LINK_PTR_H_ diff --git a/hw/qca6290/v1/rx_mpdu_start.h b/hw/qca6290/v1/rx_mpdu_start.h new file mode 100644 index 000000000000..be5ddfcdc47b --- /dev/null +++ b/hw/qca6290/v1/rx_mpdu_start.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-22 struct rx_mpdu_info rx_mpdu_info_details; +// 23 raw_mpdu[0], reserved_23[31:1] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_START 24 + +struct rx_mpdu_start { + struct rx_mpdu_info rx_mpdu_info_details; + uint32_t raw_mpdu : 1, //[0] + reserved_23 : 31; //[31:1] +}; + +/* + +struct rx_mpdu_info rx_mpdu_info_details + + Structure containing all the MPDU header details that + might be needed for other modules further down the received + path + +raw_mpdu + + Set by OLE when it has not performed any .11 to .3 + header conversion on this MPDU. + + + +reserved_23 + + +*/ + +#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000004 +#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000000c +#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000010 +#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000014 +#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000018 +#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000020 +#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000003c +#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000044 +#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000048 +#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000050 +#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000058 +#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff + +/* Description RX_MPDU_START_23_RAW_MPDU + + Set by OLE when it has not performed any .11 to .3 + header conversion on this MPDU. + + +*/ +#define RX_MPDU_START_23_RAW_MPDU_OFFSET 0x0000005c +#define RX_MPDU_START_23_RAW_MPDU_LSB 0 +#define RX_MPDU_START_23_RAW_MPDU_MASK 0x00000001 + +/* Description RX_MPDU_START_23_RESERVED_23 + + +*/ +#define RX_MPDU_START_23_RESERVED_23_OFFSET 0x0000005c +#define RX_MPDU_START_23_RESERVED_23_LSB 1 +#define RX_MPDU_START_23_RESERVED_23_MASK 0xfffffffe + + +#endif // _RX_MPDU_START_H_ diff --git a/hw/qca6290/v1/rx_msdu_desc_info.h b/hw/qca6290/v1/rx_msdu_desc_info.h new file mode 100644 index 000000000000..1a05ac150c19 --- /dev/null +++ b/hw/qca6290/v1/rx_msdu_desc_info.h @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], reserved_0a[31:28] +// 1 reserved_1a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 + +struct rx_msdu_desc_info { + uint32_t first_msdu_in_mpdu_flag : 1, //[0] + last_msdu_in_mpdu_flag : 1, //[1] + msdu_continuation : 1, //[2] + msdu_length : 14, //[16:3] + reo_destination_indication : 5, //[21:17] + msdu_drop : 1, //[22] + sa_is_valid : 1, //[23] + sa_idx_timeout : 1, //[24] + da_is_valid : 1, //[25] + da_is_mcbc : 1, //[26] + da_idx_timeout : 1, //[27] + reserved_0a : 4; //[31:28] + uint32_t reserved_1a : 32; //[31:0] +}; + +/* + +first_msdu_in_mpdu_flag + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + +last_msdu_in_mpdu_flag + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + +msdu_continuation + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + + +msdu_length + + Field is only valid in combination with the + 'first_msdu_in_mpdu_flag ' being set. When the + 'first_msdu_in_mpdu_flag ' is not set, this field shall be + 0. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +msdu_drop + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + + +sa_is_valid + + Indicates that OLE found a valid SA entry for this MSDU + + + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + + +da_is_valid + + Indicates that OLE found a valid DA entry for this MSDU + + + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + + +reserved_0a + + + +reserved_1a + + +*/ + + +/* Description RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. +*/ +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + +*/ +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_LENGTH + + Field is only valid in combination with the + 'first_msdu_in_mpdu_flag ' being set. When the + 'first_msdu_in_mpdu_flag ' is not set, this field shall be + 0. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_DESC_INFO_0_SA_IS_VALID + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IS_VALID + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_DESC_INFO_0_RESERVED_0A + + +*/ +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_LSB 28 +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_DESC_INFO_1_RESERVED_1A + + +*/ +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_LSB 0 +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_MASK 0xffffffff + + +#endif // _RX_MSDU_DESC_INFO_H_ diff --git a/hw/qca6290/v1/rx_msdu_details.h b/hw/qca6290/v1/rx_msdu_details.h new file mode 100644 index 000000000000..02e52e2d4ed4 --- /dev/null +++ b/hw/qca6290/v1/rx_msdu_details.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_msdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buffer_addr_info_details; +// 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; +}; + +/* + +struct buffer_addr_info buffer_addr_info_details + + Consumer: REO/SW + + Producer: RXDMA + + + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) + +struct rx_msdu_desc_info rx_msdu_desc_info_details + + Consumer: REO/SW + + Producer: RXDMA + + + + General information related to the MSDU that should be + passed on from RXDMA all the way to to the REO destination + ring. +*/ + +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff + + +#endif // _RX_MSDU_DETAILS_H_ diff --git a/hw/qca6290/v1/rx_msdu_end.h b/hw/qca6290/v1/rx_msdu_end.h new file mode 100644 index 000000000000..6a148102f5d3 --- /dev/null +++ b/hw/qca6290/v1/rx_msdu_end.h @@ -0,0 +1,1238 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 ip_hdr_chksum[15:0], tcp_udp_chksum[31:16] +// 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] +// 3 ext_wapi_pn_95_64[31:0] +// 4 ext_wapi_pn_127_96[31:0] +// 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], reserved_5a[31:26] +// 6 ipv6_options_crc[31:0] +// 7 tcp_seq_number[31:0] +// 8 tcp_ack_number[31:0] +// 9 tcp_flag[8:0], lro_eligible[9], l3_header_padding[12:10], reserved_9a[15:13], window_size[31:16] +// 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21] +// 11 rule_indication_31_0[31:0] +// 12 rule_indication_63_32[31:0] +// 13 sa_idx[15:0], da_idx[31:16] +// 14 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26] +// 15 fse_metadata[31:0] +// 16 cce_metadata[15:0], sa_sw_peer_id[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_END 17 + +struct rx_msdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t ip_hdr_chksum : 16, //[15:0] + tcp_udp_chksum : 16; //[31:16] + uint32_t key_id_octet : 8, //[7:0] + cce_super_rule : 6, //[13:8] + cce_classify_not_done_truncate : 1, //[14] + cce_classify_not_done_cce_dis : 1, //[15] + ext_wapi_pn_63_48 : 16; //[31:16] + uint32_t ext_wapi_pn_95_64 : 32; //[31:0] + uint32_t ext_wapi_pn_127_96 : 32; //[31:0] + uint32_t reported_mpdu_length : 14, //[13:0] + first_msdu : 1, //[14] + last_msdu : 1, //[15] + sa_idx_timeout : 1, //[16] + da_idx_timeout : 1, //[17] + msdu_limit_error : 1, //[18] + flow_idx_timeout : 1, //[19] + flow_idx_invalid : 1, //[20] + wifi_parser_error : 1, //[21] + amsdu_parser_error : 1, //[22] + sa_is_valid : 1, //[23] + da_is_valid : 1, //[24] + da_is_mcbc : 1, //[25] + reserved_5a : 6; //[31:26] + uint32_t ipv6_options_crc : 32; //[31:0] + uint32_t tcp_seq_number : 32; //[31:0] + uint32_t tcp_ack_number : 32; //[31:0] + uint32_t tcp_flag : 9, //[8:0] + lro_eligible : 1, //[9] + l3_header_padding : 3, //[12:10] + reserved_9a : 3, //[15:13] + window_size : 16; //[31:16] + uint32_t da_offset : 6, //[5:0] + sa_offset : 6, //[11:6] + da_offset_valid : 1, //[12] + sa_offset_valid : 1, //[13] + type_offset : 7, //[20:14] + reserved_10a : 11; //[31:21] + uint32_t rule_indication_31_0 : 32; //[31:0] + uint32_t rule_indication_63_32 : 32; //[31:0] + uint32_t sa_idx : 16, //[15:0] + da_idx : 16; //[31:16] + uint32_t msdu_drop : 1, //[0] + reo_destination_indication : 5, //[5:1] + flow_idx : 20, //[25:6] + reserved_14 : 6; //[31:26] + uint32_t fse_metadata : 32; //[31:0] + uint32_t cce_metadata : 16, //[15:0] + sa_sw_peer_id : 16; //[31:16] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +ip_hdr_chksum + + This can include the IP header checksum or the pseudo + header checksum used by TCP/UDP checksum. + +tcp_udp_chksum + + The value of the computed TCP/UDP checksum. A mode bit + selects whether this checksum is the full checksum or the + partial checksum which does not include the pseudo header. + +key_id_octet + + The key ID octet from the IV. Only valid when + first_msdu is set. + +cce_super_rule + + Indicates the super filter rule + +cce_classify_not_done_truncate + + Classification failed due to truncated frame + +cce_classify_not_done_cce_dis + + Classification failed due to CCE global disable + +ext_wapi_pn_63_48 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [63:48] (pn6 and pn7). + The WAPI PN bits [63:0] are in the pn field of the + rx_mpdu_start descriptor. + +ext_wapi_pn_95_64 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 + and pn11). + +ext_wapi_pn_127_96 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [127:96] (pn12, pn13, + pn14, pn15). + +reported_mpdu_length + + MPDU length before decapsulation. Only valid when + first_msdu is set. This field is taken directly from the + length field of the A-MPDU delimiter or the preamble length + field for non-A-MPDU frames. + +first_msdu + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a + non-aggregated MSDU frame: normal MPDU. Interior MSDU in an + A-MSDU shall have both first_mpdu and last_mpdu bits set to + 0. + +last_msdu + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. + +msdu_limit_error + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decapsulated but will be DMA'ed in RAW format as a single + MSDU buffer + +flow_idx_timeout + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + + +flow_idx_invalid + + flow id is not valid + + + +wifi_parser_error + + TODO: add details to the description + + + +amsdu_parser_error + + A-MSDU could not be properly de-agregated. + + + +sa_is_valid + + Indicates that OLE found a valid SA entry + +da_is_valid + + Indicates that OLE found a valid DA entry + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. + +reserved_5a + + + +ipv6_options_crc + + 32 bit CRC computed out of IP v6 extension headers + +tcp_seq_number + + TCP sequence number + +tcp_ack_number + + TCP acknowledge number + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} + +lro_eligible + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO + +l3_header_padding + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary + +reserved_9a + + + +window_size + + TCP receive window size + +da_offset + + Offset into MSDU buffer for DA + +sa_offset + + Offset into MSDU buffer for SA + +da_offset_valid + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed + +sa_offset_valid + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed + +type_offset + + Offset into MSDU buffer for Type + +reserved_10a + + + +rule_indication_31_0 + + Bitmap indicating which of rules 31-0 have matched + +rule_indication_63_32 + + Bitmap indicating which of rules 63-32 have matched + +sa_idx + + The offset in the address table which matches the MAC + source address. + +da_idx + + The offset in the address table which matches the MAC + source address + +msdu_drop + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +flow_idx + + Flow table index + + + +reserved_14 + + + +fse_metadata + + FSE related meta data: + + + +cce_metadata + + CCE related meta data: + + + +sa_sw_peer_id + + sw_peer_id from the address search entry corresponding + to the source address of the MSDU + + +*/ + + +/* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MSDU_END_0_RESERVED_0 + + +*/ +#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_0_RESERVED_0_LSB 9 +#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MSDU_END_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MSDU_END_1_IP_HDR_CHKSUM + + This can include the IP header checksum or the pseudo + header checksum used by TCP/UDP checksum. +*/ +#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff + +/* Description RX_MSDU_END_1_TCP_UDP_CHKSUM + + The value of the computed TCP/UDP checksum. A mode bit + selects whether this checksum is the full checksum or the + partial checksum which does not include the pseudo header. +*/ +#define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK 0xffff0000 + +/* Description RX_MSDU_END_2_KEY_ID_OCTET + + The key ID octet from the IV. Only valid when + first_msdu is set. +*/ +#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 +#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MSDU_END_2_CCE_SUPER_RULE + + Indicates the super filter rule +*/ +#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 + +/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE + + Classification failed due to truncated frame +*/ +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS + + Classification failed due to CCE global disable +*/ +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +/* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [63:48] (pn6 and pn7). + The WAPI PN bits [63:0] are in the pn field of the + rx_mpdu_start descriptor. +*/ +#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET 0x00000008 +#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB 16 +#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 + +/* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 + and pn11). +*/ +#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET 0x0000000c +#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB 0 +#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff + +/* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [127:96] (pn12, pn13, + pn14, pn15). +*/ +#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET 0x00000010 +#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB 0 +#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff + +/* Description RX_MSDU_END_5_REPORTED_MPDU_LENGTH + + MPDU length before decapsulation. Only valid when + first_msdu is set. This field is taken directly from the + length field of the A-MPDU delimiter or the preamble length + field for non-A-MPDU frames. +*/ +#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET 0x00000014 +#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB 0 +#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK 0x00003fff + +/* Description RX_MSDU_END_5_FIRST_MSDU + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a + non-aggregated MSDU frame: normal MPDU. Interior MSDU in an + A-MSDU shall have both first_mpdu and last_mpdu bits set to + 0. +*/ +#define RX_MSDU_END_5_FIRST_MSDU_OFFSET 0x00000014 +#define RX_MSDU_END_5_FIRST_MSDU_LSB 14 +#define RX_MSDU_END_5_FIRST_MSDU_MASK 0x00004000 + +/* Description RX_MSDU_END_5_LAST_MSDU + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. +*/ +#define RX_MSDU_END_5_LAST_MSDU_OFFSET 0x00000014 +#define RX_MSDU_END_5_LAST_MSDU_LSB 15 +#define RX_MSDU_END_5_LAST_MSDU_MASK 0x00008000 + +/* Description RX_MSDU_END_5_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ +#define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK 0x00010000 + +/* Description RX_MSDU_END_5_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ +#define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MSDU_END_5_MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decapsulated but will be DMA'ed in RAW format as a single + MSDU buffer +*/ +#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET 0x00000014 +#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB 18 +#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK 0x00040000 + +/* Description RX_MSDU_END_5_FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + +*/ +#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET 0x00000014 +#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB 19 +#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK 0x00080000 + +/* Description RX_MSDU_END_5_FLOW_IDX_INVALID + + flow id is not valid + + +*/ +#define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB 20 +#define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK 0x00100000 + +/* Description RX_MSDU_END_5_WIFI_PARSER_ERROR + + TODO: add details to the description + + +*/ +#define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET 0x00000014 +#define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB 21 +#define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK 0x00200000 + +/* Description RX_MSDU_END_5_AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + + +*/ +#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET 0x00000014 +#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB 22 +#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK 0x00400000 + +/* Description RX_MSDU_END_5_SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ +#define RX_MSDU_END_5_SA_IS_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_5_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_END_5_DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ +#define RX_MSDU_END_5_DA_IS_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_5_DA_IS_VALID_MASK 0x01000000 + +/* Description RX_MSDU_END_5_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. +*/ +#define RX_MSDU_END_5_DA_IS_MCBC_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 + +/* Description RX_MSDU_END_5_RESERVED_5A + + +*/ +#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_5_RESERVED_5A_LSB 26 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0xfc000000 + +/* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC + + 32 bit CRC computed out of IP v6 extension headers +*/ +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff + +/* Description RX_MSDU_END_7_TCP_SEQ_NUMBER + + TCP sequence number +*/ +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff + +/* Description RX_MSDU_END_8_TCP_ACK_NUMBER + + TCP acknowledge number +*/ +#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff + +/* Description RX_MSDU_END_9_TCP_FLAG + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ +#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_9_TCP_FLAG_LSB 0 +#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff + +/* Description RX_MSDU_END_9_LRO_ELIGIBLE + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO +*/ +#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 + +/* Description RX_MSDU_END_9_L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ +#define RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET 0x00000024 +#define RX_MSDU_END_9_L3_HEADER_PADDING_LSB 10 +#define RX_MSDU_END_9_L3_HEADER_PADDING_MASK 0x00001c00 + +/* Description RX_MSDU_END_9_RESERVED_9A + + +*/ +#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_9_RESERVED_9A_LSB 13 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000e000 + +/* Description RX_MSDU_END_9_WINDOW_SIZE + + TCP receive window size +*/ +#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 + +/* Description RX_MSDU_END_10_DA_OFFSET + + Offset into MSDU buffer for DA +*/ +#define RX_MSDU_END_10_DA_OFFSET_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_OFFSET_LSB 0 +#define RX_MSDU_END_10_DA_OFFSET_MASK 0x0000003f + +/* Description RX_MSDU_END_10_SA_OFFSET + + Offset into MSDU buffer for SA +*/ +#define RX_MSDU_END_10_SA_OFFSET_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_OFFSET_LSB 6 +#define RX_MSDU_END_10_SA_OFFSET_MASK 0x00000fc0 + +/* Description RX_MSDU_END_10_DA_OFFSET_VALID + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed +*/ +#define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_10_DA_OFFSET_VALID_MASK 0x00001000 + +/* Description RX_MSDU_END_10_SA_OFFSET_VALID + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed +*/ +#define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_10_SA_OFFSET_VALID_MASK 0x00002000 + +/* Description RX_MSDU_END_10_TYPE_OFFSET + + Offset into MSDU buffer for Type +*/ +#define RX_MSDU_END_10_TYPE_OFFSET_OFFSET 0x00000028 +#define RX_MSDU_END_10_TYPE_OFFSET_LSB 14 +#define RX_MSDU_END_10_TYPE_OFFSET_MASK 0x001fc000 + +/* Description RX_MSDU_END_10_RESERVED_10A + + +*/ +#define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 +#define RX_MSDU_END_10_RESERVED_10A_LSB 21 +#define RX_MSDU_END_10_RESERVED_10A_MASK 0xffe00000 + +/* Description RX_MSDU_END_11_RULE_INDICATION_31_0 + + Bitmap indicating which of rules 31-0 have matched +*/ +#define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET 0x0000002c +#define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK 0xffffffff + +/* Description RX_MSDU_END_12_RULE_INDICATION_63_32 + + Bitmap indicating which of rules 63-32 have matched +*/ +#define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET 0x00000030 +#define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK 0xffffffff + +/* Description RX_MSDU_END_13_SA_IDX + + The offset in the address table which matches the MAC + source address. +*/ +#define RX_MSDU_END_13_SA_IDX_OFFSET 0x00000034 +#define RX_MSDU_END_13_SA_IDX_LSB 0 +#define RX_MSDU_END_13_SA_IDX_MASK 0x0000ffff + +/* Description RX_MSDU_END_13_DA_IDX + + The offset in the address table which matches the MAC + source address +*/ +#define RX_MSDU_END_13_DA_IDX_OFFSET 0x00000034 +#define RX_MSDU_END_13_DA_IDX_LSB 16 +#define RX_MSDU_END_13_DA_IDX_MASK 0xffff0000 + +/* Description RX_MSDU_END_14_MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_END_14_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_END_14_MSDU_DROP_LSB 0 +#define RX_MSDU_END_14_MSDU_DROP_MASK 0x00000001 + +/* Description RX_MSDU_END_14_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET 0x00000038 +#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK 0x0000003e + +/* Description RX_MSDU_END_14_FLOW_IDX + + Flow table index + + +*/ +#define RX_MSDU_END_14_FLOW_IDX_OFFSET 0x00000038 +#define RX_MSDU_END_14_FLOW_IDX_LSB 6 +#define RX_MSDU_END_14_FLOW_IDX_MASK 0x03ffffc0 + +/* Description RX_MSDU_END_14_RESERVED_14 + + +*/ +#define RX_MSDU_END_14_RESERVED_14_OFFSET 0x00000038 +#define RX_MSDU_END_14_RESERVED_14_LSB 26 +#define RX_MSDU_END_14_RESERVED_14_MASK 0xfc000000 + +/* Description RX_MSDU_END_15_FSE_METADATA + + FSE related meta data: + + +*/ +#define RX_MSDU_END_15_FSE_METADATA_OFFSET 0x0000003c +#define RX_MSDU_END_15_FSE_METADATA_LSB 0 +#define RX_MSDU_END_15_FSE_METADATA_MASK 0xffffffff + +/* Description RX_MSDU_END_16_CCE_METADATA + + CCE related meta data: + + +*/ +#define RX_MSDU_END_16_CCE_METADATA_OFFSET 0x00000040 +#define RX_MSDU_END_16_CCE_METADATA_LSB 0 +#define RX_MSDU_END_16_CCE_METADATA_MASK 0x0000ffff + +/* Description RX_MSDU_END_16_SA_SW_PEER_ID + + sw_peer_id from the address search entry corresponding + to the source address of the MSDU + + +*/ +#define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET 0x00000040 +#define RX_MSDU_END_16_SA_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_16_SA_SW_PEER_ID_MASK 0xffff0000 + + +#endif // _RX_MSDU_END_H_ diff --git a/hw/qca6290/v1/rx_msdu_link.h b/hw/qca6290/v1/rx_msdu_link.h new file mode 100644 index 000000000000..8f7cc6d7dded --- /dev/null +++ b/hw/qca6290/v1/rx_msdu_link.h @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; +// 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8-11 struct rx_msdu_details msdu_0; +// 12-15 struct rx_msdu_details msdu_1; +// 16-19 struct rx_msdu_details msdu_2; +// 20-23 struct rx_msdu_details msdu_3; +// 24-27 struct rx_msdu_details msdu_4; +// 28-31 struct rx_msdu_details msdu_5; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, //[15:0] + first_rx_msdu_link_struct : 1, //[16] + reserved_3a : 15; //[31:17] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_MSDU_Link_descriptor + +struct buffer_addr_info next_msdu_link_desc_addr_info + + Details of the physical address of the next MSDU link + descriptor that contains info about additional MSDUs that + are part of this MPDU. + +receive_queue_number + + Indicates the Receive queue to which this MPDU + descriptor belongs + + Used for tracking, finding bugs and debugging. + + + +first_rx_msdu_link_struct + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + + + +reserved_3a + + + +pn_31_0 + + + + + 31-0 bits of the 256-bit packet number bitmap. + + + +pn_63_32 + + + + + 63-32 bits of the 256-bit packet number bitmap. + + + +pn_95_64 + + + + + 95-64 bits of the 256-bit packet number bitmap. + + + +pn_127_96 + + + + + 127-96 bits of the 256-bit packet number bitmap. + + + +struct rx_msdu_details msdu_0 + + When First_RX_MSDU_link_struct is set, this MSDU is the + first in the MPDU + + + + When First_RX_MSDU_link_struct is NOT set, this MSDU + follows the last MSDU in the previous RX_MSDU_link data + structure + +struct rx_msdu_details msdu_1 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_2 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_3 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_4 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_5 + + Details of next MSDU in this (MSDU flow) linked list +*/ + +#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 +#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff +#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff + +/* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER + + Indicates the Receive queue to which this MPDU + descriptor belongs + + Used for tracking, finding bugs and debugging. + + +*/ +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + + +*/ +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +/* Description RX_MSDU_LINK_3_RESERVED_3A + + +*/ +#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 + +/* Description RX_MSDU_LINK_4_PN_31_0 + + + + + 31-0 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_4_PN_31_0_LSB 0 +#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_5_PN_63_32 + + + + + 63-32 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_5_PN_63_32_LSB 0 +#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff + +/* Description RX_MSDU_LINK_6_PN_95_64 + + + + + 95-64 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_6_PN_95_64_LSB 0 +#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff + +/* Description RX_MSDU_LINK_7_PN_127_96 + + + + + 127-96 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_7_PN_127_96_LSB 0 +#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff +#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000030 +#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000040 +#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000050 +#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000060 +#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000070 +#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff +#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff +#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff +#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff + + +#endif // _RX_MSDU_LINK_H_ diff --git a/hw/qca6290/v1/rx_msdu_start.h b/hw/qca6290/v1/rx_msdu_start.h new file mode 100644 index 000000000000..0be1a43d5b6b --- /dev/null +++ b/hw/qca6290/v1/rx_msdu_start.h @@ -0,0 +1,1081 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24] +// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], reserved_2a[31:16] +// 3 reserved_3a[10:0], da_is_bcast_mcast[11], reserved_3b[15:12], ip4_protocol_ip6_next_header[23:16], reserved_3c[30:24], toeplitz_hash[31] +// 4 toeplitz_hash_2_or_4[31:0] +// 5 flow_id_toeplitz[31:0] +// 6 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_6[31:26] +// 7 ppdu_start_timestamp[31:0] +// 8 sw_phy_meta_data[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_START 9 + +struct rx_msdu_start { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t msdu_length : 14, //[13:0] + reserved_1a : 1, //[14] + ipsec_esp : 1, //[15] + l3_offset : 7, //[22:16] + ipsec_ah : 1, //[23] + l4_offset : 8; //[31:24] + uint32_t msdu_number : 8, //[7:0] + decap_format : 2, //[9:8] + ipv4_proto : 1, //[10] + ipv6_proto : 1, //[11] + tcp_proto : 1, //[12] + udp_proto : 1, //[13] + ip_frag : 1, //[14] + tcp_only_ack : 1, //[15] + reserved_2a : 16; //[31:16] + uint32_t reserved_3a : 11, //[10:0] + da_is_bcast_mcast : 1, //[11] + reserved_3b : 4, //[15:12] + ip4_protocol_ip6_next_header : 8, //[23:16] + reserved_3c : 7, //[30:24] + toeplitz_hash : 1; //[31] + uint32_t toeplitz_hash_2_or_4 : 32; //[31:0] + uint32_t flow_id_toeplitz : 32; //[31:0] + uint32_t user_rssi : 8, //[7:0] + pkt_type : 4, //[11:8] + stbc : 1, //[12] + sgi : 2, //[14:13] + rate_mcs : 4, //[18:15] + receive_bandwidth : 2, //[20:19] + reception_type : 2, //[22:21] + nss : 3, //[25:23] + reserved_6 : 6; //[31:26] + uint32_t ppdu_start_timestamp : 32; //[31:0] + uint32_t sw_phy_meta_data : 32; //[31:0] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +msdu_length + + MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + +reserved_1a + + + +ipsec_esp + + Set if IPv4/v6 packet is using IPsec ESP + +l3_offset + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the IP + offset in bytes from the start of the packet after + decapsulation.  The latter is only valid if ipv4_proto or + ipv6_proto is set. + +ipsec_ah + + Set if IPv4/v6 packet is using IPsec AH + +l4_offset + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid if + tcp_proto or udp_proto is set).  The value 0 indicates that + the offset is longer than 127 bytes. + +msdu_number + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number of + MSDU exceeds 255 this number will wrap using modulo 256. + +decap_format + + Indicates the format after decapsulation: + + + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + + +ipv4_proto + + Set if L2 layer indicates IPv4 protocol. + +ipv6_proto + + Set if L2 layer indicates IPv6 protocol. + +tcp_proto + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates TCP. + +udp_proto + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates UDP. + +ip_frag + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is a + fragmented IP packet. + +tcp_only_ack + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. + +reserved_2a + + + +reserved_3a + + + +da_is_bcast_mcast + + The destination address is broadcast or multicast. + +reserved_3b + + + +ip4_protocol_ip6_next_header + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). + +reserved_3c + + + +toeplitz_hash + + Actual choosen Hash. + + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP + destination address)1 -> Toeplitz hash of 4-tuple (IP source + address, IP destination address, L4 (TCP/UDP) source port, + L4 (TCP/UDP) destination port) + +toeplitz_hash_2_or_4 + + Controlled by RxOLE register - If register bit set to 0, + Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest + addresses; otherwise, toeplitz hash is computed over 4-tuple + IPv4 or IPv6 src/dest addresses and src/dest ports + +flow_id_toeplitz + + Toeplitz hash of 5-tuple + + {IP source address, IP destination address, IP source + port, IP destination port, L4 protocol} in case of + non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + + {IP source address, IP destination address, SPI, L4 + protocol} + + + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE.The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + + +user_rssi + + RSSI for this user + + + +pkt_type + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + +stbc + + When set, use STBC transmission rates + +sgi + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + + +rate_mcs + + For details, refer to MCS_TYPE description + + + +receive_bandwidth + + Full receive Bandwidth + + + + + + + + + + + + + + + +reception_type + + Indicates what type of reception this is. + + + + + + + + + + + +nss + + Field only valid when Reception_type = + reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO + + + + Number of Spatial Streams occupied by the User + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams + +reserved_6 + + + +ppdu_start_timestamp + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + +sw_phy_meta_data + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + + +*/ + + +/* Description RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MSDU_START_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MSDU_START_0_RESERVED_0 + + +*/ +#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_0_RESERVED_0_LSB 9 +#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MSDU_START_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MSDU_START_1_MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without +*/ +#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff + +/* Description RX_MSDU_START_1_RESERVED_1A + + +*/ +#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_START_1_RESERVED_1A_LSB 14 +#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 + +/* Description RX_MSDU_START_1_IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ +#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 + +/* Description RX_MSDU_START_1_L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the IP + offset in bytes from the start of the packet after + decapsulation.  The latter is only valid if ipv4_proto or + ipv6_proto is set. +*/ +#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L3_OFFSET_LSB 16 +#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 + +/* Description RX_MSDU_START_1_IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ +#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_AH_LSB 23 +#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 + +/* Description RX_MSDU_START_1_L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid if + tcp_proto or udp_proto is set).  The value 0 indicates that + the offset is longer than 127 bytes. +*/ +#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L4_OFFSET_LSB 24 +#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 + +/* Description RX_MSDU_START_2_MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number of + MSDU exceeds 255 this number will wrap using modulo 256. +*/ +#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff + +/* Description RX_MSDU_START_2_DECAP_FORMAT + + Indicates the format after decapsulation: + + + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + +*/ +#ifndef RX_MSDU_START_2_DECAP_FORMAT_OFFSET +#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 +#endif +#ifndef RX_MSDU_START_2_DECAP_FORMAT_LSB +#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 +#endif +#ifndef RX_MSDU_START_2_DECAP_FORMAT_MASK +#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 +#endif +/* Description RX_MSDU_START_2_IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ +#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 + +/* Description RX_MSDU_START_2_IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ +#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 + +/* Description RX_MSDU_START_2_TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates TCP. +*/ +#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_PROTO_LSB 12 +#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 + +/* Description RX_MSDU_START_2_UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates UDP. +*/ +#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_UDP_PROTO_LSB 13 +#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 + +/* Description RX_MSDU_START_2_IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is a + fragmented IP packet. +*/ +#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FRAG_LSB 14 +#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 + +/* Description RX_MSDU_START_2_TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ +#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 + +/* Description RX_MSDU_START_2_RESERVED_2A + + +*/ +#define RX_MSDU_START_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_START_2_RESERVED_2A_LSB 16 +#define RX_MSDU_START_2_RESERVED_2A_MASK 0xffff0000 + +/* Description RX_MSDU_START_3_RESERVED_3A + + +*/ +#define RX_MSDU_START_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_START_3_RESERVED_3A_LSB 0 +#define RX_MSDU_START_3_RESERVED_3A_MASK 0x000007ff + +/* Description RX_MSDU_START_3_DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ +#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_OFFSET 0x0000000c +#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_LSB 11 +#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_MASK 0x00000800 + +/* Description RX_MSDU_START_3_RESERVED_3B + + +*/ +#define RX_MSDU_START_3_RESERVED_3B_OFFSET 0x0000000c +#define RX_MSDU_START_3_RESERVED_3B_LSB 12 +#define RX_MSDU_START_3_RESERVED_3B_MASK 0x0000f000 + +/* Description RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). +*/ +#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000c +#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 16 +#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00ff0000 + +/* Description RX_MSDU_START_3_RESERVED_3C + + +*/ +#define RX_MSDU_START_3_RESERVED_3C_OFFSET 0x0000000c +#define RX_MSDU_START_3_RESERVED_3C_LSB 24 +#define RX_MSDU_START_3_RESERVED_3C_MASK 0x7f000000 + +/* Description RX_MSDU_START_3_TOEPLITZ_HASH + + Actual choosen Hash. + + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP + destination address)1 -> Toeplitz hash of 4-tuple (IP source + address, IP destination address, L4 (TCP/UDP) source port, + L4 (TCP/UDP) destination port) +*/ +#define RX_MSDU_START_3_TOEPLITZ_HASH_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_LSB 31 +#define RX_MSDU_START_3_TOEPLITZ_HASH_MASK 0x80000000 + +/* Description RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4 + + Controlled by RxOLE register - If register bit set to 0, + Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest + addresses; otherwise, toeplitz hash is computed over 4-tuple + IPv4 or IPv6 src/dest addresses and src/dest ports +*/ +#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_OFFSET 0x00000010 +#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +/* Description RX_MSDU_START_5_FLOW_ID_TOEPLITZ + + Toeplitz hash of 5-tuple + + {IP source address, IP destination address, IP source + port, IP destination port, L4 protocol} in case of + non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + + {IP source address, IP destination address, SPI, L4 + protocol} + + + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE.The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + +*/ +#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_OFFSET 0x00000014 +#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +/* Description RX_MSDU_START_6_USER_RSSI + + RSSI for this user + + +*/ +#define RX_MSDU_START_6_USER_RSSI_OFFSET 0x00000018 +#define RX_MSDU_START_6_USER_RSSI_LSB 0 +#define RX_MSDU_START_6_USER_RSSI_MASK 0x000000ff + +/* Description RX_MSDU_START_6_PKT_TYPE + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type +*/ +#define RX_MSDU_START_6_PKT_TYPE_OFFSET 0x00000018 +#define RX_MSDU_START_6_PKT_TYPE_LSB 8 +#define RX_MSDU_START_6_PKT_TYPE_MASK 0x00000f00 + +/* Description RX_MSDU_START_6_STBC + + When set, use STBC transmission rates +*/ +#define RX_MSDU_START_6_STBC_OFFSET 0x00000018 +#define RX_MSDU_START_6_STBC_LSB 12 +#define RX_MSDU_START_6_STBC_MASK 0x00001000 + +/* Description RX_MSDU_START_6_SGI + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + +*/ +#define RX_MSDU_START_6_SGI_OFFSET 0x00000018 +#define RX_MSDU_START_6_SGI_LSB 13 +#define RX_MSDU_START_6_SGI_MASK 0x00006000 + +/* Description RX_MSDU_START_6_RATE_MCS + + For details, refer to MCS_TYPE description + + +*/ +#define RX_MSDU_START_6_RATE_MCS_OFFSET 0x00000018 +#define RX_MSDU_START_6_RATE_MCS_LSB 15 +#define RX_MSDU_START_6_RATE_MCS_MASK 0x00078000 + +/* Description RX_MSDU_START_6_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_OFFSET 0x00000018 +#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_MASK 0x00180000 + +/* Description RX_MSDU_START_6_RECEPTION_TYPE + + Indicates what type of reception this is. + + + + + + + + + + +*/ +#define RX_MSDU_START_6_RECEPTION_TYPE_OFFSET 0x00000018 +#define RX_MSDU_START_6_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_6_RECEPTION_TYPE_MASK 0x00600000 + +/* Description RX_MSDU_START_6_NSS + + Field only valid when Reception_type = + reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO + + + + Number of Spatial Streams occupied by the User + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define RX_MSDU_START_6_NSS_OFFSET 0x00000018 +#define RX_MSDU_START_6_NSS_LSB 23 +#define RX_MSDU_START_6_NSS_MASK 0x03800000 + +/* Description RX_MSDU_START_6_RESERVED_6 + + +*/ +#define RX_MSDU_START_6_RESERVED_6_OFFSET 0x00000018 +#define RX_MSDU_START_6_RESERVED_6_LSB 26 +#define RX_MSDU_START_6_RESERVED_6_MASK 0xfc000000 + +/* Description RX_MSDU_START_7_PPDU_START_TIMESTAMP + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + +*/ +#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_OFFSET 0x0000001c +#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_MASK 0xffffffff + +/* Description RX_MSDU_START_8_SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + + +*/ +#define RX_MSDU_START_8_SW_PHY_META_DATA_OFFSET 0x00000020 +#define RX_MSDU_START_8_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_8_SW_PHY_META_DATA_MASK 0xffffffff + + +#endif // _RX_MSDU_START_H_ diff --git a/hw/qca6290/v1/rx_reo_queue.h b/hw/qca6290/v1/rx_reo_queue.h new file mode 100644 index 000000000000..a3f2eebcb005 --- /dev/null +++ b/hw/qca6290/v1/rx_reo_queue.h @@ -0,0 +1,1662 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1 receive_queue_number[15:0], reserved_1b[31:16] +// 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] +// 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8 last_rx_enqueue_timestamp[31:0] +// 9 last_rx_dequeue_timestamp[31:0] +// 10 ptr_to_next_aging_queue_31_0[31:0] +// 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] +// 12 ptr_to_previous_aging_queue_31_0[31:0] +// 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] +// 14 rx_bitmap_31_0[31:0] +// 15 rx_bitmap_63_32[31:0] +// 16 rx_bitmap_95_64[31:0] +// 17 rx_bitmap_127_96[31:0] +// 18 rx_bitmap_159_128[31:0] +// 19 rx_bitmap_191_160[31:0] +// 20 rx_bitmap_223_192[31:0] +// 21 rx_bitmap_255_224[31:0] +// 22 current_mpdu_count[6:0], current_msdu_count[31:7] +// 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] +// 24 frames_in_order_count[23:0], bar_received_count[31:24] +// 25 mpdu_frames_processed_count[31:0] +// 26 msdu_frames_processed_count[31:0] +// 27 total_processed_byte_count[31:0] +// 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] +// 29 reserved_29[31:0] +// 30 reserved_30[31:0] +// 31 reserved_31[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, //[15:0] + reserved_1b : 16; //[31:16] + uint32_t vld : 1, //[0] + associated_link_descriptor_counter: 2, //[2:1] + disable_duplicate_detection : 1, //[3] + soft_reorder_enable : 1, //[4] + ac : 2, //[6:5] + bar : 1, //[7] + rty : 1, //[8] + chk_2k_mode : 1, //[9] + oor_mode : 1, //[10] + ba_window_size : 8, //[18:11] + pn_check_needed : 1, //[19] + pn_shall_be_even : 1, //[20] + pn_shall_be_uneven : 1, //[21] + pn_handling_enable : 1, //[22] + pn_size : 2, //[24:23] + ignore_ampdu_flag : 1, //[25] + reserved_2b : 6; //[31:26] + uint32_t svld : 1, //[0] + ssn : 12, //[12:1] + current_index : 8, //[20:13] + seq_2k_error_detected_flag : 1, //[21] + pn_error_detected_flag : 1, //[22] + reserved_3a : 8, //[30:23] + pn_valid : 1; //[31] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t last_rx_enqueue_timestamp : 32; //[31:0] + uint32_t last_rx_dequeue_timestamp : 32; //[31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] + uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] + reserved_11a : 24; //[31:8] + uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] + uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] + reserved_13a : 24; //[31:8] + uint32_t rx_bitmap_31_0 : 32; //[31:0] + uint32_t rx_bitmap_63_32 : 32; //[31:0] + uint32_t rx_bitmap_95_64 : 32; //[31:0] + uint32_t rx_bitmap_127_96 : 32; //[31:0] + uint32_t rx_bitmap_159_128 : 32; //[31:0] + uint32_t rx_bitmap_191_160 : 32; //[31:0] + uint32_t rx_bitmap_223_192 : 32; //[31:0] + uint32_t rx_bitmap_255_224 : 32; //[31:0] + uint32_t current_mpdu_count : 7, //[6:0] + current_msdu_count : 25; //[31:7] + uint32_t reserved_23 : 4, //[3:0] + timeout_count : 6, //[9:4] + forward_due_to_bar_count : 6, //[15:10] + duplicate_count : 16; //[31:16] + uint32_t frames_in_order_count : 24, //[23:0] + bar_received_count : 8; //[31:24] + uint32_t mpdu_frames_processed_count : 32; //[31:0] + uint32_t msdu_frames_processed_count : 32; //[31:0] + uint32_t total_processed_byte_count : 32; //[31:0] + uint32_t late_receive_mpdu_count : 12, //[11:0] + window_jump_2k : 4, //[15:12] + hole_count : 16; //[31:16] + uint32_t reserved_29 : 32; //[31:0] + uint32_t reserved_30 : 32; //[31:0] + uint32_t reserved_31 : 32; //[31:0] +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_REO_queue_descriptor + +receive_queue_number + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + + +reserved_1b + + + +vld + + Valid bit indicating a session is established and the + queue descriptor is valid(Filled by SW) + + + +associated_link_descriptor_counter + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + + MSDU link descriptors related with MPDUs stored in the + re-order buffer shall also be included in this count. + + + + + +disable_duplicate_detection + + When set, do not perform any duplicate detection. + + + + + +soft_reorder_enable + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes. + + + + Note that this implies that REO is also not going to + perform any MSDU level operations, and the entire MPDU (and + thus pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW + programmable configuration register in REO + + + + + +ac + + Indicates which access category the queue descriptor + belongs to(filled by SW) + + + +bar + + Indicates if BAR has been received (mostly used for + debug purpose and this is filled by REO) + + + +rty + + Retry bit is checked if this bit is set. + + + +chk_2k_mode + + Indicates what type of operation is expected from Reo + when the received frame SN falls within the 2K window + + + + See REO MLD document for programming details. + + + +oor_mode + + Out of Order mode: + + Indicates what type of operation is expected when the + received frame falls within the OOR window. + + + + See REO MLD document for programming details. + + + +ba_window_size + + Indicates the negotiated (window size + 1). + + it can go up to Max of 256bits. + + + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 + (means non-BA session, with window size of 0). The 3 values + here are the main values validated, but other values should + work as well. + + + + A BA window size of 0 (=> one frame entry bitmat), means + that there is NO RX_REO_QUEUE_EXT descriptor following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 1 - 105, means that there is 1 + RX_REO_QUEUE_EXT descriptor directly following this + RX_REO_QUEUE STRUCT in memory. + + + + A BA window size of 106 - 210, means that there are 2 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 211 - 256, means that there are 3 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + + +pn_check_needed + + When set, REO shall perform the PN increment check + + + +pn_shall_be_even + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + + + +pn_shall_be_uneven + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + + +pn_handling_enable + + Field only valid when 'pn_check_needed' is set. + + + + When set, and REO detected a PN error, HW shall set the + 'pn_error_detected_flag'. + + + +pn_size + + Size of the PN field check. + + Needed for wrap around handling... + + + + + + + + + + + + + +ignore_ampdu_flag + + When set, REO shall ignore the ampdu_flag on the + entrance descriptor for this queue. + + + +reserved_2b + + + +svld + + Sequence number in next field is valid one. It can be + filled by SW if the want to fill in the any negotiated SSN, + otherwise REO will fill the sequence number of first + received packet and set this bit to 1. + + + +ssn + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + + +current_index + + Points to last forwarded packet + + + +seq_2k_error_detected_flag + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a 2k error jump in the + sequence number and from that moment forward, all new frames + are forwarded directly to FW, without duplicate detect, + reordering, etc. + + + +pn_error_detected_flag + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a PN error and from that + moment forward, all new frames are forwarded directly to FW, + without duplicate detect, reordering, etc. + + + +reserved_3a + + + +pn_valid + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet and + set this bit to 1. + + + +pn_31_0 + + + + +pn_63_32 + + Bits [63:32] of the PN number. + + + +pn_95_64 + + Bits [95:64] of the PN number. + + + +pn_127_96 + + Bits [127:96] of the PN number. + + + +last_rx_enqueue_timestamp + + This timestamp is updated when an MPDU is received and + accesses this Queue Descriptor. It does not include the + access due to Command TLVs or Aging (which will be updated + in Last_rx_dequeue_timestamp). + + + +last_rx_dequeue_timestamp + + This timestamp is used for Aging. When an MPDU or + multiple MPDUs are forwarded, either due to window movement, + bar, aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + + +ptr_to_next_aging_queue_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + + +ptr_to_next_aging_queue_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + + +reserved_11a + + + +ptr_to_previous_aging_queue_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + + +ptr_to_previous_aging_queue_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + + +reserved_13a + + + +rx_bitmap_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + + +rx_bitmap_63_32 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_95_64 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_127_96 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_159_128 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_191_160 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_223_192 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_255_224 + + See Rx_bitmap_31_0 description + + + +current_mpdu_count + + The number of MPDUs in the queue. + + + + + +current_msdu_count + + The number of MSDUs in the queue. + + + +reserved_23 + + + +timeout_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + + +forward_due_to_bar_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + + +duplicate_count + + The number of duplicate frames that have been detected + + + +frames_in_order_count + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + + +bar_received_count + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + + +mpdu_frames_processed_count + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + + + + +msdu_frames_processed_count + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + + +total_processed_byte_count + + An approximation of the number of bytes processed for + this queue. + + 'Processing' here means that REO has received them out + of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + In 64 byte units + + + +late_receive_mpdu_count + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + + +window_jump_2k + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + + +hole_count + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + + +reserved_29 + + + +reserved_30 + + + +reserved_31 + + +*/ + +#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 +#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff + +/* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description RX_REO_QUEUE_1_RESERVED_1B + + +*/ +#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_2_VLD + + Valid bit indicating a session is established and the + queue descriptor is valid(Filled by SW) + + +*/ +#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_VLD_LSB 0 +#define RX_REO_QUEUE_2_VLD_MASK 0x00000001 + +/* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + + MSDU link descriptors related with MPDUs stored in the + re-order buffer shall also be included in this count. + + + + +*/ +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +/* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION + + When set, do not perform any duplicate detection. + + + + +*/ +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +/* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes. + + + + Note that this implies that REO is also not going to + perform any MSDU level operations, and the entire MPDU (and + thus pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW + programmable configuration register in REO + + + + +*/ +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 + +/* Description RX_REO_QUEUE_2_AC + + Indicates which access category the queue descriptor + belongs to(filled by SW) + + +*/ +#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_AC_LSB 5 +#define RX_REO_QUEUE_2_AC_MASK 0x00000060 + +/* Description RX_REO_QUEUE_2_BAR + + Indicates if BAR has been received (mostly used for + debug purpose and this is filled by REO) + + +*/ +#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BAR_LSB 7 +#define RX_REO_QUEUE_2_BAR_MASK 0x00000080 + +/* Description RX_REO_QUEUE_2_RTY + + Retry bit is checked if this bit is set. + + +*/ +#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RTY_LSB 8 +#define RX_REO_QUEUE_2_RTY_MASK 0x00000100 + +/* Description RX_REO_QUEUE_2_CHK_2K_MODE + + Indicates what type of operation is expected from Reo + when the received frame SN falls within the 2K window + + + + See REO MLD document for programming details. + + +*/ +#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 + +/* Description RX_REO_QUEUE_2_OOR_MODE + + Out of Order mode: + + Indicates what type of operation is expected when the + received frame falls within the OOR window. + + + + See REO MLD document for programming details. + + +*/ +#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 + +/* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE + + Indicates the negotiated (window size + 1). + + it can go up to Max of 256bits. + + + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 + (means non-BA session, with window size of 0). The 3 values + here are the main values validated, but other values should + work as well. + + + + A BA window size of 0 (=> one frame entry bitmat), means + that there is NO RX_REO_QUEUE_EXT descriptor following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 1 - 105, means that there is 1 + RX_REO_QUEUE_EXT descriptor directly following this + RX_REO_QUEUE STRUCT in memory. + + + + A BA window size of 106 - 210, means that there are 2 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 211 - 256, means that there are 3 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + +*/ +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 + +/* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED + + When set, REO shall perform the PN increment check + + +*/ +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 + +/* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + + +*/ +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 + +/* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + +*/ +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +/* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE + + Field only valid when 'pn_check_needed' is set. + + + + When set, and REO detected a PN error, HW shall set the + 'pn_error_detected_flag'. + + +*/ +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 + +/* Description RX_REO_QUEUE_2_PN_SIZE + + Size of the PN field check. + + Needed for wrap around handling... + + + + + + + + + + + + +*/ +#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SIZE_LSB 23 +#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 + +/* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG + + When set, REO shall ignore the ampdu_flag on the + entrance descriptor for this queue. + + +*/ +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 + +/* Description RX_REO_QUEUE_2_RESERVED_2B + + +*/ +#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 +#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 + +/* Description RX_REO_QUEUE_3_SVLD + + Sequence number in next field is valid one. It can be + filled by SW if the want to fill in the any negotiated SSN, + otherwise REO will fill the sequence number of first + received packet and set this bit to 1. + + +*/ +#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SVLD_LSB 0 +#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 + +/* Description RX_REO_QUEUE_3_SSN + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + +*/ +#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SSN_LSB 1 +#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe + +/* Description RX_REO_QUEUE_3_CURRENT_INDEX + + Points to last forwarded packet + + +*/ +#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 + +/* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a 2k error jump in the + sequence number and from that moment forward, all new frames + are forwarded directly to FW, without duplicate detect, + reordering, etc. + + +*/ +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 + +/* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a PN error and from that + moment forward, all new frames are forwarded directly to FW, + without duplicate detect, reordering, etc. + + +*/ +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 + +/* Description RX_REO_QUEUE_3_RESERVED_3A + + +*/ +#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 +#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 + +/* Description RX_REO_QUEUE_3_PN_VALID + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet and + set this bit to 1. + + +*/ +#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_VALID_LSB 31 +#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 + +/* Description RX_REO_QUEUE_4_PN_31_0 + + + +*/ +#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_4_PN_31_0_LSB 0 +#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_5_PN_63_32 + + Bits [63:32] of the PN number. + + +*/ +#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_5_PN_63_32_LSB 0 +#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff + +/* Description RX_REO_QUEUE_6_PN_95_64 + + Bits [95:64] of the PN number. + + +*/ +#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_6_PN_95_64_LSB 0 +#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff + +/* Description RX_REO_QUEUE_7_PN_127_96 + + Bits [127:96] of the PN number. + + +*/ +#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_7_PN_127_96_LSB 0 +#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff + +/* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP + + This timestamp is updated when an MPDU is received and + accesses this Queue Descriptor. It does not include the + access due to Command TLVs or Aging (which will be updated + in Last_rx_dequeue_timestamp). + + +*/ +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP + + This timestamp is used for Aging. When an MPDU or + multiple MPDUs are forwarded, either due to window movement, + bar, aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + +*/ +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + +*/ +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + +*/ +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_11_RESERVED_11A + + +*/ +#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + +*/ +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + +*/ +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_13_RESERVED_13A + + +*/ +#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 +#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + +*/ +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff + +/* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff + +/* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff + +/* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff + +/* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff + +/* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff + +/* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff + +/* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + + + +*/ +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f + +/* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + + +*/ +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +/* Description RX_REO_QUEUE_23_RESERVED_23 + + +*/ +#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_RESERVED_23_LSB 0 +#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f + +/* Description RX_REO_QUEUE_23_TIMEOUT_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 + +/* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +/* Description RX_REO_QUEUE_23_DUPLICATE_COUNT + + The number of duplicate frames that have been detected + + +*/ +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + +*/ +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +/* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + +*/ +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 + +/* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + + + +*/ +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + +*/ +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes processed for + this queue. + + 'Processing' here means that REO has received them out + of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + In 64 byte units + + +*/ +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + +*/ +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +/* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + +*/ +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 + +/* Description RX_REO_QUEUE_28_HOLE_COUNT + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + +*/ +#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_29_RESERVED_29 + + +*/ +#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_29_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff + +/* Description RX_REO_QUEUE_30_RESERVED_30 + + +*/ +#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_30_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff + +/* Description RX_REO_QUEUE_31_RESERVED_31 + + +*/ +#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_31_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff + + +#endif // _RX_REO_QUEUE_H_ diff --git a/hw/qca6290/v1/rx_reo_queue_ext.h b/hw/qca6290/v1/rx_reo_queue_ext.h new file mode 100644 index 000000000000..f829fac9a3d0 --- /dev/null +++ b/hw/qca6290/v1/rx_reo_queue_ext.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "rx_mpdu_link_ptr.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1 reserved_1a[31:0] +// 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; +// 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; +// 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; +// 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; +// 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; +// 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; +// 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; +// 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; +// 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; +// 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; +// 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; +// 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; +// 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; +// 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; +// 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; //[31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_REO_queue_ext_descriptor + +reserved_1a + + + +struct rx_mpdu_link_ptr mpdu_link_pointer_0 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_1 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_2 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_3 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_4 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_5 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_6 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_7 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_8 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_9 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_10 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_11 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_12 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_13 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_14 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue +*/ + +#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 +#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_1_RESERVED_1A + + +*/ +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB 0 +#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB 0 +#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB 0 +#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB 0 +#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB 0 +#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB 0 +#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB 0 +#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB 0 +#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0 +#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0 +#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0 +#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0 +#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0 +#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0 +#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0 +#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0 +#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0 +#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0 +#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0 +#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0 +#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0 +#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0 +#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0 +#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0 +#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0 +#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0 +#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0 +#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0 +#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0 +#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0 +#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff + + +#endif // _RX_REO_QUEUE_EXT_H_ diff --git a/hw/qca6290/v1/rxpt_classify_info.h b/hw/qca6290/v1/rxpt_classify_info.h new file mode 100644 index 000000000000..216c2dd9e480 --- /dev/null +++ b/hw/qca6290/v1/rxpt_classify_info.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_destination_indication[4:0], use_flow_id_toeplitz_clfy[5], reserved_0a[31:6] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { + uint32_t reo_destination_indication : 5, //[4:0] + use_flow_id_toeplitz_clfy : 1, //[5] + reserved_0a : 26; //[31:6] +}; + +/* + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +use_flow_id_toeplitz_clfy + + indication to Rx OLE to enable classification based on + 'flow_id_toeplitz' from Common Parser, in case flow search + fails + + + +reserved_0a + + +*/ + + +/* Description RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f + +/* Description RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY + + indication to Rx OLE to enable classification based on + 'flow_id_toeplitz' from Common Parser, in case flow search + fails + + +*/ +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 5 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000020 + +/* Description RXPT_CLASSIFY_INFO_0_RESERVED_0A + + +*/ +#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_LSB 6 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_MASK 0xffffffc0 + + +#endif // _RXPT_CLASSIFY_INFO_H_ diff --git a/hw/qca6290/v1/seq_hwio.h b/hw/qca6290/v1/seq_hwio.h new file mode 100644 index 000000000000..fd489f20d8a1 --- /dev/null +++ b/hw/qca6290/v1/seq_hwio.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/********************************************************************************* + * + * DESCRIPTION + * - This is an extension of standard msmhwio.h to support relative addressing + * scheme used in SCALe auto-generated sequences. + * - The objective of this new addressing scheme is enable the same C function + * definition to be applicable to multiple baseances of the same block. + * - Such code reuse is not feasible with the standard HWIO macros that use a + * absolute addressing scheme. + * - Compared to the standard HWIO macros, the new macros defined here take an + * additional parameter 'baseance offset'. So are the C functions generated + * by SCALe Autoseq from .seq inputs. + * - As such, macros defined in this file must be used with 'seq_msmhwiobase.h', + * 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq. + * - Macros defined in this file leverage the lower-level macros from the + * standard 'msmhwio.h', and the two sets of macros are compatible. + * + ********************************************************************************/ + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + + + +/**** Register Ref Read ****/ +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +/**** Masked Register Read ****/ +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + + +/**** Ref Reg Field Read ****/ +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + + +/**** Ref Register Write ****/ +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +/**** Ref Register Masked Write ****/ +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + + +/**** Ref Register Field Write ****/ +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + + +/**** seq_msg() **** + +typedef enum { + DEBUG, + INFO, + WARNING, + ERROR, + FATAL +} SeverityLevel ; + +void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... ); + +*/ + +/************ seq_wait() ************/ + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + + +/************ seq_poll() ************/ +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif /* __SEQ_H__ */ + + + + + + + + + + + + + + + + + + + diff --git a/hw/qca6290/v1/sw_xml_headers.h b/hw/qca6290/v1/sw_xml_headers.h new file mode 100644 index 000000000000..f263386f85be --- /dev/null +++ b/hw/qca6290/v1/sw_xml_headers.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + +#ifndef _SW_XML_HEADERS_H_ +#define _SW_XML_HEADERS_H_ + + +#include "ack_report.h" +#include "addr_search_entry.h" +#include "buffer_addr_info.h" +#include "cce_rule.h" +#include "ce_src_desc.h" +#include "he_sig_a_mu_dl_info.h" +#include "he_sig_a_mu_ul_info.h" +#include "he_sig_a_su_info.h" +#include "he_sig_b1_mu_info.h" +#include "he_sig_b2_mu_info.h" +#include "he_sig_b2_ofdma_info.h" +#include "ht_sig_info.h" +#include "l_sig_a_info.h" +#include "l_sig_b_info.h" +#include "mactx_abort_request_info.h" +#include "mimo_control_info.h" +#include "no_ack_report.h" +#include "pcu_ppdu_setup_end_info.h" +#include "pdg_response_rate_setting.h" +#include "peer_table_entry.h" +#include "phyrx_abort_request_info.h" +#include "ppdu_rate_setting.h" +#include "prot_rate_setting.h" +#include "receive_rssi_info.h" +#include "receive_user_info.h" +#include "received_trigger_info_details.h" +#include "reo_destination_ring.h" +#include "reo_entrance_ring.h" +#include "reo_to_ppe_ring.h" +#include "response_rate_setting.h" +#include "rx_flow_search_entry.h" +#include "rx_location_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_mpdu_details.h" +#include "rx_mpdu_info.h" +#include "rx_mpdu_link.h" +#include "rx_mpdu_link_ptr.h" +#include "rx_msdu_desc_info.h" +#include "rx_msdu_details.h" +#include "rx_msdu_link.h" +#include "rx_peer_entry_details.h" +#include "rx_reo_queue.h" +#include "rx_reo_queue_ext.h" +#include "rx_reo_queue_reference.h" +#include "rx_rxpcu_classification_overview.h" +#include "rx_timing_offset_info.h" +#include "rxole_cce_classify_info.h" +#include "rxole_cce_info.h" +#include "rxole_cce_superrule.h" +#include "rxpt_classify_info.h" +#include "scheduler_cmd.h" +#include "service_info.h" +#include "sw_peer_info.h" +#include "tcl_cce_classify_info.h" +#include "tcl_cce_info.h" +#include "tcl_cce_superrule.h" +#include "tcl_compact_exit_ring.h" +#include "tcl_entrance_from_ppe_ring.h" +#include "tcl_exit_base.h" +#include "tcl_extended_exit_ring.h" +#include "tcl_regular_exit_ring.h" +#include "tcl_status_ring.h" +#include "tqm_entrance_ring.h" +#include "tx_flow_search_entry.h" +#include "tx_mpdu_details.h" +#include "tx_mpdu_link.h" +#include "tx_mpdu_link_ptr.h" +#include "tx_mpdu_queue_ext.h" +#include "tx_mpdu_queue_ext_ptr.h" +#include "tx_mpdu_queue_head.h" +#include "tx_msdu_details.h" +#include "tx_msdu_extension.h" +#include "tx_msdu_flow.h" +#include "tx_msdu_link.h" +#include "tx_msdu_link_entry_ptr.h" +#include "tx_rate_stats_info.h" +#include "txpcu_buffer_basics.h" +#include "txpt_classify_info.h" +#include "uniform_descriptor_header.h" +#include "uniform_reo_cmd_header.h" +#include "uniform_reo_status_header.h" +#include "uniform_tqm_cmd_header.h" +#include "uniform_tqm_status_header.h" +#include "uplink_common_info.h" +#include "uplink_user_setup_info.h" +#include "user_rate_setting.h" +#include "vht_sig_a_info.h" +#include "vht_sig_b_mu160_info.h" +#include "vht_sig_b_mu20_info.h" +#include "vht_sig_b_mu40_info.h" +#include "vht_sig_b_mu80_info.h" +#include "vht_sig_b_su160_info.h" +#include "vht_sig_b_su20_info.h" +#include "vht_sig_b_su40_info.h" +#include "vht_sig_b_su80_info.h" +#include "wbm_buffer_ring.h" +#include "wbm_link_descriptor_ring.h" +#include "wbm_release_ring.h" +#include "who_classify_info.h" +#include "macrx_abort_request_info.h" +#include "phytx_abort_request_info.h" +#include "ce_stat_desc.h" +#include "coex_mac_nap.h" +#include "coex_rx_status.h" +#include "coex_status_broadcast.h" +#include "coex_tx_req.h" +#include "coex_tx_resp.h" +#include "coex_tx_status.h" +#include "coex_tx_stop_ctrl.h" +#include "crypto_status.h" +#include "expected_response.h" +#include "mactx_abort_request.h" +#include "mactx_bf_params_common.h" +#include "mactx_coex_phy_ctrl.h" +#include "mactx_delete_cv.h" +#include "mactx_he_sig_a_mu_dl.h" +#include "mactx_he_sig_a_mu_ul.h" +#include "mactx_he_sig_a_su.h" +#include "mactx_he_sig_b1_mu.h" +#include "mactx_he_sig_b2_mu.h" +#include "mactx_he_sig_b2_ofdma.h" +#include "mactx_ht_sig.h" +#include "mactx_l_sig_a.h" +#include "mactx_l_sig_b.h" +#include "mactx_mu_uplink_common.h" +#include "mactx_phy_desc.h" +#include "mactx_phy_nap.h" +#include "mactx_pre_phy_desc.h" +#include "mactx_prefetch_cv.h" +#include "mactx_user_desc_common.h" +#include "mactx_vht_sig_a.h" +#include "mactx_vht_sig_b_su160.h" +#include "mactx_vht_sig_b_su20.h" +#include "mactx_vht_sig_b_su40.h" +#include "mactx_vht_sig_b_su80.h" +#include "ofdma_trigger_details.h" +#include "ole_buf_status.h" +#include "pcu_ppdu_setup_end.h" +#include "pcu_ppdu_setup_init.h" +#include "pcu_ppdu_setup_start.h" +#include "pdg_fes_setup.h" +#include "pdg_response.h" +#include "pdg_sw_mode_bw_start.h" +#include "pdg_tx_req.h" +#include "pdg_wait_for_mac_request.h" +#include "pdg_wait_for_phy_request.h" +#include "phyrx_cbf_read_request_ack.h" +#include "phyrx_generated_cbf_details.h" +#include "phyrx_he_sig_a_mu_dl.h" +#include "phyrx_he_sig_a_mu_ul.h" +#include "phyrx_he_sig_a_su.h" +#include "phyrx_he_sig_b1_mu.h" +#include "phyrx_he_sig_b2_mu.h" +#include "phyrx_he_sig_b2_ofdma.h" +#include "phyrx_ht_sig.h" +#include "phyrx_l_sig_a.h" +#include "phyrx_l_sig_b.h" +#include "phyrx_pkt_end.h" +#include "phyrx_rssi_ht.h" +#include "phyrx_rssi_legacy.h" +#include "phyrx_vht_sig_a.h" +#include "phyrx_vht_sig_b_su160.h" +#include "phyrx_vht_sig_b_su20.h" +#include "phyrx_vht_sig_b_su40.h" +#include "phyrx_vht_sig_b_su80.h" +#include "received_response_info.h" +#include "received_trigger_info.h" +#include "reo_descriptor_threshold_reached_status.h" +#include "reo_flush_cache.h" +#include "reo_flush_cache_status.h" +#include "reo_flush_queue.h" +#include "reo_flush_queue_status.h" +#include "reo_flush_timeout_list.h" +#include "reo_flush_timeout_list_status.h" +#include "reo_get_queue_stats.h" +#include "reo_get_queue_stats_status.h" +#include "reo_unblock_cache.h" +#include "reo_unblock_cache_status.h" +#include "reo_update_rx_reo_queue.h" +#include "reo_update_rx_reo_queue_status.h" +#include "response_end_status.h" +#include "response_start_status.h" +#include "rx_frame_bitmap_req.h" +#include "rx_frameless_bar_details.h" +#include "rx_pm_info.h" +#include "rx_ppdu_ack_report.h" +#include "rx_ppdu_end_status_done.h" +#include "rx_ppdu_no_ack_report.h" +#include "rx_ppdu_start.h" +#include "rx_preamble.h" +#include "rx_response_required_info.h" +#include "rx_ring_mask.h" +#include "rx_start_param.h" +#include "rx_trig_info.h" +#include "rxpcu_ppdu_end_info.h" +#include "rxpcu_setup.h" +#include "sch_coex_status.h" +#include "sch_wait_instr.h" +#include "scheduler_command_status.h" +#include "scheduler_rx_ppdu_no_response_status.h" +#include "scheduler_rx_sifs_response_trigger_status.h" +#include "scheduler_selfgen_response_status.h" +#include "tcl_data_cmd.h" +#include "tcl_gse_cmd.h" +#include "tqm_acked_mpdu_status.h" +#include "tqm_add_msdu_status.h" +#include "tqm_descriptor_threshold_reached_status.h" +#include "tqm_flow_empty_status.h" +#include "tqm_flow_not_empty_status.h" +#include "tqm_flush_cache.h" +#include "tqm_flush_cache_status.h" +#include "tqm_gen_mpdu_length_list.h" +#include "tqm_gen_mpdu_length_list_status.h" +#include "tqm_gen_mpdus.h" +#include "tqm_gen_mpdus_status.h" +#include "tqm_get_mpdu_head_info.h" +#include "tqm_get_mpdu_head_info_status.h" +#include "tqm_get_mpdu_queue_stats.h" +#include "tqm_get_mpdu_queue_stats_status.h" +#include "tqm_get_msdu_flow_stats.h" +#include "tqm_get_msdu_flow_stats_status.h" +#include "tqm_remove_mpdu.h" +#include "tqm_remove_mpdu_status.h" +#include "tqm_remove_msdu.h" +#include "tqm_remove_msdu_status.h" +#include "tqm_sync_cmd.h" +#include "tqm_sync_cmd_status.h" +#include "tqm_threshold_drop_notification_status.h" +#include "tqm_unblock_cache.h" +#include "tqm_unblock_cache_status.h" +#include "tqm_update_tx_mpdu_count_status.h" +#include "tqm_update_tx_mpdu_queue_head.h" +#include "tqm_update_tx_mpdu_queue_head_status.h" +#include "tqm_update_tx_msdu_flow.h" +#include "tqm_update_tx_msdu_flow_status.h" +#include "tqm_write_cmd.h" +#include "tqm_write_cmd_status.h" +#include "tx_cbf_info.h" +#include "tx_data_sync.h" +#include "tx_fes_setup.h" +#include "tx_fes_status_end.h" +#include "tx_fes_status_prot.h" +#include "tx_fes_status_start.h" +#include "tx_fes_status_start_ppdu.h" +#include "tx_fes_status_start_prot.h" +#include "tx_flush_req.h" +#include "tx_sw_mode_setup.h" +#include "txpcu_buffer_status.h" +#include "who_terminate.h" +#include "data_to_time_config.h" +#include "mactx_bf_params_per_user.h" +#include "mactx_expect_cbf_common.h" +#include "mactx_expect_cbf_per_user.h" +#include "mactx_mu_uplink_user_setup.h" +#include "mactx_service.h" +#include "mactx_user_desc_per_user.h" +#include "mactx_vht_sig_b_mu160.h" +#include "mactx_vht_sig_b_mu20.h" +#include "mactx_vht_sig_b_mu40.h" +#include "mactx_vht_sig_b_mu80.h" +#include "mpdu_info.h" +#include "mpdu_info_bitmap.h" +#include "mpdu_limit.h" +#include "pcu_ppdu_setup_user.h" +#include "pdg_user_setup.h" +#include "phyrx_common_user_info.h" +#include "phyrx_user_info.h" +#include "phyrx_vht_sig_b_mu160.h" +#include "phyrx_vht_sig_b_mu20.h" +#include "phyrx_vht_sig_b_mu40.h" +#include "phyrx_vht_sig_b_mu80.h" +#include "rx_attention.h" +#include "rx_frame_bitmap_ack.h" +#include "rx_header.h" +#include "rx_mpdu_end.h" +#include "rx_mpdu_pcu_start.h" +#include "rx_mpdu_start.h" +#include "rx_msdu_end.h" +#include "rx_msdu_start.h" +#include "rx_peer_entry.h" +#include "rx_ppdu_end_user_stats.h" +#include "rx_ppdu_end_user_stats_ext.h" +#include "rx_ppdu_start_user_info.h" +#include "rxpcu_user_setup.h" +#include "rxpcu_user_setup_ext.h" +#include "tqm_acked_mpdu.h" +#include "tqm_update_tx_mpdu_count.h" +#include "tx_11ah_setup.h" +#include "tx_cv_start.h" +#include "tx_fes_status_ack_or_ba.h" +#include "tx_fes_status_user_ppdu.h" +#include "tx_fes_status_user_response.h" +#include "tx_mpdu_start.h" +#include "tx_msdu_start.h" +#include "tx_peer_entry.h" +#include "tx_queue_extension.h" +#include "tx_raw_or_native_frame_setup.h" +#include "txpcu_user_buffer_status.h" +#include "txpcu_user_setup.h" +#include "who_anchor_value.h" +#include "who_cce_info.h" +#include "who_commit_done.h" +#include "who_l2_llc.h" +#include "who_l3_checksum.h" +#include "who_l3_info.h" +#include "who_l4_checksum.h" +#include "who_l4_info.h" +#include "who_mesh_control.h" +#include "who_msdu_misc.h" +#include "who_packet_hdr.h" +#include "who_tso.h" +#include "who_wmac_header_pv0.h" +#include "who_wmac_header_pv1.h" +#include "who_wmac_iv.h" +#include "tlv_tag_def.h" +#include "mactx_cbf_data.h" +#include "mactx_cbf_done.h" +#include "mactx_cbf_start.h" +#include "mactx_data_resp.h" +#include "phyrx_abort_request.h" +#include "phyrx_cbf_data_resp.h" +#include "phyrx_data.h" +#include "phyrx_user_abort_notification.h" +#include "macrx_abort_request.h" +#include "macrx_cbf_data_request.h" +#include "macrx_cbf_read_request.h" +#include "macrx_chain_mask.h" +#include "macrx_expect_ndp_reception.h" +#include "macrx_freeze_capture_channel.h" +#include "macrx_req_implicit_fb.h" +#include "phytx_abort_request.h" +#include "phytx_bf_cv_loading_done.h" +#include "phytx_nap_ack.h" +#include "phytx_pkt_end.h" +#include "phytx_ppdu_header_info_request.h" +#include "phytx_request_ctrl_info.h" + + +#endif diff --git a/hw/qca6290/v1/tcl_data_cmd.h b/hw/qca6290/v1/tcl_data_cmd.h new file mode 100644 index 000000000000..dd4920945cde --- /dev/null +++ b/hw/qca6290/v1/tcl_data_cmd.h @@ -0,0 +1,890 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_addr_info; +// 2 buf_or_ext_desc_type[0], epd[1], encap_type[3:2], encrypt_type[7:4], src_buffer_swap[8], link_meta_swap[9], reserved[13:10], addrx_en[14], addry_en[15], tcl_cmd_number[31:16] +// 3 data_length[15:0], ipv4_checksum_en[16], udp_over_ipv4_checksum_en[17], udp_over_ipv6_checksum_en[18], tcp_over_ipv4_checksum_en[19], tcp_over_ipv6_checksum_en[20], to_fw[21], dscp_to_tid_priority_table_id[22], packet_offset[31:23] +// 4 buffer_timestamp[18:0], buffer_timestamp_valid[19], mesh_enable[20], hlos_tid_overwrite[21], hlos_tid[25:22], reserved_4[31:26] +// 5 reserved_5[31:0] +// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_DATA_CMD 7 + +struct tcl_data_cmd { + struct buffer_addr_info buf_addr_info; + uint32_t buf_or_ext_desc_type : 1, //[0] + epd : 1, //[1] + encap_type : 2, //[3:2] + encrypt_type : 4, //[7:4] + src_buffer_swap : 1, //[8] + link_meta_swap : 1, //[9] + reserved : 4, //[13:10] + addrx_en : 1, //[14] + addry_en : 1, //[15] + tcl_cmd_number : 16; //[31:16] + uint32_t data_length : 16, //[15:0] + ipv4_checksum_en : 1, //[16] + udp_over_ipv4_checksum_en : 1, //[17] + udp_over_ipv6_checksum_en : 1, //[18] + tcp_over_ipv4_checksum_en : 1, //[19] + tcp_over_ipv6_checksum_en : 1, //[20] + to_fw : 1, //[21] + dscp_to_tid_priority_table_id : 1, //[22] + packet_offset : 9; //[31:23] + uint32_t buffer_timestamp : 19, //[18:0] + buffer_timestamp_valid : 1, //[19] + mesh_enable : 1, //[20] + hlos_tid_overwrite : 1, //[21] + hlos_tid : 4, //[25:22] + reserved_4 : 6; //[31:26] + uint32_t reserved_5 : 32; //[31:0] + uint32_t reserved_6a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info buf_addr_info + + Details of the physical address for a single buffer + + It also contains return ownership info as well as some + meta data for SW related to this buffer. + + + + In case of Buf_or_ext_desc_type indicating + 'MSDU_buffer', this address indicates the start of the meta + data that is preceding the actual packet data. + + The start of the actual packet data is provided by + field: Packet_offset + +buf_or_ext_desc_type + + The address points to an MSDU + buffer. + + The address points to an + MSDU link extension descriptor + + < legal all> + +epd + + When this bit is set then input packet is an EPD type + + + +encap_type + + Indicates the encapsulation that HW will perform: + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + Used by the OLE during encapsulation. + + + +encrypt_type + + Field only valid for encap_type: RAW + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + +src_buffer_swap + + Treats source memory (packet buffer) organization as + big-endian. The packets are read and byte swapped. + + 1'b0: Source memory is little endian + + 1'b1: Source memory is big endian + + + +link_meta_swap + + Treats link descriptor and Metadata as big-endian. The + link descriptor/Metadata is read and byte swapped. + + 1'b0: Memory is little endian + + 1'b1: Memory is big endian + + + +reserved + + + +addrx_en + + Address X search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + + +addry_en + + Address Y search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + + +tcl_cmd_number + + This number can be used by SW to track, identify and + link the created commands with the command statuses + + + + Is set to the value 'TCL_CMD_Number' of the related + TCL_DATA command + + + +data_length + + Valid Data length in bytes. + + + + MSDU length in case of direct descriptor. + + Length of link extension descriptor in case of Link + extension descriptor. This is used to know the size of + Metadata. + + + +ipv4_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable IPv4 checksum replacement + +udp_over_ipv4_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. + +udp_over_ipv6_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. + +tcp_over_ipv4_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv4 replacement + +tcp_over_ipv6_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv6 replacement + +to_fw + + Forward packet to FW along with classification result. + The packet will not be forward to TQM when this bit is set + + 1'b0: Use classification result to forward the packet. + + 1'b1: Override classification result and forward packet + only to FW. + +dscp_to_tid_priority_table_id + + The DSCP to tid conversion table to be used for this + frame + + + +packet_offset + + Packet offset from Metadata in case of direct buffer + descriptor. This field is valid when Buf_or_ext_desc_type is + reset(= 0). + + + +buffer_timestamp + + Field only valid when 'Buffer_timestamp_valid ' is set. + + + + Frame system entrance timestamp. The timestamp is + related to the global system timer + + + + Generally the first module (SW, TCL or TQM). that sees + this frame and this timestamp field is not valid, shall fill + in this field. + + + + Timestamp in units of 1024 us + +buffer_timestamp_valid + + When set, the Buffer_timestamp field contains valid + info. + +mesh_enable + + If set to 1: + + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit is + ignored), + + * For native WiFi frames, this indicates that a 'Mesh + Control' field is present between the header and the LLC. + +hlos_tid_overwrite + + When set, TCL shall ignore the IP DSCP and VLAN PCP + fields and use HLOS_TID as the final TID. Otherwise TCL + shall consider the DSCP and PCP fields as well as HLOS_TID + and choose a final TID based on the configured priority + + + +hlos_tid + + HLOS MSDU priority + + + + Field is used when HLOS_TID_overwrite is set. + + + + Field is also used when HLOS_TID_overwrite is not set + and DSCP/PCP is not available in the packet + + + +reserved_4 + + + +reserved_5 + + + +reserved_6a + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000000 +#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 28 +#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff +#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 28 +#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff + +/* Description TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE + + The address points to an MSDU + buffer. + + The address points to an + MSDU link extension descriptor + + < legal all> +*/ +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 + +/* Description TCL_DATA_CMD_2_EPD + + When this bit is set then input packet is an EPD type + + +*/ +#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_EPD_LSB 1 +#define TCL_DATA_CMD_2_EPD_MASK 0x00000002 + +/* Description TCL_DATA_CMD_2_ENCAP_TYPE + + Indicates the encapsulation that HW will perform: + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + Used by the OLE during encapsulation. + + +*/ +#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 +#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c + +/* Description TCL_DATA_CMD_2_ENCRYPT_TYPE + + Field only valid for encap_type: RAW + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + +*/ +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 + +/* Description TCL_DATA_CMD_2_SRC_BUFFER_SWAP + + Treats source memory (packet buffer) organization as + big-endian. The packets are read and byte swapped. + + 1'b0: Source memory is little endian + + 1'b1: Source memory is big endian + + +*/ +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 + +/* Description TCL_DATA_CMD_2_LINK_META_SWAP + + Treats link descriptor and Metadata as big-endian. The + link descriptor/Metadata is read and byte swapped. + + 1'b0: Memory is little endian + + 1'b1: Memory is big endian + + +*/ +#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 +#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 + +/* Description TCL_DATA_CMD_2_RESERVED + + +*/ +#define TCL_DATA_CMD_2_RESERVED_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_RESERVED_LSB 10 +#define TCL_DATA_CMD_2_RESERVED_MASK 0x00003c00 + +/* Description TCL_DATA_CMD_2_ADDRX_EN + + Address X search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + +*/ +#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 +#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 + +/* Description TCL_DATA_CMD_2_ADDRY_EN + + Address Y search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + +*/ +#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 +#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 + +/* Description TCL_DATA_CMD_2_TCL_CMD_NUMBER + + This number can be used by SW to track, identify and + link the created commands with the command statuses + + + + Is set to the value 'TCL_CMD_Number' of the related + TCL_DATA command + + +*/ +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 + +/* Description TCL_DATA_CMD_3_DATA_LENGTH + + Valid Data length in bytes. + + + + MSDU length in case of direct descriptor. + + Length of link extension descriptor in case of Link + extension descriptor. This is used to know the size of + Metadata. + + +*/ +#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff + +/* Description TCL_DATA_CMD_3_IPV4_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable IPv4 checksum replacement +*/ +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 + +/* Description TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +/* Description TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +/* Description TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv4 replacement +*/ +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +/* Description TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv6 replacement +*/ +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +/* Description TCL_DATA_CMD_3_TO_FW + + Forward packet to FW along with classification result. + The packet will not be forward to TQM when this bit is set + + 1'b0: Use classification result to forward the packet. + + 1'b1: Override classification result and forward packet + only to FW. +*/ +#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TO_FW_LSB 21 +#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 + +/* Description TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID + + The DSCP to tid conversion table to be used for this + frame + + +*/ +#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_LSB 22 +#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_MASK 0x00400000 + +/* Description TCL_DATA_CMD_3_PACKET_OFFSET + + Packet offset from Metadata in case of direct buffer + descriptor. This field is valid when Buf_or_ext_desc_type is + reset(= 0). + + +*/ +#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 + +/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP + + Field only valid when 'Buffer_timestamp_valid ' is set. + + + + Frame system entrance timestamp. The timestamp is + related to the global system timer + + + + Generally the first module (SW, TCL or TQM). that sees + this frame and this timestamp field is not valid, shall fill + in this field. + + + + Timestamp in units of 1024 us +*/ +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff + +/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID + + When set, the Buffer_timestamp field contains valid + info. +*/ +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 + +/* Description TCL_DATA_CMD_4_MESH_ENABLE + + If set to 1: + + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit is + ignored), + + * For native WiFi frames, this indicates that a 'Mesh + Control' field is present between the header and the LLC. +*/ +#define TCL_DATA_CMD_4_MESH_ENABLE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_MESH_ENABLE_LSB 20 +#define TCL_DATA_CMD_4_MESH_ENABLE_MASK 0x00100000 + +/* Description TCL_DATA_CMD_4_HLOS_TID_OVERWRITE + + When set, TCL shall ignore the IP DSCP and VLAN PCP + fields and use HLOS_TID as the final TID. Otherwise TCL + shall consider the DSCP and PCP fields as well as HLOS_TID + and choose a final TID based on the configured priority + + +*/ +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 + +/* Description TCL_DATA_CMD_4_HLOS_TID + + HLOS MSDU priority + + + + Field is used when HLOS_TID_overwrite is set. + + + + Field is also used when HLOS_TID_overwrite is not set + and DSCP/PCP is not available in the packet + + +*/ +#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_LSB 22 +#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 + +/* Description TCL_DATA_CMD_4_RESERVED_4 + + +*/ +#define TCL_DATA_CMD_4_RESERVED_4_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4_LSB 26 +#define TCL_DATA_CMD_4_RESERVED_4_MASK 0xfc000000 + +/* Description TCL_DATA_CMD_5_RESERVED_5 + + +*/ +#define TCL_DATA_CMD_5_RESERVED_5_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_RESERVED_5_LSB 0 +#define TCL_DATA_CMD_5_RESERVED_5_MASK 0xffffffff + +/* Description TCL_DATA_CMD_6_RESERVED_6A + + +*/ +#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 +#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff + +/* Description TCL_DATA_CMD_6_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RING_ID_LSB 20 +#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 + +/* Description TCL_DATA_CMD_6_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_DATA_CMD_H_ diff --git a/hw/qca6290/v1/tcl_gse_cmd.h b/hw/qca6290/v1/tcl_gse_cmd.h new file mode 100644 index 000000000000..56eee91a6ca9 --- /dev/null +++ b/hw/qca6290/v1/tcl_gse_cmd.h @@ -0,0 +1,408 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 control_buffer_addr_31_0[31:0] +// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15] +// 2 cmd_meta_data_31_0[31:0] +// 3 cmd_meta_data_63_32[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_GSE_CMD 7 + +struct tcl_gse_cmd { + uint32_t control_buffer_addr_31_0 : 32; //[31:0] + uint32_t control_buffer_addr_39_32 : 8, //[7:0] + gse_ctrl : 4, //[11:8] + gse_sel : 1, //[12] + status_destination_ring_id : 1, //[13] + swap : 1, //[14] + reserved_1a : 17; //[31:15] + uint32_t cmd_meta_data_31_0 : 32; //[31:0] + uint32_t cmd_meta_data_63_32 : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +control_buffer_addr_31_0 + + Address (lower 32 bits) of a control buffer containing + additional info needed for this command execution. + + + +control_buffer_addr_39_32 + + Address (upper 8 bits) of a control buffer containing + additional info needed for this command execution. + + + +gse_ctrl + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported + +gse_sel + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + + 0: FSE select + + 1: ASE select + +status_destination_ring_id + + The TCL status ring to which the GSE status needs to be + send. + + + + + + + + + + + +swap + + Bit to enable byte swapping of contents of buffer + + + + + + + +reserved_1a + + + +cmd_meta_data_31_0 + + Meta data to be returned in the status descriptor + + + +cmd_meta_data_63_32 + + Meta data to be returned in the status descriptor + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +ring_id + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of a control buffer containing + additional info needed for this command execution. + + +*/ +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of a control buffer containing + additional info needed for this command execution. + + +*/ +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description TCL_GSE_CMD_1_GSE_CTRL + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported +*/ +#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 + +/* Description TCL_GSE_CMD_1_GSE_SEL + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + + 0: FSE select + + 1: ASE select +*/ +#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 + +/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID + + The TCL status ring to which the GSE status needs to be + send. + + + + + + + + + + +*/ +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +/* Description TCL_GSE_CMD_1_SWAP + + Bit to enable byte swapping of contents of buffer + + + + + + +*/ +#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_SWAP_LSB 14 +#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 + +/* Description TCL_GSE_CMD_1_RESERVED_1A + + +*/ +#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_RESERVED_1A_LSB 15 +#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xffff8000 + +/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 + + Meta data to be returned in the status descriptor + + +*/ +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff + +/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 + + Meta data to be returned in the status descriptor + + +*/ +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff + +/* Description TCL_GSE_CMD_4_RESERVED_4A + + +*/ +#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 +#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff + +/* Description TCL_GSE_CMD_5_RESERVED_5A + + +*/ +#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff + +/* Description TCL_GSE_CMD_6_RESERVED_6A + + +*/ +#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff + +/* Description TCL_GSE_CMD_6_RING_ID + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RING_ID_LSB 20 +#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 + +/* Description TCL_GSE_CMD_6_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_GSE_CMD_H_ diff --git a/hw/qca6290/v1/tcl_status_ring.h b/hw/qca6290/v1/tcl_status_ring.h new file mode 100644 index 000000000000..c4178c93da33 --- /dev/null +++ b/hw/qca6290/v1/tcl_status_ring.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], reserved_0a[7], msdu_cnt_n[31:8] +// 1 msdu_byte_cnt_n[31:0] +// 2 msdu_timestmp_n[31:0] +// 3 cmd_meta_data_31_0[31:0] +// 4 cmd_meta_data_63_32[31:0] +// 5 hash_indx_val[19:0], reserved_5a[31:20] +// 6 reserved_6a[31:0] +// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { + uint32_t gse_ctrl : 4, //[3:0] + ase_fse_sel : 1, //[4] + cache_op_res : 2, //[6:5] + reserved_0a : 1, //[7] + msdu_cnt_n : 24; //[31:8] + uint32_t msdu_byte_cnt_n : 32; //[31:0] + uint32_t msdu_timestmp_n : 32; //[31:0] + uint32_t cmd_meta_data_31_0 : 32; //[31:0] + uint32_t cmd_meta_data_63_32 : 32; //[31:0] + uint32_t hash_indx_val : 20, //[19:0] + reserved_5a : 12; //[31:20] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +gse_ctrl + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported + +ase_fse_sel + + Search Engine for which operation is done. + + 1'b0: Address Search Engine Result + + 1'b1: Flow Search Engine result + +cache_op_res + + Cache operation result. Following are results of cache + operation. + + Operation successful + + Entry not found in Table + + Timeout Error + + + +reserved_0a + + + +msdu_cnt_n + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 + +msdu_byte_cnt_n + + MSDU byte count for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 + +msdu_timestmp_n + + MSDU timestamp for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 + +cmd_meta_data_31_0 + + Meta data from input ring + + + +cmd_meta_data_63_32 + + Meta data from input ring + + + +hash_indx_val + + + Hash value of the entry in table in case of search + failed or search disable. + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +ring_id + + The buffer pointer ring ID. + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description TCL_STATUS_RING_0_GSE_CTRL + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported +*/ +#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f + +/* Description TCL_STATUS_RING_0_ASE_FSE_SEL + + Search Engine for which operation is done. + + 1'b0: Address Search Engine Result + + 1'b1: Flow Search Engine result +*/ +#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 + +/* Description TCL_STATUS_RING_0_CACHE_OP_RES + + Cache operation result. Following are results of cache + operation. + + Operation successful + + Entry not found in Table + + Timeout Error + + +*/ +#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 + +/* Description TCL_STATUS_RING_0_RESERVED_0A + + +*/ +#define TCL_STATUS_RING_0_RESERVED_0A_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_RESERVED_0A_LSB 7 +#define TCL_STATUS_RING_0_RESERVED_0A_MASK 0x00000080 + +/* Description TCL_STATUS_RING_0_MSDU_CNT_N + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 +*/ +#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 + +/* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N + + MSDU byte count for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 +*/ +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff + +/* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N + + MSDU timestamp for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 +*/ +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff + +/* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0 + + Meta data from input ring + + +*/ +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff + +/* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32 + + Meta data from input ring + + +*/ +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff + +/* Description TCL_STATUS_RING_5_HASH_INDX_VAL + + + Hash value of the entry in table in case of search + failed or search disable. + + +*/ +#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff + +/* Description TCL_STATUS_RING_5_RESERVED_5A + + +*/ +#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_RESERVED_5A_LSB 20 +#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xfff00000 + +/* Description TCL_STATUS_RING_6_RESERVED_6A + + +*/ +#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff + +/* Description TCL_STATUS_RING_7_RESERVED_7A + + +*/ +#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff + +/* Description TCL_STATUS_RING_7_RING_ID + + The buffer pointer ring ID. + + + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RING_ID_LSB 20 +#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description TCL_STATUS_RING_7_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_STATUS_RING_H_ diff --git a/hw/qca6290/v1/tlv_hdr.h b/hw/qca6290/v1/tlv_hdr.h new file mode 100644 index 000000000000..17957c0d8946 --- /dev/null +++ b/hw/qca6290/v1/tlv_hdr.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +struct tlv_usr_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_usrid : 6; +}; + +struct tlv_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_reserved : 6; +}; + +struct tlv_usr_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6; +}; + +struct tlv_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 6; +}; + +struct tlv_usr_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6, + tlv_reserved : 10, + pad_42to64_bit : 22; +}; + +struct tlv_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 16, + pad_42to64_bit : 22; +}; + +struct tlv_usr_c_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_ctag : 3, + tlv_usrid : 6, + tlv_cdata : 32, + pad_42to64_bit : 22; +}; + +#endif diff --git a/hw/qca6290/v1/tlv_tag_def.h b/hw/qca6290/v1/tlv_tag_def.h new file mode 100644 index 000000000000..ca0c5aff3037 --- /dev/null +++ b/hw/qca6290/v1/tlv_tag_def.h @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * Generated file ... Do not hand edit ... + */ + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum { + + WIFIMACTX_CBF_START_E = 0 /* 0x0 */, + WIFIPHYRX_DATA_E = 1 /* 0x1 */, + WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */, + WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */, + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */, + WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */, + WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */, + WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */, + WIFIMACRX_CBF_READ_REQUEST_E = 8 /* 0x8 */, + WIFIMACRX_CBF_DATA_REQUEST_E = 9 /* 0x9 */, + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 /* 0xa */, + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 /* 0xb */, + WIFIMACRX_NDP_TIMEOUT_E = 12 /* 0xc */, + WIFIMACRX_ABORT_ACK_E = 13 /* 0xd */, + WIFIMACRX_REQ_IMPLICIT_FB_E = 14 /* 0xe */, + WIFIMACRX_CHAIN_MASK_E = 15 /* 0xf */, + WIFIMACRX_NAP_USER_E = 16 /* 0x10 */, + WIFIMACRX_ABORT_REQUEST_E = 17 /* 0x11 */, + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 /* 0x12 */, + WIFIPHYTX_ABORT_ACK_E = 19 /* 0x13 */, + WIFIPHYTX_ABORT_REQUEST_E = 20 /* 0x14 */, + WIFIPHYTX_PKT_END_E = 21 /* 0x15 */, + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 /* 0x16 */, + WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 /* 0x17 */, + WIFIPHYTX_DATA_REQUEST_E = 24 /* 0x18 */, + WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 /* 0x19 */, + WIFIPHYTX_NAP_ACK_E = 26 /* 0x1a */, + WIFIPHYTX_NAP_DONE_E = 27 /* 0x1b */, + WIFIPHYTX_OFF_ACK_E = 28 /* 0x1c */, + WIFIPHYTX_ON_ACK_E = 29 /* 0x1d */, + WIFIPHYTX_SYNTH_OFF_ACK_E = 30 /* 0x1e */, + WIFIPHYTX_DEBUG16_E = 31 /* 0x1f */, + WIFIMACTX_ABORT_REQUEST_E = 32 /* 0x20 */, + WIFIMACTX_ABORT_ACK_E = 33 /* 0x21 */, + WIFIMACTX_PKT_END_E = 34 /* 0x22 */, + WIFIMACTX_PRE_PHY_DESC_E = 35 /* 0x23 */, + WIFIMACTX_BF_PARAMS_COMMON_E = 36 /* 0x24 */, + WIFIMACTX_BF_PARAMS_PER_USER_E = 37 /* 0x25 */, + WIFIMACTX_PREFETCH_CV_E = 38 /* 0x26 */, + WIFIMACTX_USER_DESC_COMMON_E = 39 /* 0x27 */, + WIFIMACTX_USER_DESC_PER_USER_E = 40 /* 0x28 */, + WIFIEXAMPLE_USER_TLV_16_E = 41 /* 0x29 */, + WIFIEXAMPLE_TLV_16_E = 42 /* 0x2a */, + WIFIMACTX_PHY_OFF_E = 43 /* 0x2b */, + WIFIMACTX_PHY_ON_E = 44 /* 0x2c */, + WIFIMACTX_SYNTH_OFF_E = 45 /* 0x2d */, + WIFIMACTX_EXPECT_CBF_COMMON_E = 46 /* 0x2e */, + WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 /* 0x2f */, + WIFIMACTX_PHY_DESC_E = 48 /* 0x30 */, + WIFIMACTX_L_SIG_A_E = 49 /* 0x31 */, + WIFIMACTX_L_SIG_B_E = 50 /* 0x32 */, + WIFIMACTX_HT_SIG_E = 51 /* 0x33 */, + WIFIMACTX_VHT_SIG_A_E = 52 /* 0x34 */, + WIFIMACTX_VHT_SIG_B_SU20_E = 53 /* 0x35 */, + WIFIMACTX_VHT_SIG_B_SU40_E = 54 /* 0x36 */, + WIFIMACTX_VHT_SIG_B_SU80_E = 55 /* 0x37 */, + WIFIMACTX_VHT_SIG_B_SU160_E = 56 /* 0x38 */, + WIFIMACTX_VHT_SIG_B_MU20_E = 57 /* 0x39 */, + WIFIMACTX_VHT_SIG_B_MU40_E = 58 /* 0x3a */, + WIFIMACTX_VHT_SIG_B_MU80_E = 59 /* 0x3b */, + WIFIMACTX_VHT_SIG_B_MU160_E = 60 /* 0x3c */, + WIFIMACTX_SERVICE_E = 61 /* 0x3d */, + WIFIMACTX_HE_SIG_A_SU_E = 62 /* 0x3e */, + WIFIMACTX_HE_SIG_A_MU_DL_E = 63 /* 0x3f */, + WIFIMACTX_HE_SIG_A_MU_UL_E = 64 /* 0x40 */, + WIFIMACTX_HE_SIG_B1_MU_E = 65 /* 0x41 */, + WIFIMACTX_HE_SIG_B2_MU_E = 66 /* 0x42 */, + WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 /* 0x43 */, + WIFIMACTX_DELETE_CV_E = 68 /* 0x44 */, + WIFIMACTX_MU_UPLINK_COMMON_E = 69 /* 0x45 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 /* 0x46 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 /* 0x47 */, + WIFIMACTX_PHY_NAP_E = 72 /* 0x48 */, + WIFIMACTX_DEBUG_E = 73 /* 0x49 */, + WIFIPHYRX_ABORT_ACK_E = 74 /* 0x4a */, + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 /* 0x4b */, + WIFIPHYRX_RSSI_LEGACY_E = 76 /* 0x4c */, + WIFIPHYRX_RSSI_HT_E = 77 /* 0x4d */, + WIFIPHYRX_USER_INFO_E = 78 /* 0x4e */, + WIFIPHYRX_PKT_END_E = 79 /* 0x4f */, + WIFIPHYRX_DEBUG_E = 80 /* 0x50 */, + WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 /* 0x51 */, + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 /* 0x52 */, + WIFIPHYRX_L_SIG_A_E = 83 /* 0x53 */, + WIFIPHYRX_L_SIG_B_E = 84 /* 0x54 */, + WIFIPHYRX_HT_SIG_E = 85 /* 0x55 */, + WIFIPHYRX_VHT_SIG_A_E = 86 /* 0x56 */, + WIFIPHYRX_VHT_SIG_B_SU20_E = 87 /* 0x57 */, + WIFIPHYRX_VHT_SIG_B_SU40_E = 88 /* 0x58 */, + WIFIPHYRX_VHT_SIG_B_SU80_E = 89 /* 0x59 */, + WIFIPHYRX_VHT_SIG_B_SU160_E = 90 /* 0x5a */, + WIFIPHYRX_VHT_SIG_B_MU20_E = 91 /* 0x5b */, + WIFIPHYRX_VHT_SIG_B_MU40_E = 92 /* 0x5c */, + WIFIPHYRX_VHT_SIG_B_MU80_E = 93 /* 0x5d */, + WIFIPHYRX_VHT_SIG_B_MU160_E = 94 /* 0x5e */, + WIFIPHYRX_HE_SIG_A_SU_E = 95 /* 0x5f */, + WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 /* 0x60 */, + WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 /* 0x61 */, + WIFIPHYRX_HE_SIG_B1_MU_E = 98 /* 0x62 */, + WIFIPHYRX_HE_SIG_B2_MU_E = 99 /* 0x63 */, + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 /* 0x64 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 /* 0x65 */, + WIFIPHYRX_COMMON_USER_INFO_E = 102 /* 0x66 */, + WIFIPHYRX_DATA_DONE_E = 103 /* 0x67 */, + WIFIRECEIVE_RSSI_INFO_E = 104 /* 0x68 */, + WIFIRECEIVE_USER_INFO_E = 105 /* 0x69 */, + WIFIMIMO_CONTROL_INFO_E = 106 /* 0x6a */, + WIFIRX_LOCATION_INFO_E = 107 /* 0x6b */, + WIFICOEX_TX_REQ_E = 108 /* 0x6c */, + WIFIDUMMY_E = 109 /* 0x6d */, + WIFIRX_TIMING_OFFSET_INFO_E = 110 /* 0x6e */, + WIFIEXAMPLE_TLV_32_NAME_E = 111 /* 0x6f */, + WIFIMPDU_LIMIT_E = 112 /* 0x70 */, + WIFINA_LENGTH_END_E = 113 /* 0x71 */, + WIFIOLE_BUF_STATUS_E = 114 /* 0x72 */, + WIFIPCU_PPDU_SETUP_DONE_E = 115 /* 0x73 */, + WIFIPCU_PPDU_SETUP_END_E = 116 /* 0x74 */, + WIFIPCU_PPDU_SETUP_INIT_E = 117 /* 0x75 */, + WIFIPCU_PPDU_SETUP_START_E = 118 /* 0x76 */, + WIFIPDG_FES_SETUP_E = 119 /* 0x77 */, + WIFIPDG_RESPONSE_E = 120 /* 0x78 */, + WIFIPDG_TX_REQ_E = 121 /* 0x79 */, + WIFISCH_WAIT_INSTR_E = 122 /* 0x7a */, + WIFISCHEDULER_TLV_E = 123 /* 0x7b */, + WIFITQM_FLOW_EMPTY_STATUS_E = 124 /* 0x7c */, + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 /* 0x7d */, + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 /* 0x7e */, + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 /* 0x7f */, + WIFITQM_GEN_MPDUS_E = 128 /* 0x80 */, + WIFITQM_GEN_MPDUS_STATUS_E = 129 /* 0x81 */, + WIFITQM_REMOVE_MPDU_E = 130 /* 0x82 */, + WIFITQM_REMOVE_MPDU_STATUS_E = 131 /* 0x83 */, + WIFITQM_REMOVE_MSDU_E = 132 /* 0x84 */, + WIFITQM_REMOVE_MSDU_STATUS_E = 133 /* 0x85 */, + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 /* 0x86 */, + WIFITQM_WRITE_CMD_E = 135 /* 0x87 */, + WIFIOFDMA_TRIGGER_DETAILS_E = 136 /* 0x88 */, + WIFITX_DATA_E = 137 /* 0x89 */, + WIFITX_FES_SETUP_E = 138 /* 0x8a */, + WIFIRX_PACKET_E = 139 /* 0x8b */, + WIFIEXPECTED_RESPONSE_E = 140 /* 0x8c */, + WIFITX_MPDU_END_E = 141 /* 0x8d */, + WIFITX_MPDU_START_E = 142 /* 0x8e */, + WIFITX_MSDU_END_E = 143 /* 0x8f */, + WIFITX_MSDU_START_E = 144 /* 0x90 */, + WIFITX_SW_MODE_SETUP_E = 145 /* 0x91 */, + WIFITXPCU_BUFFER_STATUS_E = 146 /* 0x92 */, + WIFITXPCU_USER_BUFFER_STATUS_E = 147 /* 0x93 */, + WIFIDATA_TO_TIME_CONFIG_E = 148 /* 0x94 */, + WIFIEXAMPLE_USER_TLV_32_E = 149 /* 0x95 */, + WIFIMPDU_INFO_E = 150 /* 0x96 */, + WIFIPDG_USER_SETUP_E = 151 /* 0x97 */, + WIFITX_11AH_SETUP_E = 152 /* 0x98 */, + WIFITX_CV_START_E = 153 /* 0x99 */, + WIFITX_PEER_ENTRY_E = 154 /* 0x9a */, + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */, + WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */, + WIFIPCU_PPDU_SETUP_END_INFO_E = 157 /* 0x9d */, + WIFIPPDU_RATE_SETTING_E = 158 /* 0x9e */, + WIFIPROT_RATE_SETTING_E = 159 /* 0x9f */, + WIFIRX_MPDU_DETAILS_E = 160 /* 0xa0 */, + WIFIEXAMPLE_USER_TLV_42_E = 161 /* 0xa1 */, + WIFIRX_MSDU_LINK_E = 162 /* 0xa2 */, + WIFIRX_REO_QUEUE_E = 163 /* 0xa3 */, + WIFIADDR_SEARCH_ENTRY_E = 164 /* 0xa4 */, + WIFISCHEDULER_CMD_E = 165 /* 0xa5 */, + WIFITX_FLUSH_E = 166 /* 0xa6 */, + WIFITQM_ENTRANCE_RING_E = 167 /* 0xa7 */, + WIFITX_DATA_WORD_E = 168 /* 0xa8 */, + WIFITX_MPDU_DETAILS_E = 169 /* 0xa9 */, + WIFITX_MPDU_LINK_E = 170 /* 0xaa */, + WIFITX_MPDU_LINK_PTR_E = 171 /* 0xab */, + WIFITX_MPDU_QUEUE_HEAD_E = 172 /* 0xac */, + WIFITX_MPDU_QUEUE_EXT_E = 173 /* 0xad */, + WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 /* 0xae */, + WIFITX_MSDU_DETAILS_E = 175 /* 0xaf */, + WIFITX_MSDU_EXTENSION_E = 176 /* 0xb0 */, + WIFITX_MSDU_FLOW_E = 177 /* 0xb1 */, + WIFITX_MSDU_LINK_E = 178 /* 0xb2 */, + WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 /* 0xb3 */, + WIFIRESPONSE_RATE_SETTING_E = 180 /* 0xb4 */, + WIFITXPCU_BUFFER_BASICS_E = 181 /* 0xb5 */, + WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 /* 0xb6 */, + WIFIUNIFORM_TQM_CMD_HEADER_E = 183 /* 0xb7 */, + WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 /* 0xb8 */, + WIFIUSER_RATE_SETTING_E = 185 /* 0xb9 */, + WIFIWBM_BUFFER_RING_E = 186 /* 0xba */, + WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 /* 0xbb */, + WIFIWBM_RELEASE_RING_E = 188 /* 0xbc */, + WIFITX_FLUSH_REQ_E = 189 /* 0xbd */, + WIFIRX_MSDU_DETAILS_E = 190 /* 0xbe */, + WIFITQM_WRITE_CMD_STATUS_E = 191 /* 0xbf */, + WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 /* 0xc0 */, + WIFITQM_GET_MSDU_FLOW_STATS_E = 193 /* 0xc1 */, + WIFIEXAMPLE_USER_CTLV_32_E = 194 /* 0xc2 */, + WIFITX_FES_STATUS_START_E = 195 /* 0xc3 */, + WIFITX_FES_STATUS_USER_PPDU_E = 196 /* 0xc4 */, + WIFITX_FES_STATUS_USER_RESPONSE_E = 197 /* 0xc5 */, + WIFITX_FES_STATUS_END_E = 198 /* 0xc6 */, + WIFIRX_TRIG_INFO_E = 199 /* 0xc7 */, + WIFIRXPCU_TX_SETUP_CLEAR_E = 200 /* 0xc8 */, + WIFIRX_FRAME_BITMAP_REQ_E = 201 /* 0xc9 */, + WIFIRX_FRAME_BITMAP_ACK_E = 202 /* 0xca */, + WIFICOEX_RX_STATUS_E = 203 /* 0xcb */, + WIFIRX_START_PARAM_E = 204 /* 0xcc */, + WIFIRX_PPDU_START_E = 205 /* 0xcd */, + WIFIRX_PPDU_END_E = 206 /* 0xce */, + WIFIRX_MPDU_START_E = 207 /* 0xcf */, + WIFIRX_MPDU_END_E = 208 /* 0xd0 */, + WIFIRX_MSDU_START_E = 209 /* 0xd1 */, + WIFIRX_MSDU_END_E = 210 /* 0xd2 */, + WIFIRX_ATTENTION_E = 211 /* 0xd3 */, + WIFIRECEIVED_RESPONSE_INFO_E = 212 /* 0xd4 */, + WIFIRX_PHY_SLEEP_E = 213 /* 0xd5 */, + WIFIRX_HEADER_E = 214 /* 0xd6 */, + WIFIRX_PEER_ENTRY_E = 215 /* 0xd7 */, + WIFIRX_FLUSH_E = 216 /* 0xd8 */, + WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 /* 0xd9 */, + WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 /* 0xda */, + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 /* 0xdb */, + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 /* 0xdc */, + WIFITX_CBF_INFO_E = 221 /* 0xdd */, + WIFIPCU_PPDU_SETUP_USER_E = 222 /* 0xde */, + WIFIRX_MPDU_PCU_START_E = 223 /* 0xdf */, + WIFIRX_PM_INFO_E = 224 /* 0xe0 */, + WIFIRX_USER_PPDU_END_E = 225 /* 0xe1 */, + WIFIRX_PRE_PPDU_START_E = 226 /* 0xe2 */, + WIFIRX_PREAMBLE_E = 227 /* 0xe3 */, + WIFITX_FES_SETUP_COMPLETE_E = 228 /* 0xe4 */, + WIFITX_LAST_MPDU_FETCHED_E = 229 /* 0xe5 */, + WIFITXDMA_STOP_REQUEST_E = 230 /* 0xe6 */, + WIFIRXPCU_SETUP_E = 231 /* 0xe7 */, + WIFIRXPCU_USER_SETUP_E = 232 /* 0xe8 */, + WIFITX_FES_STATUS_ACK_OR_BA_E = 233 /* 0xe9 */, + WIFITQM_ACKED_MPDU_E = 234 /* 0xea */, + WIFICOEX_TX_RESP_E = 235 /* 0xeb */, + WIFICOEX_TX_STATUS_E = 236 /* 0xec */, + WIFIMACTX_COEX_PHY_CTRL_E = 237 /* 0xed */, + WIFICOEX_STATUS_BROADCAST_E = 238 /* 0xee */, + WIFIRESPONSE_START_STATUS_E = 239 /* 0xef */, + WIFIRESPONSE_END_STATUS_E = 240 /* 0xf0 */, + WIFICRYPTO_STATUS_E = 241 /* 0xf1 */, + WIFIRECEIVED_TRIGGER_INFO_E = 242 /* 0xf2 */, + WIFIREO_ENTRANCE_RING_E = 243 /* 0xf3 */, + WIFIRX_MPDU_LINK_E = 244 /* 0xf4 */, + WIFICOEX_TX_STOP_CTRL_E = 245 /* 0xf5 */, + WIFIRX_PPDU_ACK_REPORT_E = 246 /* 0xf6 */, + WIFIRX_PPDU_NO_ACK_REPORT_E = 247 /* 0xf7 */, + WIFISCH_COEX_STATUS_E = 248 /* 0xf8 */, + WIFISCHEDULER_COMMAND_STATUS_E = 249 /* 0xf9 */, + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */, + WIFITX_FES_STATUS_PROT_E = 251 /* 0xfb */, + WIFITX_FES_STATUS_START_PPDU_E = 252 /* 0xfc */, + WIFITX_FES_STATUS_START_PROT_E = 253 /* 0xfd */, + WIFITXPCU_PHYTX_DEBUG32_E = 254 /* 0xfe */, + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 /* 0xff */, + WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 /* 0x100 */, + WIFIWHO_ANCHOR_OFFSET_E = 257 /* 0x101 */, + WIFIWHO_ANCHOR_VALUE_E = 258 /* 0x102 */, + WIFIWHO_CCE_INFO_E = 259 /* 0x103 */, + WIFIWHO_COMMIT_E = 260 /* 0x104 */, + WIFIWHO_COMMIT_DONE_E = 261 /* 0x105 */, + WIFIWHO_FLUSH_E = 262 /* 0x106 */, + WIFIWHO_L2_LLC_E = 263 /* 0x107 */, + WIFIWHO_L2_PAYLOAD_E = 264 /* 0x108 */, + WIFIWHO_L3_CHECKSUM_E = 265 /* 0x109 */, + WIFIWHO_L3_INFO_E = 266 /* 0x10a */, + WIFIWHO_L4_CHECKSUM_E = 267 /* 0x10b */, + WIFIWHO_L4_INFO_E = 268 /* 0x10c */, + WIFIWHO_MSDU_E = 269 /* 0x10d */, + WIFIWHO_MSDU_MISC_E = 270 /* 0x10e */, + WIFIWHO_PACKET_DATA_E = 271 /* 0x10f */, + WIFIWHO_PACKET_HDR_E = 272 /* 0x110 */, + WIFIWHO_PPDU_END_E = 273 /* 0x111 */, + WIFIWHO_PPDU_START_E = 274 /* 0x112 */, + WIFIWHO_TSO_E = 275 /* 0x113 */, + WIFIWHO_WMAC_HEADER_PV0_E = 276 /* 0x114 */, + WIFIWHO_WMAC_HEADER_PV1_E = 277 /* 0x115 */, + WIFIWHO_WMAC_IV_E = 278 /* 0x116 */, + WIFIMPDU_INFO_END_E = 279 /* 0x117 */, + WIFIMPDU_INFO_BITMAP_E = 280 /* 0x118 */, + WIFITX_QUEUE_EXTENSION_E = 281 /* 0x119 */, + WIFIRX_PEER_ENTRY_DETAILS_E = 282 /* 0x11a */, + WIFIRX_REO_QUEUE_REFERENCE_E = 283 /* 0x11b */, + WIFIRX_REO_QUEUE_EXT_E = 284 /* 0x11c */, + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 /* 0x11d */, + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 /* 0x11e */, + WIFITQM_ACKED_MPDU_STATUS_E = 287 /* 0x11f */, + WIFITQM_ADD_MSDU_STATUS_E = 288 /* 0x120 */, + WIFIRX_MPDU_LINK_PTR_E = 289 /* 0x121 */, + WIFIREO_DESTINATION_RING_E = 290 /* 0x122 */, + WIFITQM_LIST_GEN_DONE_E = 291 /* 0x123 */, + WIFIWHO_TERMINATE_E = 292 /* 0x124 */, + WIFITX_LAST_MPDU_END_E = 293 /* 0x125 */, + WIFITX_CV_DATA_E = 294 /* 0x126 */, + WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 /* 0x127 */, + WIFIPPDU_TX_END_E = 296 /* 0x128 */, + WIFIPROT_TX_END_E = 297 /* 0x129 */, + WIFIPDG_RESPONSE_RATE_SETTING_E = 298 /* 0x12a */, + WIFIMPDU_INFO_GLOBAL_END_E = 299 /* 0x12b */, + WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 /* 0x12c */, + WIFIRX_PPDU_END_USER_STATS_E = 301 /* 0x12d */, + WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 /* 0x12e */, + WIFINO_ACK_REPORT_E = 303 /* 0x12f */, + WIFIACK_REPORT_E = 304 /* 0x130 */, + WIFIUNIFORM_REO_CMD_HEADER_E = 305 /* 0x131 */, + WIFIREO_GET_QUEUE_STATS_E = 306 /* 0x132 */, + WIFIREO_FLUSH_QUEUE_E = 307 /* 0x133 */, + WIFIREO_FLUSH_CACHE_E = 308 /* 0x134 */, + WIFIREO_UNBLOCK_CACHE_E = 309 /* 0x135 */, + WIFIUNIFORM_REO_STATUS_HEADER_E = 310 /* 0x136 */, + WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 /* 0x137 */, + WIFIREO_FLUSH_QUEUE_STATUS_E = 312 /* 0x138 */, + WIFIREO_FLUSH_CACHE_STATUS_E = 313 /* 0x139 */, + WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 /* 0x13a */, + WIFITQM_FLUSH_CACHE_E = 315 /* 0x13b */, + WIFITQM_UNBLOCK_CACHE_E = 316 /* 0x13c */, + WIFITQM_FLUSH_CACHE_STATUS_E = 317 /* 0x13d */, + WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 /* 0x13e */, + WIFIRX_PPDU_END_STATUS_DONE_E = 319 /* 0x13f */, + WIFIRX_STATUS_BUFFER_DONE_E = 320 /* 0x140 */, + WIFIBUFFER_ADDR_INFO_E = 321 /* 0x141 */, + WIFIRX_MSDU_DESC_INFO_E = 322 /* 0x142 */, + WIFIRX_MPDU_DESC_INFO_E = 323 /* 0x143 */, + WIFITCL_DATA_CMD_E = 324 /* 0x144 */, + WIFITCL_GSE_CMD_E = 325 /* 0x145 */, + WIFITCL_EXIT_BASE_E = 326 /* 0x146 */, + WIFITCL_COMPACT_EXIT_RING_E = 327 /* 0x147 */, + WIFITCL_REGULAR_EXIT_RING_E = 328 /* 0x148 */, + WIFITCL_EXTENDED_EXIT_RING_E = 329 /* 0x149 */, + WIFIUPLINK_COMMON_INFO_E = 330 /* 0x14a */, + WIFIUPLINK_USER_SETUP_INFO_E = 331 /* 0x14b */, + WIFITX_DATA_SYNC_E = 332 /* 0x14c */, + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 /* 0x14d */, + WIFITCL_STATUS_RING_E = 334 /* 0x14e */, + WIFITQM_GET_MPDU_HEAD_INFO_E = 335 /* 0x14f */, + WIFITQM_SYNC_CMD_E = 336 /* 0x150 */, + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 /* 0x151 */, + WIFITQM_SYNC_CMD_STATUS_E = 338 /* 0x152 */, + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */, + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */, + WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 /* 0x155 */, + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 /* 0x156 */, + WIFIREO_TO_PPE_RING_E = 343 /* 0x157 */, + WIFIRX_MPDU_INFO_E = 344 /* 0x158 */, + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */, + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */, + WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 /* 0x15b */, + WIFIRX_PPDU_START_USER_INFO_E = 348 /* 0x15c */, + WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 /* 0x15d */, + WIFIRX_RING_MASK_E = 350 /* 0x15e */, + WIFIWHO_CLASSIFY_INFO_E = 351 /* 0x15f */, + WIFITXPT_CLASSIFY_INFO_E = 352 /* 0x160 */, + WIFIRXPT_CLASSIFY_INFO_E = 353 /* 0x161 */, + WIFITX_FLOW_SEARCH_ENTRY_E = 354 /* 0x162 */, + WIFIRX_FLOW_SEARCH_ENTRY_E = 355 /* 0x163 */, + WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 /* 0x164 */, + WIFICOEX_MAC_NAP_E = 357 /* 0x165 */, + WIFIMACRX_ABORT_REQUEST_INFO_E = 358 /* 0x166 */, + WIFIMACTX_ABORT_REQUEST_INFO_E = 359 /* 0x167 */, + WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 /* 0x168 */, + WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 /* 0x169 */, + WIFIRXPCU_PPDU_END_INFO_E = 362 /* 0x16a */, + WIFIWHO_MESH_CONTROL_E = 363 /* 0x16b */, + WIFIL_SIG_A_INFO_E = 364 /* 0x16c */, + WIFIL_SIG_B_INFO_E = 365 /* 0x16d */, + WIFIHT_SIG_INFO_E = 366 /* 0x16e */, + WIFIVHT_SIG_A_INFO_E = 367 /* 0x16f */, + WIFIVHT_SIG_B_SU20_INFO_E = 368 /* 0x170 */, + WIFIVHT_SIG_B_SU40_INFO_E = 369 /* 0x171 */, + WIFIVHT_SIG_B_SU80_INFO_E = 370 /* 0x172 */, + WIFIVHT_SIG_B_SU160_INFO_E = 371 /* 0x173 */, + WIFIVHT_SIG_B_MU20_INFO_E = 372 /* 0x174 */, + WIFIVHT_SIG_B_MU40_INFO_E = 373 /* 0x175 */, + WIFIVHT_SIG_B_MU80_INFO_E = 374 /* 0x176 */, + WIFIVHT_SIG_B_MU160_INFO_E = 375 /* 0x177 */, + WIFISERVICE_INFO_E = 376 /* 0x178 */, + WIFIHE_SIG_A_SU_INFO_E = 377 /* 0x179 */, + WIFIHE_SIG_A_MU_DL_INFO_E = 378 /* 0x17a */, + WIFIHE_SIG_A_MU_UL_INFO_E = 379 /* 0x17b */, + WIFIHE_SIG_B1_MU_INFO_E = 380 /* 0x17c */, + WIFIHE_SIG_B2_MU_INFO_E = 381 /* 0x17d */, + WIFIHE_SIG_B2_OFDMA_INFO_E = 382 /* 0x17e */, + WIFIPDG_SW_MODE_BW_START_E = 383 /* 0x17f */, + WIFIPDG_SW_MODE_BW_END_E = 384 /* 0x180 */, + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 /* 0x181 */, + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 /* 0x182 */, + WIFISCHEDULER_END_E = 387 /* 0x183 */, + WIFIPEER_TABLE_ENTRY_E = 388 /* 0x184 */, + WIFISW_PEER_INFO_E = 389 /* 0x185 */, + WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 /* 0x186 */, + WIFITCL_CCE_CLASSIFY_INFO_E = 391 /* 0x187 */, + WIFIRXOLE_CCE_INFO_E = 392 /* 0x188 */, + WIFITCL_CCE_INFO_E = 393 /* 0x189 */, + WIFITCL_CCE_SUPERRULE_E = 394 /* 0x18a */, + WIFICCE_RULE_E = 395 /* 0x18b */, + WIFIRX_PPDU_START_DROPPED_E = 396 /* 0x18c */, + WIFIRX_PPDU_END_DROPPED_E = 397 /* 0x18d */, + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 /* 0x18e */, + WIFIRX_MPDU_START_DROPPED_E = 399 /* 0x18f */, + WIFIRX_MSDU_START_DROPPED_E = 400 /* 0x190 */, + WIFIRX_MSDU_END_DROPPED_E = 401 /* 0x191 */, + WIFIRX_MPDU_END_DROPPED_E = 402 /* 0x192 */, + WIFIRX_ATTENTION_DROPPED_E = 403 /* 0x193 */, + WIFITXPCU_USER_SETUP_E = 404 /* 0x194 */, + WIFIRXPCU_USER_SETUP_EXT_E = 405 /* 0x195 */, + WIFICE_SRC_DESC_E = 406 /* 0x196 */, + WIFICE_STAT_DESC_E = 407 /* 0x197 */, + WIFIRXOLE_CCE_SUPERRULE_E = 408 /* 0x198 */, + WIFITX_RATE_STATS_INFO_E = 409 /* 0x199 */, + WIFICMD_PART_0_END_E = 410 /* 0x19a */, + WIFIMACTX_SYNTH_ON_E = 411 /* 0x19b */, + WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 /* 0x19c */, + WIFITQM_MPDU_GLOBAL_START_E = 413 /* 0x19d */, + WIFIEXAMPLE_TLV_32_E = 414 /* 0x19e */, + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 /* 0x19f */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 /* 0x1a0 */, + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */, + WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 420 /* 0x1a4 */, + WIFITLV_BASE_E = 511 /* 0x1ff */ + +} tlv_tag_def__e; ///< tlv_tag_def Enum Type + +#endif // _TLV_TAG_DEF_ diff --git a/hw/qca6290/v1/tx_msdu_extension.h b/hw/qca6290/v1/tx_msdu_extension.h new file mode 100644 index 000000000000..bf7f00f2da8e --- /dev/null +++ b/hw/qca6290/v1/tx_msdu_extension.h @@ -0,0 +1,827 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 tso_enable[0], ipv4_checksum_en[1], udp_over_ipv4_checksum_en[2], udp_over_ipv6_checksum_en[3], tcp_over_ipv4_checksum_en[4], tcp_over_ipv6_checksum_en[5], reserved_0a[6], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25] +// 1 l2_length[15:0], ip_length[31:16] +// 2 tcp_seq_number[31:0] +// 3 ip_identification[15:0], udp_length[31:16] +// 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30] +// 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17] +// 6 buf0_ptr_31_0[31:0] +// 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16] +// 8 buf1_ptr_31_0[31:0] +// 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16] +// 10 buf2_ptr_31_0[31:0] +// 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16] +// 12 buf3_ptr_31_0[31:0] +// 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16] +// 14 buf4_ptr_31_0[31:0] +// 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16] +// 16 buf5_ptr_31_0[31:0] +// 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { + uint32_t tso_enable : 1, //[0] + ipv4_checksum_en : 1, //[1] + udp_over_ipv4_checksum_en : 1, //[2] + udp_over_ipv6_checksum_en : 1, //[3] + tcp_over_ipv4_checksum_en : 1, //[4] + tcp_over_ipv6_checksum_en : 1, //[5] + reserved_0a : 1, //[6] + tcp_flag : 9, //[15:7] + tcp_flag_mask : 9, //[24:16] + reserved_0b : 7; //[31:25] + uint32_t l2_length : 16, //[15:0] + ip_length : 16; //[31:16] + uint32_t tcp_seq_number : 32; //[31:0] + uint32_t ip_identification : 16, //[15:0] + udp_length : 16; //[31:16] + uint32_t checksum_offset : 14, //[13:0] + partial_checksum_en : 1, //[14] + reserved_4a : 1, //[15] + payload_start_offset : 14, //[29:16] + reserved_4b : 2; //[31:30] + uint32_t payload_end_offset : 14, //[13:0] + reserved_5a : 2, //[15:14] + wds : 1, //[16] + reserved_5b : 15; //[31:17] + uint32_t buf0_ptr_31_0 : 32; //[31:0] + uint32_t buf0_ptr_39_32 : 8, //[7:0] + reserved_7a : 8, //[15:8] + buf0_len : 16; //[31:16] + uint32_t buf1_ptr_31_0 : 32; //[31:0] + uint32_t buf1_ptr_39_32 : 8, //[7:0] + reserved_9a : 8, //[15:8] + buf1_len : 16; //[31:16] + uint32_t buf2_ptr_31_0 : 32; //[31:0] + uint32_t buf2_ptr_39_32 : 8, //[7:0] + reserved_11a : 8, //[15:8] + buf2_len : 16; //[31:16] + uint32_t buf3_ptr_31_0 : 32; //[31:0] + uint32_t buf3_ptr_39_32 : 8, //[7:0] + reserved_13a : 8, //[15:8] + buf3_len : 16; //[31:16] + uint32_t buf4_ptr_31_0 : 32; //[31:0] + uint32_t buf4_ptr_39_32 : 8, //[7:0] + reserved_15a : 8, //[15:8] + buf4_len : 16; //[31:16] + uint32_t buf5_ptr_31_0 : 32; //[31:0] + uint32_t buf5_ptr_39_32 : 8, //[7:0] + reserved_17a : 8, //[15:8] + buf5_len : 16; //[31:16] +}; + +/* + +tso_enable + + Enable transmit segmentation offload + +ipv4_checksum_en + + Enable IPv4 checksum replacement + +udp_over_ipv4_checksum_en + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. + +udp_over_ipv6_checksum_en + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. + +tcp_over_ipv4_checksum_en + + Enable TCP checksum over IPv4 replacement + +tcp_over_ipv6_checksum_en + + Enable TCP checksum over IPv6 eplacement + +reserved_0a + + FW will set to 0, MAC will ignore.  + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} + +tcp_flag_mask + + TCP flag mask. Tcp_flag is inserted into the header + based on the mask, if tso is enabled + +reserved_0b + + FW will set to 0, MAC will ignore.  + +l2_length + + L2 length for the msdu, if tso is enabled + +ip_length + + Ip length for the msdu, if tso is enabled + +tcp_seq_number + + Tcp_seq_number for the msdu, if tso is enabled + +ip_identification + + Ip_identification for the msdu, if tso is enabled + +udp_length + + TXDMA is copies this field into MSDU START TLV + +checksum_offset + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field + +partial_checksum_en + + Partial Checksum Enable Bit. + + + +reserved_4a + + + +payload_start_offset + + L4 checksum calculations will start fromt this offset + + + +reserved_4b + + + +payload_end_offset + + L4 checksum calculations will end at this offset. + + + +reserved_5a + + + +wds + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by the + OLE during encapsulation. + + Note: there is also global wds tx control in the + TX_PEER_ENTRY + + + +reserved_5b + + + +buf0_ptr_31_0 + + Lower 32 bits of the first buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf0_ptr_39_32 + + Upper 8 bits of the first buffer pointer + +reserved_7a + + + +buf0_len + + Length of the first buffer + +buf1_ptr_31_0 + + Lower 32 bits of the second buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf1_ptr_39_32 + + Upper 8 bits of the second buffer pointer + +reserved_9a + + + +buf1_len + + Length of the second buffer + +buf2_ptr_31_0 + + Lower 32 bits of the third buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf2_ptr_39_32 + + Upper 8 bits of the third buffer pointer + +reserved_11a + + + +buf2_len + + Length of the third buffer + +buf3_ptr_31_0 + + Lower 32 bits of the fourth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf3_ptr_39_32 + + Upper 8 bits of the fourth buffer pointer + +reserved_13a + + + +buf3_len + + Length of the fourth buffer + +buf4_ptr_31_0 + + Lower 32 bits of the fifth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf4_ptr_39_32 + + Upper 8 bits of the fifth buffer pointer + +reserved_15a + + + +buf4_len + + Length of the fifth buffer + +buf5_ptr_31_0 + + Lower 32 bits of the sixth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf5_ptr_39_32 + + Upper 8 bits of the sixth buffer pointer + +reserved_17a + + + +buf5_len + + Length of the sixth buffer +*/ + + +/* Description TX_MSDU_EXTENSION_0_TSO_ENABLE + + Enable transmit segmentation offload +*/ +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 + +/* Description TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN + + Enable IPv4 checksum replacement +*/ +#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_LSB 1 +#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_MASK 0x00000002 + +/* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_LSB 2 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000004 + +/* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_LSB 3 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000008 + +/* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN + + Enable TCP checksum over IPv4 replacement +*/ +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_LSB 4 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000010 + +/* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN + + Enable TCP checksum over IPv6 eplacement +*/ +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_LSB 5 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000020 + +/* Description TX_MSDU_EXTENSION_0_RESERVED_0A + + FW will set to 0, MAC will ignore.  +*/ +#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 6 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x00000040 + +/* Description TX_MSDU_EXTENSION_0_TCP_FLAG + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ +#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 + +/* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header + based on the mask, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 + +/* Description TX_MSDU_EXTENSION_0_RESERVED_0B + + FW will set to 0, MAC will ignore.  +*/ +#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 + +/* Description TX_MSDU_EXTENSION_1_L2_LENGTH + + L2 length for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff + +/* Description TX_MSDU_EXTENSION_1_IP_LENGTH + + Ip length for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION + + Ip_identification for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff + +/* Description TX_MSDU_EXTENSION_3_UDP_LENGTH + + TXDMA is copies this field into MSDU START TLV +*/ +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff + +/* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN + + Partial Checksum Enable Bit. + + +*/ +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +/* Description TX_MSDU_EXTENSION_4_RESERVED_4A + + +*/ +#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 + +/* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + + +*/ +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +/* Description TX_MSDU_EXTENSION_4_RESERVED_4B + + +*/ +#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 + +/* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + + +*/ +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff + +/* Description TX_MSDU_EXTENSION_5_RESERVED_5A + + +*/ +#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 + +/* Description TX_MSDU_EXTENSION_5_WDS + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by the + OLE during encapsulation. + + Note: there is also global wds tx control in the + TX_PEER_ENTRY + + +*/ +#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_WDS_LSB 16 +#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 + +/* Description TX_MSDU_EXTENSION_5_RESERVED_5B + + +*/ +#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 + +/* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0 + + Lower 32 bits of the first buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32 + + Upper 8 bits of the first buffer pointer +*/ +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_7_RESERVED_7A + + +*/ +#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 +#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_7_BUF0_LEN + + Length of the first buffer +*/ +#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0 + + Lower 32 bits of the second buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32 + + Upper 8 bits of the second buffer pointer +*/ +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_9_RESERVED_9A + + +*/ +#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_9_BUF1_LEN + + Length of the second buffer +*/ +#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0 + + Lower 32 bits of the third buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32 + + Upper 8 bits of the third buffer pointer +*/ +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_11_RESERVED_11A + + +*/ +#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 +#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_11_BUF2_LEN + + Length of the third buffer +*/ +#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0 + + Lower 32 bits of the fourth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32 + + Upper 8 bits of the fourth buffer pointer +*/ +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_13_RESERVED_13A + + +*/ +#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_13_BUF3_LEN + + Length of the fourth buffer +*/ +#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0 + + Lower 32 bits of the fifth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32 + + Upper 8 bits of the fifth buffer pointer +*/ +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_15_RESERVED_15A + + +*/ +#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_15_BUF4_LEN + + Length of the fifth buffer +*/ +#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0 + + Lower 32 bits of the sixth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32 + + Upper 8 bits of the sixth buffer pointer +*/ +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_17_RESERVED_17A + + +*/ +#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_17_BUF5_LEN + + Length of the sixth buffer +*/ +#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 + + +#endif // _TX_MSDU_EXTENSION_H_ diff --git a/hw/qca6290/v1/tx_rate_stats_info.h b/hw/qca6290/v1/tx_rate_stats_info.h new file mode 100644 index 000000000000..d0955884981c --- /dev/null +++ b/hw/qca6290/v1/tx_rate_stats_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28] +// 1 tsf_directly_after_ppdu_transmission[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { + uint32_t tx_rate_stats_info_valid : 1, //[0] + transmit_bw : 2, //[2:1] + transmit_pkt_type : 4, //[6:3] + transmit_stbc : 1, //[7] + transmit_ldpc : 1, //[8] + transmit_sgi : 2, //[10:9] + transmit_mcs : 4, //[14:11] + ofdma_transmission : 1, //[15] + tones_in_ru : 12, //[27:16] + reserved_0a : 4; //[31:28] + uint32_t tsf_directly_after_ppdu_transmission: 32; //[31:0] +}; + +/* + +tx_rate_stats_info_valid + + When set all other fields in this STRUCT contain valid + info. + + + + + + +transmit_bw + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + + +transmit_pkt_type + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + +transmit_stbc + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. + +transmit_ldpc + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates + +transmit_sgi + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + + +transmit_mcs + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + + +ofdma_transmission + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + + +tones_in_ru + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + + + TODO: not clear yet what the number of tones is for RUs + of 160 or 80 + 80 ??? + + For now assumption is that this value for this scenario + will indicate: 0x7FF + + + +reserved_0a + + + +tsf_directly_after_ppdu_transmission + + Field only valid when Tx_rate_stats_info_valid is set + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + +*/ + + +/* Description TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid + info. + + + + + +*/ +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800 + +/* Description TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + +*/ +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000 + +/* Description TX_RATE_STATS_INFO_0_TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + + + TODO: not clear yet what the number of tones is for RUs + of 160 or 80 + 80 ??? + + For now assumption is that this value for this scenario + will indicate: 0x7FF + + +*/ +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000 + +/* Description TX_RATE_STATS_INFO_0_RESERVED_0A + + +*/ +#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000 + +/* Description TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + +*/ +#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_LSB 0 +#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_MASK 0xffffffff + + +#endif // _TX_RATE_STATS_INFO_H_ diff --git a/hw/qca6290/v1/uniform_descriptor_header.h b/hw/qca6290/v1/uniform_descriptor_header.h new file mode 100644 index 000000000000..bb0214f6487e --- /dev/null +++ b/hw/qca6290/v1/uniform_descriptor_header.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { + uint32_t owner : 4, //[3:0] + buffer_type : 4, //[7:4] + reserved_0a : 24; //[31:8] +}; + +/* + +owner + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + + +buffer_type + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +reserved_0a + + +*/ + + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 + + +#endif // _UNIFORM_DESCRIPTOR_HEADER_H_ diff --git a/hw/qca6290/v1/uniform_reo_cmd_header.h b/hw/qca6290/v1/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..843fc4735fc1 --- /dev/null +++ b/hw/qca6290/v1/uniform_reo_cmd_header.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { + uint32_t reo_cmd_number : 16, //[15:0] + reo_status_required : 1, //[16] + reserved_0a : 15; //[31:17] +}; + +/* + +reo_cmd_number + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + + +reo_status_required + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + + +reserved_0a + + +*/ + + +/* Description UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description UNIFORM_REO_CMD_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000 + + +#endif // _UNIFORM_REO_CMD_HEADER_H_ diff --git a/hw/qca6290/v1/uniform_reo_status_header.h b/hw/qca6290/v1/uniform_reo_status_header.h new file mode 100644 index 000000000000..6f7fd94b8634 --- /dev/null +++ b/hw/qca6290/v1/uniform_reo_status_header.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28] +// 1 timestamp[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { + uint32_t reo_status_number : 16, //[15:0] + cmd_execution_time : 10, //[25:16] + reo_cmd_execution_status : 2, //[27:26] + reserved_0a : 4; //[31:28] + uint32_t timestamp : 32; //[31:0] +}; + +/* + +reo_status_number + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + + +cmd_execution_time + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + + +reo_cmd_execution_status + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + + +reserved_0a + + + +timestamp + + Timestamp at the moment that this status report is + written. + + + + +*/ + + +/* Description UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000 + +/* Description UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff + + +#endif // _UNIFORM_REO_STATUS_HEADER_H_ diff --git a/hw/qca6290/v1/wbm_buffer_ring.h b/hw/qca6290/v1/wbm_buffer_ring.h new file mode 100644 index 000000000000..eaffc26dca9d --- /dev/null +++ b/hw/qca6290/v1/wbm_buffer_ring.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { + struct buffer_addr_info buf_addr_info; +}; + +/* + +struct buffer_addr_info buf_addr_info + + Consumer: WBM + + Producer: WBM + + + + Details of the physical address of the buffer + source + buffer owner + some SW meta data. + + All modules getting this buffer address info, shall keep + all the 64 bits of info in this descriptor together and + eventually all 64 bits shall be given back to WMB when the + buffer is released. +*/ + +#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000000 +#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 0 +#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff +#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 0 +#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff + + +#endif // _WBM_BUFFER_RING_H_ diff --git a/hw/qca6290/v1/wbm_link_descriptor_ring.h b/hw/qca6290/v1/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..28448c5e24d4 --- /dev/null +++ b/hw/qca6290/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info desc_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { + struct buffer_addr_info desc_addr_info; +}; + +/* + +struct buffer_addr_info desc_addr_info + + Consumer: WBM + + Producer: WBM + + + + Details of the physical address of the buffer + source + buffer owner + some SW meta data + + All modules getting this link descriptor address info, + shall keep all the 64 bits in this descriptor together and + eventually all 64 bits shall be given back to WBM when the + link descriptor is released. +*/ + +#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff +#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff + + +#endif // _WBM_LINK_DESCRIPTOR_RING_H_ diff --git a/hw/qca6290/v1/wbm_reg_seq_hwiobase.h b/hw/qca6290/v1/wbm_reg_seq_hwiobase.h new file mode 100644 index 000000000000..f0d267b67a53 --- /dev/null +++ b/hw/qca6290/v1/wbm_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WBM_REG_SEQ_BASE_H__ +#define __WBM_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/hw/qca6290/v1/wbm_reg_seq_hwioreg.h b/hw/qca6290/v1/wbm_reg_seq_hwioreg.h new file mode 100644 index 000000000000..600376c48c60 --- /dev/null +++ b/hw/qca6290/v1/wbm_reg_seq_hwioreg.h @@ -0,0 +1,12394 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WBM_REG_SEQ_REG_H__ +#define __WBM_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "wbm_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WBM_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WBM_R0_GENERAL_ENABLE //// + +#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) +#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) +#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK 0x000000ff +#define HWIO_WBM_R0_GENERAL_ENABLE_SHFT 0 +#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), HWIO_WBM_R0_GENERAL_ENABLE_RMSK) +#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_GENERAL_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x00000080 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 0x7 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT 0x6 + +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT 0x5 + +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_ENABLE //// + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x) (x+0x00000004) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x) (x+0x00000004) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_SHFT 0x0 + +//// Register WBM_R0_MSDU_BUFFER_RING_ENABLE //// + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x) (x+0x00000008) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x) (x+0x00000008) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_BMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_SHFT 0x0 + +//// Register WBM_R0_LINK_DESC_RING_ENABLE //// + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x) (x+0x0000000c) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x) (x+0x0000000c) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_BMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_SHFT 0x0 + +//// Register WBM_R0_MISC_RING_ENABLE //// + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x) (x+0x00000010) +#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x) (x+0x00000010) +#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK 0x0000001f +#define HWIO_WBM_R0_MISC_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MISC_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_BMSK 0x00000010 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_SHFT 0x4 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW2_BUFFER_RING_BMSK 0x00000008 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW2_BUFFER_RING_SHFT 0x3 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW1_BUFFER_RING_BMSK 0x00000004 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW1_BUFFER_RING_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW0_BUFFER_RING_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW0_BUFFER_RING_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_FW_BUFFER_RING_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_FW_BUFFER_RING_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000014) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000014) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_BMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_MSDU_BUFFER_RING_STATUS //// + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x) (x+0x00000018) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x) (x+0x00000018) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_BMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_LINK_DESC_RING_STATUS //// + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x) (x+0x0000001c) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x) (x+0x0000001c) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_BMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_MISC_RING_STATUS //// + +#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x) (x+0x00000020) +#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x) (x+0x00000020) +#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK 0x000001ff +#define HWIO_WBM_R0_MISC_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), HWIO_WBM_R0_MISC_RING_STATUS_RMSK) +#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MISC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x00000100 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 0x8 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_FLUSH //// + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x) (x+0x00000024) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x) (x+0x00000024) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK 0x00013fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x00010000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 0x10 + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x00002000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 0xd + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x00001000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 0xc + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0x00000fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0x0 + +//// Register WBM_R0_IDLE_STATUS //// + +#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x) (x+0x00000028) +#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x) (x+0x00000028) +#define HWIO_WBM_R0_IDLE_STATUS_RMSK 0x00007fff +#define HWIO_WBM_R0_IDLE_STATUS_SHFT 0 +#define HWIO_WBM_R0_IDLE_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), HWIO_WBM_R0_IDLE_STATUS_RMSK) +#define HWIO_WBM_R0_IDLE_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x00004000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 0xe + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK 0x00002000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT 0xd + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK 0x00001000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT 0xc + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK 0x00000800 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT 0xb + +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000400 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0xa + +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000200 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x9 + +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000100 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x8 + +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT 0x0 + +//// Register WBM_R0_IDLE_SEQUENCE //// + +#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x) (x+0x0000002c) +#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x) (x+0x0000002c) +#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK 0x0000003f +#define HWIO_WBM_R0_IDLE_SEQUENCE_SHFT 0 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), HWIO_WBM_R0_IDLE_SEQUENCE_RMSK) +#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x00000020 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 0x5 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK 0x0000000f +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT 0x0 + +//// Register WBM_R0_MSDU_PARSER_CONTROL //// + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x) (x+0x00000030) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x) (x+0x00000030) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK 0x00000007 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_SHFT 0 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x00000004 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 0x2 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x00000002 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 0x1 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x00000001 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0x0 + +//// Register WBM_R0_MSDU_PARSER_STATUS //// + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) (x+0x00000034) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) (x+0x00000034) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x0007ffff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT 0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x00078000 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 0xf + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x00004000 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 0xe + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_MAIN_STATE_BMSK 0x00003c00 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_MAIN_STATE_SHFT 0xa + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_BMSK 0x000003e0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_SHFT 0x5 + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x0000001f +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0x0 + +//// Register WBM_R0_MISC_CONTROL //// + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) (x+0x00000038) +#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x) (x+0x00000038) +#define HWIO_WBM_R0_MISC_CONTROL_RMSK 0x0000ffff +#define HWIO_WBM_R0_MISC_CONTROL_SHFT 0 +#define HWIO_WBM_R0_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_MISC_CONTROL_RMSK) +#define HWIO_WBM_R0_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0x0000fffc +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT 0x0 + +//// Register WBM_R0_WATCHDOG_TIMEOUT //// + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000003c) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000003c) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_SHFT 0 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), val) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0x00000fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0x0 + +//// Register WBM_R0_INTERRUPT_DATA_CAPTURE //// + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x) (x+0x00000040) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x) (x+0x00000040) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK 0x000001ff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SHFT 0 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), val) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask, val, HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_BMSK 0x000001ff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_SHFT 0x0 + +//// Register WBM_R0_INVALID_APB_ACC_ADDR //// + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x00000044) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x00000044) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK 0x0001ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_SHFT 0 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ + out_dword( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x0001ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0x0 + +//// Register WBM_R0_IDLE_LIST_CONTROL //// + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) (x+0x00000048) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) (x+0x00000048) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x000007ff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SHFT 0 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x000007fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 0x2 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x00000002 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 0x1 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x00000001 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0x0 + +//// Register WBM_R0_IDLE_LIST_SIZE //// + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) (x+0x0000004c) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) (x+0x0000004c) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SHFT 0 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 0x10 + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0x0000ffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_LSB //// + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x) (x+0x00000050) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_PHYS(x) (x+0x00000050) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_MSB //// + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x) (x+0x00000054) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_PHYS(x) (x+0x00000054) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) (x+0x00000058) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) (x+0x00000058) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) (x+0x0000005c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) (x+0x0000005c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000060) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000060) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x00000064) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x00000064) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000068) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000068) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x0000006c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x0000006c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000070) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000070) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x00000074) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x00000074) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000078) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000078) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x0000007c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x0000007c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HP //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x) (x+0x00000080) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_PHYS(x) (x+0x00000080) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HP //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) (x+0x00000084) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) (x+0x00000084) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TP //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x) (x+0x00000088) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_PHYS(x) (x+0x00000088) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TP //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) (x+0x0000008c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) (x+0x0000008c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_CLK_GATE_CTRL //// + +#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000090) +#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000090) +#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK 0x0003ffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_SHFT 0 +#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), HWIO_WBM_R0_CLK_GATE_CTRL_RMSK) +#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), val) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x00020000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 0x11 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x00010000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 0x10 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK 0x0000ffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000094) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000094) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000098) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000098) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000009c) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000009c) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register WBM_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000000a0) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000000a0) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WBM_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000000a4) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000000a4) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000000a8) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000000a8) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000000ac) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000000ac) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000000b0) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000000b0) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000000b4) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000000b4) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000000b8) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000000b8) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000000bc) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000000bc) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000000c0) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000000c0) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000000c4) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000000c4) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000000c8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000000c8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000000cc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000000cc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) (x+0x000000d0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) (x+0x000000d0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x) (x+0x000000d4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_PHYS(x) (x+0x000000d4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x) (x+0x000000d8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_PHYS(x) (x+0x000000d8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000e4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000e4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000e8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000e8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000f8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000f8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000fc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000fc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000100) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000100) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000104) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000104) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000108) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000108) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000010c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000010c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000011c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000011c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000120) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000120) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000124) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000124) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) (x+0x00000128) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) (x+0x00000128) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) (x+0x0000012c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) (x+0x0000012c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x) (x+0x00000130) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x) (x+0x00000130) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000013c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000013c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000140) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000140) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000150) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000150) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000154) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000154) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000158) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000158) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000015c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000015c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000160) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000160) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000164) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000164) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000174) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000174) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000178) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000178) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x0000017c) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x0000017c) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x00000180) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x00000180) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x00000184) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x00000184) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x00000188) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x00000188) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000194) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000194) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000198) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000198) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001a8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001a8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001ac) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001ac) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001b0) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001b0) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001bc) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001bc) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001cc) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001cc) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000001d0) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000001d0) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000001d4) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000001d4) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) (x+0x000001d8) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) (x+0x000001d8) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) (x+0x000001dc) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) (x+0x000001dc) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) (x+0x000001e0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) (x+0x000001e0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000200) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000200) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000204) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000204) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000208) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000208) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000020c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000020c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000210) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000210) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000214) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000214) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000218) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000218) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000021c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000021c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000220) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000220) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000224) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000224) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000228) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000228) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x0000022c) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x0000022c) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) (x+0x00000230) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) (x+0x00000230) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x) (x+0x00000234) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x) (x+0x00000234) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x) (x+0x00000238) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x) (x+0x00000238) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000244) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000244) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000248) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000248) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000258) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000258) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000025c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000025c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000260) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000260) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000264) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000264) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000268) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000268) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000026c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000026c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000270) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000270) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000274) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000274) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000278) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000278) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000027c) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000027c) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000280) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000280) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000284) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000284) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) (x+0x00000288) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) (x+0x00000288) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x) (x+0x0000028c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x) (x+0x0000028c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x) (x+0x00000290) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x) (x+0x00000290) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000029c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000029c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000002a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000002a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000002b0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000002b0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000002b4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000002b4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000002b8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000002b8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002bc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002bc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000002c0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000002c0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000002c4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000002c4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000002d8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000002d8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000002dc) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000002dc) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x) (x+0x000002e0) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_PHYS(x) (x+0x000002e0) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x) (x+0x000002e4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_PHYS(x) (x+0x000002e4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x) (x+0x000002e8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_PHYS(x) (x+0x000002e8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000002f4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000002f4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000002f8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000002f8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000308) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000308) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000030c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000030c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000310) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000310) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000314) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000314) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000318) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000318) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000031c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000031c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000032c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000032c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000330) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000330) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000334) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000334) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x) (x+0x00000338) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_PHYS(x) (x+0x00000338) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x) (x+0x0000033c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_PHYS(x) (x+0x0000033c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x) (x+0x00000340) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_PHYS(x) (x+0x00000340) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000034c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000034c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000350) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000350) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000360) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000360) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000364) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000364) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000368) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000368) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000036c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000036c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000370) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000370) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000374) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000374) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000384) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000384) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000388) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000388) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x) (x+0x0000038c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_PHYS(x) (x+0x0000038c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x) (x+0x00000390) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_PHYS(x) (x+0x00000390) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x) (x+0x00000394) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_PHYS(x) (x+0x00000394) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x) (x+0x00000398) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_PHYS(x) (x+0x00000398) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000039c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000039c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003a0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003a0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003ac) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003ac) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003b0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003b0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003dc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003dc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x) (x+0x000003e0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_PHYS(x) (x+0x000003e0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x) (x+0x000003e4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_PHYS(x) (x+0x000003e4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x) (x+0x000003e8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_PHYS(x) (x+0x000003e8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x) (x+0x000003ec) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_PHYS(x) (x+0x000003ec) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x) (x+0x000003f0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_PHYS(x) (x+0x000003f0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003f4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003f4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003f8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003f8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000404) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000404) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000040c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000040c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000428) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000428) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000042c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000042c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x00000430) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x00000430) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000434) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000434) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000438) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000438) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x) (x+0x0000043c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_PHYS(x) (x+0x0000043c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x) (x+0x00000440) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_PHYS(x) (x+0x00000440) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x) (x+0x00000444) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_PHYS(x) (x+0x00000444) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x) (x+0x00000448) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_PHYS(x) (x+0x00000448) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000044c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000044c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000450) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000450) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000045c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000045c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000460) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000460) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000464) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000464) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000480) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000480) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000484) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000484) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x00000488) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x00000488) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000048c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000048c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000490) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000490) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000494) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000494) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x) (x+0x00000498) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_PHYS(x) (x+0x00000498) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x) (x+0x0000049c) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_PHYS(x) (x+0x0000049c) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x) (x+0x000004a0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_PHYS(x) (x+0x000004a0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004a4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004a4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004a8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004a8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004b4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004b4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004b8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004b8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004bc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004bc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004e4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004e4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x) (x+0x000004e8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_PHYS(x) (x+0x000004e8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x) (x+0x000004ec) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_PHYS(x) (x+0x000004ec) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x) (x+0x000004f0) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_PHYS(x) (x+0x000004f0) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x) (x+0x000004f4) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_PHYS(x) (x+0x000004f4) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x) (x+0x000004f8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_PHYS(x) (x+0x000004f8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004fc) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004fc) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000500) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000500) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000050c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000050c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000510) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000510) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000514) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000514) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000053c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000053c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000540) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000540) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000544) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000544) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x) (x+0x00000548) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_PHYS(x) (x+0x00000548) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x) (x+0x0000054c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_PHYS(x) (x+0x0000054c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x) (x+0x00000550) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_PHYS(x) (x+0x00000550) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000554) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000554) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000558) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000558) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000564) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000564) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000568) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000568) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000056c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000056c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000594) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000594) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000598) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000598) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) (x+0x0000059c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) (x+0x0000059c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) (x+0x000005a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) (x+0x000005a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) (x+0x000005a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) (x+0x000005a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) (x+0x000005a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) (x+0x000005a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000005ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000005ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000005b0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000005b0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000005bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000005bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000005c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000005c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000005c4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000005c4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x000005f0) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x000005f0) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x000005f4) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x000005f4) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x000005f8) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x000005f8) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x000005fc) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x000005fc) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x00000600) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x00000600) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000604) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000604) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000608) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000608) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000614) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000614) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000618) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000618) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000061c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000061c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000644) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000644) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000648) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000648) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) (x+0x0000064c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) (x+0x0000064c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) (x+0x00000650) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) (x+0x00000650) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) (x+0x00000654) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) (x+0x00000654) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) (x+0x00000658) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) (x+0x00000658) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000065c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000065c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000660) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000660) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000066c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000066c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000670) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000670) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000674) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000674) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000690) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000690) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000694) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000694) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x00000698) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x00000698) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000069c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000069c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x) (x+0x000006a0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x) (x+0x000006a0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x) (x+0x000006a4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x) (x+0x000006a4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x) (x+0x000006a8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x) (x+0x000006a8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x) (x+0x000006ac) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x) (x+0x000006ac) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x) (x+0x000006b0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x) (x+0x000006b0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006b4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006b4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006b8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006b8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006c4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006c4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006c8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006c8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006cc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006cc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006e8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006e8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006ec) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006ec) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000006f0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000006f0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006f4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006f4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x) (x+0x000006f8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x) (x+0x000006f8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x) (x+0x000006fc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x) (x+0x000006fc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x) (x+0x00000700) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x) (x+0x00000700) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x) (x+0x00000704) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x) (x+0x00000704) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x) (x+0x00000708) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x) (x+0x00000708) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000070c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000070c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000710) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000710) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000071c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000071c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000720) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000720) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000724) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000724) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000074c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000074c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000750) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000750) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000754) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000754) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x) (x+0x00000758) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_PHYS(x) (x+0x00000758) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x) (x+0x0000075c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_PHYS(x) (x+0x0000075c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x) (x+0x00000760) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_PHYS(x) (x+0x00000760) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000764) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000764) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000768) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000768) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000774) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000774) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000778) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000778) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000077c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000077c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007a4) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007a4) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x) (x+0x000007a8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_PHYS(x) (x+0x000007a8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x) (x+0x000007ac) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_PHYS(x) (x+0x000007ac) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x) (x+0x000007b0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_PHYS(x) (x+0x000007b0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x) (x+0x000007b4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_PHYS(x) (x+0x000007b4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x) (x+0x000007b8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_PHYS(x) (x+0x000007b8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000007bc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000007bc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000007c0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000007c0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000007cc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000007cc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007d0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007d0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007d4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007d4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007fc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007fc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000800) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000800) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000804) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000804) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x) (x+0x00000808) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_PHYS(x) (x+0x00000808) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x) (x+0x0000080c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_PHYS(x) (x+0x0000080c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x) (x+0x00000810) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_PHYS(x) (x+0x00000810) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000814) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000814) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000818) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000818) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000081c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000081c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000820) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000820) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000824) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000824) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000828) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000828) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000082c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000082c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000830) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000830) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000834) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000834) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000838) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000838) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000083c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000083c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000840) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000840) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000844) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000844) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000854) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000854) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000858) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000858) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) (x+0x0000085c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) (x+0x0000085c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) (x+0x00000860) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) (x+0x00000860) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) (x+0x00000864) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) (x+0x00000864) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) (x+0x00000868) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) (x+0x00000868) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000086c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000086c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000870) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000870) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000874) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000874) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000878) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000878) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000087c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000087c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000880) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000880) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000884) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000884) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000888) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000888) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000088c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000088c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000890) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000890) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000894) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000894) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000898) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000898) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000089c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000089c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008ac) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008ac) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000008b0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000008b0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000008b4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000008b4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x) (x+0x000008b8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x) (x+0x000008b8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x) (x+0x000008bc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x) (x+0x000008bc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x) (x+0x000008c0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x) (x+0x000008c0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008c4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008c4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008c8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008c8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008d4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008d4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008d8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008d8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008dc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008dc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008f8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008f8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008fc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008fc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000900) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000900) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000904) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000904) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000908) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000908) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x0000090c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x0000090c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) (x+0x00000910) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) (x+0x00000910) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000914) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000914) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) (x+0x00000918) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) (x+0x00000918) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000091c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000091c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000920) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000920) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000092c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000092c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000930) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000930) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000934) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000934) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000950) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000950) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000954) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000954) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000958) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000958) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000095c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000095c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000960) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000960) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000964) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000964) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) (x+0x00000968) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) (x+0x00000968) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) (x+0x0000096c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) (x+0x0000096c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) (x+0x00000970) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) (x+0x00000970) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000974) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000974) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000978) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000978) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000984) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000984) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000988) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000988) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000098c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000098c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000009a8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000009a8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009ac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009ac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000009b0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000009b0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009b4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009b4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000009b8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000009b8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000009bc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000009bc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) (x+0x000009c0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) (x+0x000009c0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) (x+0x000009c4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) (x+0x000009c4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) (x+0x000009c8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) (x+0x000009c8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000009cc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000009cc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000009d0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000009d0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000009dc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000009dc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009e0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009e0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009e4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009e4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000a10) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000a10) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000a14) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000a14) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) (x+0x00000a18) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) (x+0x00000a18) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) (x+0x00000a1c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) (x+0x00000a1c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) (x+0x00000a20) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) (x+0x00000a20) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000a24) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000a24) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000a28) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000a28) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000a34) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000a34) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000a38) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000a38) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a3c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a3c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a5c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a5c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a60) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a60) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R1_END_OF_TEST_CHECK //// + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_CTRL //// + +#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002004) +#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002004) +#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK 0x00001f3f +#define HWIO_WBM_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), HWIO_WBM_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_BMSK 0x00001f00 +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_SHFT 0x8 + +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK 0x0000003f +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_LOWER //// + +#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002008) +#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002008) +#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R1_TESTBUS_LOWER_RMSK) +#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_HIGHER //// + +#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x) (x+0x0000200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x) (x+0x0000200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK 0x000000ff +#define HWIO_WBM_R1_TESTBUS_HIGHER_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), HWIO_WBM_R1_TESTBUS_HIGHER_RMSK) +#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 + +//// Register WBM_R1_SM_STATES_IX_0 //// + +#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002010) +#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002010) +#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK 0x7fffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_0_RMSK) +#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WBM_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WBM_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 0x1d + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK 0x18000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT 0x1b + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK 0x06000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT 0x19 + +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK 0x01800000 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT 0x17 + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK 0x00600000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT 0x15 + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK 0x00180000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT 0x13 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK 0x00060000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT 0x11 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK 0x00018000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT 0xf + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK 0x00007000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT 0xc + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK 0x00000c00 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT 0xa + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x00000380 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT 0x7 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x00000060 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT 0x5 + +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK 0x0000001c +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT 0x2 + +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK 0x00000003 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT 0x0 + +//// Register WBM_R1_SM_STATES_IX_1 //// + +#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002014) +#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002014) +#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK 0x0000ffff +#define HWIO_WBM_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_1_RMSK) +#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_WBM_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_WBM_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0x0000e000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 0xd + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK 0x00001c00 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT 0xa + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK 0x00000380 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT 0x7 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK 0x00000070 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT 0x4 + +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK 0x0000000c +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT 0x2 + +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK 0x00000003 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_0 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00002018) +#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00002018) +#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_1 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000201c) +#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000201c) +#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_2 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00002020) +#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00002020) +#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_3 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00002024) +#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00002024) +#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_3_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0x0 + +//// Register WBM_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00002028) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00002028) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register WBM_R2_PPE_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x) (x+0x00003000) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_PHYS(x) (x+0x00003000) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_PPE_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x) (x+0x00003004) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_PHYS(x) (x+0x00003004) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_TQM_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x) (x+0x00003008) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x) (x+0x00003008) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_TQM_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x) (x+0x0000300c) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x) (x+0x0000300c) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_REO_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003010) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003010) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_REO_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003014) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003014) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_SW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) (x+0x00003018) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) (x+0x00003018) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_SW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) (x+0x0000301c) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) (x+0x0000301c) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_FW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x) (x+0x00003020) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x) (x+0x00003020) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_FW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x) (x+0x00003024) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x) (x+0x00003024) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA0_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x) (x+0x00003028) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x) (x+0x00003028) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA0_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x) (x+0x0000302c) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x) (x+0x0000302c) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA1_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x) (x+0x00003030) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_PHYS(x) (x+0x00003030) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA1_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x) (x+0x00003034) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_PHYS(x) (x+0x00003034) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA2_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x) (x+0x00003038) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_PHYS(x) (x+0x00003038) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA2_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x) (x+0x0000303c) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_PHYS(x) (x+0x0000303c) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2PPE_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x) (x+0x00003040) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_PHYS(x) (x+0x00003040) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2PPE_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x) (x+0x00003044) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_PHYS(x) (x+0x00003044) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x) (x+0x00003048) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_PHYS(x) (x+0x00003048) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x) (x+0x0000304c) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_PHYS(x) (x+0x0000304c) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x) (x+0x00003050) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_PHYS(x) (x+0x00003050) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x) (x+0x00003054) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_PHYS(x) (x+0x00003054) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x) (x+0x00003058) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_PHYS(x) (x+0x00003058) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x) (x+0x0000305c) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_PHYS(x) (x+0x0000305c) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x) (x+0x00003060) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_PHYS(x) (x+0x00003060) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x) (x+0x00003064) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_PHYS(x) (x+0x00003064) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x) (x+0x00003068) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_PHYS(x) (x+0x00003068) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x) (x+0x0000306c) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_PHYS(x) (x+0x0000306c) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2TQM_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) (x+0x00003070) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) (x+0x00003070) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2TQM_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) (x+0x00003074) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) (x+0x00003074) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2REO_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003078) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003078) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2REO_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000307c) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000307c) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x) (x+0x00003080) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x) (x+0x00003080) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x) (x+0x00003084) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x) (x+0x00003084) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x) (x+0x00003088) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x) (x+0x00003088) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x) (x+0x0000308c) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x) (x+0x0000308c) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x) (x+0x00003090) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x) (x+0x00003090) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x) (x+0x00003094) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x) (x+0x00003094) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x) (x+0x00003098) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_PHYS(x) (x+0x00003098) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x) (x+0x0000309c) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_PHYS(x) (x+0x0000309c) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x) (x+0x000030a0) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_PHYS(x) (x+0x000030a0) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x) (x+0x000030a4) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_PHYS(x) (x+0x000030a4) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x) (x+0x000030a8) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_PHYS(x) (x+0x000030a8) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x) (x+0x000030ac) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_PHYS(x) (x+0x000030ac) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) (x+0x000030b0) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) (x+0x000030b0) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) (x+0x000030b4) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) (x+0x000030b4) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x) (x+0x000030b8) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x) (x+0x000030b8) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x) (x+0x000030bc) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x) (x+0x000030bc) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW0_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) (x+0x000030c0) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) (x+0x000030c0) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW0_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) (x+0x000030c4) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) (x+0x000030c4) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW1_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) (x+0x000030c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) (x+0x000030c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW1_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) (x+0x000030cc) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) (x+0x000030cc) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW2_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) (x+0x000030d0) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) (x+0x000030d0) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW2_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) (x+0x000030d4) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) (x+0x000030d4) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW3_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) (x+0x000030d8) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) (x+0x000030d8) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW3_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) (x+0x000030dc) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) (x+0x000030dc) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/hw/qca6290/v1/wbm_release_ring.h b/hw/qca6290/v1/wbm_release_ring.h new file mode 100644 index 000000000000..fb25038ad76f --- /dev/null +++ b/hw/qca6290/v1/wbm_release_ring.h @@ -0,0 +1,1418 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "tx_rate_stats_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info released_buff_or_desc_addr_info; +// 2 release_source_module[2:0], bm_action[5:3], buffer_or_desc_type[8:6], first_msdu_index[12:9], tqm_release_reason[15:13], rxdma_push_reason[17:16], rxdma_error_code[22:18], reo_push_reason[24:23], reo_error_code[29:25], wbm_internal_error[30], reserved_2[31] +// 3 tqm_status_number[23:0], transmit_count[30:24], reserved_3a[31] +// 4 ack_frame_rssi[7:0], sw_release_details_valid[8], first_msdu[9], last_msdu[10], msdu_part_of_amsdu[11], fw_tx_notify_frame[12], buffer_timestamp[31:13] +// 5-6 struct tx_rate_stats_info tx_rate_stats; +// 7 sw_peer_id[15:0], tid[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, //[2:0] + bm_action : 3, //[5:3] + buffer_or_desc_type : 3, //[8:6] + first_msdu_index : 4, //[12:9] + tqm_release_reason : 3, //[15:13] + rxdma_push_reason : 2, //[17:16] + rxdma_error_code : 5, //[22:18] + reo_push_reason : 2, //[24:23] + reo_error_code : 5, //[29:25] + wbm_internal_error : 1, //[30] + reserved_2 : 1; //[31] + uint32_t tqm_status_number : 24, //[23:0] + transmit_count : 7, //[30:24] + reserved_3a : 1; //[31] + uint32_t ack_frame_rssi : 8, //[7:0] + sw_release_details_valid : 1, //[8] + first_msdu : 1, //[9] + last_msdu : 1, //[10] + msdu_part_of_amsdu : 1, //[11] + fw_tx_notify_frame : 1, //[12] + buffer_timestamp : 19; //[31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, //[15:0] + tid : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info released_buff_or_desc_addr_info + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Details of the physical address of the buffer or link + descriptor that is being released. Note that within this + descriptor, WBM will look at the 'owner' of the released + buffer/descriptor and forward it to SW/FW is WBM is not the + owner. + +release_source_module + + Indicates which module initiated the release of this + buffer or descriptor + + + + TQM released this buffer or + descriptor + + RXDMA released this buffer + or descriptor + + REO released this buffer or + descriptor + + FW released this buffer or + descriptor + + SW released this buffer or + descriptor + + + +bm_action + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + + WBM_IDLE_BUF_LIST or + + WBM_IDLE_DESC_LIST + + + + An MSDU extension descriptor shall never be marked as + + + + Put the buffer or descriptor + back in the idle list. In case of MSDU or MDPU link + descriptor, BM does not need to check to release any + individual MSDU buffers + + + + This BM action can only be + used in combination with buffer_or_desc_type being + msdu_link_descriptor. Field first_msdu_index points out + which MSDU pointer in the MSDU link descriptor is the first + of an MPDU that is released. + + BM shall release all the MSDU buffers linked to this + first MSDU buffer pointer. All related MSDU buffer pointer + entries shall be set to value 0, which represents the 'NULL + pointer. When all MSDU buffer pointers in the MSDU link + descriptor are 'NULL', the MSDU link descriptor itself shall + also be released. + + + + CURRENTLY NOT + IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + + + +buffer_or_desc_type + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when WBM is marked as the + return_buffer_manager in the Released_Buffer_address_info + + + + Indicates that type of buffer or descriptor is being + released + + + + The address points to an MSDU + buffer + + The address points to an + TX MSDU link descriptor + + The address points to an + MPDU link descriptor + + The address points to an + MSDU extension descriptor. + + In case BM finds this one in a release ring, it passes + it on to FW... + + The address points to an + TQM queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + + + + +first_msdu_index + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid for the bm_action release_msdu_list. + + + + The index of the first MSDU in an MSDU link descriptor + all belonging to the same MPDU. + + + + + +tqm_release_reason + + Consumer: WBM/SW/FW + + Producer: TQM + + + + Field only valid when Release_source_module is set to + release_source_TQM + + + + (rr = Release Reason) + + frame is removed because an + ACK of BA for it was received + + frame is removed because a + remove command of type Remove_mpdus initiated by SW + + frame is removed because a + remove command of type Remove_transmitted_mpdus initiated by + SW + + frame is removed because a + remove command of type Remove_untransmitted_mpdus initiated + by SW + + frame is removed because a + remove command of type Remove_aged_mpdus or + Remove_aged_msdus initiated by SW + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + + + + +rxdma_push_reason + + Field only valid when Release_source_module is set to + release_source_RXDMA + + + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + + +rxdma_error_code + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + +reo_push_reason + + Field only valid when Release_source_module is set to + release_source_REO + + + + Indicates why REO pushed the frame to this release ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + +reo_error_code + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + + +wbm_internal_error + + Can only be set by WBM. + + + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link + related activity + + OR + + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + + + + +reserved_2 + + + +tqm_status_number + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The value in this field is equal to value of the + 'TQM_CMD_Number' field the TQM command or the + 'TQM_add_cmd_Number' field from the TQM entrance ring + descriptor + + + + This field helps to correlate the statuses with the TQM + commands. + + + + NOTE that SW could program this number to be equal to + the PPDU_ID number in case direct correlation with the PPDU + ID is desired + + + + + +transmit_count + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The number of times this frame has been transmitted + +reserved_3a + + + +ack_frame_rssi + + This field is only valid when the source is TQM. + + + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the + received ACK or BA frame. + + + + When the frame is removed as result of a direct remove + command from the SW, this field is set to 0x0 (which is + never a valid value when real RSSI is available) + + + + + +sw_release_details_valid + + Consumer: SW + + Producer: WBM + + + + When set, some WBM specific release info for SW is + valid. + + This is set when WMB got a 'release_msdu_list' command + from TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + + + + +first_msdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the first MSDU pointed to in the + 'release_msdu_list' command. + + + + + +last_msdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the last MSDU pointed to in the + 'release_msdu_list' command. + + + + + +msdu_part_of_amsdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU was part of an A-MSDU in MPDU + + + +fw_tx_notify_frame + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the FW_tx_notify_frame field from the + + + +buffer_timestamp + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the Buffer_timestamp field from the + + + +struct tx_rate_stats_info tx_rate_stats + + Consumer: TQM + + Producer: SW/SCH(from TXPCU, PDG) + + + + Details for command execution tracking purposes. + +sw_peer_id + + Field only valid when Release_source_module is set to + release_source_TQM + + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or + TX_MPDU_QUEUE descriptor + + + +tid + + Field only valid when Release_source_module is set to + release_source_TQM + + + + TID of the flow or MPDU queue + + + +ring_id + + Consumer: TQM/REO/RXDMA/SW + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + A count value that indicates the number of times the + producer of entries into the Buffer Manager Ring has looped + around the ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_OFFSET 0x00000000 +#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_LSB 28 +#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_MASK 0xffffffff +#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_LSB 28 +#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_MASK 0xffffffff + +/* Description WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this + buffer or descriptor + + + + TQM released this buffer or + descriptor + + RXDMA released this buffer + or descriptor + + REO released this buffer or + descriptor + + FW released this buffer or + descriptor + + SW released this buffer or + descriptor + + +*/ +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +/* Description WBM_RELEASE_RING_2_BM_ACTION + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + + WBM_IDLE_BUF_LIST or + + WBM_IDLE_DESC_LIST + + + + An MSDU extension descriptor shall never be marked as + + + + Put the buffer or descriptor + back in the idle list. In case of MSDU or MDPU link + descriptor, BM does not need to check to release any + individual MSDU buffers + + + + This BM action can only be + used in combination with buffer_or_desc_type being + msdu_link_descriptor. Field first_msdu_index points out + which MSDU pointer in the MSDU link descriptor is the first + of an MPDU that is released. + + BM shall release all the MSDU buffers linked to this + first MSDU buffer pointer. All related MSDU buffer pointer + entries shall be set to value 0, which represents the 'NULL + pointer. When all MSDU buffer pointers in the MSDU link + descriptor are 'NULL', the MSDU link descriptor itself shall + also be released. + + + + CURRENTLY NOT + IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + + +*/ +#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 + +/* Description WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when WBM is marked as the + return_buffer_manager in the Released_Buffer_address_info + + + + Indicates that type of buffer or descriptor is being + released + + + + The address points to an MSDU + buffer + + The address points to an + TX MSDU link descriptor + + The address points to an + MPDU link descriptor + + The address points to an + MSDU extension descriptor. + + In case BM finds this one in a release ring, it passes + it on to FW... + + The address points to an + TQM queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + + + +*/ +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +/* Description WBM_RELEASE_RING_2_FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid for the bm_action release_msdu_list. + + + + The index of the first MSDU in an MSDU link descriptor + all belonging to the same MPDU. + + + + +*/ +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 + +/* Description WBM_RELEASE_RING_2_TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + + Producer: TQM + + + + Field only valid when Release_source_module is set to + release_source_TQM + + + + (rr = Release Reason) + + frame is removed because an + ACK of BA for it was received + + frame is removed because a + remove command of type Remove_mpdus initiated by SW + + frame is removed because a + remove command of type Remove_transmitted_mpdus initiated by + SW + + frame is removed because a + remove command of type Remove_untransmitted_mpdus initiated + by SW + + frame is removed because a + remove command of type Remove_aged_mpdus or + Remove_aged_msdus initiated by SW + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + + + +*/ +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0000e000 + +/* Description WBM_RELEASE_RING_2_RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to + release_source_RXDMA + + + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + +*/ +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 16 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00030000 + +/* Description WBM_RELEASE_RING_2_RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request +*/ +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 18 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x007c0000 + +/* Description WBM_RELEASE_RING_2_REO_PUSH_REASON + + Field only valid when Release_source_module is set to + release_source_REO + + + + Indicates why REO pushed the frame to this release ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + +*/ +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 23 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x01800000 + +/* Description WBM_RELEASE_RING_2_REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + +*/ +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 25 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x3e000000 + +/* Description WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR + + Can only be set by WBM. + + + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link + related activity + + OR + + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + + + +*/ +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 30 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x40000000 + +/* Description WBM_RELEASE_RING_2_RESERVED_2 + + +*/ +#define WBM_RELEASE_RING_2_RESERVED_2_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RESERVED_2_LSB 31 +#define WBM_RELEASE_RING_2_RESERVED_2_MASK 0x80000000 + +/* Description WBM_RELEASE_RING_3_TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The value in this field is equal to value of the + 'TQM_CMD_Number' field the TQM command or the + 'TQM_add_cmd_Number' field from the TQM entrance ring + descriptor + + + + This field helps to correlate the statuses with the TQM + commands. + + + + NOTE that SW could program this number to be equal to + the PPDU_ID number in case direct correlation with the PPDU + ID is desired + + + + +*/ +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff + +/* Description WBM_RELEASE_RING_3_TRANSMIT_COUNT + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The number of times this frame has been transmitted +*/ +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 + +/* Description WBM_RELEASE_RING_3_RESERVED_3A + + +*/ +#define WBM_RELEASE_RING_3_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_RESERVED_3A_LSB 31 +#define WBM_RELEASE_RING_3_RESERVED_3A_MASK 0x80000000 + +/* Description WBM_RELEASE_RING_4_ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the + received ACK or BA frame. + + + + When the frame is removed as result of a direct remove + command from the SW, this field is set to 0x0 (which is + never a valid value when real RSSI is available) + + + + +*/ +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff + +/* Description WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID + + Consumer: SW + + Producer: WBM + + + + When set, some WBM specific release info for SW is + valid. + + This is set when WMB got a 'release_msdu_list' command + from TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + + + +*/ +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 + +/* Description WBM_RELEASE_RING_4_FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the first MSDU pointed to in the + 'release_msdu_list' command. + + + + +*/ +#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 +#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 + +/* Description WBM_RELEASE_RING_4_LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the last MSDU pointed to in the + 'release_msdu_list' command. + + + + +*/ +#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 +#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 + +/* Description WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU was part of an A-MSDU in MPDU + + +*/ +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 + +/* Description WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the FW_tx_notify_frame field from the + + +*/ +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 + +/* Description WBM_RELEASE_RING_4_BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the Buffer_timestamp field from the + + +*/ +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 13 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 0xffffffff +#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 0x00000018 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 13 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 0xffffffff + +/* Description WBM_RELEASE_RING_7_SW_PEER_ID + + Field only valid when Release_source_module is set to + release_source_TQM + + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or + TX_MPDU_QUEUE descriptor + + +*/ +#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff + +/* Description WBM_RELEASE_RING_7_TID + + Field only valid when Release_source_module is set to + release_source_TQM + + + + TID of the flow or MPDU queue + + +*/ +#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_TID_LSB 16 +#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 + +/* Description WBM_RELEASE_RING_7_RING_ID + + Consumer: TQM/REO/RXDMA/SW + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_RING_ID_LSB 20 +#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description WBM_RELEASE_RING_7_LOOPING_COUNT + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + A count value that indicates the number of times the + producer of entries into the Buffer Manager Ring has looped + around the ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _WBM_RELEASE_RING_H_ diff --git a/hw/qca6290/v1/wcss_seq_hwiobase.h b/hw/qca6290/v1/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..8efcab08ecce --- /dev/null +++ b/hw/qca6290/v1/wcss_seq_hwiobase.h @@ -0,0 +1,731 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WCSS_SEQ_BASE_H__ +#define __WCSS_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wcss +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WCSS_ECAHB_OFFSET 0x00008000 +#define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 +#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 +#define SEQ_WCSS_MPSS_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00240000 +#define SEQ_WCSS_MPSS_PCSS_B_REG_MAP_OFFSET 0x00250000 +#define SEQ_WCSS_PHYA0_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 +#define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET 0x00484000 +#define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 +#define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 +#define SEQ_WCSS_PHYA0_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 +#define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 +#define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00530000 +#define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 +#define SEQ_WCSS_PHYA1_OFFSET 0x00600000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00600000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET 0x00680000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00680400 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00680800 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00680c00 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00681000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00681400 +#define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET 0x00684000 +#define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET 0x00688000 +#define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET 0x00700000 +#define SEQ_WCSS_PHYA1_WFAX_ROBE_REG_MAP_OFFSET 0x00720000 +#define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET 0x00728000 +#define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00730000 +#define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET 0x007a0000 +#define SEQ_WCSS_PHYB_OFFSET 0x00800000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 +#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 +#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 +#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00900000 +#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000 +#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 +#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 +#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 +#define SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 +#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 +#define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 +#define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 +#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 +#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 +#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 +#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 +#define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000 +#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 +#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 +#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 +#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 +#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 +#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 +#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 +#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 +#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 +#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 +#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 +#define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000 +#define SEQ_WCSS_WMAC1_OFFSET 0x00ac0000 +#define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00ac0000 +#define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00ac3000 +#define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00ac6000 +#define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00ac9000 +#define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00acc000 +#define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00acf000 +#define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00ad2000 +#define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00ad5000 +#define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00ad8000 +#define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00adb000 +#define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00ade000 +#define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00ae1000 +#define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00ae4000 +#define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00ae7000 +#define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00aea000 +#define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00af0000 +#define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00af3000 +#define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00af6000 +#define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00af9000 +#define SEQ_WCSS_WMAC2_OFFSET 0x00b00000 +#define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000 +#define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000 +#define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000 +#define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000 +#define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000 +#define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000 +#define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000 +#define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000 +#define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 +#define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000 +#define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000 +#define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 +#define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000 +#define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000 +#define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000 +#define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000 +#define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000 +#define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000 +#define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000 +#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 +#define SEQ_WCSS_WCMN_OFFSET 0x00b50000 +#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 +#define SEQ_WCSS_PMM_OFFSET 0x00b70000 +#define SEQ_WCSS_ZINC_RFA_CMN_OFFSET 0x00b80000 +#define SEQ_WCSS_ZINC_RFA_CMN_PLL_A_OFFSET 0x00b80000 +#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00b80100 +#define SEQ_WCSS_ZINC_RFA_CMN_PLL_B_OFFSET 0x00b82000 +#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00b82100 +#define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00b84000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00b88000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00b88100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x00b884c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00b88500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00b88600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00b88800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00b88900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88a00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00b88cc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00b88d00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00b88e00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00b89000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00b89100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x00b894c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00b89500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00b89600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00b89800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00b89900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89a00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00b89cc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00b89d00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00b89e00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x00b8a000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x00b8a100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x00b8a4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x00b8a500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x00b8a600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x00b8a800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x00b8a900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8aa00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x00b8acc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x00b8ad00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x00b8ae00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x00b8b000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x00b8b100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x00b8b4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x00b8b500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x00b8b600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x00b8b800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x00b8b900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8ba00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x00b8bcc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x00b8bd00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x00b8be00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x00b8c000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x00b8c100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x00b8c440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x00b8c4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x00b8c500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x00b8c600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x00b8c800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x00b8c900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8ca00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x00b8cc40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x00b8ccc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x00b8cd00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x00b8ce00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x00b8d000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x00b8d100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x00b8d440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x00b8d4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x00b8d500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x00b8d600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x00b8d800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x00b8d900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8da00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x00b8dc40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x00b8dcc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x00b8dd00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x00b8de00 +#define SEQ_WCSS_DBG_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 +#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 +#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 +#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 +#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 +#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 +#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 +#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 +#define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 +#define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 +#define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 +#define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000 +#define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 +#define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 +#define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 +#define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYA_CPU1_AHB_AP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 +#define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 +#define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 +#define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET 0x00bce000 +#define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET 0x00bf0000 +#define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 +#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 +#define SEQ_WCSS_CC_OFFSET 0x00c30000 +#define SEQ_WCSS_ACMT_OFFSET 0x00c40000 +#define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 +#define SEQ_WCSS_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00c60000 +#define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 +#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 +#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfax_top +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 +#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 +#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00130000 +#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfax_top_b +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 +#define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 +#define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 +#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 +#define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block umac_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 +#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 +#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 +#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 +#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 +#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 +#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 +#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 +#define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfss_ce_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 +#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block cxc_top_reg_14lpp +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_CXC_TOP_REG_14LPP_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_PMH_REG_OFFSET 0x0000a000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wmac_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 +#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_cmn +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_CMN_PLL_A_OFFSET 0x00000000 +#define SEQ_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100 +#define SEQ_RFA_CMN_PLL_B_OFFSET 0x00002000 +#define SEQ_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100 +#define SEQ_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008200 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008a00 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009200 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009a00 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a200 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000aa00 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b200 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000ba00 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c200 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000ca00 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d200 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000da00 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wcssdbg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 +#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 +#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 +#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 +#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 +#define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 +#define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 +#define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 +#define SEQ_WCSSDBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 +#define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 +#define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 +#define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 +#define SEQ_WCSSDBG_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYA_CPU1_AHB_AP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 +#define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 +#define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 +#define SEQ_WCSSDBG_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000 +#define SEQ_WCSSDBG_UMAC_CPU_AHB_AP_OFFSET 0x00060000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wrapper_acmt +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block qdsp6ss_public +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block qdsp6ss_private +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 +#define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 +#define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 +#define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 + + +#endif + diff --git a/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h b/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h new file mode 100644 index 000000000000..a27a10d8aad9 --- /dev/null +++ b/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WFSS_CE_REG_SEQ_BASE_H__ +#define __WFSS_CE_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfss_ce_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 +#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 + + +#endif + diff --git a/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h b/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h new file mode 100644 index 000000000000..b66ae4fffda2 --- /dev/null +++ b/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h @@ -0,0 +1,2361 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WFSS_CE_REG_SEQ_REG_H__ +#define __WFSS_CE_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "wfss_ce_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_CHANNEL_DST_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) (x+0x00000064) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) (x+0x00000064) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) (x+0x00000068) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) (x+0x00000068) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000006c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000006c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000070) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000070) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000000a8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000000a8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) (x+0x000000b0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) (x+0x000000b0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x0001ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) (x+0x000000b4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) (x+0x000000b4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) (x+0x000000b8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) (x+0x000000b8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0x0000000f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) (x+0x00000408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) (x+0x00000408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) (x+0x0000040c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) (x+0x0000040c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_CHANNEL_SRC_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x0000001f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x0000001f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_COMMON_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) (x+0x00000000) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) (x+0x00000000) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) (x+0x00000004) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) (x+0x00000004) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) (x+0x00000008) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) (x+0x00000008) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000000c) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000000c) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000010) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000010) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) (x+0x00000014) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) (x+0x00000014) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) (x+0x00000018) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) (x+0x00000018) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x0000001c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x0000001c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000020) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000020) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) (x+0x00000024) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) (x+0x00000024) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000028) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000028) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) (x+0x0000002c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) (x+0x0000002c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000030) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000030) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) (x+0x00000034) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) (x+0x00000034) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x01ffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x01000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0x00fff000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) (x+0x00000038) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) (x+0x00000038) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_SECURITY //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) (x+0x0000003c) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) (x+0x0000003c) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0x00ffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0x00fff000 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) (x+0x00000040) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) (x+0x00000040) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x01ffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x01000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0x00fff000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) (x+0x00000044) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) (x+0x00000044) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) (x+0x00000048) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) (x+0x00000048) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) (x+0x0000004c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) (x+0x0000004c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) (x+0x00000050) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) (x+0x00000050) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) (x+0x00000054) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) (x+0x00000054) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) (x+0x00000058) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) (x+0x00000058) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) (x+0x0000005c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) (x+0x0000005c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x) (x+0x00000060) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x) (x+0x00000060) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK 0xfffdffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT 0x1f + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK 0x40000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT 0x1e + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK 0x3ffc0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT 0x12 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK 0x00010000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK 0x0000f000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) (x+0x00000400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 //// + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00000404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00000404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 //// + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00000408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00000408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_TESTBUS_LOW //// + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) (x+0x0000040c) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) (x+0x0000040c) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH //// + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) (x+0x00000410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) (x+0x00000410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00000414) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00000414) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK //// + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00000418) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00000418) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + + +#endif + diff --git a/hw/qca6290/v1/wfss_pmm_base_struct.h b/hw/qca6290/v1/wfss_pmm_base_struct.h new file mode 100644 index 000000000000..f8ef4721273c --- /dev/null +++ b/hw/qca6290/v1/wfss_pmm_base_struct.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +////////////////////////////////////////////////////////////////////////////// +// wfss_pmm_base_struct.h generated by: GenCStruct.pm +////////////////////////////////////////////////////////////////////////////// +// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!! +////////////////////////////////////////////////////////////////////////////// +// RCS File : -USE CVS LOG- +// Revision : -USE CVS LOG- +// Last Check In : -USE CVS LOG- +////////////////////////////////////////////////////////////////////////////// +// Description : Top C Struct file +// +////////////////////////////////////////////////////////////////////////////// + +#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #ifdef _LSB_TO_MSB_REGS + #ifdef _MSB_TO_LSB_REGS + #error You can not define both _LSB_TO_MSB_REGS and _MSB_TO_LSB_REGS! + #endif + + #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #include "wfss_pmm_base_struct_ltm.h" + #endif + + #ifdef _MSB_TO_LSB_REGS + #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #include "wfss_pmm_base_struct_mtl.h" + #endif + + #ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #error You have to define _LSB_TO_MSB_REGS or _MSB_TO_LSB_REGS + #endif + +#endif + diff --git a/hw/qca8074/v1/HALcomdef.h b/hw/qca8074/v1/HALcomdef.h new file mode 100644 index 000000000000..cc351b126107 --- /dev/null +++ b/hw/qca8074/v1/HALcomdef.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H +/* +============================================================================== + +FILE: HALcomdef.h + +DESCRIPTION: + +============================================================================== + + Edit History + +$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $ + +when who what, where, why +-------- --- ----------------------------------------------------------- +06/17/10 sc Included com_dtypes.h and cleaned up typedefs +05/15/08 gfr Added HAL_ENUM_32BITS macro. +02/14/08 gfr Added bool32 type. +11/13/07 gfr Removed dependency on comdef.h +01/08/07 hxw Created + +*/ + + +/* + * Assembly wrapper + */ +#ifndef _ARM_ASM_ + +/* + * C++ wrapper + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +/* ----------------------------------------------------------------------- +** Types +** ----------------------------------------------------------------------- */ + +/* + * Standard integer types. + * + * bool32 - boolean, 32 bit (TRUE or FALSE) + */ +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +/* + * Macro to allow forcing an enum to 32 bits. The argument should be + * an identifier in the namespace of the enumeration in question, i.e. + * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx). + */ +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + +/*=========================================================================== + +FUNCTION inp, outp, inpw, outpw, inpdw, outpdw + +DESCRIPTION + IN/OUT port macros for byte and word ports, typically inlined by compilers + which support these routines + +PARAMETERS + inp( xx_addr ) + inpw( xx_addr ) + inpdw( xx_addr ) + outp( xx_addr, xx_byte_val ) + outpw( xx_addr, xx_word_val ) + outpdw( xx_addr, xx_dword_val ) + xx_addr - Address of port to read or write (may be memory mapped) + xx_byte_val - 8 bit value to write + xx_word_val - 16 bit value to write + xx_dword_val - 32 bit value to write + +DEPENDENCIES + None + +RETURN VALUE + inp/inpw/inpdw: the byte, word or dword read from the given address + outp/outpw/outpdw: the byte, word or dword written to the given address + +SIDE EFFECTS + None. + +===========================================================================*/ + + /* ARM based targets use memory mapped i/o, so the inp/outp calls are + ** macroized to access memory directly + */ + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif /* !_ARM_ASM_ */ + +#endif /* HAL_COMDEF_H */ + diff --git a/hw/qca8074/v1/HALhwio.h b/hw/qca8074/v1/HALhwio.h new file mode 100644 index 000000000000..4e51df01439f --- /dev/null +++ b/hw/qca8074/v1/HALhwio.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H +/* +=========================================================================== +*/ +/** + @file HALhwio.h + + Public interface include file for accessing the HWIO HAL definitions. + + The HALhwio.h file is the public API interface to the HW I/O (HWIO) + register access definitions. +*/ + +/*========================================================================= + Include Files +==========================================================================*/ + + +/* + * Common types. + */ +#include "HALcomdef.h" + + + +/* ----------------------------------------------------------------------- +** Macros +** ----------------------------------------------------------------------- */ + +/** + @addtogroup macros + @{ +*/ + +/** + * Map a base name to the pointer to access the base. + * + * This macro maps a base name to the pointer to access the base. + * This is generally just used internally. + * + */ +#define HWIO_BASE_PTR(base) base##_BASE_PTR + + +/** + * Declare a HWIO base pointer. + * + * This macro will declare a HWIO base pointer data structure. The pointer + * will always be declared as a weak symbol so multiple declarations will + * resolve correctly to the same data at link-time. + */ +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +/** + @} +*/ + + +/** + @addtogroup hwio_macros + @{ +*/ + +/** + * @name Address Macros + * + * Macros for getting register addresses. + * These macros are used for retrieving the address of a register. + * HWIO_ADDR* will return the directly accessible address (virtual or physical based + * on environment), HWIO_PHYS* will always return the physical address. + * The offset from the base region can be retrieved using HWIO_OFFS*. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * @{ + */ +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) +/** @} */ + +/** + * @name Input Macros + * + * These macros are used for reading from a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the input will be masked with the supplied mask. The HWIO_INF* + * macros take a field name and will do the appropriate masking and shifting + * to return just the value of that field. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing). + * + * @{ + */ +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Output Macros + * + * These macros are used for writing to a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the output will be masked with the supplied mask (meaning these + * macros do a read first, mask in the supplied data, then write it back). + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * The HWIO_OUTF* macros take a field name and will do the appropriate masking + * and shifting to output just the value of that field. + * HWIO_OUTV* registers take a named value instead of a numeric value and + * do the same masking/shifting as HWIO_OUTF. + * + * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing). + * + * @{ + */ +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Shift and Mask Macros + * + * Macros for getting shift and mask values for fields and registers. + * HWIO_RMSK: The mask value for accessing an entire register. For example: + * @code + * HWIO_RMSK(REG) -> 0xFFFFFFFF + * @endcode + * HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n + * HWIO_SHFT: The right-shift value for accessing a field in a register. For example: + * @code + * HWIO_SHFT(REG, FLD) -> 8 + * @endcode + * HWIO_FMSK: The mask value for accessing a field in a register. For example: + * @code + * HWIO_FMSK(REG, FLD) -> 0xFF00 + * @endcode + * HWIO_VAL: The value for a field in a register. For example: + * @code + * HWIO_VAL(REG, FLD, ON) -> 0x1 + * @endcode + * HWIO_FVAL: This macro takes a numerical value and will shift and mask it into + * the given field position. For example: + * @code + * HWIO_FVAL(REG, FLD, 0x1) -> 0x100 + * @endcode + * HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it + * into the given field position. For example: + * @code + * HWIO_FVALV(REG, FLD, ON) -> 0x100 + * @endcode + * + * @{ + */ +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +/** @} */ + +/** + * @name Shadow Register Macros + * + * These macros are used for directly reading the value stored in a + * shadow register. + * Shadow registers are defined for write-only registers. Generally these + * macros should not be necessary as HWIO_OUTM* macros will automatically use + * the shadow values internally. + * + * @{ + */ +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) +/** @} */ + +/** + @} +*/ /* end_group */ + + +/** @cond */ + +/* + * Map to final symbols. This remapping is done to allow register + * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN + * then remappings like "#define xreg xregnew" do not work as expected. + */ +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + + +/* + * HWIO_INTLOCK + * + * Macro used by autogenerated code for mutual exclusion around + * read-mask-write operations. This is not supported in HAL + * code but can be overridden by non-HAL code. + */ +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + + +/* + * Input/output port macros for memory mapped IO. + */ +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + + +#ifdef HAL_HWIO_EXTERNAL + +/* + * Replace macros with externally supplied functions. + */ +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif /* HAL_HWIO_EXTERNAL */ + + +/* + * Base 8-bit byte accessing macros. + */ +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 16-bit word accessing macros. + */ +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 32-bit double-word accessing macros. + */ +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +/** @endcond */ + +#endif /* HAL_HWIO_H */ + diff --git a/hw/qca8074/v1/buffer_addr_info.h b/hw/qca8074/v1/buffer_addr_info.h new file mode 100644 index 000000000000..433fc6b2be7d --- /dev/null +++ b/hw/qca8074/v1/buffer_addr_info.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 buffer_addr_31_0[31:0] +// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { + uint32_t buffer_addr_31_0 : 32; //[31:0] + uint32_t buffer_addr_39_32 : 8, //[7:0] + return_buffer_manager : 3, //[10:8] + sw_buffer_cookie : 21; //[31:11] +}; + +/* + +buffer_addr_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + + +buffer_addr_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + + +return_buffer_manager + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + + + + +sw_buffer_cookie + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The two most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + +*/ + + +/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + + + +*/ +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The two most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + +*/ +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _BUFFER_ADDR_INFO_H_ diff --git a/hw/qca8074/v1/ce_src_desc.h b/hw/qca8074/v1/ce_src_desc.h new file mode 100644 index 000000000000..8dd6bc39c9d2 --- /dev/null +++ b/hw/qca8074/v1/ce_src_desc.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 src_buffer_low[31:0] +// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16] +// 2 fw_metadata[15:0], ce_res_1[31:16] +// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { + uint32_t src_buffer_low : 32; //[31:0] + uint32_t src_buffer_high : 8, //[7:0] + toeplitz_en : 1, //[8] + src_swap : 1, //[9] + dest_swap : 1, //[10] + gather : 1, //[11] + ce_res_0 : 4, //[15:12] + length : 16; //[31:16] + uint32_t fw_metadata : 16, //[15:0] + ce_res_1 : 16; //[31:16] + uint32_t ce_res_2 : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +src_buffer_low + + LSB 32 bits of the 40 Bit Pointer to the source buffer + + + +src_buffer_high + + MSB 8 bits of the 40 Bit Pointer to the source buffer + + + +toeplitz_en + + Enable generation of 32-bit Toeplitz-LFSR hash for the + data transfer + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +src_swap + + Treats source memory organization as big-endian. For + each dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +dest_swap + + Treats destination memory organization as big-endian. + For each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +gather + + Enables gather of multiple copy engine source + descriptors to one destination. + + + +ce_res_0 + + Reserved + + + +length + + Length of the buffer in units of octets of the current + descriptor + + + +fw_metadata + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +ce_res_1 + + Reserved + + + +ce_res_2 + + Reserved + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW + + LSB 32 bits of the 40 Bit Pointer to the source buffer + + +*/ +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff + +/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH + + MSB 8 bits of the 40 Bit Pointer to the source buffer + + +*/ +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff + +/* Description CE_SRC_DESC_1_TOEPLITZ_EN + + Enable generation of 32-bit Toeplitz-LFSR hash for the + data transfer + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100 + +/* Description CE_SRC_DESC_1_SRC_SWAP + + Treats source memory organization as big-endian. For + each dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200 + +/* Description CE_SRC_DESC_1_DEST_SWAP + + Treats destination memory organization as big-endian. + For each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400 + +/* Description CE_SRC_DESC_1_GATHER + + Enables gather of multiple copy engine source + descriptors to one destination. + + +*/ +#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_1_GATHER_LSB 11 +#define CE_SRC_DESC_1_GATHER_MASK 0x00000800 + +/* Description CE_SRC_DESC_1_CE_RES_0 + + Reserved + + +*/ +#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_1_CE_RES_0_LSB 12 +#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000 + +/* Description CE_SRC_DESC_1_LENGTH + + Length of the buffer in units of octets of the current + descriptor + + +*/ +#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_LENGTH_LSB 16 +#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000 + +/* Description CE_SRC_DESC_2_FW_METADATA + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_2_FW_METADATA_LSB 0 +#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff + +/* Description CE_SRC_DESC_2_CE_RES_1 + + Reserved + + +*/ +#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008 +#define CE_SRC_DESC_2_CE_RES_1_LSB 16 +#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000 + +/* Description CE_SRC_DESC_3_CE_RES_2 + + Reserved + + +*/ +#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c +#define CE_SRC_DESC_3_CE_RES_2_LSB 0 +#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff + +/* Description CE_SRC_DESC_3_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_3_RING_ID_LSB 20 +#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000 + +/* Description CE_SRC_DESC_3_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _CE_SRC_DESC_H_ diff --git a/hw/qca8074/v1/ce_stat_desc.h b/hw/qca8074/v1/ce_stat_desc.h new file mode 100644 index 000000000000..4667d1447546 --- /dev/null +++ b/hw/qca8074/v1/ce_stat_desc.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16] +// 1 toeplitz_hash_0[31:0] +// 2 toeplitz_hash_1[31:0] +// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { + uint32_t ce_res_5 : 8, //[7:0] + toeplitz_en : 1, //[8] + src_swap : 1, //[9] + dest_swap : 1, //[10] + gather : 1, //[11] + ce_res_6 : 4, //[15:12] + length : 16; //[31:16] + uint32_t toeplitz_hash_0 : 32; //[31:0] + uint32_t toeplitz_hash_1 : 32; //[31:0] + uint32_t fw_metadata : 16, //[15:0] + ce_res_7 : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +ce_res_5 + + Reserved + + + +toeplitz_en + + + + +src_swap + + Source memory buffer swapped + + + +dest_swap + + Destination memory buffer swapped + + + +gather + + Gather of multiple copy engine source descriptors to one + destination enabled + + + +ce_res_6 + + Reserved + + + +length + + Sum of all the Lengths of the source descriptor in the + gather chain + + + +toeplitz_hash_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + + + +toeplitz_hash_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + + + +fw_metadata + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +ce_res_7 + + Reserved + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description CE_STAT_DESC_0_CE_RES_5 + + Reserved + + +*/ +#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_5_LSB 0 +#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff + +/* Description CE_STAT_DESC_0_TOEPLITZ_EN + + + +*/ +#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100 + +/* Description CE_STAT_DESC_0_SRC_SWAP + + Source memory buffer swapped + + +*/ +#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200 + +/* Description CE_STAT_DESC_0_DEST_SWAP + + Destination memory buffer swapped + + +*/ +#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400 + +/* Description CE_STAT_DESC_0_GATHER + + Gather of multiple copy engine source descriptors to one + destination enabled + + +*/ +#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_0_GATHER_LSB 11 +#define CE_STAT_DESC_0_GATHER_MASK 0x00000800 + +/* Description CE_STAT_DESC_0_CE_RES_6 + + Reserved + + +*/ +#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_6_LSB 12 +#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000 + +/* Description CE_STAT_DESC_0_LENGTH + + Sum of all the Lengths of the source descriptor in the + gather chain + + +*/ +#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_0_LENGTH_LSB 16 +#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000 + +/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + + +*/ +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff + +/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + + +*/ +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff + +/* Description CE_STAT_DESC_3_FW_METADATA + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_3_FW_METADATA_LSB 0 +#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff + +/* Description CE_STAT_DESC_3_CE_RES_7 + + Reserved + + +*/ +#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_3_CE_RES_7_LSB 16 +#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000 + +/* Description CE_STAT_DESC_3_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_3_RING_ID_LSB 20 +#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000 + +/* Description CE_STAT_DESC_3_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _CE_STAT_DESC_H_ diff --git a/hw/qca8074/v1/com_dtypes.h b/hw/qca8074/v1/com_dtypes.h new file mode 100644 index 000000000000..a1c0edccc566 --- /dev/null +++ b/hw/qca8074/v1/com_dtypes.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +/** + @file com_dtypes.h + @brief This header file contains general data types that are of use to all + modules. + +*/ +/*=========================================================================== +NOTE: The @brief description and any detailed descriptions above do not appear + in the PDF. + + The Utility_Services_API_mainpage.dox file contains all file/group + descriptions that are in the output PDF generated using Doxygen and + Latex. To edit or update any of the file/group text in the PDF, edit + the Utility_Services_API_mainpage.dox file or contact Tech Pubs. + + The above description for this file is part of the "utils_services" + group description in the Utility_Services_API_mainpage.dox file. +===========================================================================*/ +/*=========================================================================== + + S T A N D A R D D E C L A R A T I O N S + +DESCRIPTION + This header file contains general data types that are of use to all modules. + The values or definitions are dependent on the specified + target. T_WINNT specifies Windows NT based targets, otherwise the + default is for ARM targets. + + T_WINNT Software is hosted on an NT platforn, triggers macro and + type definitions, unlike definition above which triggers + actual OS calls + +===========================================================================*/ + + +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $ + +when who what, where, why +-------- --- ---------------------------------------------------------- +03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup. +11/09/10 EBR Doxygenated file. +09/15/09 pc Created file. +===========================================================================*/ + + +/*=========================================================================== + + Data Declarations + +===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* For NT apps we want to use the Win32 definitions and/or those + supplied by the Win32 compiler for things like NULL, MAX, MIN + abs, labs, etc. +*/ +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +/* ------------------------------------------------------------------------ +** Constants +** ------------------------------------------------------------------------ */ + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +/** @addtogroup utils_services +@{ */ + +/** @name Macros for Common Data Types +@{ */ +#define TRUE 1 /**< Boolean TRUE value. */ +#define FALSE 0 /**< Boolean FALSE value. */ + +#define ON 1 /**< ON value. */ +#define OFF 0 /**< OFF value. */ + +#ifndef NULL + #define NULL 0 /**< NULL value. */ +#endif +/** @} */ /* end_name_group Macros for Common Data Types */ + +/* ----------------------------------------------------------------------- +** Standard Types +** ----------------------------------------------------------------------- */ + +/** @} */ /* end_addtogroup utils_services */ + +/* The following definitions are the same across platforms. This first + group are the sanctioned types. +*/ +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +/** @addtogroup utils_services +@{ */ +/** Boolean value type. +*/ +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +/** @cond +*/ +#if defined(DALSTDDEF_H) /* guards against a known re-definer */ +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif /* #if !defined(DALSTDDEF_H) */ +/** @endcond */ + +#ifndef _UINT32_DEFINED +/** Unsigned 32-bit value. +*/ +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED +/** Unsigned 16-bit value. +*/ +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED +/** Unsigned 8-bit value. +*/ +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED +/** Signed 32-bit value. +*/ +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED +/** Signed 16-bit value. +*/ +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED +/** Signed 8-bit value. +*/ +typedef signed char int8; +#define _INT8_DEFINED +#endif + +/** @cond +*/ +/* This group are the deprecated types. Their use should be +** discontinued and new code should use the types above +*/ +#ifndef _BYTE_DEFINED +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +/** DEPRECATED: Unsinged 16 bit value type. +*/ +typedef unsigned short word; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long dword; + +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char uint1; +/** DEPRECATED: Unsigned 16 bit value type. +*/ +typedef unsigned short uint2; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long uint4; + +/** DEPRECATED: Signed 8 bit value type. +*/ +typedef signed char int1; +/** DEPRECATED: Signed 16 bit value type. +*/ +typedef signed short int2; +/** DEPRECATED: Signed 32 bit value type. +*/ +typedef long int int4; + +/** DEPRECATED: Signed 32 bit value. +*/ +typedef signed long sint31; +/** DEPRECATED: Signed 16 bit value. +*/ +typedef signed short sint15; +/** DEPRECATED: Signed 8 bit value. +*/ +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; +/** @endcond */ + +#if (! defined T_WINNT) && (! defined __GNUC__) + /* Non WinNT Targets */ + #ifndef _INT64_DEFINED + /** Signed 64-bit value. + */ + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + /** Unsigned 64-bit value. + */ + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */ + /* WINNT or SOLARIS based targets */ + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; /* Signed 64-bit value */ + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; /* Unsigned 64-bit value */ + #define _UINT64_DEFINED + #endif + #endif +#endif /* T_WINNT */ + +#endif /* _ARM_ASM_ */ + +#ifdef __cplusplus +} +#endif + +/** @} */ /* end_addtogroup utils_services */ +#endif /* COM_DTYPES_H */ diff --git a/hw/qca8074/v1/lithium_top_reg.h b/hw/qca8074/v1/lithium_top_reg.h new file mode 100644 index 000000000000..87e1b3d2514e --- /dev/null +++ b/hw/qca8074/v1/lithium_top_reg.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +////////////////////////////////////////////////////////////////////////////// +// lithium_top_reg.h generated by: GenArmCHeader.pl +////////////////////////////////////////////////////////////////////////////// +// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!! +////////////////////////////////////////////////////////////////////////////// +// RCS File : -USE CVS LOG- +// Revision : -USE CVS LOG- +// Last Check In : -USE CVS LOG- +////////////////////////////////////////////////////////////////////////////// +// Description : Constants related to Hardware Registers +// +// Byte Addresses are used for all BASES and ADDRESSES +////////////////////////////////////////////////////////////////////////////// +#ifndef LITHIUM_TOP_REG_H +#define LITHIUM_TOP_REG_H + +#define UMAC_CE_COMMON_CE_HOST_IE_0 (0x00A18034) +#define UMAC_CE_COMMON_CE_HOST_IE_1 (0x00A18038) + +#endif diff --git a/hw/qca8074/v1/mac_tcl_reg_seq_hwiobase.h b/hw/qca8074/v1/mac_tcl_reg_seq_hwiobase.h new file mode 100644 index 000000000000..a845897e8938 --- /dev/null +++ b/hw/qca8074/v1/mac_tcl_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __MAC_TCL_REG_SEQ_BASE_H__ +#define __MAC_TCL_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h b/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h new file mode 100644 index 000000000000..73f4cc2b369a --- /dev/null +++ b/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h @@ -0,0 +1,6821 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __MAC_TCL_REG_SEQ_REG_H__ +#define __MAC_TCL_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "mac_tcl_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block MAC_TCL_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register TCL_R0_SW2TCL1_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CTRL //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0007ffe1 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_SHFT 0x0 + +//// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00000007 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_CTRL //// + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_CTRL //// + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_CTRL //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_CTRL //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_GEN_CTRL //// + +#define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) +#define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7e1d +#define HWIO_TCL_R0_GEN_CTRL_SHFT 0 +#define HWIO_TCL_R0_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) +#define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 + +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe + +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd + +#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 +#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc + +#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK 0x00000e00 +#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT 0x9 + +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 + +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 + +#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_BMSK 0x00000004 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_SHFT 0x2 + +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_0 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x) (x+0x0000002c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_PHYS(x) (x+0x0000002c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_1 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x) (x+0x00000030) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_PHYS(x) (x+0x00000030) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_2 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x) (x+0x00000034) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_PHYS(x) (x+0x00000034) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_3 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x) (x+0x00000038) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_PHYS(x) (x+0x00000038) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_4 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x) (x+0x0000003c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_PHYS(x) (x+0x0000003c) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_5 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x) (x+0x00000040) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_PHYS(x) (x+0x00000040) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID1_MAP_6 //// + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x) (x+0x00000044) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_PHYS(x) (x+0x00000044) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK 0x00000fff +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_0 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x) (x+0x00000048) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_PHYS(x) (x+0x00000048) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_1 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x) (x+0x0000004c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_PHYS(x) (x+0x0000004c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_2 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x) (x+0x00000050) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_PHYS(x) (x+0x00000050) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_3 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x) (x+0x00000054) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_PHYS(x) (x+0x00000054) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_4 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x) (x+0x00000058) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_PHYS(x) (x+0x00000058) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_5 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x) (x+0x0000005c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_PHYS(x) (x+0x0000005c) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK 0x3fffffff +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK 0x38000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT 0x1b + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_BMSK 0x07000000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_SHFT 0x18 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_BMSK 0x00e00000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_SHFT 0x15 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_BMSK 0x001c0000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_SHFT 0x12 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_BMSK 0x00038000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_SHFT 0xf + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_BMSK 0x00007000 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_SHFT 0xc + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID2_MAP_6 //// + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x) (x+0x00000060) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_PHYS(x) (x+0x00000060) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK 0x00000fff +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val) +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK 0x00000e00 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT 0x9 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_BMSK 0x000001c0 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_SHFT 0x6 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_BMSK 0x00000038 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_SHFT 0x3 + +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_BMSK 0x00000007 +#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_SHFT 0x0 + +//// Register TCL_R0_PCP_TID_MAP //// + +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x00000064) +#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x00000064) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff +#define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 +#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) +#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) +#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) +#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_31_0 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x00000068) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x00000068) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_63_32 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x0000006c) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x0000006c) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_64 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x00000070) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x00000070) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_31_0 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x) (x+0x00000074) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x) (x+0x00000074) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_63_32 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x) (x+0x00000078) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x) (x+0x00000078) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_95_64 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x) (x+0x0000007c) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x) (x+0x0000007c) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_127_96 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x) (x+0x00000080) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x) (x+0x00000080) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_159_128 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x) (x+0x00000084) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x) (x+0x00000084) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_191_160 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x) (x+0x00000088) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x) (x+0x00000088) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_223_192 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x) (x+0x0000008c) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x) (x+0x0000008c) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_255_224 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x) (x+0x00000090) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x) (x+0x00000090) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_287_256 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x) (x+0x00000094) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x) (x+0x00000094) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_HASH_KEY_314_288 //// + +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x) (x+0x00000098) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x) (x+0x00000098) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK 0x07ffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT 0 +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff +#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 + +//// Register TCL_R0_CONFIG_SEARCH_QUEUE //// + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x0000009c) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x0000009c) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00003dfc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 + +//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a0) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a0) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000a4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000a4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a8) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a8) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000ac) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000ac) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_CONFIG_SEARCH_METADATA //// + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000000b0) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000000b0) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 + +//// Register TCL_R0_TID_MAP_PRTY //// + +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000000b4) +#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000000b4) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef +#define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 +#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) +#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 + +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 + +//// Register TCL_R0_INVALID_APB_ACC_ADDR //// + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000000b8) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000000b8) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ + out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 + +//// Register TCL_R0_WATCHDOG //// + +#define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000000bc) +#define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000000bc) +#define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) +#define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x000000c0) +#define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x000000c0) +#define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000000c4) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000000c4) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000000c8) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000000c8) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000000cc) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000000cc) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000000d0) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000000d0) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000000d4) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000000d4) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000e0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000e0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000e4) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000e4) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000f4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000f4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000f8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000f8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000fc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000fc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000100) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000100) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000104) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000104) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000108) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000108) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000010c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000010c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000110) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000110) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000114) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000114) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000118) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000118) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x0000011c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x0000011c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x00000120) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x00000120) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000124) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000124) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000128) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000128) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x0000012c) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x0000012c) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000138) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000138) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000013c) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000013c) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000014c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000014c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000150) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000150) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000154) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000154) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000158) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000158) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000015c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000015c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000160) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000160) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000164) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000164) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000168) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000168) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000016c) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000016c) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000170) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000170) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000174) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000174) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000178) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000178) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000017c) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000017c) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000180) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000180) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000184) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000184) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000190) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000190) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000194) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000194) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001a4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001a4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001a8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001a8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001ac) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001ac) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b0) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b0) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b4) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001b8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001b8) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001bc) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001bc) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001c0) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001c0) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x000001c4) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x000001c4) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001c8) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001c8) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x000001cc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x000001cc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x000001d0) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x000001d0) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x000001d4) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x000001d4) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x000001d8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x000001d8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x000001dc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x000001dc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001e8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001e8) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001ec) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001ec) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001fc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001fc) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000200) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000200) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000204) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000204) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000208) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000208) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000020c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000020c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000210) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000210) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000214) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000214) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000218) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000218) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x0000021c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x0000021c) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000220) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000220) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000224) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000224) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000228) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000228) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_ID //// + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x0000022c) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x0000022c) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000230) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000230) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MISC //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000234) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000234) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000240) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000240) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000244) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000244) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000254) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000254) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000258) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000258) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000025c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000025c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000260) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000260) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000264) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000264) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000268) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000268) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000026c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000026c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000270) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000270) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000274) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000274) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000278) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000278) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000027c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000027c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000280) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000280) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_ID //// + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000284) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000284) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_STATUS //// + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000288) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000288) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_MISC //// + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000028c) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000028c) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000290) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000290) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000294) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000294) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002a0) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002a0) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002a4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002a4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002a8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002a8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d0) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d0) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000002d4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000002d4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000002d8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000002d8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_ID //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000002dc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000002dc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000002e0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000002e0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MISC //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000002e4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000002e4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002f8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002f8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002fc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002fc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000300) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000300) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000031c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000031c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000320) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000320) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x00000324) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x00000324) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000328) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000328) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x0000032c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x0000032c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000330) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000330) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_ID //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000334) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000334) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000338) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000338) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MISC //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000033c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000033c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000340) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000340) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000344) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000344) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000350) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000350) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000354) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000354) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000358) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000358) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000374) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000374) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000378) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000378) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000037c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000037c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000380) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000380) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000384) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000384) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000388) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000388) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_ID //// + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000038c) +#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000038c) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_STATUS //// + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000390) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000390) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_MISC //// + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000394) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000394) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x0000003f +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000398) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000398) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000039c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000039c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003a8) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003a8) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003ac) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003ac) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b0) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b0) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003d8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003d8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000003dc) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000003dc) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000003e0) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000003e0) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000003e4) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000003e4) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register TCL_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000003e8) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000003e8) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000003ec) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000003ec) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000003f0) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000003f0) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000003f4) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000003f4) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000003f8) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000003f8) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000003fc) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000003fc) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000400) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000400) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000404) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000404) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x0000040c) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x0000040c) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000410) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000410) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000414) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000414) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_SIZE //// + +#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000418) +#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000418) +#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff +#define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) +#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_SEARCH_CTRL //// + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x0000041c) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x0000041c) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff03ff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 + +//// Register TCL_R0_ASE_WATCHDOG //// + +#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000420) +#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000420) +#define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) +#define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_ASE_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000424) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000424) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_WRITE_BACK_PENDING //// + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000428) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000428) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 + +//// Register TCL_R0_FSE_GST_BASE_ADDR_LOW //// + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x0000042c) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x0000042c) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT 0 +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH //// + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000430) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000430) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT 0 +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_GST_SIZE //// + +#define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x) (x+0x00000434) +#define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x) (x+0x00000434) +#define HWIO_TCL_R0_FSE_GST_SIZE_RMSK 0x000fffff +#define HWIO_TCL_R0_FSE_GST_SIZE_SHFT 0 +#define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) +#define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) +#define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff +#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_SEARCH_CTRL //// + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x) (x+0x00000438) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x) (x+0x00000438) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK 0xffff03ff +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT 0 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 + +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 + +//// Register TCL_R0_FSE_WATCHDOG //// + +#define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x) (x+0x0000043c) +#define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x) (x+0x0000043c) +#define HWIO_TCL_R0_FSE_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) +#define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_FSE_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x) (x+0x00000440) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x) (x+0x00000440) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_WRITE_BACK_PENDING //// + +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000444) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000444) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK 0x00000001 +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT 0 +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 +#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 + +//// Register TCL_R1_SM_STATES_IX_0 //// + +#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) +#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) +#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff +#define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) +#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 + +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 + +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 + +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc + +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 + +//// Register TCL_R1_SM_STATES_IX_1 //// + +#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) +#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) +#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x00007fff +#define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) +#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_CTRL_0 //// + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x1fffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f +#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_LOW //// + +#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) +#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_HIGH //// + +#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) +#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_0 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) +#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) +#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_1 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_2 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_3 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 + +//// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register TCL_R1_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_ASE_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 + +//// Register TCL_R1_ASE_SM_STATES //// + +#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff +#define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 +#define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) +#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) +#define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 + +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 + +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 + +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 +#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 + +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 + +//// Register TCL_R1_FSE_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x) (x+0x000010d0) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x) (x+0x000010d0) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS //// + +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x000010d4) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x000010d4) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 +#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x000010d8) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x000010d8) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x000010dc) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x000010dc) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x000010e0) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x000010e0) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa + +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff +#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 + +//// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER //// + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x000010e4) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x000010e4) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 + +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f +#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 + +//// Register TCL_R1_FSE_SM_STATES //// + +#define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x) (x+0x000010e8) +#define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x) (x+0x000010e8) +#define HWIO_TCL_R1_FSE_SM_STATES_RMSK 0x003fffff +#define HWIO_TCL_R1_FSE_SM_STATES_SHFT 0 +#define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) +#define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) +#define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 +#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 + +#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 +#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb + +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 +#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 + +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 + +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 +#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 + +#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f +#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 + +//// Register TCL_R1_FSE_CACHE_DEBUG //// + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x) (x+0x000010ec) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x) (x+0x000010ec) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK 0x000003ff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT 0 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 + +//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS //// + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x000010f0) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x000010f0) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 + +//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n //// + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x10F4+0x4*n) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x10F4+0x4*n) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT 0 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 + +//// Register TCL_R2_SW2TCL1_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL1_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL2_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL2_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL3_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL3_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL_CMD_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL_CMD_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_FW2TCL1_RING_HP //// + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_FW2TCL1_RING_TP //// + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2TQM_RING_HP //// + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2TQM_RING_TP //// + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS1_RING_HP //// + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS1_RING_TP //// + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS2_RING_HP //// + +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS2_RING_TP //// + +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2FW_RING_HP //// + +#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) +#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) +#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2FW_RING_TP //// + +#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) +#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) +#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/hw/qca8074/v1/msmhwio.h b/hw/qca8074/v1/msmhwio.h new file mode 100644 index 000000000000..23223cfdc9a1 --- /dev/null +++ b/hw/qca8074/v1/msmhwio.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef MSMHWIO_H +#define MSMHWIO_H +/* +=========================================================================== +*/ +/** + @file msmhwio.h + + Deprecated public interface include file for accessing the HWIO macro + definitions. + + The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO) + register access definitions. See HALhwio.h and DDIHWIO.h for the new + interfaces. +*/ +/* + ==================================================================== + $Header: //components/rel/core.mpss/3.9.2/api/systemdrivers/msmhwio.h#1 $ $DateTime: 2016/01/19 23:36:58 $ $Author: pwbldsvc $ + ==================================================================== +*/ + +/*========================================================================= + Include Files +==========================================================================*/ + +/* + * Include main HWIO macros. + */ +#include "HALhwio.h" + + +#endif /* MSMHWIO_H */ + diff --git a/hw/qca8074/v1/reo_destination_ring.h b/hw/qca8074/v1/reo_destination_ring.h new file mode 100644 index 000000000000..fd6900d858a0 --- /dev/null +++ b/hw/qca8074/v1/reo_destination_ring.h @@ -0,0 +1,730 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_msdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; +// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +// 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; +// 6 rx_reo_queue_desc_addr_31_0[31:0] +// 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] +// 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_DESTINATION_RING 16 + +struct reo_destination_ring { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + reo_dest_buffer_type : 1, //[8] + reo_push_reason : 2, //[10:9] + reo_error_code : 5, //[15:11] + receive_queue_number : 16; //[31:16] + uint32_t soft_reorder_info_valid : 1, //[0] + reorder_opcode : 4, //[4:1] + reorder_slot_index : 8, //[12:5] + reserved_8a : 19; //[31:13] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15 : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info buf_or_link_desc_addr_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Details of the physical address of the a buffer or MSDU + link descriptor + +struct rx_mpdu_desc_info rx_mpdu_desc_info_details + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + General information related to the MPDU that is passed + on from REO entrance ring to the REO destination ring + +struct rx_msdu_desc_info rx_msdu_desc_info_details + + General information related to the MSDU that is passed + on from RXDMA all the way to to the REO destination ring. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + + +reo_dest_buffer_type + + Indicates the type of address provided in the + 'Buf_or_link_desc_addr_info' + + + + The address of an MSDU buffer + + The address of the MSDU + link descriptor. + + + + + +reo_push_reason + + Indicates why REO pushed the frame to this exit ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + + + +reo_error_code + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + + +receive_queue_number + + This field indicates the REO MPDU reorder queue ID from + which this frame originated. This field is populated from a + field with the same name in the RX_REO_QUEUE descriptor. + + + +soft_reorder_info_valid + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes + + + +reorder_opcode + + Field is valid when 'Soft_reorder_info_valid' is set. + This field is always valid for debug purpose as well. + + Details are in the MLD. + + + + + + + + + + + + + + + + + + + + + + the error reason code is in + reo_error_code field. + + + + + + + + + + + + + + + + + +reorder_slot_index + + Field only valid when 'Soft_reorder_info_valid' is set. + + + + TODO: add description + + + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15 + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 +#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 +#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 +#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + +*/ +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + +*/ +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE + + Indicates the type of address provided in the + 'Buf_or_link_desc_addr_info' + + + + The address of an MSDU buffer + + The address of the MSDU + link descriptor. + + + + +*/ +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 + +/* Description REO_DESTINATION_RING_7_REO_PUSH_REASON + + Indicates why REO pushed the frame to this exit ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + + +*/ +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 + +/* Description REO_DESTINATION_RING_7_REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + +*/ +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 + +/* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER + + This field indicates the REO MPDU reorder queue ID from + which this frame originated. This field is populated from a + field with the same name in the RX_REO_QUEUE descriptor. + + +*/ +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + +/* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes + + +*/ +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 + +/* Description REO_DESTINATION_RING_8_REORDER_OPCODE + + Field is valid when 'Soft_reorder_info_valid' is set. + This field is always valid for debug purpose as well. + + Details are in the MLD. + + + + + + + + + + + + + + + + + + + + + + the error reason code is in + reo_error_code field. + + + + + + + + + + + + + + + + +*/ +#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e + +/* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX + + Field only valid when 'Soft_reorder_info_valid' is set. + + + + TODO: add description + + + + +*/ +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 + +/* Description REO_DESTINATION_RING_8_RESERVED_8A + + +*/ +#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 13 +#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffffe000 + +/* Description REO_DESTINATION_RING_9_RESERVED_9A + + +*/ +#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0 +#define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_10_RESERVED_10A + + +*/ +#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 +#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_11_RESERVED_11A + + +*/ +#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 +#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_12_RESERVED_12A + + +*/ +#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 +#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_13_RESERVED_13A + + +*/ +#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 +#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_14_RESERVED_14A + + +*/ +#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 +#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_15_RESERVED_15 + + +*/ +#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 +#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff + +/* Description REO_DESTINATION_RING_15_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RING_ID_LSB 20 +#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 + +/* Description REO_DESTINATION_RING_15_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_DESTINATION_RING_H_ diff --git a/hw/qca8074/v1/reo_entrance_ring.h b/hw/qca8074/v1/reo_entrance_ring.h new file mode 100644 index 000000000000..8b3f4e9fccc9 --- /dev/null +++ b/hw/qca8074/v1/reo_entrance_ring.h @@ -0,0 +1,722 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; +// 4 rx_reo_queue_desc_addr_31_0[31:0] +// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] +// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7] +// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + rounded_mpdu_byte_count : 14, //[21:8] + reo_destination_indication : 5, //[26:22] + frameless_bar : 1, //[27] + reserved_5a : 4; //[31:28] + uint32_t rxdma_push_reason : 2, //[1:0] + rxdma_error_code : 5, //[6:2] + reserved_6a : 25; //[31:7] + uint32_t reserved_7a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct rx_mpdu_details reo_level_mpdu_frame_info + + Consumer: REO + + Producer: RXDMA + + + + Details related to the MPDU being pushed into the REO + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + + +rounded_mpdu_byte_count + + An approximation of the number of bytes received in this + MPDU. + + Used to keeps stats on the amount of data flowing + through a queue. + + + +reo_destination_indication + + RXDMA copy the MPDU's first MSDU's destination + indication field here. This is used for REO to be able to + re-route the packet to a different SW destination ring if + the packet is detected as error in REO. + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +frameless_bar + + When set, this REO entrance ring struct contains BAR + info from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is set are: + + Rx_reo_queue_desc_addr_31_0 + + RX_reo_queue_desc_addr_39_32 + + + + And within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0 + + + + + +reserved_5a + + + +rxdma_push_reason + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + This field is ignored by REO. + + + +rxdma_error_code + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + This field is ignored by REO. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + +reserved_6a + + + +reserved_7a + + + +ring_id + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff +#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff +#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff +#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 +#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + +*/ +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + +*/ +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT + + An approximation of the number of bytes received in this + MPDU. + + Used to keeps stats on the amount of data flowing + through a queue. + + +*/ +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION + + RXDMA copy the MPDU's first MSDU's destination + indication field here. This is used for REO to be able to + re-route the packet to a different SW destination ring if + the packet is detected as error in REO. + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR + + When set, this REO entrance ring struct contains BAR + info from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is set are: + + Rx_reo_queue_desc_addr_31_0 + + RX_reo_queue_desc_addr_39_32 + + + + And within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0 + + + + +*/ +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 + +/* Description REO_ENTRANCE_RING_5_RESERVED_5A + + +*/ +#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 + +/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + This field is ignored by REO. + + +*/ +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + This field is ignored by REO. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request +*/ +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +/* Description REO_ENTRANCE_RING_6_RESERVED_6A + + +*/ +#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 7 +#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xffffff80 + +/* Description REO_ENTRANCE_RING_7_RESERVED_7A + + +*/ +#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0 +#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff + +/* Description REO_ENTRANCE_RING_7_RING_ID + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_ENTRANCE_RING_H_ diff --git a/hw/qca8074/v1/reo_get_queue_stats.h b/hw/qca8074/v1/reo_get_queue_stats.h new file mode 100644 index 000000000000..6cc4b0728ea8 --- /dev/null +++ b/hw/qca8074/v1/reo_get_queue_stats.h @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 rx_reo_queue_desc_addr_31_0[31:0] +// 2 rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + clear_stats : 1, //[8] + reserved_2a : 23; //[31:9] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + + +clear_stats + + Clear stat settings.... + + + + Do NOT clear the stats after + generating the status + + Clear the stats after + generating the status. + + + + The stats actually cleared are: + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + +#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 +#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + +*/ +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + +*/ +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_GET_QUEUE_STATS_2_CLEAR_STATS + + Clear stat settings.... + + + + Do NOT clear the stats after + generating the status + + Clear the stats after + generating the status. + + + + The stats actually cleared are: + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + +*/ +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 + +/* Description REO_GET_QUEUE_STATS_2_RESERVED_2A + + +*/ +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 + +/* Description REO_GET_QUEUE_STATS_3_RESERVED_3A + + +*/ +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_4_RESERVED_4A + + +*/ +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_5_RESERVED_5A + + +*/ +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_6_RESERVED_6A + + +*/ +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_7_RESERVED_7A + + +*/ +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_8_RESERVED_8A + + +*/ +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_GET_QUEUE_STATS_H_ diff --git a/hw/qca8074/v1/reo_get_queue_stats_status.h b/hw/qca8074/v1/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..cf89d0d4d64a --- /dev/null +++ b/hw/qca8074/v1/reo_get_queue_stats_status.h @@ -0,0 +1,868 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 ssn[11:0], current_index[19:12], reserved_2[31:20] +// 3 pn_31_0[31:0] +// 4 pn_63_32[31:0] +// 5 pn_95_64[31:0] +// 6 pn_127_96[31:0] +// 7 last_rx_enqueue_timestamp[31:0] +// 8 last_rx_dequeue_timestamp[31:0] +// 9 rx_bitmap_31_0[31:0] +// 10 rx_bitmap_63_32[31:0] +// 11 rx_bitmap_95_64[31:0] +// 12 rx_bitmap_127_96[31:0] +// 13 rx_bitmap_159_128[31:0] +// 14 rx_bitmap_191_160[31:0] +// 15 rx_bitmap_223_192[31:0] +// 16 rx_bitmap_255_224[31:0] +// 17 current_mpdu_count[6:0], current_msdu_count[31:7] +// 18 reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] +// 19 frames_in_order_count[23:0], bar_received_count[31:24] +// 20 mpdu_frames_processed_count[31:0] +// 21 msdu_frames_processed_count[31:0] +// 22 total_processed_byte_count[31:0] +// 23 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25 + +struct reo_get_queue_stats_status { + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, //[11:0] + current_index : 8, //[19:12] + reserved_2 : 12; //[31:20] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t last_rx_enqueue_timestamp : 32; //[31:0] + uint32_t last_rx_dequeue_timestamp : 32; //[31:0] + uint32_t rx_bitmap_31_0 : 32; //[31:0] + uint32_t rx_bitmap_63_32 : 32; //[31:0] + uint32_t rx_bitmap_95_64 : 32; //[31:0] + uint32_t rx_bitmap_127_96 : 32; //[31:0] + uint32_t rx_bitmap_159_128 : 32; //[31:0] + uint32_t rx_bitmap_191_160 : 32; //[31:0] + uint32_t rx_bitmap_223_192 : 32; //[31:0] + uint32_t rx_bitmap_255_224 : 32; //[31:0] + uint32_t current_mpdu_count : 7, //[6:0] + current_msdu_count : 25; //[31:7] + uint32_t reserved_18 : 4, //[3:0] + timeout_count : 6, //[9:4] + forward_due_to_bar_count : 6, //[15:10] + duplicate_count : 16; //[31:16] + uint32_t frames_in_order_count : 24, //[23:0] + bar_received_count : 8; //[31:24] + uint32_t mpdu_frames_processed_count : 32; //[31:0] + uint32_t msdu_frames_processed_count : 32; //[31:0] + uint32_t total_processed_byte_count : 32; //[31:0] + uint32_t late_receive_mpdu_count : 12, //[11:0] + window_jump_2k : 4, //[15:12] + hole_count : 16; //[31:16] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +ssn + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + + +current_index + + Points to last forwarded packet + + + +reserved_2 + + + +pn_31_0 + + + + +pn_63_32 + + Bits [63:32] of the PN number. + + + +pn_95_64 + + Bits [95:64] of the PN number. + + + +pn_127_96 + + Bits [127:96] of the PN number. + + + +last_rx_enqueue_timestamp + + Timestamp of arrival of the last MPDU for this queue + + + +last_rx_dequeue_timestamp + + Timestamp of forwarding an MPDU + + + + If the queue is empty when a frame gets received, this + time shall be initialized to the 'enqueue' timestamp + + + + Used for aging + + + +rx_bitmap_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + + +rx_bitmap_63_32 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_95_64 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_127_96 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_159_128 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_191_160 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_223_192 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_255_224 + + See Rx_bitmap_31_0 description + + + +current_mpdu_count + + The number of MPDUs in the queue. + + + + + +current_msdu_count + + The number of MSDUs in the queue. + + + +reserved_18 + + + +timeout_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + + +forward_due_to_bar_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + + +duplicate_count + + The number of duplicate frames that have been detected + + + +frames_in_order_count + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + + +bar_received_count + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + + +mpdu_frames_processed_count + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + + + + +msdu_frames_processed_count + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + + + + +total_processed_byte_count + + An approximation of the number of bytes received for + this queue. + + + + In 64 byte units + + + +late_receive_mpdu_count + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + + +window_jump_2k + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + + +hole_count + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff +#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_2_SSN + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff + +/* Description REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX + + Points to last forwarded packet + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000 + +/* Description REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2 + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000 + +/* Description REO_GET_QUEUE_STATS_STATUS_3_PN_31_0 + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_4_PN_63_32 + + Bits [63:32] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_5_PN_95_64 + + Bits [95:64] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_6_PN_127_96 + + Bits [127:96] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP + + Timestamp of arrival of the last MPDU for this queue + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP + + Timestamp of forwarding an MPDU + + + + If the queue is empty when a frame gets received, this + time shall be initialized to the 'enqueue' timestamp + + + + Used for aging + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f + +/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18 + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f + +/* Description REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT + + The number of duplicate frames that have been detected + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000 + +/* Description REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes received for + this queue. + + + + In 64 byte units + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +/* Description REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000 + +/* Description REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_GET_QUEUE_STATS_STATUS_H_ diff --git a/hw/qca8074/v1/reo_reg_seq_hwiobase.h b/hw/qca8074/v1/reo_reg_seq_hwiobase.h new file mode 100644 index 000000000000..2120cf611a2e --- /dev/null +++ b/hw/qca8074/v1/reo_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __REO_REG_SEQ_BASE_H__ +#define __REO_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/hw/qca8074/v1/reo_reg_seq_hwioreg.h b/hw/qca8074/v1/reo_reg_seq_hwioreg.h new file mode 100644 index 000000000000..263123e3a540 --- /dev/null +++ b/hw/qca8074/v1/reo_reg_seq_hwioreg.h @@ -0,0 +1,8639 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __REO_REG_SEQ_REG_H__ +#define __REO_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "reo_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block REO_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register REO_R0_GENERAL_ENABLE //// + +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) +#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) +#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0x1fffffff +#define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 +#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) +#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) +#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ + out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) +#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x10000000 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1c + +#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x0e000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x19 + +#define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK 0x01c00000 +#define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_SHFT 0x16 + +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00200000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x15 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00100000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x14 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00080000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x13 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00040000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x12 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00020000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x11 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00010000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x10 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00008000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0xf + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00004000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xe + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00002000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xd + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00001000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xc + +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000800 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xb + +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000700 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000080 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x7 + +#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 +#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 + +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 + +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x8 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffff00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1d + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x1c000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x1a + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x03800000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x17 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00700000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x000e0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0x11 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x0001c000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0xe + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00003800 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0xb + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000700 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x8 + +//// Register REO_R0_TIMESTAMP //// + +#define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) +#define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) +#define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_SHFT 0 +#define HWIO_REO_R0_TIMESTAMP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) +#define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) +#define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ + out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) +#define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 + +//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x3fffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT 0x1b + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_BMSK 0x07000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_SHFT 0x18 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x00e00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x15 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x001c0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x12 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00038000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0xf + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00007000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0xc + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00000e00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0x9 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x000001c0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x6 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000038 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x3 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 + +//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x0003ffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0xf + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x00007000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0xc + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00000e00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x9 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000001c0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x6 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00000038 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0x3 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000007 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x0 + +//// Register REO_R0_IDLE_REQ_CTRL //// + +#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) +#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) +#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 +#define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) +#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 + +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x) (x+0x0000008c) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_PHYS(x) (x+0x0000008c) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000090) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000090) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x) (x+0x00000098) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_PHYS(x) (x+0x00000098) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x) (x+0x0000009c) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_PHYS(x) (x+0x0000009c) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x) (x+0x000000e4) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_PHYS(x) (x+0x000000e4) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x) (x+0x000000e8) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_PHYS(x) (x+0x000000e8) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x) (x+0x000000f0) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_PHYS(x) (x+0x000000f0) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x) (x+0x000000f4) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_PHYS(x) (x+0x000000f4) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x) (x+0x00000134) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_PHYS(x) (x+0x00000134) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000013c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000013c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000140) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000140) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_ID //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000148) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000148) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_MISC //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000014c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000014c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000194) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000194) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000198) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000198) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_ID //// + +#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) +#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000001a0) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000001a0) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MISC //// + +#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000001a4) +#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000001a4) +#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x000001ec) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x000001ec) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x000001f0) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x000001f0) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_ID //// + +#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) +#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) +#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x000001f8) +#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x000001f8) +#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MISC //// + +#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x000001fc) +#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x000001fc) +#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_DATA //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x00000244) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x00000244) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x00000248) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x00000248) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_ID //// + +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x0000024c) +#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x0000024c) +#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x00000250) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x00000250) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MISC //// + +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x00000254) +#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x00000254) +#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x00000294) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x00000294) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x0000029c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x0000029c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x000002a0) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x000002a0) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_ID //// + +#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x000002a4) +#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x000002a4) +#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x000002a8) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x000002a8) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MISC //// + +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x000002ac) +#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x000002ac) +#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x000002f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x000002f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002f8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002f8) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_ID //// + +#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002fc) +#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002fc) +#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x00000300) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x00000300) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MISC //// + +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x00000304) +#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x00000304) +#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x00000344) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x00000344) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x0000034c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x0000034c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x00000350) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x00000350) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_ID //// + +#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x00000354) +#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x00000354) +#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000358) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000358) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MISC //// + +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x0000035c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x0000035c) +#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003a4) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003a4) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x000003a8) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x000003a8) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_ID //// + +#define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x000003ac) +#define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x000003ac) +#define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_STATUS //// + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x000003b0) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x000003b0) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MISC //// + +#define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x000003b4) +#define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x000003b4) +#define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x000003fc) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x000003fc) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000400) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000400) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_ID //// + +#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x00000404) +#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x00000404) +#define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) +#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_STATUS //// + +#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MISC //// + +#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x0000040c) +#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x0000040c) +#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000454) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000454) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000458) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000458) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_ID //// + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x0000045c) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x0000045c) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_STATUS //// + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x00000460) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x00000460) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_MISC //// + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x00000464) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x00000464) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x000004ac) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x000004ac) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x000004b0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x000004b0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_ID //// + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x000004b4) +#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x000004b4) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_STATUS //// + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x000004b8) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x000004b8) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MISC //// + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x000004bc) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x000004bc) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x0000003f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_WATCHDOG_TIMEOUT //// + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x00000504) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x00000504) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x0fff0fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ + out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_BMSK 0x0fff0000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_SHFT 0x10 + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 + +//// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000508) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000508) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_0 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x0000050c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x0000050c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_1 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000510) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000510) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_2 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x00000514) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x00000514) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_3 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000518) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000518) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x0000051c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x0000051c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000520) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000520) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x00000524) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x00000524) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000528) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000528) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x0000052c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x0000052c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000530) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000530) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x00000534) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x00000534) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000538) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000538) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x0000053c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x0000053c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000540) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000540) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x00000544) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x00000544) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x00000548) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x00000548) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x0000054c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x0000054c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x00000550) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x00000550) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x00000554) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x00000554) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x00000558) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x00000558) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x0000055c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x0000055c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x00000560) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x00000560) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x00000564) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x00000564) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x00000568) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x00000568) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_0 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x0000056c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x0000056c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_1 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x00000570) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x00000570) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_2 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x00000574) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x00000574) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_3 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x00000578) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x00000578) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_CONTROL //// + +#define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x0000057c) +#define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x0000057c) +#define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f +#define HWIO_REO_R0_AGING_CONTROL_SHFT 0 +#define HWIO_REO_R0_AGING_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) +#define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_HIGH_MEMORY_THRESHOLD //// + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x00000580) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x00000580) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ + out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_0 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x00000584) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x00000584) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_1 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x00000588) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x00000588) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_2 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x0000058c) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x0000058c) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_3 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x00000590) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x00000590) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x00000594) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x00000594) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x00000598) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x00000598) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x0000059c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x0000059c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005a0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005a0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x000005a4) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x000005a4) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x000005a8) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x000005a8) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x000005ac) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x000005ac) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x000005b0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x000005b0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x000005b4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x000005b4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x000005b8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x000005b8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x000005bc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x000005bc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x000005c0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x000005c0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x000005c4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x000005c4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x000005c8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x000005c8) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x000005cc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x000005cc) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x000005d0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x000005d0) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x000005d4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x000005d4) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 + +//// Register REO_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000005d8) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000005d8) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000005dc) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000005dc) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000005e0) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000005e0) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register REO_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000005e4) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000005e4) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000005e8) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000005e8) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000005ec) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000005ec) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000005f0) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000005f0) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000005f4) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000005f4) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000005f8) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000005f8) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000005fc) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000005fc) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000600) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000600) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000604) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000604) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000608) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000608) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONFIG //// + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x0000060c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x0000060c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0x003f7fff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00200000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x15 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00100000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x14 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00080000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x13 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00040000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x12 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00020000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x11 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00010000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x10 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x00007f00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x8 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000000ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONTROL //// + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x00000610) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x00000610) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000001 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 + +//// Register REO_R0_CLK_GATE_CTRL //// + +#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000614) +#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000614) +#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff +#define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 +#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) +#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_BMSK 0x00001000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_SHFT 0xc + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_BMSK 0x00000800 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_SHFT 0xb + +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_0 //// + +#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x00000618) +#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x00000618) +#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_1 //// + +#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x0000061c) +#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x0000061c) +#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_2 //// + +#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x00000620) +#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x00000620) +#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_3 //// + +#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x00000624) +#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x00000624) +#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 + +//// Register REO_R1_MISC_DEBUG_CTRL //// + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0x3fffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 + +//// Register REO_R1_MISC_PERF_DEBUG_CTRL //// + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000200 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0x9 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000100 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0x8 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000080 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x7 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x0000007f +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0x03ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0x03ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_STM //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_BMSK 0xff000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_SHFT 0x18 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_BMSK 0x00ff0000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_SHFT 0x10 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0000ff00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0x8 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000000ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x00002024) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x00002024) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R1_END_OF_TEST_CHECK //// + +#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002028) +#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002028) +#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R1_SM_ALL_IDLE //// + +#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x0000202c) +#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x0000202c) +#define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 +#define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 +#define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) +#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) +#define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) +#define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 + +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 + +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 + +//// Register REO_R1_TESTBUS_CTRL //// + +#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002030) +#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002030) +#define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f +#define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) +#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 + +//// Register REO_R1_TESTBUS_LOWER //// + +#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002034) +#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002034) +#define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 +#define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) +#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register REO_R1_TESTBUS_HIGHER //// + +#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002038) +#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002038) +#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff +#define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 +#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) +#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_0 //// + +#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x0000203c) +#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x0000203c) +#define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_1 //// + +#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002040) +#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002040) +#define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_2 //// + +#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x00002044) +#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x00002044) +#define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_3 //// + +#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002048) +#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002048) +#define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_4 //// + +#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x0000204c) +#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x0000204c) +#define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_5 //// + +#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002050) +#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002050) +#define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_6 //// + +#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 + +//// Register REO_R1_IDLE_STATES_IX_0 //// + +#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002058) +#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002058) +#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 +#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) +#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 + +//// Register REO_R1_INVALID_APB_ACCESS //// + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x0000205c) +#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x0000205c) +#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 +#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) +#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ + out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO0_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO0_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO1_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x) (x+0x00003008) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_PHYS(x) (x+0x00003008) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO1_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x) (x+0x0000300c) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_PHYS(x) (x+0x0000300c) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO2_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x) (x+0x00003010) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_PHYS(x) (x+0x00003010) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO2_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x) (x+0x00003014) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_PHYS(x) (x+0x00003014) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_WBM2REO_LINK_RING_HP //// + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_WBM2REO_LINK_RING_TP //// + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_CMD_RING_HP //// + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003020) +#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003020) +#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) +#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_CMD_RING_TP //// + +#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003024) +#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003024) +#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) +#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO_RING_HP //// + +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003028) +#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003028) +#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 +#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) +#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO_RING_TP //// + +#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000302c) +#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000302c) +#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 +#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) +#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW1_RING_HP //// + +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003030) +#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003030) +#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW1_RING_TP //// + +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x00003034) +#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x00003034) +#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW2_RING_HP //// + +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003038) +#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003038) +#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW2_RING_TP //// + +#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x0000303c) +#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x0000303c) +#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW3_RING_HP //// + +#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003040) +#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003040) +#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW3_RING_TP //// + +#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x00003044) +#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x00003044) +#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW4_RING_HP //// + +#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003048) +#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003048) +#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW4_RING_TP //// + +#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x0000304c) +#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x0000304c) +#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2TCL_RING_HP //// + +#define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003050) +#define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003050) +#define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) +#define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2TCL_RING_TP //// + +#define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x00003054) +#define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x00003054) +#define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) +#define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2FW_RING_HP //// + +#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003058) +#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003058) +#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) +#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2FW_RING_TP //// + +#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x0000305c) +#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x0000305c) +#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) +#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_RELEASE_RING_HP //// + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003060) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003060) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_RELEASE_RING_TP //// + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003064) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003064) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_STATUS_RING_HP //// + +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003068) +#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003068) +#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) +#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_STATUS_RING_TP //// + +#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x0000306c) +#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x0000306c) +#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) +#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/hw/qca8074/v1/rx_attention.h b/hw/qca8074/v1/rx_attention.h new file mode 100644 index 000000000000..bc5f09901acd --- /dev/null +++ b/hw/qca8074/v1/rx_attention.h @@ -0,0 +1,1168 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31] +// 2 flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t first_mpdu : 1, //[0] + reserved_1a : 1, //[1] + mcast_bcast : 1, //[2] + ast_index_not_found : 1, //[3] + ast_index_timeout : 1, //[4] + power_mgmt : 1, //[5] + non_qos : 1, //[6] + null_data : 1, //[7] + mgmt_type : 1, //[8] + ctrl_type : 1, //[9] + more_data : 1, //[10] + eosp : 1, //[11] + a_msdu_error : 1, //[12] + fragment_flag : 1, //[13] + order : 1, //[14] + cce_match : 1, //[15] + overflow_err : 1, //[16] + msdu_length_err : 1, //[17] + tcp_udp_chksum_fail : 1, //[18] + ip_chksum_fail : 1, //[19] + sa_idx_invalid : 1, //[20] + da_idx_invalid : 1, //[21] + reserved_1b : 1, //[22] + rx_in_tx_decrypt_byp : 1, //[23] + encrypt_required : 1, //[24] + directed : 1, //[25] + buffer_fragment : 1, //[26] + mpdu_length_err : 1, //[27] + tkip_mic_err : 1, //[28] + decrypt_err : 1, //[29] + unencrypted_frame_err : 1, //[30] + fcs_err : 1; //[31] + uint32_t flow_idx_timeout : 1, //[0] + flow_idx_invalid : 1, //[1] + wifi_parser_error : 1, //[2] + amsdu_parser_error : 1, //[3] + sa_idx_timeout : 1, //[4] + da_idx_timeout : 1, //[5] + msdu_limit_error : 1, //[6] + da_is_valid : 1, //[7] + da_is_mcbc : 1, //[8] + sa_is_valid : 1, //[9] + decrypt_status_code : 3, //[12:10] + rx_bitmap_not_updated : 1, //[13] + reserved_2 : 17, //[30:14] + msdu_done : 1; //[31] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +first_mpdu + + Indicates the first MSDU of the PPDU. If both + first_mpdu and last_mpdu are set in the MSDU then this is a + not an A-MPDU frame but a stand alone MPDU. Interior MPDU + in an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. + +reserved_1a + + + +mcast_bcast + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when + first_msdu is set. + +ast_index_not_found + + Only valid when first_msdu is set. + + + + Indicates no AST matching entries within the the max + search count. + +ast_index_timeout + + Only valid when first_msdu is set. + + + + Indicates an unsuccessful search in the address seach + table due to timeout. + +power_mgmt + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. + +non_qos + + Set if packet is not a non-QoS data frame. Only set + when first_msdu is set. + +null_data + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. + +mgmt_type + + Set if packet is a management packet. Only set when + first_msdu is set. + +ctrl_type + + Set if packet is a control packet. Only set when + first_msdu is set. + +more_data + + Set if more bit in frame control is set. Only set when + first_msdu is set. + +eosp + + Set if the EOSP (end of service period) bit in the QoS + control field is set. Only set when first_msdu is set. + +a_msdu_error + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this MPDU + without decapsulation. + +fragment_flag + + Indicates that this is an 802.11 fragment frame. This + is set when either the more_frag bit is set in the frame + control or the fragment number is not zero. Only set when + first_msdu is set. + +order + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. + +cce_match + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. + +overflow_err + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time + +msdu_length_err + + Indicates that the MSDU length from the 802.3 + encapsulated length field extends beyond the MPDU boundary + or if the length is less than 14 bytes. + + Merged with original other_msdu_err: Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated but + will be DMA'ed in RAW format as a single MSDU buffer + +tcp_udp_chksum_fail + + Indicates that the computed checksum (tcp_udp_chksum) + did not match the checksum in the TCP/UDP header. + +ip_chksum_fail + + Indicates that the computed checksum did not match the + checksum in the IP header. + +sa_idx_invalid + + Indicates no matching entry was found in the address + search table for the source MAC address. + +da_idx_invalid + + Indicates no matching entry was found in the address + search table for the destination MAC address. + +reserved_1b + + +rx_in_tx_decrypt_byp + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. + +encrypt_required + + Indicates that this data type frame is not encrypted + even if the policy for this MPDU requires encryption as + indicated in the peer entry key type. + +directed + + MPDU is a directed packet which means that the RA + matched our STA addresses. In proxySTA it means that the TA + matched an entry in our address search table with the + corresponding no_ack bit is the address search entry + cleared. + +buffer_fragment + + Indicates that at least one of the rx buffers has been + fragmented. If set the FW should look at the rx_frag_info + descriptor described below. + +mpdu_length_err + + Indicates that the MPDU was pre-maturely terminated + resulting in a truncated MPDU. Don't trust the MPDU length + field. + +tkip_mic_err + + Indicates that the MPDU Michael integrity check failed + +decrypt_err + + Indicates that the MPDU decrypt integrity check failed + +unencrypted_frame_err + + Copied here by RX OLE from the RX_MPDU_END TLV + +fcs_err + + Indicates that the MPDU FCS check failed + +flow_idx_timeout + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + + +flow_idx_invalid + + flow id is not valid + + + +wifi_parser_error + + TODO: add details to the description + + + +amsdu_parser_error + + A-MSDU could not be properly de-agregated. + + + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. + +msdu_limit_error + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decasulated but will be DMA'ed in RAW format as a single + MSDU buffer + +da_is_valid + + Indicates that OLE found a valid DA entry + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. + +sa_is_valid + + Indicates that OLE found a valid SA entry + +decrypt_status_code + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + + +rx_bitmap_not_updated + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + + +reserved_2 + + + +msdu_done + + If set indicates that the RX packet data, RX header + data, RX PPDU start descriptor, RX MPDU start/end + descriptor, RX MSDU start/end descriptors and RX Attention + descriptor are all valid. This bit must be in the last + octet of the descriptor. +*/ + + +/* Description RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_ATTENTION_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_ATTENTION_0_RESERVED_0 + + +*/ +#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_0_RESERVED_0_LSB 9 +#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_ATTENTION_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_ATTENTION_1_FIRST_MPDU + + Indicates the first MSDU of the PPDU. If both + first_mpdu and last_mpdu are set in the MSDU then this is a + not an A-MPDU frame but a stand alone MPDU. Interior MPDU + in an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. +*/ +#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_1_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 + +/* Description RX_ATTENTION_1_RESERVED_1A + + +*/ +#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1A_LSB 1 +#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 + +/* Description RX_ATTENTION_1_MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_1_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 + +/* Description RX_ATTENTION_1_AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + + + Indicates no AST matching entries within the the max + search count. +*/ +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +/* Description RX_ATTENTION_1_AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + + + Indicates an unsuccessful search in the address seach + table due to timeout. +*/ +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 + +/* Description RX_ATTENTION_1_POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ +#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_1_POWER_MGMT_LSB 5 +#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 + +/* Description RX_ATTENTION_1_NON_QOS + + Set if packet is not a non-QoS data frame. Only set + when first_msdu is set. +*/ +#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_1_NON_QOS_LSB 6 +#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 + +/* Description RX_ATTENTION_1_NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ +#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_NULL_DATA_LSB 7 +#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 + +/* Description RX_ATTENTION_1_MGMT_TYPE + + Set if packet is a management packet. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 + +/* Description RX_ATTENTION_1_CTRL_TYPE + + Set if packet is a control packet. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 + +/* Description RX_ATTENTION_1_MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_MORE_DATA_LSB 10 +#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 + +/* Description RX_ATTENTION_1_EOSP + + Set if the EOSP (end of service period) bit in the QoS + control field is set. Only set when first_msdu is set. +*/ +#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_1_EOSP_LSB 11 +#define RX_ATTENTION_1_EOSP_MASK 0x00000800 + +/* Description RX_ATTENTION_1_A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this MPDU + without decapsulation. +*/ +#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 + +/* Description RX_ATTENTION_1_FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This + is set when either the more_frag bit is set in the frame + control or the fragment number is not zero. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 + +/* Description RX_ATTENTION_1_ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ +#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_1_ORDER_LSB 14 +#define RX_ATTENTION_1_ORDER_MASK 0x00004000 + +/* Description RX_ATTENTION_1_CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ +#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_1_CCE_MATCH_LSB 15 +#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 + +/* Description RX_ATTENTION_1_OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time +*/ +#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 + +/* Description RX_ATTENTION_1_MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 + encapsulated length field extends beyond the MPDU boundary + or if the length is less than 14 bytes. + + Merged with original other_msdu_err: Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated but + will be DMA'ed in RAW format as a single MSDU buffer +*/ +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 + +/* Description RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum) + did not match the checksum in the TCP/UDP header. +*/ +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +/* Description RX_ATTENTION_1_IP_CHKSUM_FAIL + + Indicates that the computed checksum did not match the + checksum in the IP header. +*/ +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 + +/* Description RX_ATTENTION_1_SA_IDX_INVALID + + Indicates no matching entry was found in the address + search table for the source MAC address. +*/ +#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 + +/* Description RX_ATTENTION_1_DA_IDX_INVALID + + Indicates no matching entry was found in the address + search table for the destination MAC address. +*/ +#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 + +/* Description RX_ATTENTION_1_RESERVED_1B + +*/ +#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1B_LSB 22 +#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 + +/* Description RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. +*/ +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +/* Description RX_ATTENTION_1_ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted + even if the policy for this MPDU requires encryption as + indicated in the peer entry key type. +*/ +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 + +/* Description RX_ATTENTION_1_DIRECTED + + MPDU is a directed packet which means that the RA + matched our STA addresses. In proxySTA it means that the TA + matched an entry in our address search table with the + corresponding no_ack bit is the address search entry + cleared. +*/ +#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_1_DIRECTED_LSB 25 +#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 + +/* Description RX_ATTENTION_1_BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been + fragmented. If set the FW should look at the rx_frag_info + descriptor described below. +*/ +#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 + +/* Description RX_ATTENTION_1_MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated + resulting in a truncated MPDU. Don't trust the MPDU length + field. +*/ +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 + +/* Description RX_ATTENTION_1_TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ +#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 + +/* Description RX_ATTENTION_1_DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed +*/ +#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 + +/* Description RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +/* Description RX_ATTENTION_1_FCS_ERR + + Indicates that the MPDU FCS check failed +*/ +#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_FCS_ERR_LSB 31 +#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 + +/* Description RX_ATTENTION_2_FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + +*/ +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +/* Description RX_ATTENTION_2_FLOW_IDX_INVALID + + flow id is not valid + + +*/ +#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 + +/* Description RX_ATTENTION_2_WIFI_PARSER_ERROR + + TODO: add details to the description + + +*/ +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 + +/* Description RX_ATTENTION_2_AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + + +*/ +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 + +/* Description RX_ATTENTION_2_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 + +/* Description RX_ATTENTION_2_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 + +/* Description RX_ATTENTION_2_MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decasulated but will be DMA'ed in RAW format as a single + MSDU buffer +*/ +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 + +/* Description RX_ATTENTION_2_DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ +#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 + +/* Description RX_ATTENTION_2_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. +*/ +#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 + +/* Description RX_ATTENTION_2_SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ +#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 + +/* Description RX_ATTENTION_2_DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + +*/ +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +/* Description RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + +*/ +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +/* Description RX_ATTENTION_2_RESERVED_2 + + +*/ +#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_2_RESERVED_2_LSB 14 +#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 + +/* Description RX_ATTENTION_2_MSDU_DONE + + If set indicates that the RX packet data, RX header + data, RX PPDU start descriptor, RX MPDU start/end + descriptor, RX MSDU start/end descriptors and RX Attention + descriptor are all valid. This bit must be in the last + octet of the descriptor. +*/ +#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_DONE_LSB 31 +#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 + + +#endif // _RX_ATTENTION_H_ diff --git a/hw/qca8074/v1/rx_mpdu_desc_info.h b/hw/qca8074/v1/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..bb9cfdeee1fc --- /dev/null +++ b/hw/qca8074/v1/rx_mpdu_desc_info.h @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], reserved[31] +// 1 peer_meta_data[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { + uint32_t msdu_count : 8, //[7:0] + mpdu_sequence_number : 12, //[19:8] + fragment_flag : 1, //[20] + mpdu_retry_bit : 1, //[21] + ampdu_flag : 1, //[22] + bar_frame : 1, //[23] + pn_fields_contain_valid_info : 1, //[24] + sa_is_valid : 1, //[25] + sa_idx_timeout : 1, //[26] + da_is_valid : 1, //[27] + da_is_mcbc : 1, //[28] + da_idx_timeout : 1, //[29] + raw_mpdu : 1, //[30] + reserved : 1; //[31] + uint32_t peer_meta_data : 32; //[31:0] +}; + +/* + +msdu_count + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + + +mpdu_sequence_number + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + + +fragment_flag + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + + +mpdu_retry_bit + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + + +ampdu_flag + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + + +bar_frame + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + + +pn_fields_contain_valid_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check + +sa_is_valid + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + + +sa_idx_timeout + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + + +da_is_valid + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + + +da_idx_timeout + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + + +raw_mpdu + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + + +reserved + + + +peer_meta_data + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ + + +/* Description RX_MPDU_DESC_INFO_0_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff + +/* Description RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description RX_MPDU_DESC_INFO_0_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000 + +/* Description RX_MPDU_DESC_INFO_0_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000 + +/* Description RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description RX_MPDU_DESC_INFO_0_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000 + +/* Description RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description RX_MPDU_DESC_INFO_0_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000 + +/* Description RX_MPDU_DESC_INFO_0_RESERVED + + +*/ +#define RX_MPDU_DESC_INFO_0_RESERVED_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RESERVED_LSB 31 +#define RX_MPDU_DESC_INFO_0_RESERVED_MASK 0x80000000 + +/* Description RX_MPDU_DESC_INFO_1_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff + + +#endif // _RX_MPDU_DESC_INFO_H_ diff --git a/hw/qca8074/v1/rx_mpdu_details.h b/hw/qca8074/v1/rx_mpdu_details.h new file mode 100644 index 000000000000..279420a43f1c --- /dev/null +++ b/hw/qca8074/v1/rx_mpdu_details.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info msdu_link_desc_addr_info; +// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +}; + +/* + +struct buffer_addr_info msdu_link_desc_addr_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Details of the physical address of the MSDU link + descriptor that contains pointers to MSDUs related to this + MPDU + +struct rx_mpdu_desc_info rx_mpdu_desc_info_details + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + General information related to the MPDU that should be +*/ + +#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff + + +#endif // _RX_MPDU_DETAILS_H_ diff --git a/hw/qca8074/v1/rx_mpdu_end.h b/hw/qca8074/v1/rx_mpdu_end.h new file mode 100644 index 000000000000..924c06be2680 --- /dev/null +++ b/hw/qca8074/v1/rx_mpdu_end.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t reserved_1a : 11, //[10:0] + unsup_ktype_short_frame : 1, //[11] + rx_in_tx_decrypt_byp : 1, //[12] + overflow_err : 1, //[13] + mpdu_length_err : 1, //[14] + tkip_mic_err : 1, //[15] + decrypt_err : 1, //[16] + unencrypted_frame_err : 1, //[17] + pn_fields_contain_valid_info : 1, //[18] + fcs_err : 1, //[19] + msdu_length_err : 1, //[20] + rxdma0_destination_ring : 2, //[22:21] + rxdma1_destination_ring : 2, //[24:23] + decrypt_status_code : 3, //[27:25] + rx_bitmap_not_updated : 1, //[28] + reserved_1b : 3; //[31:29] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +reserved_1a + + + +unsup_ktype_short_frame + + This bit will be '1' when WEP or TKIP or WAPI key type + is received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. + +rx_in_tx_decrypt_byp + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. + +overflow_err + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time + +mpdu_length_err + + Set by RXPCU if the expected MPDU length does not + correspond with the actually received number of bytes in the + MPDU. + +tkip_mic_err + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error + for this MPDU + +decrypt_err + + Set by RX CRYPTO when CRYPTO detected a decrypt error + for this MPDU. + +unencrypted_frame_err + + Set by RX CRYPTO when CRYPTO detected an unencrypted + frame while in the peer entry field + 'All_frames_shall_be_encrypted' is set. + +pn_fields_contain_valid_info + + Set by RX CRYPTO to indicate that there is a valid PN + field present in this MPDU + +fcs_err + + Set by RXPCU when there is an FCS error detected for + this MPDU + +msdu_length_err + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU + +rxdma0_destination_ring + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + + + RXDMA0 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA0 shall push the frame to + the FW ring + + + + RXDMA0 shall push the frame to + the SW ring + + + + RXDMA0 shall push the frame + to the REO entrance ring + + + + + +rxdma1_destination_ring + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + + + RXDMA1 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA1 shall push the frame to + the FW ring + + + + RXDMA1 shall push the frame to + the SW ring + + + + RXDMA1 shall push the frame + to the REO entrance ring + + + + + +decrypt_status_code + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + + +rx_bitmap_not_updated + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + + +reserved_1b + + +*/ + + +/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_END_0_RESERVED_0 + + +*/ +#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_0_RESERVED_0_LSB 9 +#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MPDU_END_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_END_1_RESERVED_1A + + +*/ +#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1A_LSB 0 +#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff + +/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME + + This bit will be '1' when WEP or TKIP or WAPI key type + is received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. +*/ +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. +*/ +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +/* Description RX_MPDU_END_1_OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time +*/ +#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 + +/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR + + Set by RXPCU if the expected MPDU length does not + correspond with the actually received number of bytes in the + MPDU. +*/ +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 + +/* Description RX_MPDU_END_1_TKIP_MIC_ERR + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error + for this MPDU +*/ +#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 + +/* Description RX_MPDU_END_1_DECRYPT_ERR + + Set by RX CRYPTO when CRYPTO detected a decrypt error + for this MPDU. +*/ +#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 + +/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR + + Set by RX CRYPTO when CRYPTO detected an unencrypted + frame while in the peer entry field + 'All_frames_shall_be_encrypted' is set. +*/ +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO + + Set by RX CRYPTO to indicate that there is a valid PN + field present in this MPDU +*/ +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +/* Description RX_MPDU_END_1_FCS_ERR + + Set by RXPCU when there is an FCS error detected for + this MPDU +*/ +#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_FCS_ERR_LSB 19 +#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 + +/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU +*/ +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 + +/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + + + RXDMA0 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA0 shall push the frame to + the FW ring + + + + RXDMA0 shall push the frame to + the SW ring + + + + RXDMA0 shall push the frame + to the REO entrance ring + + + + +*/ +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 + +/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + + + RXDMA1 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA1 shall push the frame to + the FW ring + + + + RXDMA1 shall push the frame to + the SW ring + + + + RXDMA1 shall push the frame + to the REO entrance ring + + + + +*/ +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 + +/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + +*/ +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 + +/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + +*/ +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 + +/* Description RX_MPDU_END_1_RESERVED_1B + + +*/ +#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1B_LSB 29 +#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 + + +#endif // _RX_MPDU_END_H_ diff --git a/hw/qca8074/v1/rx_mpdu_info.h b/hw/qca8074/v1/rx_mpdu_info.h new file mode 100644 index 000000000000..de155604a27c --- /dev/null +++ b/hw/qca8074/v1/rx_mpdu_info.h @@ -0,0 +1,2871 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] +// 1 ast_index[15:0], sw_peer_id[31:16] +// 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] +// 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], mesh_sta[6], bssid_hit[7], bssid_number[11:8], tid[15:12], reserved_3a[31:16] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8 peer_meta_data[31:0] +// 9 struct rxpt_classify_info rxpt_classify_info_details; +// 10 rx_reo_queue_desc_addr_31_0[31:0] +// 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] +// 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] +// 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30] +// 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] +// 15 mac_addr_ad1_31_0[31:0] +// 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] +// 17 mac_addr_ad2_47_16[31:0] +// 18 mac_addr_ad3_31_0[31:0] +// 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] +// 20 mac_addr_ad4_31_0[31:0] +// 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] +// 22 mpdu_ht_control_field[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_INFO 23 + +struct rx_mpdu_info { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + ndp_frame : 1, //[9] + phy_err : 1, //[10] + phy_err_during_mpdu_header : 1, //[11] + protocol_version_err : 1, //[12] + ast_based_lookup_valid : 1, //[13] + reserved_0a : 2, //[15:14] + phy_ppdu_id : 16; //[31:16] + uint32_t ast_index : 16, //[15:0] + sw_peer_id : 16; //[31:16] + uint32_t mpdu_frame_control_valid : 1, //[0] + mpdu_duration_valid : 1, //[1] + mac_addr_ad1_valid : 1, //[2] + mac_addr_ad2_valid : 1, //[3] + mac_addr_ad3_valid : 1, //[4] + mac_addr_ad4_valid : 1, //[5] + mpdu_sequence_control_valid : 1, //[6] + mpdu_qos_control_valid : 1, //[7] + mpdu_ht_control_valid : 1, //[8] + frame_encryption_info_valid : 1, //[9] + reserved_2a : 6, //[15:10] + fr_ds : 1, //[16] + to_ds : 1, //[17] + encrypted : 1, //[18] + mpdu_retry : 1, //[19] + mpdu_sequence_number : 12; //[31:20] + uint32_t epd_en : 1, //[0] + all_frames_shall_be_encrypted : 1, //[1] + encrypt_type : 4, //[5:2] + mesh_sta : 1, //[6] + bssid_hit : 1, //[7] + bssid_number : 4, //[11:8] + tid : 4, //[15:12] + reserved_3a : 16; //[31:16] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t peer_meta_data : 32; //[31:0] + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + receive_queue_number : 16, //[23:8] + pre_delim_err_warning : 1, //[24] + first_delim_err : 1, //[25] + reserved_11 : 6; //[31:26] + uint32_t key_id_octet : 8, //[7:0] + new_peer_entry : 1, //[8] + decrypt_needed : 1, //[9] + decap_type : 2, //[11:10] + rx_insert_vlan_c_tag_padding : 1, //[12] + rx_insert_vlan_s_tag_padding : 1, //[13] + strip_vlan_c_tag_decap : 1, //[14] + strip_vlan_s_tag_decap : 1, //[15] + pre_delim_count : 12, //[27:16] + ampdu_flag : 1, //[28] + bar_frame : 1, //[29] + reserved_12 : 2; //[31:30] + uint32_t mpdu_length : 14, //[13:0] + first_mpdu : 1, //[14] + mcast_bcast : 1, //[15] + ast_index_not_found : 1, //[16] + ast_index_timeout : 1, //[17] + power_mgmt : 1, //[18] + non_qos : 1, //[19] + null_data : 1, //[20] + mgmt_type : 1, //[21] + ctrl_type : 1, //[22] + more_data : 1, //[23] + eosp : 1, //[24] + fragment_flag : 1, //[25] + order : 1, //[26] + u_apsd_trigger : 1, //[27] + encrypt_required : 1, //[28] + directed : 1, //[29] + reserved_13 : 2; //[31:30] + uint32_t mpdu_frame_control_field : 16, //[15:0] + mpdu_duration_field : 16; //[31:16] + uint32_t mac_addr_ad1_31_0 : 32; //[31:0] + uint32_t mac_addr_ad1_47_32 : 16, //[15:0] + mac_addr_ad2_15_0 : 16; //[31:16] + uint32_t mac_addr_ad2_47_16 : 32; //[31:0] + uint32_t mac_addr_ad3_31_0 : 32; //[31:0] + uint32_t mac_addr_ad3_47_32 : 16, //[15:0] + mpdu_sequence_control_field : 16; //[31:16] + uint32_t mac_addr_ad4_31_0 : 32; //[31:0] + uint32_t mac_addr_ad4_47_32 : 16, //[15:0] + mpdu_qos_control_field : 16; //[31:16] + uint32_t mpdu_ht_control_field : 32; //[31:0] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + + +ndp_frame + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + + +phy_err + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + + +phy_err_during_mpdu_header + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + + +protocol_version_err + + Set when RXPCU detected a version error in the Frame + control field + + + +ast_based_lookup_valid + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + + +reserved_0a + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +ast_index + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + + +sw_peer_id + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + + +mpdu_frame_control_valid + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + + +mpdu_duration_valid + + When set, the field Mpdu_duration_field has valid + information + + + + + + +mac_addr_ad1_valid + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + + +mac_addr_ad2_valid + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + + +mac_addr_ad3_valid + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + + +mac_addr_ad4_valid + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + + +mpdu_sequence_control_valid + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + + +mpdu_qos_control_valid + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + + +mpdu_ht_control_valid + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + + +frame_encryption_info_valid + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + + +reserved_2a + + + +fr_ds + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + + +to_ds + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + + +encrypted + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + + +mpdu_retry + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + + +mpdu_sequence_number + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + + +epd_en + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + + +all_frames_shall_be_encrypted + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + + +encrypt_type + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + + + +mesh_sta + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA + + + +bssid_hit + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + + +bssid_number + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + + +tid + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + + +reserved_3a + + + +pn_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + + +pn_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + + +pn_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + + +pn_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + + +peer_meta_data + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + + +struct rxpt_classify_info rxpt_classify_info_details + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + RXOLE related classification info + + + +rx_reo_queue_desc_addr_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + + +receive_queue_number + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + + +pre_delim_err_warning + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + + +first_delim_err + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + + +reserved_11 + + + +key_id_octet + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + +new_peer_entry + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + + +decrypt_needed + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + + +decap_type + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or + 802.3 (uses SNAP/LLC) + + + +rx_insert_vlan_c_tag_padding + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + + +rx_insert_vlan_s_tag_padding + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + + +strip_vlan_c_tag_decap + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + + +strip_vlan_s_tag_decap + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + + +pre_delim_count + + The number of delimiters before this MPDU. + + + + In case of ndp or phy_err, this field will be set to 0 + +ampdu_flag + + When set, received frame was part of an A-MPDU. + + + + + + +bar_frame + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + + +reserved_12 + + . + +mpdu_length + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + + +first_mpdu + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + + +mcast_bcast + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ast_index_not_found + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ast_index_timeout + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +power_mgmt + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +non_qos + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + + +null_data + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +mgmt_type + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ctrl_type + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +more_data + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +eosp + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +fragment_flag + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +order + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + + +u_apsd_trigger + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +encrypt_required + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +directed + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +reserved_13 + + + +mpdu_frame_control_field + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + + +mpdu_duration_field + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + + +mac_addr_ad1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + + +mac_addr_ad1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + + +mac_addr_ad2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + + +mac_addr_ad2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + + +mac_addr_ad3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + + +mac_addr_ad3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + + +mpdu_sequence_control_field + + + + + The sequence control field of the MPDU + + + +mac_addr_ad4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + + +mac_addr_ad4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + + +mpdu_qos_control_field + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + + +mpdu_ht_control_field + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ + + +/* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + +*/ +#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + +*/ +#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_INFO_0_NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + +*/ +#define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 + +/* Description RX_MPDU_INFO_0_PHY_ERR + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + +*/ +#define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 + +/* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + +*/ +#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +/* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame + control field + + +*/ +#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +/* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + +*/ +#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +/* Description RX_MPDU_INFO_0_RESERVED_0A + + +*/ +#define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 +#define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 + +/* Description RX_MPDU_INFO_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_1_AST_INDEX + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + +*/ +#define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_1_SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + +*/ +#define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +/* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid + information + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +/* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +/* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +/* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +/* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +/* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + +*/ +#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +/* Description RX_MPDU_INFO_2_RESERVED_2A + + +*/ +#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RESERVED_2A_LSB 10 +#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x0000fc00 + +/* Description RX_MPDU_INFO_2_FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + +*/ +#define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FR_DS_LSB 16 +#define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 + +/* Description RX_MPDU_INFO_2_TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + +*/ +#define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_TO_DS_LSB 17 +#define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 + +/* Description RX_MPDU_INFO_2_ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + +*/ +#define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 + +/* Description RX_MPDU_INFO_2_MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + +*/ +#define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 + +/* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + +*/ +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +/* Description RX_MPDU_INFO_3_EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + +*/ +#define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_EPD_EN_LSB 0 +#define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 + +/* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + +*/ +#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +/* Description RX_MPDU_INFO_3_ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + + +*/ +#define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c + +/* Description RX_MPDU_INFO_3_MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA + + +*/ +#define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_MESH_STA_LSB 6 +#define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000040 + +/* Description RX_MPDU_INFO_3_BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + +*/ +#define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_BSSID_HIT_LSB 7 +#define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000080 + +/* Description RX_MPDU_INFO_3_BSSID_NUMBER + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + +*/ +#define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 8 +#define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00000f00 + +/* Description RX_MPDU_INFO_3_TID + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + +*/ +#define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_TID_LSB 12 +#define RX_MPDU_INFO_3_TID_MASK 0x0000f000 + +/* Description RX_MPDU_INFO_3_RESERVED_3A + + +*/ +#define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_RESERVED_3A_LSB 16 +#define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_4_PN_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + +*/ +#define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_INFO_4_PN_31_0_LSB 0 +#define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_5_PN_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_INFO_5_PN_63_32_LSB 0 +#define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff + +/* Description RX_MPDU_INFO_6_PN_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_INFO_6_PN_95_64_LSB 0 +#define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff + +/* Description RX_MPDU_INFO_7_PN_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_PN_127_96_LSB 0 +#define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff + +/* Description RX_MPDU_INFO_8_PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff +#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 +#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff + +/* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (lower 32 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +/* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + +*/ +#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +/* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + +*/ +#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 + +/* Description RX_MPDU_INFO_11_RESERVED_11 + + +*/ +#define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RESERVED_11_LSB 26 +#define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 + +/* Description RX_MPDU_INFO_12_KEY_ID_OCTET + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + +*/ +#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + +*/ +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 + +/* Description RX_MPDU_INFO_12_DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + +*/ +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 + +/* Description RX_MPDU_INFO_12_DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or + 802.3 (uses SNAP/LLC) + + +*/ +#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 + +/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + +*/ +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + +*/ +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +/* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + +*/ +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +/* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + +*/ +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +/* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + + + In case of ndp or phy_err, this field will be set to 0 +*/ +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 + +/* Description RX_MPDU_INFO_12_AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + + + + +*/ +#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 + +/* Description RX_MPDU_INFO_12_BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + +*/ +#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 + +/* Description RX_MPDU_INFO_12_RESERVED_12 + + . +*/ +#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RESERVED_12_LSB 30 +#define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 + +/* Description RX_MPDU_INFO_13_MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + +*/ +#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff + +/* Description RX_MPDU_INFO_13_FIRST_MPDU + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + +*/ +#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 + +/* Description RX_MPDU_INFO_13_MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 + +/* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +/* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MPDU_INFO_13_POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 + +/* Description RX_MPDU_INFO_13_NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NON_QOS_LSB 19 +#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 + +/* Description RX_MPDU_INFO_13_NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 + +/* Description RX_MPDU_INFO_13_MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 + +/* Description RX_MPDU_INFO_13_CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 + +/* Description RX_MPDU_INFO_13_MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 + +/* Description RX_MPDU_INFO_13_EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_EOSP_LSB 24 +#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 + +/* Description RX_MPDU_INFO_13_FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 + +/* Description RX_MPDU_INFO_13_ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + +*/ +#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ORDER_LSB 26 +#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 + +/* Description RX_MPDU_INFO_13_U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 + +/* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 + +/* Description RX_MPDU_INFO_13_DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_DIRECTED_LSB 29 +#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 + +/* Description RX_MPDU_INFO_13_RESERVED_13 + + +*/ +#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_RESERVED_13_LSB 30 +#define RX_MPDU_INFO_13_RESERVED_13_MASK 0xc0000000 + +/* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + +*/ +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + +*/ +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +/* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD + + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + +#endif // _RX_MPDU_INFO_H_ diff --git a/hw/qca8074/v1/rx_mpdu_link_ptr.h b/hw/qca8074/v1/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..afd9d7bfeb0d --- /dev/null +++ b/hw/qca8074/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info mpdu_link_desc_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { + struct buffer_addr_info mpdu_link_desc_addr_info; +}; + +/* + +struct buffer_addr_info mpdu_link_desc_addr_info + + Details of the physical address of an MPDU link + descriptor +*/ + +#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff + + +#endif // _RX_MPDU_LINK_PTR_H_ diff --git a/hw/qca8074/v1/rx_mpdu_start.h b/hw/qca8074/v1/rx_mpdu_start.h new file mode 100644 index 000000000000..be5ddfcdc47b --- /dev/null +++ b/hw/qca8074/v1/rx_mpdu_start.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-22 struct rx_mpdu_info rx_mpdu_info_details; +// 23 raw_mpdu[0], reserved_23[31:1] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_START 24 + +struct rx_mpdu_start { + struct rx_mpdu_info rx_mpdu_info_details; + uint32_t raw_mpdu : 1, //[0] + reserved_23 : 31; //[31:1] +}; + +/* + +struct rx_mpdu_info rx_mpdu_info_details + + Structure containing all the MPDU header details that + might be needed for other modules further down the received + path + +raw_mpdu + + Set by OLE when it has not performed any .11 to .3 + header conversion on this MPDU. + + + +reserved_23 + + +*/ + +#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000004 +#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000000c +#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000010 +#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000014 +#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000018 +#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000020 +#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000003c +#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000044 +#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000048 +#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000050 +#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff +#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000058 +#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1 +#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff + +/* Description RX_MPDU_START_23_RAW_MPDU + + Set by OLE when it has not performed any .11 to .3 + header conversion on this MPDU. + + +*/ +#define RX_MPDU_START_23_RAW_MPDU_OFFSET 0x0000005c +#define RX_MPDU_START_23_RAW_MPDU_LSB 0 +#define RX_MPDU_START_23_RAW_MPDU_MASK 0x00000001 + +/* Description RX_MPDU_START_23_RESERVED_23 + + +*/ +#define RX_MPDU_START_23_RESERVED_23_OFFSET 0x0000005c +#define RX_MPDU_START_23_RESERVED_23_LSB 1 +#define RX_MPDU_START_23_RESERVED_23_MASK 0xfffffffe + + +#endif // _RX_MPDU_START_H_ diff --git a/hw/qca8074/v1/rx_msdu_desc_info.h b/hw/qca8074/v1/rx_msdu_desc_info.h new file mode 100644 index 000000000000..1a05ac150c19 --- /dev/null +++ b/hw/qca8074/v1/rx_msdu_desc_info.h @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], reserved_0a[31:28] +// 1 reserved_1a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 + +struct rx_msdu_desc_info { + uint32_t first_msdu_in_mpdu_flag : 1, //[0] + last_msdu_in_mpdu_flag : 1, //[1] + msdu_continuation : 1, //[2] + msdu_length : 14, //[16:3] + reo_destination_indication : 5, //[21:17] + msdu_drop : 1, //[22] + sa_is_valid : 1, //[23] + sa_idx_timeout : 1, //[24] + da_is_valid : 1, //[25] + da_is_mcbc : 1, //[26] + da_idx_timeout : 1, //[27] + reserved_0a : 4; //[31:28] + uint32_t reserved_1a : 32; //[31:0] +}; + +/* + +first_msdu_in_mpdu_flag + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + +last_msdu_in_mpdu_flag + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + +msdu_continuation + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + + +msdu_length + + Field is only valid in combination with the + 'first_msdu_in_mpdu_flag ' being set. When the + 'first_msdu_in_mpdu_flag ' is not set, this field shall be + 0. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +msdu_drop + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + + +sa_is_valid + + Indicates that OLE found a valid SA entry for this MSDU + + + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + + +da_is_valid + + Indicates that OLE found a valid DA entry for this MSDU + + + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + + +reserved_0a + + + +reserved_1a + + +*/ + + +/* Description RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. +*/ +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + +*/ +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_LENGTH + + Field is only valid in combination with the + 'first_msdu_in_mpdu_flag ' being set. When the + 'first_msdu_in_mpdu_flag ' is not set, this field shall be + 0. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_DESC_INFO_0_SA_IS_VALID + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IS_VALID + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_DESC_INFO_0_RESERVED_0A + + +*/ +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_LSB 28 +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_DESC_INFO_1_RESERVED_1A + + +*/ +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_LSB 0 +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_MASK 0xffffffff + + +#endif // _RX_MSDU_DESC_INFO_H_ diff --git a/hw/qca8074/v1/rx_msdu_details.h b/hw/qca8074/v1/rx_msdu_details.h new file mode 100644 index 000000000000..02e52e2d4ed4 --- /dev/null +++ b/hw/qca8074/v1/rx_msdu_details.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_msdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buffer_addr_info_details; +// 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; +}; + +/* + +struct buffer_addr_info buffer_addr_info_details + + Consumer: REO/SW + + Producer: RXDMA + + + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) + +struct rx_msdu_desc_info rx_msdu_desc_info_details + + Consumer: REO/SW + + Producer: RXDMA + + + + General information related to the MSDU that should be + passed on from RXDMA all the way to to the REO destination + ring. +*/ + +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff + + +#endif // _RX_MSDU_DETAILS_H_ diff --git a/hw/qca8074/v1/rx_msdu_end.h b/hw/qca8074/v1/rx_msdu_end.h new file mode 100644 index 000000000000..6a148102f5d3 --- /dev/null +++ b/hw/qca8074/v1/rx_msdu_end.h @@ -0,0 +1,1238 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 ip_hdr_chksum[15:0], tcp_udp_chksum[31:16] +// 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] +// 3 ext_wapi_pn_95_64[31:0] +// 4 ext_wapi_pn_127_96[31:0] +// 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], reserved_5a[31:26] +// 6 ipv6_options_crc[31:0] +// 7 tcp_seq_number[31:0] +// 8 tcp_ack_number[31:0] +// 9 tcp_flag[8:0], lro_eligible[9], l3_header_padding[12:10], reserved_9a[15:13], window_size[31:16] +// 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21] +// 11 rule_indication_31_0[31:0] +// 12 rule_indication_63_32[31:0] +// 13 sa_idx[15:0], da_idx[31:16] +// 14 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26] +// 15 fse_metadata[31:0] +// 16 cce_metadata[15:0], sa_sw_peer_id[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_END 17 + +struct rx_msdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t ip_hdr_chksum : 16, //[15:0] + tcp_udp_chksum : 16; //[31:16] + uint32_t key_id_octet : 8, //[7:0] + cce_super_rule : 6, //[13:8] + cce_classify_not_done_truncate : 1, //[14] + cce_classify_not_done_cce_dis : 1, //[15] + ext_wapi_pn_63_48 : 16; //[31:16] + uint32_t ext_wapi_pn_95_64 : 32; //[31:0] + uint32_t ext_wapi_pn_127_96 : 32; //[31:0] + uint32_t reported_mpdu_length : 14, //[13:0] + first_msdu : 1, //[14] + last_msdu : 1, //[15] + sa_idx_timeout : 1, //[16] + da_idx_timeout : 1, //[17] + msdu_limit_error : 1, //[18] + flow_idx_timeout : 1, //[19] + flow_idx_invalid : 1, //[20] + wifi_parser_error : 1, //[21] + amsdu_parser_error : 1, //[22] + sa_is_valid : 1, //[23] + da_is_valid : 1, //[24] + da_is_mcbc : 1, //[25] + reserved_5a : 6; //[31:26] + uint32_t ipv6_options_crc : 32; //[31:0] + uint32_t tcp_seq_number : 32; //[31:0] + uint32_t tcp_ack_number : 32; //[31:0] + uint32_t tcp_flag : 9, //[8:0] + lro_eligible : 1, //[9] + l3_header_padding : 3, //[12:10] + reserved_9a : 3, //[15:13] + window_size : 16; //[31:16] + uint32_t da_offset : 6, //[5:0] + sa_offset : 6, //[11:6] + da_offset_valid : 1, //[12] + sa_offset_valid : 1, //[13] + type_offset : 7, //[20:14] + reserved_10a : 11; //[31:21] + uint32_t rule_indication_31_0 : 32; //[31:0] + uint32_t rule_indication_63_32 : 32; //[31:0] + uint32_t sa_idx : 16, //[15:0] + da_idx : 16; //[31:16] + uint32_t msdu_drop : 1, //[0] + reo_destination_indication : 5, //[5:1] + flow_idx : 20, //[25:6] + reserved_14 : 6; //[31:26] + uint32_t fse_metadata : 32; //[31:0] + uint32_t cce_metadata : 16, //[15:0] + sa_sw_peer_id : 16; //[31:16] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +ip_hdr_chksum + + This can include the IP header checksum or the pseudo + header checksum used by TCP/UDP checksum. + +tcp_udp_chksum + + The value of the computed TCP/UDP checksum. A mode bit + selects whether this checksum is the full checksum or the + partial checksum which does not include the pseudo header. + +key_id_octet + + The key ID octet from the IV. Only valid when + first_msdu is set. + +cce_super_rule + + Indicates the super filter rule + +cce_classify_not_done_truncate + + Classification failed due to truncated frame + +cce_classify_not_done_cce_dis + + Classification failed due to CCE global disable + +ext_wapi_pn_63_48 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [63:48] (pn6 and pn7). + The WAPI PN bits [63:0] are in the pn field of the + rx_mpdu_start descriptor. + +ext_wapi_pn_95_64 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 + and pn11). + +ext_wapi_pn_127_96 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [127:96] (pn12, pn13, + pn14, pn15). + +reported_mpdu_length + + MPDU length before decapsulation. Only valid when + first_msdu is set. This field is taken directly from the + length field of the A-MPDU delimiter or the preamble length + field for non-A-MPDU frames. + +first_msdu + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a + non-aggregated MSDU frame: normal MPDU. Interior MSDU in an + A-MSDU shall have both first_mpdu and last_mpdu bits set to + 0. + +last_msdu + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. + +msdu_limit_error + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decapsulated but will be DMA'ed in RAW format as a single + MSDU buffer + +flow_idx_timeout + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + + +flow_idx_invalid + + flow id is not valid + + + +wifi_parser_error + + TODO: add details to the description + + + +amsdu_parser_error + + A-MSDU could not be properly de-agregated. + + + +sa_is_valid + + Indicates that OLE found a valid SA entry + +da_is_valid + + Indicates that OLE found a valid DA entry + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. + +reserved_5a + + + +ipv6_options_crc + + 32 bit CRC computed out of IP v6 extension headers + +tcp_seq_number + + TCP sequence number + +tcp_ack_number + + TCP acknowledge number + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} + +lro_eligible + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO + +l3_header_padding + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary + +reserved_9a + + + +window_size + + TCP receive window size + +da_offset + + Offset into MSDU buffer for DA + +sa_offset + + Offset into MSDU buffer for SA + +da_offset_valid + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed + +sa_offset_valid + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed + +type_offset + + Offset into MSDU buffer for Type + +reserved_10a + + + +rule_indication_31_0 + + Bitmap indicating which of rules 31-0 have matched + +rule_indication_63_32 + + Bitmap indicating which of rules 63-32 have matched + +sa_idx + + The offset in the address table which matches the MAC + source address. + +da_idx + + The offset in the address table which matches the MAC + source address + +msdu_drop + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +flow_idx + + Flow table index + + + +reserved_14 + + + +fse_metadata + + FSE related meta data: + + + +cce_metadata + + CCE related meta data: + + + +sa_sw_peer_id + + sw_peer_id from the address search entry corresponding + to the source address of the MSDU + + +*/ + + +/* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MSDU_END_0_RESERVED_0 + + +*/ +#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_0_RESERVED_0_LSB 9 +#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MSDU_END_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MSDU_END_1_IP_HDR_CHKSUM + + This can include the IP header checksum or the pseudo + header checksum used by TCP/UDP checksum. +*/ +#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff + +/* Description RX_MSDU_END_1_TCP_UDP_CHKSUM + + The value of the computed TCP/UDP checksum. A mode bit + selects whether this checksum is the full checksum or the + partial checksum which does not include the pseudo header. +*/ +#define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK 0xffff0000 + +/* Description RX_MSDU_END_2_KEY_ID_OCTET + + The key ID octet from the IV. Only valid when + first_msdu is set. +*/ +#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 +#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MSDU_END_2_CCE_SUPER_RULE + + Indicates the super filter rule +*/ +#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 + +/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE + + Classification failed due to truncated frame +*/ +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS + + Classification failed due to CCE global disable +*/ +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +/* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [63:48] (pn6 and pn7). + The WAPI PN bits [63:0] are in the pn field of the + rx_mpdu_start descriptor. +*/ +#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET 0x00000008 +#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB 16 +#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 + +/* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 + and pn11). +*/ +#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET 0x0000000c +#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB 0 +#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff + +/* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 + + Extension PN (packet number) which is only used by WAPI. + This corresponds to WAPI PN bits [127:96] (pn12, pn13, + pn14, pn15). +*/ +#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET 0x00000010 +#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB 0 +#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff + +/* Description RX_MSDU_END_5_REPORTED_MPDU_LENGTH + + MPDU length before decapsulation. Only valid when + first_msdu is set. This field is taken directly from the + length field of the A-MPDU delimiter or the preamble length + field for non-A-MPDU frames. +*/ +#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET 0x00000014 +#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB 0 +#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK 0x00003fff + +/* Description RX_MSDU_END_5_FIRST_MSDU + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a + non-aggregated MSDU frame: normal MPDU. Interior MSDU in an + A-MSDU shall have both first_mpdu and last_mpdu bits set to + 0. +*/ +#define RX_MSDU_END_5_FIRST_MSDU_OFFSET 0x00000014 +#define RX_MSDU_END_5_FIRST_MSDU_LSB 14 +#define RX_MSDU_END_5_FIRST_MSDU_MASK 0x00004000 + +/* Description RX_MSDU_END_5_LAST_MSDU + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. +*/ +#define RX_MSDU_END_5_LAST_MSDU_OFFSET 0x00000014 +#define RX_MSDU_END_5_LAST_MSDU_LSB 15 +#define RX_MSDU_END_5_LAST_MSDU_MASK 0x00008000 + +/* Description RX_MSDU_END_5_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ +#define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK 0x00010000 + +/* Description RX_MSDU_END_5_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ +#define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MSDU_END_5_MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decapsulated but will be DMA'ed in RAW format as a single + MSDU buffer +*/ +#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET 0x00000014 +#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB 18 +#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK 0x00040000 + +/* Description RX_MSDU_END_5_FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + +*/ +#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET 0x00000014 +#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB 19 +#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK 0x00080000 + +/* Description RX_MSDU_END_5_FLOW_IDX_INVALID + + flow id is not valid + + +*/ +#define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB 20 +#define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK 0x00100000 + +/* Description RX_MSDU_END_5_WIFI_PARSER_ERROR + + TODO: add details to the description + + +*/ +#define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET 0x00000014 +#define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB 21 +#define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK 0x00200000 + +/* Description RX_MSDU_END_5_AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + + +*/ +#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET 0x00000014 +#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB 22 +#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK 0x00400000 + +/* Description RX_MSDU_END_5_SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ +#define RX_MSDU_END_5_SA_IS_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_5_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_END_5_DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ +#define RX_MSDU_END_5_DA_IS_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_5_DA_IS_VALID_MASK 0x01000000 + +/* Description RX_MSDU_END_5_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. +*/ +#define RX_MSDU_END_5_DA_IS_MCBC_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 + +/* Description RX_MSDU_END_5_RESERVED_5A + + +*/ +#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_5_RESERVED_5A_LSB 26 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0xfc000000 + +/* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC + + 32 bit CRC computed out of IP v6 extension headers +*/ +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff + +/* Description RX_MSDU_END_7_TCP_SEQ_NUMBER + + TCP sequence number +*/ +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff + +/* Description RX_MSDU_END_8_TCP_ACK_NUMBER + + TCP acknowledge number +*/ +#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff + +/* Description RX_MSDU_END_9_TCP_FLAG + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ +#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_9_TCP_FLAG_LSB 0 +#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff + +/* Description RX_MSDU_END_9_LRO_ELIGIBLE + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO +*/ +#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 + +/* Description RX_MSDU_END_9_L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ +#define RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET 0x00000024 +#define RX_MSDU_END_9_L3_HEADER_PADDING_LSB 10 +#define RX_MSDU_END_9_L3_HEADER_PADDING_MASK 0x00001c00 + +/* Description RX_MSDU_END_9_RESERVED_9A + + +*/ +#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_9_RESERVED_9A_LSB 13 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000e000 + +/* Description RX_MSDU_END_9_WINDOW_SIZE + + TCP receive window size +*/ +#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 + +/* Description RX_MSDU_END_10_DA_OFFSET + + Offset into MSDU buffer for DA +*/ +#define RX_MSDU_END_10_DA_OFFSET_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_OFFSET_LSB 0 +#define RX_MSDU_END_10_DA_OFFSET_MASK 0x0000003f + +/* Description RX_MSDU_END_10_SA_OFFSET + + Offset into MSDU buffer for SA +*/ +#define RX_MSDU_END_10_SA_OFFSET_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_OFFSET_LSB 6 +#define RX_MSDU_END_10_SA_OFFSET_MASK 0x00000fc0 + +/* Description RX_MSDU_END_10_DA_OFFSET_VALID + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed +*/ +#define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_10_DA_OFFSET_VALID_MASK 0x00001000 + +/* Description RX_MSDU_END_10_SA_OFFSET_VALID + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed +*/ +#define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_10_SA_OFFSET_VALID_MASK 0x00002000 + +/* Description RX_MSDU_END_10_TYPE_OFFSET + + Offset into MSDU buffer for Type +*/ +#define RX_MSDU_END_10_TYPE_OFFSET_OFFSET 0x00000028 +#define RX_MSDU_END_10_TYPE_OFFSET_LSB 14 +#define RX_MSDU_END_10_TYPE_OFFSET_MASK 0x001fc000 + +/* Description RX_MSDU_END_10_RESERVED_10A + + +*/ +#define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 +#define RX_MSDU_END_10_RESERVED_10A_LSB 21 +#define RX_MSDU_END_10_RESERVED_10A_MASK 0xffe00000 + +/* Description RX_MSDU_END_11_RULE_INDICATION_31_0 + + Bitmap indicating which of rules 31-0 have matched +*/ +#define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET 0x0000002c +#define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK 0xffffffff + +/* Description RX_MSDU_END_12_RULE_INDICATION_63_32 + + Bitmap indicating which of rules 63-32 have matched +*/ +#define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET 0x00000030 +#define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK 0xffffffff + +/* Description RX_MSDU_END_13_SA_IDX + + The offset in the address table which matches the MAC + source address. +*/ +#define RX_MSDU_END_13_SA_IDX_OFFSET 0x00000034 +#define RX_MSDU_END_13_SA_IDX_LSB 0 +#define RX_MSDU_END_13_SA_IDX_MASK 0x0000ffff + +/* Description RX_MSDU_END_13_DA_IDX + + The offset in the address table which matches the MAC + source address +*/ +#define RX_MSDU_END_13_DA_IDX_OFFSET 0x00000034 +#define RX_MSDU_END_13_DA_IDX_LSB 16 +#define RX_MSDU_END_13_DA_IDX_MASK 0xffff0000 + +/* Description RX_MSDU_END_14_MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_END_14_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_END_14_MSDU_DROP_LSB 0 +#define RX_MSDU_END_14_MSDU_DROP_MASK 0x00000001 + +/* Description RX_MSDU_END_14_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET 0x00000038 +#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK 0x0000003e + +/* Description RX_MSDU_END_14_FLOW_IDX + + Flow table index + + +*/ +#define RX_MSDU_END_14_FLOW_IDX_OFFSET 0x00000038 +#define RX_MSDU_END_14_FLOW_IDX_LSB 6 +#define RX_MSDU_END_14_FLOW_IDX_MASK 0x03ffffc0 + +/* Description RX_MSDU_END_14_RESERVED_14 + + +*/ +#define RX_MSDU_END_14_RESERVED_14_OFFSET 0x00000038 +#define RX_MSDU_END_14_RESERVED_14_LSB 26 +#define RX_MSDU_END_14_RESERVED_14_MASK 0xfc000000 + +/* Description RX_MSDU_END_15_FSE_METADATA + + FSE related meta data: + + +*/ +#define RX_MSDU_END_15_FSE_METADATA_OFFSET 0x0000003c +#define RX_MSDU_END_15_FSE_METADATA_LSB 0 +#define RX_MSDU_END_15_FSE_METADATA_MASK 0xffffffff + +/* Description RX_MSDU_END_16_CCE_METADATA + + CCE related meta data: + + +*/ +#define RX_MSDU_END_16_CCE_METADATA_OFFSET 0x00000040 +#define RX_MSDU_END_16_CCE_METADATA_LSB 0 +#define RX_MSDU_END_16_CCE_METADATA_MASK 0x0000ffff + +/* Description RX_MSDU_END_16_SA_SW_PEER_ID + + sw_peer_id from the address search entry corresponding + to the source address of the MSDU + + +*/ +#define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET 0x00000040 +#define RX_MSDU_END_16_SA_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_16_SA_SW_PEER_ID_MASK 0xffff0000 + + +#endif // _RX_MSDU_END_H_ diff --git a/hw/qca8074/v1/rx_msdu_link.h b/hw/qca8074/v1/rx_msdu_link.h new file mode 100644 index 000000000000..8f7cc6d7dded --- /dev/null +++ b/hw/qca8074/v1/rx_msdu_link.h @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; +// 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8-11 struct rx_msdu_details msdu_0; +// 12-15 struct rx_msdu_details msdu_1; +// 16-19 struct rx_msdu_details msdu_2; +// 20-23 struct rx_msdu_details msdu_3; +// 24-27 struct rx_msdu_details msdu_4; +// 28-31 struct rx_msdu_details msdu_5; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, //[15:0] + first_rx_msdu_link_struct : 1, //[16] + reserved_3a : 15; //[31:17] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_MSDU_Link_descriptor + +struct buffer_addr_info next_msdu_link_desc_addr_info + + Details of the physical address of the next MSDU link + descriptor that contains info about additional MSDUs that + are part of this MPDU. + +receive_queue_number + + Indicates the Receive queue to which this MPDU + descriptor belongs + + Used for tracking, finding bugs and debugging. + + + +first_rx_msdu_link_struct + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + + + +reserved_3a + + + +pn_31_0 + + + + + 31-0 bits of the 256-bit packet number bitmap. + + + +pn_63_32 + + + + + 63-32 bits of the 256-bit packet number bitmap. + + + +pn_95_64 + + + + + 95-64 bits of the 256-bit packet number bitmap. + + + +pn_127_96 + + + + + 127-96 bits of the 256-bit packet number bitmap. + + + +struct rx_msdu_details msdu_0 + + When First_RX_MSDU_link_struct is set, this MSDU is the + first in the MPDU + + + + When First_RX_MSDU_link_struct is NOT set, this MSDU + follows the last MSDU in the previous RX_MSDU_link data + structure + +struct rx_msdu_details msdu_1 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_2 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_3 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_4 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_5 + + Details of next MSDU in this (MSDU flow) linked list +*/ + +#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 +#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff +#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 +#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff +#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0 +#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff + +/* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER + + Indicates the Receive queue to which this MPDU + descriptor belongs + + Used for tracking, finding bugs and debugging. + + +*/ +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + + +*/ +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +/* Description RX_MSDU_LINK_3_RESERVED_3A + + +*/ +#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 + +/* Description RX_MSDU_LINK_4_PN_31_0 + + + + + 31-0 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_4_PN_31_0_LSB 0 +#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_5_PN_63_32 + + + + + 63-32 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_5_PN_63_32_LSB 0 +#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff + +/* Description RX_MSDU_LINK_6_PN_95_64 + + + + + 95-64 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_6_PN_95_64_LSB 0 +#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff + +/* Description RX_MSDU_LINK_7_PN_127_96 + + + + + 127-96 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_7_PN_127_96_LSB 0 +#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff +#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_LSB 0 +#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff +#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000030 +#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_LSB 0 +#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff +#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000040 +#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_LSB 0 +#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff +#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000050 +#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_LSB 0 +#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff +#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000060 +#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_LSB 0 +#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff +#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000070 +#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff +#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff +#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff +#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_LSB 0 +#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff + + +#endif // _RX_MSDU_LINK_H_ diff --git a/hw/qca8074/v1/rx_msdu_start.h b/hw/qca8074/v1/rx_msdu_start.h new file mode 100644 index 000000000000..0be1a43d5b6b --- /dev/null +++ b/hw/qca8074/v1/rx_msdu_start.h @@ -0,0 +1,1081 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24] +// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], reserved_2a[31:16] +// 3 reserved_3a[10:0], da_is_bcast_mcast[11], reserved_3b[15:12], ip4_protocol_ip6_next_header[23:16], reserved_3c[30:24], toeplitz_hash[31] +// 4 toeplitz_hash_2_or_4[31:0] +// 5 flow_id_toeplitz[31:0] +// 6 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_6[31:26] +// 7 ppdu_start_timestamp[31:0] +// 8 sw_phy_meta_data[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_START 9 + +struct rx_msdu_start { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t msdu_length : 14, //[13:0] + reserved_1a : 1, //[14] + ipsec_esp : 1, //[15] + l3_offset : 7, //[22:16] + ipsec_ah : 1, //[23] + l4_offset : 8; //[31:24] + uint32_t msdu_number : 8, //[7:0] + decap_format : 2, //[9:8] + ipv4_proto : 1, //[10] + ipv6_proto : 1, //[11] + tcp_proto : 1, //[12] + udp_proto : 1, //[13] + ip_frag : 1, //[14] + tcp_only_ack : 1, //[15] + reserved_2a : 16; //[31:16] + uint32_t reserved_3a : 11, //[10:0] + da_is_bcast_mcast : 1, //[11] + reserved_3b : 4, //[15:12] + ip4_protocol_ip6_next_header : 8, //[23:16] + reserved_3c : 7, //[30:24] + toeplitz_hash : 1; //[31] + uint32_t toeplitz_hash_2_or_4 : 32; //[31:0] + uint32_t flow_id_toeplitz : 32; //[31:0] + uint32_t user_rssi : 8, //[7:0] + pkt_type : 4, //[11:8] + stbc : 1, //[12] + sgi : 2, //[14:13] + rate_mcs : 4, //[18:15] + receive_bandwidth : 2, //[20:19] + reception_type : 2, //[22:21] + nss : 3, //[25:23] + reserved_6 : 6; //[31:26] + uint32_t ppdu_start_timestamp : 32; //[31:0] + uint32_t sw_phy_meta_data : 32; //[31:0] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +msdu_length + + MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + +reserved_1a + + + +ipsec_esp + + Set if IPv4/v6 packet is using IPsec ESP + +l3_offset + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the IP + offset in bytes from the start of the packet after + decapsulation.  The latter is only valid if ipv4_proto or + ipv6_proto is set. + +ipsec_ah + + Set if IPv4/v6 packet is using IPsec AH + +l4_offset + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid if + tcp_proto or udp_proto is set).  The value 0 indicates that + the offset is longer than 127 bytes. + +msdu_number + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number of + MSDU exceeds 255 this number will wrap using modulo 256. + +decap_format + + Indicates the format after decapsulation: + + + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + + +ipv4_proto + + Set if L2 layer indicates IPv4 protocol. + +ipv6_proto + + Set if L2 layer indicates IPv6 protocol. + +tcp_proto + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates TCP. + +udp_proto + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates UDP. + +ip_frag + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is a + fragmented IP packet. + +tcp_only_ack + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. + +reserved_2a + + + +reserved_3a + + + +da_is_bcast_mcast + + The destination address is broadcast or multicast. + +reserved_3b + + + +ip4_protocol_ip6_next_header + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). + +reserved_3c + + + +toeplitz_hash + + Actual choosen Hash. + + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP + destination address)1 -> Toeplitz hash of 4-tuple (IP source + address, IP destination address, L4 (TCP/UDP) source port, + L4 (TCP/UDP) destination port) + +toeplitz_hash_2_or_4 + + Controlled by RxOLE register - If register bit set to 0, + Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest + addresses; otherwise, toeplitz hash is computed over 4-tuple + IPv4 or IPv6 src/dest addresses and src/dest ports + +flow_id_toeplitz + + Toeplitz hash of 5-tuple + + {IP source address, IP destination address, IP source + port, IP destination port, L4 protocol} in case of + non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + + {IP source address, IP destination address, SPI, L4 + protocol} + + + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE.The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + + +user_rssi + + RSSI for this user + + + +pkt_type + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + +stbc + + When set, use STBC transmission rates + +sgi + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + + +rate_mcs + + For details, refer to MCS_TYPE description + + + +receive_bandwidth + + Full receive Bandwidth + + + + + + + + + + + + + + + +reception_type + + Indicates what type of reception this is. + + + + + + + + + + + +nss + + Field only valid when Reception_type = + reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO + + + + Number of Spatial Streams occupied by the User + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams + +reserved_6 + + + +ppdu_start_timestamp + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + +sw_phy_meta_data + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + + +*/ + + +/* Description RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MSDU_START_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MSDU_START_0_RESERVED_0 + + +*/ +#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_0_RESERVED_0_LSB 9 +#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MSDU_START_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MSDU_START_1_MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without +*/ +#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff + +/* Description RX_MSDU_START_1_RESERVED_1A + + +*/ +#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_START_1_RESERVED_1A_LSB 14 +#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 + +/* Description RX_MSDU_START_1_IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ +#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 + +/* Description RX_MSDU_START_1_L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the IP + offset in bytes from the start of the packet after + decapsulation.  The latter is only valid if ipv4_proto or + ipv6_proto is set. +*/ +#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L3_OFFSET_LSB 16 +#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 + +/* Description RX_MSDU_START_1_IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ +#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_AH_LSB 23 +#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 + +/* Description RX_MSDU_START_1_L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid if + tcp_proto or udp_proto is set).  The value 0 indicates that + the offset is longer than 127 bytes. +*/ +#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L4_OFFSET_LSB 24 +#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 + +/* Description RX_MSDU_START_2_MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number of + MSDU exceeds 255 this number will wrap using modulo 256. +*/ +#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff + +/* Description RX_MSDU_START_2_DECAP_FORMAT + + Indicates the format after decapsulation: + + + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + +*/ +#ifndef RX_MSDU_START_2_DECAP_FORMAT_OFFSET +#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 +#endif +#ifndef RX_MSDU_START_2_DECAP_FORMAT_LSB +#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 +#endif +#ifndef RX_MSDU_START_2_DECAP_FORMAT_MASK +#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 +#endif +/* Description RX_MSDU_START_2_IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ +#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 + +/* Description RX_MSDU_START_2_IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ +#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 + +/* Description RX_MSDU_START_2_TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates TCP. +*/ +#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_PROTO_LSB 12 +#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 + +/* Description RX_MSDU_START_2_UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates UDP. +*/ +#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_UDP_PROTO_LSB 13 +#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 + +/* Description RX_MSDU_START_2_IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is a + fragmented IP packet. +*/ +#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FRAG_LSB 14 +#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 + +/* Description RX_MSDU_START_2_TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ +#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 + +/* Description RX_MSDU_START_2_RESERVED_2A + + +*/ +#define RX_MSDU_START_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_START_2_RESERVED_2A_LSB 16 +#define RX_MSDU_START_2_RESERVED_2A_MASK 0xffff0000 + +/* Description RX_MSDU_START_3_RESERVED_3A + + +*/ +#define RX_MSDU_START_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_START_3_RESERVED_3A_LSB 0 +#define RX_MSDU_START_3_RESERVED_3A_MASK 0x000007ff + +/* Description RX_MSDU_START_3_DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ +#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_OFFSET 0x0000000c +#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_LSB 11 +#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_MASK 0x00000800 + +/* Description RX_MSDU_START_3_RESERVED_3B + + +*/ +#define RX_MSDU_START_3_RESERVED_3B_OFFSET 0x0000000c +#define RX_MSDU_START_3_RESERVED_3B_LSB 12 +#define RX_MSDU_START_3_RESERVED_3B_MASK 0x0000f000 + +/* Description RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). +*/ +#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000c +#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 16 +#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00ff0000 + +/* Description RX_MSDU_START_3_RESERVED_3C + + +*/ +#define RX_MSDU_START_3_RESERVED_3C_OFFSET 0x0000000c +#define RX_MSDU_START_3_RESERVED_3C_LSB 24 +#define RX_MSDU_START_3_RESERVED_3C_MASK 0x7f000000 + +/* Description RX_MSDU_START_3_TOEPLITZ_HASH + + Actual choosen Hash. + + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP + destination address)1 -> Toeplitz hash of 4-tuple (IP source + address, IP destination address, L4 (TCP/UDP) source port, + L4 (TCP/UDP) destination port) +*/ +#define RX_MSDU_START_3_TOEPLITZ_HASH_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_LSB 31 +#define RX_MSDU_START_3_TOEPLITZ_HASH_MASK 0x80000000 + +/* Description RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4 + + Controlled by RxOLE register - If register bit set to 0, + Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest + addresses; otherwise, toeplitz hash is computed over 4-tuple + IPv4 or IPv6 src/dest addresses and src/dest ports +*/ +#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_OFFSET 0x00000010 +#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +/* Description RX_MSDU_START_5_FLOW_ID_TOEPLITZ + + Toeplitz hash of 5-tuple + + {IP source address, IP destination address, IP source + port, IP destination port, L4 protocol} in case of + non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + + {IP source address, IP destination address, SPI, L4 + protocol} + + + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE.The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + +*/ +#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_OFFSET 0x00000014 +#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +/* Description RX_MSDU_START_6_USER_RSSI + + RSSI for this user + + +*/ +#define RX_MSDU_START_6_USER_RSSI_OFFSET 0x00000018 +#define RX_MSDU_START_6_USER_RSSI_LSB 0 +#define RX_MSDU_START_6_USER_RSSI_MASK 0x000000ff + +/* Description RX_MSDU_START_6_PKT_TYPE + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type +*/ +#define RX_MSDU_START_6_PKT_TYPE_OFFSET 0x00000018 +#define RX_MSDU_START_6_PKT_TYPE_LSB 8 +#define RX_MSDU_START_6_PKT_TYPE_MASK 0x00000f00 + +/* Description RX_MSDU_START_6_STBC + + When set, use STBC transmission rates +*/ +#define RX_MSDU_START_6_STBC_OFFSET 0x00000018 +#define RX_MSDU_START_6_STBC_LSB 12 +#define RX_MSDU_START_6_STBC_MASK 0x00001000 + +/* Description RX_MSDU_START_6_SGI + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + +*/ +#define RX_MSDU_START_6_SGI_OFFSET 0x00000018 +#define RX_MSDU_START_6_SGI_LSB 13 +#define RX_MSDU_START_6_SGI_MASK 0x00006000 + +/* Description RX_MSDU_START_6_RATE_MCS + + For details, refer to MCS_TYPE description + + +*/ +#define RX_MSDU_START_6_RATE_MCS_OFFSET 0x00000018 +#define RX_MSDU_START_6_RATE_MCS_LSB 15 +#define RX_MSDU_START_6_RATE_MCS_MASK 0x00078000 + +/* Description RX_MSDU_START_6_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_OFFSET 0x00000018 +#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_MASK 0x00180000 + +/* Description RX_MSDU_START_6_RECEPTION_TYPE + + Indicates what type of reception this is. + + + + + + + + + + +*/ +#define RX_MSDU_START_6_RECEPTION_TYPE_OFFSET 0x00000018 +#define RX_MSDU_START_6_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_6_RECEPTION_TYPE_MASK 0x00600000 + +/* Description RX_MSDU_START_6_NSS + + Field only valid when Reception_type = + reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO + + + + Number of Spatial Streams occupied by the User + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define RX_MSDU_START_6_NSS_OFFSET 0x00000018 +#define RX_MSDU_START_6_NSS_LSB 23 +#define RX_MSDU_START_6_NSS_MASK 0x03800000 + +/* Description RX_MSDU_START_6_RESERVED_6 + + +*/ +#define RX_MSDU_START_6_RESERVED_6_OFFSET 0x00000018 +#define RX_MSDU_START_6_RESERVED_6_LSB 26 +#define RX_MSDU_START_6_RESERVED_6_MASK 0xfc000000 + +/* Description RX_MSDU_START_7_PPDU_START_TIMESTAMP + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + +*/ +#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_OFFSET 0x0000001c +#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_MASK 0xffffffff + +/* Description RX_MSDU_START_8_SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + + +*/ +#define RX_MSDU_START_8_SW_PHY_META_DATA_OFFSET 0x00000020 +#define RX_MSDU_START_8_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_8_SW_PHY_META_DATA_MASK 0xffffffff + + +#endif // _RX_MSDU_START_H_ diff --git a/hw/qca8074/v1/rx_reo_queue.h b/hw/qca8074/v1/rx_reo_queue.h new file mode 100644 index 000000000000..a3f2eebcb005 --- /dev/null +++ b/hw/qca8074/v1/rx_reo_queue.h @@ -0,0 +1,1662 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1 receive_queue_number[15:0], reserved_1b[31:16] +// 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] +// 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8 last_rx_enqueue_timestamp[31:0] +// 9 last_rx_dequeue_timestamp[31:0] +// 10 ptr_to_next_aging_queue_31_0[31:0] +// 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] +// 12 ptr_to_previous_aging_queue_31_0[31:0] +// 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] +// 14 rx_bitmap_31_0[31:0] +// 15 rx_bitmap_63_32[31:0] +// 16 rx_bitmap_95_64[31:0] +// 17 rx_bitmap_127_96[31:0] +// 18 rx_bitmap_159_128[31:0] +// 19 rx_bitmap_191_160[31:0] +// 20 rx_bitmap_223_192[31:0] +// 21 rx_bitmap_255_224[31:0] +// 22 current_mpdu_count[6:0], current_msdu_count[31:7] +// 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] +// 24 frames_in_order_count[23:0], bar_received_count[31:24] +// 25 mpdu_frames_processed_count[31:0] +// 26 msdu_frames_processed_count[31:0] +// 27 total_processed_byte_count[31:0] +// 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] +// 29 reserved_29[31:0] +// 30 reserved_30[31:0] +// 31 reserved_31[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, //[15:0] + reserved_1b : 16; //[31:16] + uint32_t vld : 1, //[0] + associated_link_descriptor_counter: 2, //[2:1] + disable_duplicate_detection : 1, //[3] + soft_reorder_enable : 1, //[4] + ac : 2, //[6:5] + bar : 1, //[7] + rty : 1, //[8] + chk_2k_mode : 1, //[9] + oor_mode : 1, //[10] + ba_window_size : 8, //[18:11] + pn_check_needed : 1, //[19] + pn_shall_be_even : 1, //[20] + pn_shall_be_uneven : 1, //[21] + pn_handling_enable : 1, //[22] + pn_size : 2, //[24:23] + ignore_ampdu_flag : 1, //[25] + reserved_2b : 6; //[31:26] + uint32_t svld : 1, //[0] + ssn : 12, //[12:1] + current_index : 8, //[20:13] + seq_2k_error_detected_flag : 1, //[21] + pn_error_detected_flag : 1, //[22] + reserved_3a : 8, //[30:23] + pn_valid : 1; //[31] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t last_rx_enqueue_timestamp : 32; //[31:0] + uint32_t last_rx_dequeue_timestamp : 32; //[31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] + uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] + reserved_11a : 24; //[31:8] + uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] + uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] + reserved_13a : 24; //[31:8] + uint32_t rx_bitmap_31_0 : 32; //[31:0] + uint32_t rx_bitmap_63_32 : 32; //[31:0] + uint32_t rx_bitmap_95_64 : 32; //[31:0] + uint32_t rx_bitmap_127_96 : 32; //[31:0] + uint32_t rx_bitmap_159_128 : 32; //[31:0] + uint32_t rx_bitmap_191_160 : 32; //[31:0] + uint32_t rx_bitmap_223_192 : 32; //[31:0] + uint32_t rx_bitmap_255_224 : 32; //[31:0] + uint32_t current_mpdu_count : 7, //[6:0] + current_msdu_count : 25; //[31:7] + uint32_t reserved_23 : 4, //[3:0] + timeout_count : 6, //[9:4] + forward_due_to_bar_count : 6, //[15:10] + duplicate_count : 16; //[31:16] + uint32_t frames_in_order_count : 24, //[23:0] + bar_received_count : 8; //[31:24] + uint32_t mpdu_frames_processed_count : 32; //[31:0] + uint32_t msdu_frames_processed_count : 32; //[31:0] + uint32_t total_processed_byte_count : 32; //[31:0] + uint32_t late_receive_mpdu_count : 12, //[11:0] + window_jump_2k : 4, //[15:12] + hole_count : 16; //[31:16] + uint32_t reserved_29 : 32; //[31:0] + uint32_t reserved_30 : 32; //[31:0] + uint32_t reserved_31 : 32; //[31:0] +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_REO_queue_descriptor + +receive_queue_number + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + + +reserved_1b + + + +vld + + Valid bit indicating a session is established and the + queue descriptor is valid(Filled by SW) + + + +associated_link_descriptor_counter + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + + MSDU link descriptors related with MPDUs stored in the + re-order buffer shall also be included in this count. + + + + + +disable_duplicate_detection + + When set, do not perform any duplicate detection. + + + + + +soft_reorder_enable + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes. + + + + Note that this implies that REO is also not going to + perform any MSDU level operations, and the entire MPDU (and + thus pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW + programmable configuration register in REO + + + + + +ac + + Indicates which access category the queue descriptor + belongs to(filled by SW) + + + +bar + + Indicates if BAR has been received (mostly used for + debug purpose and this is filled by REO) + + + +rty + + Retry bit is checked if this bit is set. + + + +chk_2k_mode + + Indicates what type of operation is expected from Reo + when the received frame SN falls within the 2K window + + + + See REO MLD document for programming details. + + + +oor_mode + + Out of Order mode: + + Indicates what type of operation is expected when the + received frame falls within the OOR window. + + + + See REO MLD document for programming details. + + + +ba_window_size + + Indicates the negotiated (window size + 1). + + it can go up to Max of 256bits. + + + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 + (means non-BA session, with window size of 0). The 3 values + here are the main values validated, but other values should + work as well. + + + + A BA window size of 0 (=> one frame entry bitmat), means + that there is NO RX_REO_QUEUE_EXT descriptor following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 1 - 105, means that there is 1 + RX_REO_QUEUE_EXT descriptor directly following this + RX_REO_QUEUE STRUCT in memory. + + + + A BA window size of 106 - 210, means that there are 2 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 211 - 256, means that there are 3 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + + +pn_check_needed + + When set, REO shall perform the PN increment check + + + +pn_shall_be_even + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + + + +pn_shall_be_uneven + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + + +pn_handling_enable + + Field only valid when 'pn_check_needed' is set. + + + + When set, and REO detected a PN error, HW shall set the + 'pn_error_detected_flag'. + + + +pn_size + + Size of the PN field check. + + Needed for wrap around handling... + + + + + + + + + + + + + +ignore_ampdu_flag + + When set, REO shall ignore the ampdu_flag on the + entrance descriptor for this queue. + + + +reserved_2b + + + +svld + + Sequence number in next field is valid one. It can be + filled by SW if the want to fill in the any negotiated SSN, + otherwise REO will fill the sequence number of first + received packet and set this bit to 1. + + + +ssn + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + + +current_index + + Points to last forwarded packet + + + +seq_2k_error_detected_flag + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a 2k error jump in the + sequence number and from that moment forward, all new frames + are forwarded directly to FW, without duplicate detect, + reordering, etc. + + + +pn_error_detected_flag + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a PN error and from that + moment forward, all new frames are forwarded directly to FW, + without duplicate detect, reordering, etc. + + + +reserved_3a + + + +pn_valid + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet and + set this bit to 1. + + + +pn_31_0 + + + + +pn_63_32 + + Bits [63:32] of the PN number. + + + +pn_95_64 + + Bits [95:64] of the PN number. + + + +pn_127_96 + + Bits [127:96] of the PN number. + + + +last_rx_enqueue_timestamp + + This timestamp is updated when an MPDU is received and + accesses this Queue Descriptor. It does not include the + access due to Command TLVs or Aging (which will be updated + in Last_rx_dequeue_timestamp). + + + +last_rx_dequeue_timestamp + + This timestamp is used for Aging. When an MPDU or + multiple MPDUs are forwarded, either due to window movement, + bar, aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + + +ptr_to_next_aging_queue_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + + +ptr_to_next_aging_queue_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + + +reserved_11a + + + +ptr_to_previous_aging_queue_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + + +ptr_to_previous_aging_queue_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + + +reserved_13a + + + +rx_bitmap_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + + +rx_bitmap_63_32 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_95_64 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_127_96 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_159_128 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_191_160 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_223_192 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_255_224 + + See Rx_bitmap_31_0 description + + + +current_mpdu_count + + The number of MPDUs in the queue. + + + + + +current_msdu_count + + The number of MSDUs in the queue. + + + +reserved_23 + + + +timeout_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + + +forward_due_to_bar_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + + +duplicate_count + + The number of duplicate frames that have been detected + + + +frames_in_order_count + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + + +bar_received_count + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + + +mpdu_frames_processed_count + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + + + + +msdu_frames_processed_count + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + + +total_processed_byte_count + + An approximation of the number of bytes processed for + this queue. + + 'Processing' here means that REO has received them out + of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + In 64 byte units + + + +late_receive_mpdu_count + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + + +window_jump_2k + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + + +hole_count + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + + +reserved_29 + + + +reserved_30 + + + +reserved_31 + + +*/ + +#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 +#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff + +/* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description RX_REO_QUEUE_1_RESERVED_1B + + +*/ +#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_2_VLD + + Valid bit indicating a session is established and the + queue descriptor is valid(Filled by SW) + + +*/ +#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_VLD_LSB 0 +#define RX_REO_QUEUE_2_VLD_MASK 0x00000001 + +/* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + + MSDU link descriptors related with MPDUs stored in the + re-order buffer shall also be included in this count. + + + + +*/ +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +/* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION + + When set, do not perform any duplicate detection. + + + + +*/ +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +/* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes. + + + + Note that this implies that REO is also not going to + perform any MSDU level operations, and the entire MPDU (and + thus pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW + programmable configuration register in REO + + + + +*/ +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 + +/* Description RX_REO_QUEUE_2_AC + + Indicates which access category the queue descriptor + belongs to(filled by SW) + + +*/ +#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_AC_LSB 5 +#define RX_REO_QUEUE_2_AC_MASK 0x00000060 + +/* Description RX_REO_QUEUE_2_BAR + + Indicates if BAR has been received (mostly used for + debug purpose and this is filled by REO) + + +*/ +#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BAR_LSB 7 +#define RX_REO_QUEUE_2_BAR_MASK 0x00000080 + +/* Description RX_REO_QUEUE_2_RTY + + Retry bit is checked if this bit is set. + + +*/ +#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RTY_LSB 8 +#define RX_REO_QUEUE_2_RTY_MASK 0x00000100 + +/* Description RX_REO_QUEUE_2_CHK_2K_MODE + + Indicates what type of operation is expected from Reo + when the received frame SN falls within the 2K window + + + + See REO MLD document for programming details. + + +*/ +#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 + +/* Description RX_REO_QUEUE_2_OOR_MODE + + Out of Order mode: + + Indicates what type of operation is expected when the + received frame falls within the OOR window. + + + + See REO MLD document for programming details. + + +*/ +#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 + +/* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE + + Indicates the negotiated (window size + 1). + + it can go up to Max of 256bits. + + + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 + (means non-BA session, with window size of 0). The 3 values + here are the main values validated, but other values should + work as well. + + + + A BA window size of 0 (=> one frame entry bitmat), means + that there is NO RX_REO_QUEUE_EXT descriptor following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 1 - 105, means that there is 1 + RX_REO_QUEUE_EXT descriptor directly following this + RX_REO_QUEUE STRUCT in memory. + + + + A BA window size of 106 - 210, means that there are 2 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 211 - 256, means that there are 3 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + +*/ +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 + +/* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED + + When set, REO shall perform the PN increment check + + +*/ +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 + +/* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + + +*/ +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 + +/* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + +*/ +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +/* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE + + Field only valid when 'pn_check_needed' is set. + + + + When set, and REO detected a PN error, HW shall set the + 'pn_error_detected_flag'. + + +*/ +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 + +/* Description RX_REO_QUEUE_2_PN_SIZE + + Size of the PN field check. + + Needed for wrap around handling... + + + + + + + + + + + + +*/ +#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SIZE_LSB 23 +#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 + +/* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG + + When set, REO shall ignore the ampdu_flag on the + entrance descriptor for this queue. + + +*/ +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 + +/* Description RX_REO_QUEUE_2_RESERVED_2B + + +*/ +#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 +#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 + +/* Description RX_REO_QUEUE_3_SVLD + + Sequence number in next field is valid one. It can be + filled by SW if the want to fill in the any negotiated SSN, + otherwise REO will fill the sequence number of first + received packet and set this bit to 1. + + +*/ +#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SVLD_LSB 0 +#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 + +/* Description RX_REO_QUEUE_3_SSN + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + +*/ +#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SSN_LSB 1 +#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe + +/* Description RX_REO_QUEUE_3_CURRENT_INDEX + + Points to last forwarded packet + + +*/ +#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 + +/* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a 2k error jump in the + sequence number and from that moment forward, all new frames + are forwarded directly to FW, without duplicate detect, + reordering, etc. + + +*/ +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 + +/* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a PN error and from that + moment forward, all new frames are forwarded directly to FW, + without duplicate detect, reordering, etc. + + +*/ +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 + +/* Description RX_REO_QUEUE_3_RESERVED_3A + + +*/ +#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 +#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 + +/* Description RX_REO_QUEUE_3_PN_VALID + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet and + set this bit to 1. + + +*/ +#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_VALID_LSB 31 +#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 + +/* Description RX_REO_QUEUE_4_PN_31_0 + + + +*/ +#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_4_PN_31_0_LSB 0 +#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_5_PN_63_32 + + Bits [63:32] of the PN number. + + +*/ +#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_5_PN_63_32_LSB 0 +#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff + +/* Description RX_REO_QUEUE_6_PN_95_64 + + Bits [95:64] of the PN number. + + +*/ +#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_6_PN_95_64_LSB 0 +#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff + +/* Description RX_REO_QUEUE_7_PN_127_96 + + Bits [127:96] of the PN number. + + +*/ +#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_7_PN_127_96_LSB 0 +#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff + +/* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP + + This timestamp is updated when an MPDU is received and + accesses this Queue Descriptor. It does not include the + access due to Command TLVs or Aging (which will be updated + in Last_rx_dequeue_timestamp). + + +*/ +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP + + This timestamp is used for Aging. When an MPDU or + multiple MPDUs are forwarded, either due to window movement, + bar, aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + +*/ +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + +*/ +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + +*/ +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_11_RESERVED_11A + + +*/ +#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + +*/ +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + +*/ +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_13_RESERVED_13A + + +*/ +#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 +#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + +*/ +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff + +/* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff + +/* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff + +/* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff + +/* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff + +/* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff + +/* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff + +/* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + + + +*/ +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f + +/* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + + +*/ +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +/* Description RX_REO_QUEUE_23_RESERVED_23 + + +*/ +#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_RESERVED_23_LSB 0 +#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f + +/* Description RX_REO_QUEUE_23_TIMEOUT_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 + +/* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +/* Description RX_REO_QUEUE_23_DUPLICATE_COUNT + + The number of duplicate frames that have been detected + + +*/ +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + +*/ +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +/* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + +*/ +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 + +/* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + + + +*/ +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + +*/ +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes processed for + this queue. + + 'Processing' here means that REO has received them out + of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + In 64 byte units + + +*/ +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + +*/ +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +/* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + +*/ +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 + +/* Description RX_REO_QUEUE_28_HOLE_COUNT + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + +*/ +#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_29_RESERVED_29 + + +*/ +#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_29_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff + +/* Description RX_REO_QUEUE_30_RESERVED_30 + + +*/ +#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_30_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff + +/* Description RX_REO_QUEUE_31_RESERVED_31 + + +*/ +#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_31_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff + + +#endif // _RX_REO_QUEUE_H_ diff --git a/hw/qca8074/v1/rx_reo_queue_ext.h b/hw/qca8074/v1/rx_reo_queue_ext.h new file mode 100644 index 000000000000..f829fac9a3d0 --- /dev/null +++ b/hw/qca8074/v1/rx_reo_queue_ext.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "rx_mpdu_link_ptr.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1 reserved_1a[31:0] +// 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; +// 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; +// 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; +// 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; +// 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; +// 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; +// 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; +// 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; +// 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; +// 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; +// 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; +// 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; +// 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; +// 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; +// 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; //[31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_REO_queue_ext_descriptor + +reserved_1a + + + +struct rx_mpdu_link_ptr mpdu_link_pointer_0 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_1 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_2 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_3 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_4 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_5 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_6 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_7 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_8 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_9 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_10 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_11 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_12 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_13 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_14 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue +*/ + +#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 +#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_1_RESERVED_1A + + +*/ +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB 0 +#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB 0 +#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB 0 +#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB 0 +#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB 0 +#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB 0 +#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB 0 +#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB 0 +#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0 +#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0 +#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0 +#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0 +#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0 +#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0 +#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0 +#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0 +#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0 +#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0 +#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0 +#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0 +#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0 +#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0 +#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0 +#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0 +#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0 +#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0 +#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0 +#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0 +#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0 +#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff +#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0 +#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff + + +#endif // _RX_REO_QUEUE_EXT_H_ diff --git a/hw/qca8074/v1/rxpt_classify_info.h b/hw/qca8074/v1/rxpt_classify_info.h new file mode 100644 index 000000000000..216c2dd9e480 --- /dev/null +++ b/hw/qca8074/v1/rxpt_classify_info.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_destination_indication[4:0], use_flow_id_toeplitz_clfy[5], reserved_0a[31:6] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { + uint32_t reo_destination_indication : 5, //[4:0] + use_flow_id_toeplitz_clfy : 1, //[5] + reserved_0a : 26; //[31:6] +}; + +/* + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +use_flow_id_toeplitz_clfy + + indication to Rx OLE to enable classification based on + 'flow_id_toeplitz' from Common Parser, in case flow search + fails + + + +reserved_0a + + +*/ + + +/* Description RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f + +/* Description RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY + + indication to Rx OLE to enable classification based on + 'flow_id_toeplitz' from Common Parser, in case flow search + fails + + +*/ +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 5 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000020 + +/* Description RXPT_CLASSIFY_INFO_0_RESERVED_0A + + +*/ +#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_LSB 6 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_MASK 0xffffffc0 + + +#endif // _RXPT_CLASSIFY_INFO_H_ diff --git a/hw/qca8074/v1/seq_hwio.h b/hw/qca8074/v1/seq_hwio.h new file mode 100644 index 000000000000..fd489f20d8a1 --- /dev/null +++ b/hw/qca8074/v1/seq_hwio.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/********************************************************************************* + * + * DESCRIPTION + * - This is an extension of standard msmhwio.h to support relative addressing + * scheme used in SCALe auto-generated sequences. + * - The objective of this new addressing scheme is enable the same C function + * definition to be applicable to multiple baseances of the same block. + * - Such code reuse is not feasible with the standard HWIO macros that use a + * absolute addressing scheme. + * - Compared to the standard HWIO macros, the new macros defined here take an + * additional parameter 'baseance offset'. So are the C functions generated + * by SCALe Autoseq from .seq inputs. + * - As such, macros defined in this file must be used with 'seq_msmhwiobase.h', + * 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq. + * - Macros defined in this file leverage the lower-level macros from the + * standard 'msmhwio.h', and the two sets of macros are compatible. + * + ********************************************************************************/ + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + + + +/**** Register Ref Read ****/ +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +/**** Masked Register Read ****/ +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + + +/**** Ref Reg Field Read ****/ +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + + +/**** Ref Register Write ****/ +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +/**** Ref Register Masked Write ****/ +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + + +/**** Ref Register Field Write ****/ +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + + +/**** seq_msg() **** + +typedef enum { + DEBUG, + INFO, + WARNING, + ERROR, + FATAL +} SeverityLevel ; + +void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... ); + +*/ + +/************ seq_wait() ************/ + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + + +/************ seq_poll() ************/ +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif /* __SEQ_H__ */ + + + + + + + + + + + + + + + + + + + diff --git a/hw/qca8074/v1/sw_xml_headers.h b/hw/qca8074/v1/sw_xml_headers.h new file mode 100644 index 000000000000..f263386f85be --- /dev/null +++ b/hw/qca8074/v1/sw_xml_headers.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + +#ifndef _SW_XML_HEADERS_H_ +#define _SW_XML_HEADERS_H_ + + +#include "ack_report.h" +#include "addr_search_entry.h" +#include "buffer_addr_info.h" +#include "cce_rule.h" +#include "ce_src_desc.h" +#include "he_sig_a_mu_dl_info.h" +#include "he_sig_a_mu_ul_info.h" +#include "he_sig_a_su_info.h" +#include "he_sig_b1_mu_info.h" +#include "he_sig_b2_mu_info.h" +#include "he_sig_b2_ofdma_info.h" +#include "ht_sig_info.h" +#include "l_sig_a_info.h" +#include "l_sig_b_info.h" +#include "mactx_abort_request_info.h" +#include "mimo_control_info.h" +#include "no_ack_report.h" +#include "pcu_ppdu_setup_end_info.h" +#include "pdg_response_rate_setting.h" +#include "peer_table_entry.h" +#include "phyrx_abort_request_info.h" +#include "ppdu_rate_setting.h" +#include "prot_rate_setting.h" +#include "receive_rssi_info.h" +#include "receive_user_info.h" +#include "received_trigger_info_details.h" +#include "reo_destination_ring.h" +#include "reo_entrance_ring.h" +#include "reo_to_ppe_ring.h" +#include "response_rate_setting.h" +#include "rx_flow_search_entry.h" +#include "rx_location_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_mpdu_details.h" +#include "rx_mpdu_info.h" +#include "rx_mpdu_link.h" +#include "rx_mpdu_link_ptr.h" +#include "rx_msdu_desc_info.h" +#include "rx_msdu_details.h" +#include "rx_msdu_link.h" +#include "rx_peer_entry_details.h" +#include "rx_reo_queue.h" +#include "rx_reo_queue_ext.h" +#include "rx_reo_queue_reference.h" +#include "rx_rxpcu_classification_overview.h" +#include "rx_timing_offset_info.h" +#include "rxole_cce_classify_info.h" +#include "rxole_cce_info.h" +#include "rxole_cce_superrule.h" +#include "rxpt_classify_info.h" +#include "scheduler_cmd.h" +#include "service_info.h" +#include "sw_peer_info.h" +#include "tcl_cce_classify_info.h" +#include "tcl_cce_info.h" +#include "tcl_cce_superrule.h" +#include "tcl_compact_exit_ring.h" +#include "tcl_entrance_from_ppe_ring.h" +#include "tcl_exit_base.h" +#include "tcl_extended_exit_ring.h" +#include "tcl_regular_exit_ring.h" +#include "tcl_status_ring.h" +#include "tqm_entrance_ring.h" +#include "tx_flow_search_entry.h" +#include "tx_mpdu_details.h" +#include "tx_mpdu_link.h" +#include "tx_mpdu_link_ptr.h" +#include "tx_mpdu_queue_ext.h" +#include "tx_mpdu_queue_ext_ptr.h" +#include "tx_mpdu_queue_head.h" +#include "tx_msdu_details.h" +#include "tx_msdu_extension.h" +#include "tx_msdu_flow.h" +#include "tx_msdu_link.h" +#include "tx_msdu_link_entry_ptr.h" +#include "tx_rate_stats_info.h" +#include "txpcu_buffer_basics.h" +#include "txpt_classify_info.h" +#include "uniform_descriptor_header.h" +#include "uniform_reo_cmd_header.h" +#include "uniform_reo_status_header.h" +#include "uniform_tqm_cmd_header.h" +#include "uniform_tqm_status_header.h" +#include "uplink_common_info.h" +#include "uplink_user_setup_info.h" +#include "user_rate_setting.h" +#include "vht_sig_a_info.h" +#include "vht_sig_b_mu160_info.h" +#include "vht_sig_b_mu20_info.h" +#include "vht_sig_b_mu40_info.h" +#include "vht_sig_b_mu80_info.h" +#include "vht_sig_b_su160_info.h" +#include "vht_sig_b_su20_info.h" +#include "vht_sig_b_su40_info.h" +#include "vht_sig_b_su80_info.h" +#include "wbm_buffer_ring.h" +#include "wbm_link_descriptor_ring.h" +#include "wbm_release_ring.h" +#include "who_classify_info.h" +#include "macrx_abort_request_info.h" +#include "phytx_abort_request_info.h" +#include "ce_stat_desc.h" +#include "coex_mac_nap.h" +#include "coex_rx_status.h" +#include "coex_status_broadcast.h" +#include "coex_tx_req.h" +#include "coex_tx_resp.h" +#include "coex_tx_status.h" +#include "coex_tx_stop_ctrl.h" +#include "crypto_status.h" +#include "expected_response.h" +#include "mactx_abort_request.h" +#include "mactx_bf_params_common.h" +#include "mactx_coex_phy_ctrl.h" +#include "mactx_delete_cv.h" +#include "mactx_he_sig_a_mu_dl.h" +#include "mactx_he_sig_a_mu_ul.h" +#include "mactx_he_sig_a_su.h" +#include "mactx_he_sig_b1_mu.h" +#include "mactx_he_sig_b2_mu.h" +#include "mactx_he_sig_b2_ofdma.h" +#include "mactx_ht_sig.h" +#include "mactx_l_sig_a.h" +#include "mactx_l_sig_b.h" +#include "mactx_mu_uplink_common.h" +#include "mactx_phy_desc.h" +#include "mactx_phy_nap.h" +#include "mactx_pre_phy_desc.h" +#include "mactx_prefetch_cv.h" +#include "mactx_user_desc_common.h" +#include "mactx_vht_sig_a.h" +#include "mactx_vht_sig_b_su160.h" +#include "mactx_vht_sig_b_su20.h" +#include "mactx_vht_sig_b_su40.h" +#include "mactx_vht_sig_b_su80.h" +#include "ofdma_trigger_details.h" +#include "ole_buf_status.h" +#include "pcu_ppdu_setup_end.h" +#include "pcu_ppdu_setup_init.h" +#include "pcu_ppdu_setup_start.h" +#include "pdg_fes_setup.h" +#include "pdg_response.h" +#include "pdg_sw_mode_bw_start.h" +#include "pdg_tx_req.h" +#include "pdg_wait_for_mac_request.h" +#include "pdg_wait_for_phy_request.h" +#include "phyrx_cbf_read_request_ack.h" +#include "phyrx_generated_cbf_details.h" +#include "phyrx_he_sig_a_mu_dl.h" +#include "phyrx_he_sig_a_mu_ul.h" +#include "phyrx_he_sig_a_su.h" +#include "phyrx_he_sig_b1_mu.h" +#include "phyrx_he_sig_b2_mu.h" +#include "phyrx_he_sig_b2_ofdma.h" +#include "phyrx_ht_sig.h" +#include "phyrx_l_sig_a.h" +#include "phyrx_l_sig_b.h" +#include "phyrx_pkt_end.h" +#include "phyrx_rssi_ht.h" +#include "phyrx_rssi_legacy.h" +#include "phyrx_vht_sig_a.h" +#include "phyrx_vht_sig_b_su160.h" +#include "phyrx_vht_sig_b_su20.h" +#include "phyrx_vht_sig_b_su40.h" +#include "phyrx_vht_sig_b_su80.h" +#include "received_response_info.h" +#include "received_trigger_info.h" +#include "reo_descriptor_threshold_reached_status.h" +#include "reo_flush_cache.h" +#include "reo_flush_cache_status.h" +#include "reo_flush_queue.h" +#include "reo_flush_queue_status.h" +#include "reo_flush_timeout_list.h" +#include "reo_flush_timeout_list_status.h" +#include "reo_get_queue_stats.h" +#include "reo_get_queue_stats_status.h" +#include "reo_unblock_cache.h" +#include "reo_unblock_cache_status.h" +#include "reo_update_rx_reo_queue.h" +#include "reo_update_rx_reo_queue_status.h" +#include "response_end_status.h" +#include "response_start_status.h" +#include "rx_frame_bitmap_req.h" +#include "rx_frameless_bar_details.h" +#include "rx_pm_info.h" +#include "rx_ppdu_ack_report.h" +#include "rx_ppdu_end_status_done.h" +#include "rx_ppdu_no_ack_report.h" +#include "rx_ppdu_start.h" +#include "rx_preamble.h" +#include "rx_response_required_info.h" +#include "rx_ring_mask.h" +#include "rx_start_param.h" +#include "rx_trig_info.h" +#include "rxpcu_ppdu_end_info.h" +#include "rxpcu_setup.h" +#include "sch_coex_status.h" +#include "sch_wait_instr.h" +#include "scheduler_command_status.h" +#include "scheduler_rx_ppdu_no_response_status.h" +#include "scheduler_rx_sifs_response_trigger_status.h" +#include "scheduler_selfgen_response_status.h" +#include "tcl_data_cmd.h" +#include "tcl_gse_cmd.h" +#include "tqm_acked_mpdu_status.h" +#include "tqm_add_msdu_status.h" +#include "tqm_descriptor_threshold_reached_status.h" +#include "tqm_flow_empty_status.h" +#include "tqm_flow_not_empty_status.h" +#include "tqm_flush_cache.h" +#include "tqm_flush_cache_status.h" +#include "tqm_gen_mpdu_length_list.h" +#include "tqm_gen_mpdu_length_list_status.h" +#include "tqm_gen_mpdus.h" +#include "tqm_gen_mpdus_status.h" +#include "tqm_get_mpdu_head_info.h" +#include "tqm_get_mpdu_head_info_status.h" +#include "tqm_get_mpdu_queue_stats.h" +#include "tqm_get_mpdu_queue_stats_status.h" +#include "tqm_get_msdu_flow_stats.h" +#include "tqm_get_msdu_flow_stats_status.h" +#include "tqm_remove_mpdu.h" +#include "tqm_remove_mpdu_status.h" +#include "tqm_remove_msdu.h" +#include "tqm_remove_msdu_status.h" +#include "tqm_sync_cmd.h" +#include "tqm_sync_cmd_status.h" +#include "tqm_threshold_drop_notification_status.h" +#include "tqm_unblock_cache.h" +#include "tqm_unblock_cache_status.h" +#include "tqm_update_tx_mpdu_count_status.h" +#include "tqm_update_tx_mpdu_queue_head.h" +#include "tqm_update_tx_mpdu_queue_head_status.h" +#include "tqm_update_tx_msdu_flow.h" +#include "tqm_update_tx_msdu_flow_status.h" +#include "tqm_write_cmd.h" +#include "tqm_write_cmd_status.h" +#include "tx_cbf_info.h" +#include "tx_data_sync.h" +#include "tx_fes_setup.h" +#include "tx_fes_status_end.h" +#include "tx_fes_status_prot.h" +#include "tx_fes_status_start.h" +#include "tx_fes_status_start_ppdu.h" +#include "tx_fes_status_start_prot.h" +#include "tx_flush_req.h" +#include "tx_sw_mode_setup.h" +#include "txpcu_buffer_status.h" +#include "who_terminate.h" +#include "data_to_time_config.h" +#include "mactx_bf_params_per_user.h" +#include "mactx_expect_cbf_common.h" +#include "mactx_expect_cbf_per_user.h" +#include "mactx_mu_uplink_user_setup.h" +#include "mactx_service.h" +#include "mactx_user_desc_per_user.h" +#include "mactx_vht_sig_b_mu160.h" +#include "mactx_vht_sig_b_mu20.h" +#include "mactx_vht_sig_b_mu40.h" +#include "mactx_vht_sig_b_mu80.h" +#include "mpdu_info.h" +#include "mpdu_info_bitmap.h" +#include "mpdu_limit.h" +#include "pcu_ppdu_setup_user.h" +#include "pdg_user_setup.h" +#include "phyrx_common_user_info.h" +#include "phyrx_user_info.h" +#include "phyrx_vht_sig_b_mu160.h" +#include "phyrx_vht_sig_b_mu20.h" +#include "phyrx_vht_sig_b_mu40.h" +#include "phyrx_vht_sig_b_mu80.h" +#include "rx_attention.h" +#include "rx_frame_bitmap_ack.h" +#include "rx_header.h" +#include "rx_mpdu_end.h" +#include "rx_mpdu_pcu_start.h" +#include "rx_mpdu_start.h" +#include "rx_msdu_end.h" +#include "rx_msdu_start.h" +#include "rx_peer_entry.h" +#include "rx_ppdu_end_user_stats.h" +#include "rx_ppdu_end_user_stats_ext.h" +#include "rx_ppdu_start_user_info.h" +#include "rxpcu_user_setup.h" +#include "rxpcu_user_setup_ext.h" +#include "tqm_acked_mpdu.h" +#include "tqm_update_tx_mpdu_count.h" +#include "tx_11ah_setup.h" +#include "tx_cv_start.h" +#include "tx_fes_status_ack_or_ba.h" +#include "tx_fes_status_user_ppdu.h" +#include "tx_fes_status_user_response.h" +#include "tx_mpdu_start.h" +#include "tx_msdu_start.h" +#include "tx_peer_entry.h" +#include "tx_queue_extension.h" +#include "tx_raw_or_native_frame_setup.h" +#include "txpcu_user_buffer_status.h" +#include "txpcu_user_setup.h" +#include "who_anchor_value.h" +#include "who_cce_info.h" +#include "who_commit_done.h" +#include "who_l2_llc.h" +#include "who_l3_checksum.h" +#include "who_l3_info.h" +#include "who_l4_checksum.h" +#include "who_l4_info.h" +#include "who_mesh_control.h" +#include "who_msdu_misc.h" +#include "who_packet_hdr.h" +#include "who_tso.h" +#include "who_wmac_header_pv0.h" +#include "who_wmac_header_pv1.h" +#include "who_wmac_iv.h" +#include "tlv_tag_def.h" +#include "mactx_cbf_data.h" +#include "mactx_cbf_done.h" +#include "mactx_cbf_start.h" +#include "mactx_data_resp.h" +#include "phyrx_abort_request.h" +#include "phyrx_cbf_data_resp.h" +#include "phyrx_data.h" +#include "phyrx_user_abort_notification.h" +#include "macrx_abort_request.h" +#include "macrx_cbf_data_request.h" +#include "macrx_cbf_read_request.h" +#include "macrx_chain_mask.h" +#include "macrx_expect_ndp_reception.h" +#include "macrx_freeze_capture_channel.h" +#include "macrx_req_implicit_fb.h" +#include "phytx_abort_request.h" +#include "phytx_bf_cv_loading_done.h" +#include "phytx_nap_ack.h" +#include "phytx_pkt_end.h" +#include "phytx_ppdu_header_info_request.h" +#include "phytx_request_ctrl_info.h" + + +#endif diff --git a/hw/qca8074/v1/tcl_data_cmd.h b/hw/qca8074/v1/tcl_data_cmd.h new file mode 100644 index 000000000000..dd4920945cde --- /dev/null +++ b/hw/qca8074/v1/tcl_data_cmd.h @@ -0,0 +1,890 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_addr_info; +// 2 buf_or_ext_desc_type[0], epd[1], encap_type[3:2], encrypt_type[7:4], src_buffer_swap[8], link_meta_swap[9], reserved[13:10], addrx_en[14], addry_en[15], tcl_cmd_number[31:16] +// 3 data_length[15:0], ipv4_checksum_en[16], udp_over_ipv4_checksum_en[17], udp_over_ipv6_checksum_en[18], tcp_over_ipv4_checksum_en[19], tcp_over_ipv6_checksum_en[20], to_fw[21], dscp_to_tid_priority_table_id[22], packet_offset[31:23] +// 4 buffer_timestamp[18:0], buffer_timestamp_valid[19], mesh_enable[20], hlos_tid_overwrite[21], hlos_tid[25:22], reserved_4[31:26] +// 5 reserved_5[31:0] +// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_DATA_CMD 7 + +struct tcl_data_cmd { + struct buffer_addr_info buf_addr_info; + uint32_t buf_or_ext_desc_type : 1, //[0] + epd : 1, //[1] + encap_type : 2, //[3:2] + encrypt_type : 4, //[7:4] + src_buffer_swap : 1, //[8] + link_meta_swap : 1, //[9] + reserved : 4, //[13:10] + addrx_en : 1, //[14] + addry_en : 1, //[15] + tcl_cmd_number : 16; //[31:16] + uint32_t data_length : 16, //[15:0] + ipv4_checksum_en : 1, //[16] + udp_over_ipv4_checksum_en : 1, //[17] + udp_over_ipv6_checksum_en : 1, //[18] + tcp_over_ipv4_checksum_en : 1, //[19] + tcp_over_ipv6_checksum_en : 1, //[20] + to_fw : 1, //[21] + dscp_to_tid_priority_table_id : 1, //[22] + packet_offset : 9; //[31:23] + uint32_t buffer_timestamp : 19, //[18:0] + buffer_timestamp_valid : 1, //[19] + mesh_enable : 1, //[20] + hlos_tid_overwrite : 1, //[21] + hlos_tid : 4, //[25:22] + reserved_4 : 6; //[31:26] + uint32_t reserved_5 : 32; //[31:0] + uint32_t reserved_6a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info buf_addr_info + + Details of the physical address for a single buffer + + It also contains return ownership info as well as some + meta data for SW related to this buffer. + + + + In case of Buf_or_ext_desc_type indicating + 'MSDU_buffer', this address indicates the start of the meta + data that is preceding the actual packet data. + + The start of the actual packet data is provided by + field: Packet_offset + +buf_or_ext_desc_type + + The address points to an MSDU + buffer. + + The address points to an + MSDU link extension descriptor + + < legal all> + +epd + + When this bit is set then input packet is an EPD type + + + +encap_type + + Indicates the encapsulation that HW will perform: + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + Used by the OLE during encapsulation. + + + +encrypt_type + + Field only valid for encap_type: RAW + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + +src_buffer_swap + + Treats source memory (packet buffer) organization as + big-endian. The packets are read and byte swapped. + + 1'b0: Source memory is little endian + + 1'b1: Source memory is big endian + + + +link_meta_swap + + Treats link descriptor and Metadata as big-endian. The + link descriptor/Metadata is read and byte swapped. + + 1'b0: Memory is little endian + + 1'b1: Memory is big endian + + + +reserved + + + +addrx_en + + Address X search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + + +addry_en + + Address Y search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + + +tcl_cmd_number + + This number can be used by SW to track, identify and + link the created commands with the command statuses + + + + Is set to the value 'TCL_CMD_Number' of the related + TCL_DATA command + + + +data_length + + Valid Data length in bytes. + + + + MSDU length in case of direct descriptor. + + Length of link extension descriptor in case of Link + extension descriptor. This is used to know the size of + Metadata. + + + +ipv4_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable IPv4 checksum replacement + +udp_over_ipv4_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. + +udp_over_ipv6_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. + +tcp_over_ipv4_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv4 replacement + +tcp_over_ipv6_checksum_en + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv6 replacement + +to_fw + + Forward packet to FW along with classification result. + The packet will not be forward to TQM when this bit is set + + 1'b0: Use classification result to forward the packet. + + 1'b1: Override classification result and forward packet + only to FW. + +dscp_to_tid_priority_table_id + + The DSCP to tid conversion table to be used for this + frame + + + +packet_offset + + Packet offset from Metadata in case of direct buffer + descriptor. This field is valid when Buf_or_ext_desc_type is + reset(= 0). + + + +buffer_timestamp + + Field only valid when 'Buffer_timestamp_valid ' is set. + + + + Frame system entrance timestamp. The timestamp is + related to the global system timer + + + + Generally the first module (SW, TCL or TQM). that sees + this frame and this timestamp field is not valid, shall fill + in this field. + + + + Timestamp in units of 1024 us + +buffer_timestamp_valid + + When set, the Buffer_timestamp field contains valid + info. + +mesh_enable + + If set to 1: + + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit is + ignored), + + * For native WiFi frames, this indicates that a 'Mesh + Control' field is present between the header and the LLC. + +hlos_tid_overwrite + + When set, TCL shall ignore the IP DSCP and VLAN PCP + fields and use HLOS_TID as the final TID. Otherwise TCL + shall consider the DSCP and PCP fields as well as HLOS_TID + and choose a final TID based on the configured priority + + + +hlos_tid + + HLOS MSDU priority + + + + Field is used when HLOS_TID_overwrite is set. + + + + Field is also used when HLOS_TID_overwrite is not set + and DSCP/PCP is not available in the packet + + + +reserved_4 + + + +reserved_5 + + + +reserved_6a + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000000 +#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 28 +#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff +#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 28 +#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff + +/* Description TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE + + The address points to an MSDU + buffer. + + The address points to an + MSDU link extension descriptor + + < legal all> +*/ +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 + +/* Description TCL_DATA_CMD_2_EPD + + When this bit is set then input packet is an EPD type + + +*/ +#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_EPD_LSB 1 +#define TCL_DATA_CMD_2_EPD_MASK 0x00000002 + +/* Description TCL_DATA_CMD_2_ENCAP_TYPE + + Indicates the encapsulation that HW will perform: + + No encapsulation + + + + Ethernet 2 (DIX) + + 802.3 (uses SNAP/LLC) + + Used by the OLE during encapsulation. + + +*/ +#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 +#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c + +/* Description TCL_DATA_CMD_2_ENCRYPT_TYPE + + Field only valid for encap_type: RAW + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + +*/ +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 + +/* Description TCL_DATA_CMD_2_SRC_BUFFER_SWAP + + Treats source memory (packet buffer) organization as + big-endian. The packets are read and byte swapped. + + 1'b0: Source memory is little endian + + 1'b1: Source memory is big endian + + +*/ +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 + +/* Description TCL_DATA_CMD_2_LINK_META_SWAP + + Treats link descriptor and Metadata as big-endian. The + link descriptor/Metadata is read and byte swapped. + + 1'b0: Memory is little endian + + 1'b1: Memory is big endian + + +*/ +#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 +#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 + +/* Description TCL_DATA_CMD_2_RESERVED + + +*/ +#define TCL_DATA_CMD_2_RESERVED_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_RESERVED_LSB 10 +#define TCL_DATA_CMD_2_RESERVED_MASK 0x00003c00 + +/* Description TCL_DATA_CMD_2_ADDRX_EN + + Address X search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + +*/ +#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 +#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 + +/* Description TCL_DATA_CMD_2_ADDRY_EN + + Address Y search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + +*/ +#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 +#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 + +/* Description TCL_DATA_CMD_2_TCL_CMD_NUMBER + + This number can be used by SW to track, identify and + link the created commands with the command statuses + + + + Is set to the value 'TCL_CMD_Number' of the related + TCL_DATA command + + +*/ +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 + +/* Description TCL_DATA_CMD_3_DATA_LENGTH + + Valid Data length in bytes. + + + + MSDU length in case of direct descriptor. + + Length of link extension descriptor in case of Link + extension descriptor. This is used to know the size of + Metadata. + + +*/ +#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff + +/* Description TCL_DATA_CMD_3_IPV4_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable IPv4 checksum replacement +*/ +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 + +/* Description TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +/* Description TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +/* Description TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv4 replacement +*/ +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +/* Description TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN + + Field only valid when msdu_buffer_type is set to + MSDU_buffer. + + + + OLE related control + + Enable TCP checksum over IPv6 replacement +*/ +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +/* Description TCL_DATA_CMD_3_TO_FW + + Forward packet to FW along with classification result. + The packet will not be forward to TQM when this bit is set + + 1'b0: Use classification result to forward the packet. + + 1'b1: Override classification result and forward packet + only to FW. +*/ +#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TO_FW_LSB 21 +#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 + +/* Description TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID + + The DSCP to tid conversion table to be used for this + frame + + +*/ +#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_LSB 22 +#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_MASK 0x00400000 + +/* Description TCL_DATA_CMD_3_PACKET_OFFSET + + Packet offset from Metadata in case of direct buffer + descriptor. This field is valid when Buf_or_ext_desc_type is + reset(= 0). + + +*/ +#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 + +/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP + + Field only valid when 'Buffer_timestamp_valid ' is set. + + + + Frame system entrance timestamp. The timestamp is + related to the global system timer + + + + Generally the first module (SW, TCL or TQM). that sees + this frame and this timestamp field is not valid, shall fill + in this field. + + + + Timestamp in units of 1024 us +*/ +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff + +/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID + + When set, the Buffer_timestamp field contains valid + info. +*/ +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 + +/* Description TCL_DATA_CMD_4_MESH_ENABLE + + If set to 1: + + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit is + ignored), + + * For native WiFi frames, this indicates that a 'Mesh + Control' field is present between the header and the LLC. +*/ +#define TCL_DATA_CMD_4_MESH_ENABLE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_MESH_ENABLE_LSB 20 +#define TCL_DATA_CMD_4_MESH_ENABLE_MASK 0x00100000 + +/* Description TCL_DATA_CMD_4_HLOS_TID_OVERWRITE + + When set, TCL shall ignore the IP DSCP and VLAN PCP + fields and use HLOS_TID as the final TID. Otherwise TCL + shall consider the DSCP and PCP fields as well as HLOS_TID + and choose a final TID based on the configured priority + + +*/ +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 + +/* Description TCL_DATA_CMD_4_HLOS_TID + + HLOS MSDU priority + + + + Field is used when HLOS_TID_overwrite is set. + + + + Field is also used when HLOS_TID_overwrite is not set + and DSCP/PCP is not available in the packet + + +*/ +#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_LSB 22 +#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 + +/* Description TCL_DATA_CMD_4_RESERVED_4 + + +*/ +#define TCL_DATA_CMD_4_RESERVED_4_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4_LSB 26 +#define TCL_DATA_CMD_4_RESERVED_4_MASK 0xfc000000 + +/* Description TCL_DATA_CMD_5_RESERVED_5 + + +*/ +#define TCL_DATA_CMD_5_RESERVED_5_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_RESERVED_5_LSB 0 +#define TCL_DATA_CMD_5_RESERVED_5_MASK 0xffffffff + +/* Description TCL_DATA_CMD_6_RESERVED_6A + + +*/ +#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 +#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff + +/* Description TCL_DATA_CMD_6_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RING_ID_LSB 20 +#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 + +/* Description TCL_DATA_CMD_6_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_DATA_CMD_H_ diff --git a/hw/qca8074/v1/tcl_gse_cmd.h b/hw/qca8074/v1/tcl_gse_cmd.h new file mode 100644 index 000000000000..56eee91a6ca9 --- /dev/null +++ b/hw/qca8074/v1/tcl_gse_cmd.h @@ -0,0 +1,408 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 control_buffer_addr_31_0[31:0] +// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15] +// 2 cmd_meta_data_31_0[31:0] +// 3 cmd_meta_data_63_32[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_GSE_CMD 7 + +struct tcl_gse_cmd { + uint32_t control_buffer_addr_31_0 : 32; //[31:0] + uint32_t control_buffer_addr_39_32 : 8, //[7:0] + gse_ctrl : 4, //[11:8] + gse_sel : 1, //[12] + status_destination_ring_id : 1, //[13] + swap : 1, //[14] + reserved_1a : 17; //[31:15] + uint32_t cmd_meta_data_31_0 : 32; //[31:0] + uint32_t cmd_meta_data_63_32 : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +control_buffer_addr_31_0 + + Address (lower 32 bits) of a control buffer containing + additional info needed for this command execution. + + + +control_buffer_addr_39_32 + + Address (upper 8 bits) of a control buffer containing + additional info needed for this command execution. + + + +gse_ctrl + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported + +gse_sel + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + + 0: FSE select + + 1: ASE select + +status_destination_ring_id + + The TCL status ring to which the GSE status needs to be + send. + + + + + + + + + + + +swap + + Bit to enable byte swapping of contents of buffer + + + + + + + +reserved_1a + + + +cmd_meta_data_31_0 + + Meta data to be returned in the status descriptor + + + +cmd_meta_data_63_32 + + Meta data to be returned in the status descriptor + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +ring_id + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of a control buffer containing + additional info needed for this command execution. + + +*/ +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of a control buffer containing + additional info needed for this command execution. + + +*/ +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description TCL_GSE_CMD_1_GSE_CTRL + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported +*/ +#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 + +/* Description TCL_GSE_CMD_1_GSE_SEL + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + + 0: FSE select + + 1: ASE select +*/ +#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 + +/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID + + The TCL status ring to which the GSE status needs to be + send. + + + + + + + + + + +*/ +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +/* Description TCL_GSE_CMD_1_SWAP + + Bit to enable byte swapping of contents of buffer + + + + + + +*/ +#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_SWAP_LSB 14 +#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 + +/* Description TCL_GSE_CMD_1_RESERVED_1A + + +*/ +#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_RESERVED_1A_LSB 15 +#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xffff8000 + +/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 + + Meta data to be returned in the status descriptor + + +*/ +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff + +/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 + + Meta data to be returned in the status descriptor + + +*/ +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff + +/* Description TCL_GSE_CMD_4_RESERVED_4A + + +*/ +#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 +#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff + +/* Description TCL_GSE_CMD_5_RESERVED_5A + + +*/ +#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff + +/* Description TCL_GSE_CMD_6_RESERVED_6A + + +*/ +#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff + +/* Description TCL_GSE_CMD_6_RING_ID + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RING_ID_LSB 20 +#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 + +/* Description TCL_GSE_CMD_6_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_GSE_CMD_H_ diff --git a/hw/qca8074/v1/tcl_status_ring.h b/hw/qca8074/v1/tcl_status_ring.h new file mode 100644 index 000000000000..c4178c93da33 --- /dev/null +++ b/hw/qca8074/v1/tcl_status_ring.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], reserved_0a[7], msdu_cnt_n[31:8] +// 1 msdu_byte_cnt_n[31:0] +// 2 msdu_timestmp_n[31:0] +// 3 cmd_meta_data_31_0[31:0] +// 4 cmd_meta_data_63_32[31:0] +// 5 hash_indx_val[19:0], reserved_5a[31:20] +// 6 reserved_6a[31:0] +// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { + uint32_t gse_ctrl : 4, //[3:0] + ase_fse_sel : 1, //[4] + cache_op_res : 2, //[6:5] + reserved_0a : 1, //[7] + msdu_cnt_n : 24; //[31:8] + uint32_t msdu_byte_cnt_n : 32; //[31:0] + uint32_t msdu_timestmp_n : 32; //[31:0] + uint32_t cmd_meta_data_31_0 : 32; //[31:0] + uint32_t cmd_meta_data_63_32 : 32; //[31:0] + uint32_t hash_indx_val : 20, //[19:0] + reserved_5a : 12; //[31:20] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +gse_ctrl + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported + +ase_fse_sel + + Search Engine for which operation is done. + + 1'b0: Address Search Engine Result + + 1'b1: Flow Search Engine result + +cache_op_res + + Cache operation result. Following are results of cache + operation. + + Operation successful + + Entry not found in Table + + Timeout Error + + + +reserved_0a + + + +msdu_cnt_n + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 + +msdu_byte_cnt_n + + MSDU byte count for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 + +msdu_timestmp_n + + MSDU timestamp for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 + +cmd_meta_data_31_0 + + Meta data from input ring + + + +cmd_meta_data_63_32 + + Meta data from input ring + + + +hash_indx_val + + + Hash value of the entry in table in case of search + failed or search disable. + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +ring_id + + The buffer pointer ring ID. + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description TCL_STATUS_RING_0_GSE_CTRL + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported +*/ +#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f + +/* Description TCL_STATUS_RING_0_ASE_FSE_SEL + + Search Engine for which operation is done. + + 1'b0: Address Search Engine Result + + 1'b1: Flow Search Engine result +*/ +#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 + +/* Description TCL_STATUS_RING_0_CACHE_OP_RES + + Cache operation result. Following are results of cache + operation. + + Operation successful + + Entry not found in Table + + Timeout Error + + +*/ +#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 + +/* Description TCL_STATUS_RING_0_RESERVED_0A + + +*/ +#define TCL_STATUS_RING_0_RESERVED_0A_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_RESERVED_0A_LSB 7 +#define TCL_STATUS_RING_0_RESERVED_0A_MASK 0x00000080 + +/* Description TCL_STATUS_RING_0_MSDU_CNT_N + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 +*/ +#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 + +/* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N + + MSDU byte count for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 +*/ +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff + +/* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N + + MSDU timestamp for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 +*/ +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff + +/* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0 + + Meta data from input ring + + +*/ +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff + +/* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32 + + Meta data from input ring + + +*/ +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff + +/* Description TCL_STATUS_RING_5_HASH_INDX_VAL + + + Hash value of the entry in table in case of search + failed or search disable. + + +*/ +#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff + +/* Description TCL_STATUS_RING_5_RESERVED_5A + + +*/ +#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_RESERVED_5A_LSB 20 +#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xfff00000 + +/* Description TCL_STATUS_RING_6_RESERVED_6A + + +*/ +#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff + +/* Description TCL_STATUS_RING_7_RESERVED_7A + + +*/ +#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff + +/* Description TCL_STATUS_RING_7_RING_ID + + The buffer pointer ring ID. + + + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RING_ID_LSB 20 +#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description TCL_STATUS_RING_7_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_STATUS_RING_H_ diff --git a/hw/qca8074/v1/tlv_hdr.h b/hw/qca8074/v1/tlv_hdr.h new file mode 100644 index 000000000000..17957c0d8946 --- /dev/null +++ b/hw/qca8074/v1/tlv_hdr.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +struct tlv_usr_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_usrid : 6; +}; + +struct tlv_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_reserved : 6; +}; + +struct tlv_usr_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6; +}; + +struct tlv_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 6; +}; + +struct tlv_usr_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6, + tlv_reserved : 10, + pad_42to64_bit : 22; +}; + +struct tlv_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 16, + pad_42to64_bit : 22; +}; + +struct tlv_usr_c_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_ctag : 3, + tlv_usrid : 6, + tlv_cdata : 32, + pad_42to64_bit : 22; +}; + +#endif diff --git a/hw/qca8074/v1/tlv_tag_def.h b/hw/qca8074/v1/tlv_tag_def.h new file mode 100644 index 000000000000..ca0c5aff3037 --- /dev/null +++ b/hw/qca8074/v1/tlv_tag_def.h @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * Generated file ... Do not hand edit ... + */ + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum { + + WIFIMACTX_CBF_START_E = 0 /* 0x0 */, + WIFIPHYRX_DATA_E = 1 /* 0x1 */, + WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */, + WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */, + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */, + WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */, + WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */, + WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */, + WIFIMACRX_CBF_READ_REQUEST_E = 8 /* 0x8 */, + WIFIMACRX_CBF_DATA_REQUEST_E = 9 /* 0x9 */, + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 /* 0xa */, + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 /* 0xb */, + WIFIMACRX_NDP_TIMEOUT_E = 12 /* 0xc */, + WIFIMACRX_ABORT_ACK_E = 13 /* 0xd */, + WIFIMACRX_REQ_IMPLICIT_FB_E = 14 /* 0xe */, + WIFIMACRX_CHAIN_MASK_E = 15 /* 0xf */, + WIFIMACRX_NAP_USER_E = 16 /* 0x10 */, + WIFIMACRX_ABORT_REQUEST_E = 17 /* 0x11 */, + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 /* 0x12 */, + WIFIPHYTX_ABORT_ACK_E = 19 /* 0x13 */, + WIFIPHYTX_ABORT_REQUEST_E = 20 /* 0x14 */, + WIFIPHYTX_PKT_END_E = 21 /* 0x15 */, + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 /* 0x16 */, + WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 /* 0x17 */, + WIFIPHYTX_DATA_REQUEST_E = 24 /* 0x18 */, + WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 /* 0x19 */, + WIFIPHYTX_NAP_ACK_E = 26 /* 0x1a */, + WIFIPHYTX_NAP_DONE_E = 27 /* 0x1b */, + WIFIPHYTX_OFF_ACK_E = 28 /* 0x1c */, + WIFIPHYTX_ON_ACK_E = 29 /* 0x1d */, + WIFIPHYTX_SYNTH_OFF_ACK_E = 30 /* 0x1e */, + WIFIPHYTX_DEBUG16_E = 31 /* 0x1f */, + WIFIMACTX_ABORT_REQUEST_E = 32 /* 0x20 */, + WIFIMACTX_ABORT_ACK_E = 33 /* 0x21 */, + WIFIMACTX_PKT_END_E = 34 /* 0x22 */, + WIFIMACTX_PRE_PHY_DESC_E = 35 /* 0x23 */, + WIFIMACTX_BF_PARAMS_COMMON_E = 36 /* 0x24 */, + WIFIMACTX_BF_PARAMS_PER_USER_E = 37 /* 0x25 */, + WIFIMACTX_PREFETCH_CV_E = 38 /* 0x26 */, + WIFIMACTX_USER_DESC_COMMON_E = 39 /* 0x27 */, + WIFIMACTX_USER_DESC_PER_USER_E = 40 /* 0x28 */, + WIFIEXAMPLE_USER_TLV_16_E = 41 /* 0x29 */, + WIFIEXAMPLE_TLV_16_E = 42 /* 0x2a */, + WIFIMACTX_PHY_OFF_E = 43 /* 0x2b */, + WIFIMACTX_PHY_ON_E = 44 /* 0x2c */, + WIFIMACTX_SYNTH_OFF_E = 45 /* 0x2d */, + WIFIMACTX_EXPECT_CBF_COMMON_E = 46 /* 0x2e */, + WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 /* 0x2f */, + WIFIMACTX_PHY_DESC_E = 48 /* 0x30 */, + WIFIMACTX_L_SIG_A_E = 49 /* 0x31 */, + WIFIMACTX_L_SIG_B_E = 50 /* 0x32 */, + WIFIMACTX_HT_SIG_E = 51 /* 0x33 */, + WIFIMACTX_VHT_SIG_A_E = 52 /* 0x34 */, + WIFIMACTX_VHT_SIG_B_SU20_E = 53 /* 0x35 */, + WIFIMACTX_VHT_SIG_B_SU40_E = 54 /* 0x36 */, + WIFIMACTX_VHT_SIG_B_SU80_E = 55 /* 0x37 */, + WIFIMACTX_VHT_SIG_B_SU160_E = 56 /* 0x38 */, + WIFIMACTX_VHT_SIG_B_MU20_E = 57 /* 0x39 */, + WIFIMACTX_VHT_SIG_B_MU40_E = 58 /* 0x3a */, + WIFIMACTX_VHT_SIG_B_MU80_E = 59 /* 0x3b */, + WIFIMACTX_VHT_SIG_B_MU160_E = 60 /* 0x3c */, + WIFIMACTX_SERVICE_E = 61 /* 0x3d */, + WIFIMACTX_HE_SIG_A_SU_E = 62 /* 0x3e */, + WIFIMACTX_HE_SIG_A_MU_DL_E = 63 /* 0x3f */, + WIFIMACTX_HE_SIG_A_MU_UL_E = 64 /* 0x40 */, + WIFIMACTX_HE_SIG_B1_MU_E = 65 /* 0x41 */, + WIFIMACTX_HE_SIG_B2_MU_E = 66 /* 0x42 */, + WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 /* 0x43 */, + WIFIMACTX_DELETE_CV_E = 68 /* 0x44 */, + WIFIMACTX_MU_UPLINK_COMMON_E = 69 /* 0x45 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 /* 0x46 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 /* 0x47 */, + WIFIMACTX_PHY_NAP_E = 72 /* 0x48 */, + WIFIMACTX_DEBUG_E = 73 /* 0x49 */, + WIFIPHYRX_ABORT_ACK_E = 74 /* 0x4a */, + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 /* 0x4b */, + WIFIPHYRX_RSSI_LEGACY_E = 76 /* 0x4c */, + WIFIPHYRX_RSSI_HT_E = 77 /* 0x4d */, + WIFIPHYRX_USER_INFO_E = 78 /* 0x4e */, + WIFIPHYRX_PKT_END_E = 79 /* 0x4f */, + WIFIPHYRX_DEBUG_E = 80 /* 0x50 */, + WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 /* 0x51 */, + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 /* 0x52 */, + WIFIPHYRX_L_SIG_A_E = 83 /* 0x53 */, + WIFIPHYRX_L_SIG_B_E = 84 /* 0x54 */, + WIFIPHYRX_HT_SIG_E = 85 /* 0x55 */, + WIFIPHYRX_VHT_SIG_A_E = 86 /* 0x56 */, + WIFIPHYRX_VHT_SIG_B_SU20_E = 87 /* 0x57 */, + WIFIPHYRX_VHT_SIG_B_SU40_E = 88 /* 0x58 */, + WIFIPHYRX_VHT_SIG_B_SU80_E = 89 /* 0x59 */, + WIFIPHYRX_VHT_SIG_B_SU160_E = 90 /* 0x5a */, + WIFIPHYRX_VHT_SIG_B_MU20_E = 91 /* 0x5b */, + WIFIPHYRX_VHT_SIG_B_MU40_E = 92 /* 0x5c */, + WIFIPHYRX_VHT_SIG_B_MU80_E = 93 /* 0x5d */, + WIFIPHYRX_VHT_SIG_B_MU160_E = 94 /* 0x5e */, + WIFIPHYRX_HE_SIG_A_SU_E = 95 /* 0x5f */, + WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 /* 0x60 */, + WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 /* 0x61 */, + WIFIPHYRX_HE_SIG_B1_MU_E = 98 /* 0x62 */, + WIFIPHYRX_HE_SIG_B2_MU_E = 99 /* 0x63 */, + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 /* 0x64 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 /* 0x65 */, + WIFIPHYRX_COMMON_USER_INFO_E = 102 /* 0x66 */, + WIFIPHYRX_DATA_DONE_E = 103 /* 0x67 */, + WIFIRECEIVE_RSSI_INFO_E = 104 /* 0x68 */, + WIFIRECEIVE_USER_INFO_E = 105 /* 0x69 */, + WIFIMIMO_CONTROL_INFO_E = 106 /* 0x6a */, + WIFIRX_LOCATION_INFO_E = 107 /* 0x6b */, + WIFICOEX_TX_REQ_E = 108 /* 0x6c */, + WIFIDUMMY_E = 109 /* 0x6d */, + WIFIRX_TIMING_OFFSET_INFO_E = 110 /* 0x6e */, + WIFIEXAMPLE_TLV_32_NAME_E = 111 /* 0x6f */, + WIFIMPDU_LIMIT_E = 112 /* 0x70 */, + WIFINA_LENGTH_END_E = 113 /* 0x71 */, + WIFIOLE_BUF_STATUS_E = 114 /* 0x72 */, + WIFIPCU_PPDU_SETUP_DONE_E = 115 /* 0x73 */, + WIFIPCU_PPDU_SETUP_END_E = 116 /* 0x74 */, + WIFIPCU_PPDU_SETUP_INIT_E = 117 /* 0x75 */, + WIFIPCU_PPDU_SETUP_START_E = 118 /* 0x76 */, + WIFIPDG_FES_SETUP_E = 119 /* 0x77 */, + WIFIPDG_RESPONSE_E = 120 /* 0x78 */, + WIFIPDG_TX_REQ_E = 121 /* 0x79 */, + WIFISCH_WAIT_INSTR_E = 122 /* 0x7a */, + WIFISCHEDULER_TLV_E = 123 /* 0x7b */, + WIFITQM_FLOW_EMPTY_STATUS_E = 124 /* 0x7c */, + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 /* 0x7d */, + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 /* 0x7e */, + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 /* 0x7f */, + WIFITQM_GEN_MPDUS_E = 128 /* 0x80 */, + WIFITQM_GEN_MPDUS_STATUS_E = 129 /* 0x81 */, + WIFITQM_REMOVE_MPDU_E = 130 /* 0x82 */, + WIFITQM_REMOVE_MPDU_STATUS_E = 131 /* 0x83 */, + WIFITQM_REMOVE_MSDU_E = 132 /* 0x84 */, + WIFITQM_REMOVE_MSDU_STATUS_E = 133 /* 0x85 */, + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 /* 0x86 */, + WIFITQM_WRITE_CMD_E = 135 /* 0x87 */, + WIFIOFDMA_TRIGGER_DETAILS_E = 136 /* 0x88 */, + WIFITX_DATA_E = 137 /* 0x89 */, + WIFITX_FES_SETUP_E = 138 /* 0x8a */, + WIFIRX_PACKET_E = 139 /* 0x8b */, + WIFIEXPECTED_RESPONSE_E = 140 /* 0x8c */, + WIFITX_MPDU_END_E = 141 /* 0x8d */, + WIFITX_MPDU_START_E = 142 /* 0x8e */, + WIFITX_MSDU_END_E = 143 /* 0x8f */, + WIFITX_MSDU_START_E = 144 /* 0x90 */, + WIFITX_SW_MODE_SETUP_E = 145 /* 0x91 */, + WIFITXPCU_BUFFER_STATUS_E = 146 /* 0x92 */, + WIFITXPCU_USER_BUFFER_STATUS_E = 147 /* 0x93 */, + WIFIDATA_TO_TIME_CONFIG_E = 148 /* 0x94 */, + WIFIEXAMPLE_USER_TLV_32_E = 149 /* 0x95 */, + WIFIMPDU_INFO_E = 150 /* 0x96 */, + WIFIPDG_USER_SETUP_E = 151 /* 0x97 */, + WIFITX_11AH_SETUP_E = 152 /* 0x98 */, + WIFITX_CV_START_E = 153 /* 0x99 */, + WIFITX_PEER_ENTRY_E = 154 /* 0x9a */, + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */, + WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */, + WIFIPCU_PPDU_SETUP_END_INFO_E = 157 /* 0x9d */, + WIFIPPDU_RATE_SETTING_E = 158 /* 0x9e */, + WIFIPROT_RATE_SETTING_E = 159 /* 0x9f */, + WIFIRX_MPDU_DETAILS_E = 160 /* 0xa0 */, + WIFIEXAMPLE_USER_TLV_42_E = 161 /* 0xa1 */, + WIFIRX_MSDU_LINK_E = 162 /* 0xa2 */, + WIFIRX_REO_QUEUE_E = 163 /* 0xa3 */, + WIFIADDR_SEARCH_ENTRY_E = 164 /* 0xa4 */, + WIFISCHEDULER_CMD_E = 165 /* 0xa5 */, + WIFITX_FLUSH_E = 166 /* 0xa6 */, + WIFITQM_ENTRANCE_RING_E = 167 /* 0xa7 */, + WIFITX_DATA_WORD_E = 168 /* 0xa8 */, + WIFITX_MPDU_DETAILS_E = 169 /* 0xa9 */, + WIFITX_MPDU_LINK_E = 170 /* 0xaa */, + WIFITX_MPDU_LINK_PTR_E = 171 /* 0xab */, + WIFITX_MPDU_QUEUE_HEAD_E = 172 /* 0xac */, + WIFITX_MPDU_QUEUE_EXT_E = 173 /* 0xad */, + WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 /* 0xae */, + WIFITX_MSDU_DETAILS_E = 175 /* 0xaf */, + WIFITX_MSDU_EXTENSION_E = 176 /* 0xb0 */, + WIFITX_MSDU_FLOW_E = 177 /* 0xb1 */, + WIFITX_MSDU_LINK_E = 178 /* 0xb2 */, + WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 /* 0xb3 */, + WIFIRESPONSE_RATE_SETTING_E = 180 /* 0xb4 */, + WIFITXPCU_BUFFER_BASICS_E = 181 /* 0xb5 */, + WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 /* 0xb6 */, + WIFIUNIFORM_TQM_CMD_HEADER_E = 183 /* 0xb7 */, + WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 /* 0xb8 */, + WIFIUSER_RATE_SETTING_E = 185 /* 0xb9 */, + WIFIWBM_BUFFER_RING_E = 186 /* 0xba */, + WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 /* 0xbb */, + WIFIWBM_RELEASE_RING_E = 188 /* 0xbc */, + WIFITX_FLUSH_REQ_E = 189 /* 0xbd */, + WIFIRX_MSDU_DETAILS_E = 190 /* 0xbe */, + WIFITQM_WRITE_CMD_STATUS_E = 191 /* 0xbf */, + WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 /* 0xc0 */, + WIFITQM_GET_MSDU_FLOW_STATS_E = 193 /* 0xc1 */, + WIFIEXAMPLE_USER_CTLV_32_E = 194 /* 0xc2 */, + WIFITX_FES_STATUS_START_E = 195 /* 0xc3 */, + WIFITX_FES_STATUS_USER_PPDU_E = 196 /* 0xc4 */, + WIFITX_FES_STATUS_USER_RESPONSE_E = 197 /* 0xc5 */, + WIFITX_FES_STATUS_END_E = 198 /* 0xc6 */, + WIFIRX_TRIG_INFO_E = 199 /* 0xc7 */, + WIFIRXPCU_TX_SETUP_CLEAR_E = 200 /* 0xc8 */, + WIFIRX_FRAME_BITMAP_REQ_E = 201 /* 0xc9 */, + WIFIRX_FRAME_BITMAP_ACK_E = 202 /* 0xca */, + WIFICOEX_RX_STATUS_E = 203 /* 0xcb */, + WIFIRX_START_PARAM_E = 204 /* 0xcc */, + WIFIRX_PPDU_START_E = 205 /* 0xcd */, + WIFIRX_PPDU_END_E = 206 /* 0xce */, + WIFIRX_MPDU_START_E = 207 /* 0xcf */, + WIFIRX_MPDU_END_E = 208 /* 0xd0 */, + WIFIRX_MSDU_START_E = 209 /* 0xd1 */, + WIFIRX_MSDU_END_E = 210 /* 0xd2 */, + WIFIRX_ATTENTION_E = 211 /* 0xd3 */, + WIFIRECEIVED_RESPONSE_INFO_E = 212 /* 0xd4 */, + WIFIRX_PHY_SLEEP_E = 213 /* 0xd5 */, + WIFIRX_HEADER_E = 214 /* 0xd6 */, + WIFIRX_PEER_ENTRY_E = 215 /* 0xd7 */, + WIFIRX_FLUSH_E = 216 /* 0xd8 */, + WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 /* 0xd9 */, + WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 /* 0xda */, + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 /* 0xdb */, + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 /* 0xdc */, + WIFITX_CBF_INFO_E = 221 /* 0xdd */, + WIFIPCU_PPDU_SETUP_USER_E = 222 /* 0xde */, + WIFIRX_MPDU_PCU_START_E = 223 /* 0xdf */, + WIFIRX_PM_INFO_E = 224 /* 0xe0 */, + WIFIRX_USER_PPDU_END_E = 225 /* 0xe1 */, + WIFIRX_PRE_PPDU_START_E = 226 /* 0xe2 */, + WIFIRX_PREAMBLE_E = 227 /* 0xe3 */, + WIFITX_FES_SETUP_COMPLETE_E = 228 /* 0xe4 */, + WIFITX_LAST_MPDU_FETCHED_E = 229 /* 0xe5 */, + WIFITXDMA_STOP_REQUEST_E = 230 /* 0xe6 */, + WIFIRXPCU_SETUP_E = 231 /* 0xe7 */, + WIFIRXPCU_USER_SETUP_E = 232 /* 0xe8 */, + WIFITX_FES_STATUS_ACK_OR_BA_E = 233 /* 0xe9 */, + WIFITQM_ACKED_MPDU_E = 234 /* 0xea */, + WIFICOEX_TX_RESP_E = 235 /* 0xeb */, + WIFICOEX_TX_STATUS_E = 236 /* 0xec */, + WIFIMACTX_COEX_PHY_CTRL_E = 237 /* 0xed */, + WIFICOEX_STATUS_BROADCAST_E = 238 /* 0xee */, + WIFIRESPONSE_START_STATUS_E = 239 /* 0xef */, + WIFIRESPONSE_END_STATUS_E = 240 /* 0xf0 */, + WIFICRYPTO_STATUS_E = 241 /* 0xf1 */, + WIFIRECEIVED_TRIGGER_INFO_E = 242 /* 0xf2 */, + WIFIREO_ENTRANCE_RING_E = 243 /* 0xf3 */, + WIFIRX_MPDU_LINK_E = 244 /* 0xf4 */, + WIFICOEX_TX_STOP_CTRL_E = 245 /* 0xf5 */, + WIFIRX_PPDU_ACK_REPORT_E = 246 /* 0xf6 */, + WIFIRX_PPDU_NO_ACK_REPORT_E = 247 /* 0xf7 */, + WIFISCH_COEX_STATUS_E = 248 /* 0xf8 */, + WIFISCHEDULER_COMMAND_STATUS_E = 249 /* 0xf9 */, + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */, + WIFITX_FES_STATUS_PROT_E = 251 /* 0xfb */, + WIFITX_FES_STATUS_START_PPDU_E = 252 /* 0xfc */, + WIFITX_FES_STATUS_START_PROT_E = 253 /* 0xfd */, + WIFITXPCU_PHYTX_DEBUG32_E = 254 /* 0xfe */, + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 /* 0xff */, + WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 /* 0x100 */, + WIFIWHO_ANCHOR_OFFSET_E = 257 /* 0x101 */, + WIFIWHO_ANCHOR_VALUE_E = 258 /* 0x102 */, + WIFIWHO_CCE_INFO_E = 259 /* 0x103 */, + WIFIWHO_COMMIT_E = 260 /* 0x104 */, + WIFIWHO_COMMIT_DONE_E = 261 /* 0x105 */, + WIFIWHO_FLUSH_E = 262 /* 0x106 */, + WIFIWHO_L2_LLC_E = 263 /* 0x107 */, + WIFIWHO_L2_PAYLOAD_E = 264 /* 0x108 */, + WIFIWHO_L3_CHECKSUM_E = 265 /* 0x109 */, + WIFIWHO_L3_INFO_E = 266 /* 0x10a */, + WIFIWHO_L4_CHECKSUM_E = 267 /* 0x10b */, + WIFIWHO_L4_INFO_E = 268 /* 0x10c */, + WIFIWHO_MSDU_E = 269 /* 0x10d */, + WIFIWHO_MSDU_MISC_E = 270 /* 0x10e */, + WIFIWHO_PACKET_DATA_E = 271 /* 0x10f */, + WIFIWHO_PACKET_HDR_E = 272 /* 0x110 */, + WIFIWHO_PPDU_END_E = 273 /* 0x111 */, + WIFIWHO_PPDU_START_E = 274 /* 0x112 */, + WIFIWHO_TSO_E = 275 /* 0x113 */, + WIFIWHO_WMAC_HEADER_PV0_E = 276 /* 0x114 */, + WIFIWHO_WMAC_HEADER_PV1_E = 277 /* 0x115 */, + WIFIWHO_WMAC_IV_E = 278 /* 0x116 */, + WIFIMPDU_INFO_END_E = 279 /* 0x117 */, + WIFIMPDU_INFO_BITMAP_E = 280 /* 0x118 */, + WIFITX_QUEUE_EXTENSION_E = 281 /* 0x119 */, + WIFIRX_PEER_ENTRY_DETAILS_E = 282 /* 0x11a */, + WIFIRX_REO_QUEUE_REFERENCE_E = 283 /* 0x11b */, + WIFIRX_REO_QUEUE_EXT_E = 284 /* 0x11c */, + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 /* 0x11d */, + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 /* 0x11e */, + WIFITQM_ACKED_MPDU_STATUS_E = 287 /* 0x11f */, + WIFITQM_ADD_MSDU_STATUS_E = 288 /* 0x120 */, + WIFIRX_MPDU_LINK_PTR_E = 289 /* 0x121 */, + WIFIREO_DESTINATION_RING_E = 290 /* 0x122 */, + WIFITQM_LIST_GEN_DONE_E = 291 /* 0x123 */, + WIFIWHO_TERMINATE_E = 292 /* 0x124 */, + WIFITX_LAST_MPDU_END_E = 293 /* 0x125 */, + WIFITX_CV_DATA_E = 294 /* 0x126 */, + WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 /* 0x127 */, + WIFIPPDU_TX_END_E = 296 /* 0x128 */, + WIFIPROT_TX_END_E = 297 /* 0x129 */, + WIFIPDG_RESPONSE_RATE_SETTING_E = 298 /* 0x12a */, + WIFIMPDU_INFO_GLOBAL_END_E = 299 /* 0x12b */, + WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 /* 0x12c */, + WIFIRX_PPDU_END_USER_STATS_E = 301 /* 0x12d */, + WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 /* 0x12e */, + WIFINO_ACK_REPORT_E = 303 /* 0x12f */, + WIFIACK_REPORT_E = 304 /* 0x130 */, + WIFIUNIFORM_REO_CMD_HEADER_E = 305 /* 0x131 */, + WIFIREO_GET_QUEUE_STATS_E = 306 /* 0x132 */, + WIFIREO_FLUSH_QUEUE_E = 307 /* 0x133 */, + WIFIREO_FLUSH_CACHE_E = 308 /* 0x134 */, + WIFIREO_UNBLOCK_CACHE_E = 309 /* 0x135 */, + WIFIUNIFORM_REO_STATUS_HEADER_E = 310 /* 0x136 */, + WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 /* 0x137 */, + WIFIREO_FLUSH_QUEUE_STATUS_E = 312 /* 0x138 */, + WIFIREO_FLUSH_CACHE_STATUS_E = 313 /* 0x139 */, + WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 /* 0x13a */, + WIFITQM_FLUSH_CACHE_E = 315 /* 0x13b */, + WIFITQM_UNBLOCK_CACHE_E = 316 /* 0x13c */, + WIFITQM_FLUSH_CACHE_STATUS_E = 317 /* 0x13d */, + WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 /* 0x13e */, + WIFIRX_PPDU_END_STATUS_DONE_E = 319 /* 0x13f */, + WIFIRX_STATUS_BUFFER_DONE_E = 320 /* 0x140 */, + WIFIBUFFER_ADDR_INFO_E = 321 /* 0x141 */, + WIFIRX_MSDU_DESC_INFO_E = 322 /* 0x142 */, + WIFIRX_MPDU_DESC_INFO_E = 323 /* 0x143 */, + WIFITCL_DATA_CMD_E = 324 /* 0x144 */, + WIFITCL_GSE_CMD_E = 325 /* 0x145 */, + WIFITCL_EXIT_BASE_E = 326 /* 0x146 */, + WIFITCL_COMPACT_EXIT_RING_E = 327 /* 0x147 */, + WIFITCL_REGULAR_EXIT_RING_E = 328 /* 0x148 */, + WIFITCL_EXTENDED_EXIT_RING_E = 329 /* 0x149 */, + WIFIUPLINK_COMMON_INFO_E = 330 /* 0x14a */, + WIFIUPLINK_USER_SETUP_INFO_E = 331 /* 0x14b */, + WIFITX_DATA_SYNC_E = 332 /* 0x14c */, + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 /* 0x14d */, + WIFITCL_STATUS_RING_E = 334 /* 0x14e */, + WIFITQM_GET_MPDU_HEAD_INFO_E = 335 /* 0x14f */, + WIFITQM_SYNC_CMD_E = 336 /* 0x150 */, + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 /* 0x151 */, + WIFITQM_SYNC_CMD_STATUS_E = 338 /* 0x152 */, + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */, + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */, + WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 /* 0x155 */, + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 /* 0x156 */, + WIFIREO_TO_PPE_RING_E = 343 /* 0x157 */, + WIFIRX_MPDU_INFO_E = 344 /* 0x158 */, + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */, + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */, + WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 /* 0x15b */, + WIFIRX_PPDU_START_USER_INFO_E = 348 /* 0x15c */, + WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 /* 0x15d */, + WIFIRX_RING_MASK_E = 350 /* 0x15e */, + WIFIWHO_CLASSIFY_INFO_E = 351 /* 0x15f */, + WIFITXPT_CLASSIFY_INFO_E = 352 /* 0x160 */, + WIFIRXPT_CLASSIFY_INFO_E = 353 /* 0x161 */, + WIFITX_FLOW_SEARCH_ENTRY_E = 354 /* 0x162 */, + WIFIRX_FLOW_SEARCH_ENTRY_E = 355 /* 0x163 */, + WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 /* 0x164 */, + WIFICOEX_MAC_NAP_E = 357 /* 0x165 */, + WIFIMACRX_ABORT_REQUEST_INFO_E = 358 /* 0x166 */, + WIFIMACTX_ABORT_REQUEST_INFO_E = 359 /* 0x167 */, + WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 /* 0x168 */, + WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 /* 0x169 */, + WIFIRXPCU_PPDU_END_INFO_E = 362 /* 0x16a */, + WIFIWHO_MESH_CONTROL_E = 363 /* 0x16b */, + WIFIL_SIG_A_INFO_E = 364 /* 0x16c */, + WIFIL_SIG_B_INFO_E = 365 /* 0x16d */, + WIFIHT_SIG_INFO_E = 366 /* 0x16e */, + WIFIVHT_SIG_A_INFO_E = 367 /* 0x16f */, + WIFIVHT_SIG_B_SU20_INFO_E = 368 /* 0x170 */, + WIFIVHT_SIG_B_SU40_INFO_E = 369 /* 0x171 */, + WIFIVHT_SIG_B_SU80_INFO_E = 370 /* 0x172 */, + WIFIVHT_SIG_B_SU160_INFO_E = 371 /* 0x173 */, + WIFIVHT_SIG_B_MU20_INFO_E = 372 /* 0x174 */, + WIFIVHT_SIG_B_MU40_INFO_E = 373 /* 0x175 */, + WIFIVHT_SIG_B_MU80_INFO_E = 374 /* 0x176 */, + WIFIVHT_SIG_B_MU160_INFO_E = 375 /* 0x177 */, + WIFISERVICE_INFO_E = 376 /* 0x178 */, + WIFIHE_SIG_A_SU_INFO_E = 377 /* 0x179 */, + WIFIHE_SIG_A_MU_DL_INFO_E = 378 /* 0x17a */, + WIFIHE_SIG_A_MU_UL_INFO_E = 379 /* 0x17b */, + WIFIHE_SIG_B1_MU_INFO_E = 380 /* 0x17c */, + WIFIHE_SIG_B2_MU_INFO_E = 381 /* 0x17d */, + WIFIHE_SIG_B2_OFDMA_INFO_E = 382 /* 0x17e */, + WIFIPDG_SW_MODE_BW_START_E = 383 /* 0x17f */, + WIFIPDG_SW_MODE_BW_END_E = 384 /* 0x180 */, + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 /* 0x181 */, + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 /* 0x182 */, + WIFISCHEDULER_END_E = 387 /* 0x183 */, + WIFIPEER_TABLE_ENTRY_E = 388 /* 0x184 */, + WIFISW_PEER_INFO_E = 389 /* 0x185 */, + WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 /* 0x186 */, + WIFITCL_CCE_CLASSIFY_INFO_E = 391 /* 0x187 */, + WIFIRXOLE_CCE_INFO_E = 392 /* 0x188 */, + WIFITCL_CCE_INFO_E = 393 /* 0x189 */, + WIFITCL_CCE_SUPERRULE_E = 394 /* 0x18a */, + WIFICCE_RULE_E = 395 /* 0x18b */, + WIFIRX_PPDU_START_DROPPED_E = 396 /* 0x18c */, + WIFIRX_PPDU_END_DROPPED_E = 397 /* 0x18d */, + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 /* 0x18e */, + WIFIRX_MPDU_START_DROPPED_E = 399 /* 0x18f */, + WIFIRX_MSDU_START_DROPPED_E = 400 /* 0x190 */, + WIFIRX_MSDU_END_DROPPED_E = 401 /* 0x191 */, + WIFIRX_MPDU_END_DROPPED_E = 402 /* 0x192 */, + WIFIRX_ATTENTION_DROPPED_E = 403 /* 0x193 */, + WIFITXPCU_USER_SETUP_E = 404 /* 0x194 */, + WIFIRXPCU_USER_SETUP_EXT_E = 405 /* 0x195 */, + WIFICE_SRC_DESC_E = 406 /* 0x196 */, + WIFICE_STAT_DESC_E = 407 /* 0x197 */, + WIFIRXOLE_CCE_SUPERRULE_E = 408 /* 0x198 */, + WIFITX_RATE_STATS_INFO_E = 409 /* 0x199 */, + WIFICMD_PART_0_END_E = 410 /* 0x19a */, + WIFIMACTX_SYNTH_ON_E = 411 /* 0x19b */, + WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 /* 0x19c */, + WIFITQM_MPDU_GLOBAL_START_E = 413 /* 0x19d */, + WIFIEXAMPLE_TLV_32_E = 414 /* 0x19e */, + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 /* 0x19f */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 /* 0x1a0 */, + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */, + WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 420 /* 0x1a4 */, + WIFITLV_BASE_E = 511 /* 0x1ff */ + +} tlv_tag_def__e; ///< tlv_tag_def Enum Type + +#endif // _TLV_TAG_DEF_ diff --git a/hw/qca8074/v1/tx_msdu_extension.h b/hw/qca8074/v1/tx_msdu_extension.h new file mode 100644 index 000000000000..bf7f00f2da8e --- /dev/null +++ b/hw/qca8074/v1/tx_msdu_extension.h @@ -0,0 +1,827 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 tso_enable[0], ipv4_checksum_en[1], udp_over_ipv4_checksum_en[2], udp_over_ipv6_checksum_en[3], tcp_over_ipv4_checksum_en[4], tcp_over_ipv6_checksum_en[5], reserved_0a[6], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25] +// 1 l2_length[15:0], ip_length[31:16] +// 2 tcp_seq_number[31:0] +// 3 ip_identification[15:0], udp_length[31:16] +// 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30] +// 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17] +// 6 buf0_ptr_31_0[31:0] +// 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16] +// 8 buf1_ptr_31_0[31:0] +// 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16] +// 10 buf2_ptr_31_0[31:0] +// 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16] +// 12 buf3_ptr_31_0[31:0] +// 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16] +// 14 buf4_ptr_31_0[31:0] +// 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16] +// 16 buf5_ptr_31_0[31:0] +// 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { + uint32_t tso_enable : 1, //[0] + ipv4_checksum_en : 1, //[1] + udp_over_ipv4_checksum_en : 1, //[2] + udp_over_ipv6_checksum_en : 1, //[3] + tcp_over_ipv4_checksum_en : 1, //[4] + tcp_over_ipv6_checksum_en : 1, //[5] + reserved_0a : 1, //[6] + tcp_flag : 9, //[15:7] + tcp_flag_mask : 9, //[24:16] + reserved_0b : 7; //[31:25] + uint32_t l2_length : 16, //[15:0] + ip_length : 16; //[31:16] + uint32_t tcp_seq_number : 32; //[31:0] + uint32_t ip_identification : 16, //[15:0] + udp_length : 16; //[31:16] + uint32_t checksum_offset : 14, //[13:0] + partial_checksum_en : 1, //[14] + reserved_4a : 1, //[15] + payload_start_offset : 14, //[29:16] + reserved_4b : 2; //[31:30] + uint32_t payload_end_offset : 14, //[13:0] + reserved_5a : 2, //[15:14] + wds : 1, //[16] + reserved_5b : 15; //[31:17] + uint32_t buf0_ptr_31_0 : 32; //[31:0] + uint32_t buf0_ptr_39_32 : 8, //[7:0] + reserved_7a : 8, //[15:8] + buf0_len : 16; //[31:16] + uint32_t buf1_ptr_31_0 : 32; //[31:0] + uint32_t buf1_ptr_39_32 : 8, //[7:0] + reserved_9a : 8, //[15:8] + buf1_len : 16; //[31:16] + uint32_t buf2_ptr_31_0 : 32; //[31:0] + uint32_t buf2_ptr_39_32 : 8, //[7:0] + reserved_11a : 8, //[15:8] + buf2_len : 16; //[31:16] + uint32_t buf3_ptr_31_0 : 32; //[31:0] + uint32_t buf3_ptr_39_32 : 8, //[7:0] + reserved_13a : 8, //[15:8] + buf3_len : 16; //[31:16] + uint32_t buf4_ptr_31_0 : 32; //[31:0] + uint32_t buf4_ptr_39_32 : 8, //[7:0] + reserved_15a : 8, //[15:8] + buf4_len : 16; //[31:16] + uint32_t buf5_ptr_31_0 : 32; //[31:0] + uint32_t buf5_ptr_39_32 : 8, //[7:0] + reserved_17a : 8, //[15:8] + buf5_len : 16; //[31:16] +}; + +/* + +tso_enable + + Enable transmit segmentation offload + +ipv4_checksum_en + + Enable IPv4 checksum replacement + +udp_over_ipv4_checksum_en + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. + +udp_over_ipv6_checksum_en + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. + +tcp_over_ipv4_checksum_en + + Enable TCP checksum over IPv4 replacement + +tcp_over_ipv6_checksum_en + + Enable TCP checksum over IPv6 eplacement + +reserved_0a + + FW will set to 0, MAC will ignore.  + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} + +tcp_flag_mask + + TCP flag mask. Tcp_flag is inserted into the header + based on the mask, if tso is enabled + +reserved_0b + + FW will set to 0, MAC will ignore.  + +l2_length + + L2 length for the msdu, if tso is enabled + +ip_length + + Ip length for the msdu, if tso is enabled + +tcp_seq_number + + Tcp_seq_number for the msdu, if tso is enabled + +ip_identification + + Ip_identification for the msdu, if tso is enabled + +udp_length + + TXDMA is copies this field into MSDU START TLV + +checksum_offset + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field + +partial_checksum_en + + Partial Checksum Enable Bit. + + + +reserved_4a + + + +payload_start_offset + + L4 checksum calculations will start fromt this offset + + + +reserved_4b + + + +payload_end_offset + + L4 checksum calculations will end at this offset. + + + +reserved_5a + + + +wds + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by the + OLE during encapsulation. + + Note: there is also global wds tx control in the + TX_PEER_ENTRY + + + +reserved_5b + + + +buf0_ptr_31_0 + + Lower 32 bits of the first buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf0_ptr_39_32 + + Upper 8 bits of the first buffer pointer + +reserved_7a + + + +buf0_len + + Length of the first buffer + +buf1_ptr_31_0 + + Lower 32 bits of the second buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf1_ptr_39_32 + + Upper 8 bits of the second buffer pointer + +reserved_9a + + + +buf1_len + + Length of the second buffer + +buf2_ptr_31_0 + + Lower 32 bits of the third buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf2_ptr_39_32 + + Upper 8 bits of the third buffer pointer + +reserved_11a + + + +buf2_len + + Length of the third buffer + +buf3_ptr_31_0 + + Lower 32 bits of the fourth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf3_ptr_39_32 + + Upper 8 bits of the fourth buffer pointer + +reserved_13a + + + +buf3_len + + Length of the fourth buffer + +buf4_ptr_31_0 + + Lower 32 bits of the fifth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf4_ptr_39_32 + + Upper 8 bits of the fifth buffer pointer + +reserved_15a + + + +buf4_len + + Length of the fifth buffer + +buf5_ptr_31_0 + + Lower 32 bits of the sixth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf5_ptr_39_32 + + Upper 8 bits of the sixth buffer pointer + +reserved_17a + + + +buf5_len + + Length of the sixth buffer +*/ + + +/* Description TX_MSDU_EXTENSION_0_TSO_ENABLE + + Enable transmit segmentation offload +*/ +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 + +/* Description TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN + + Enable IPv4 checksum replacement +*/ +#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_LSB 1 +#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_MASK 0x00000002 + +/* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_LSB 2 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000004 + +/* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_LSB 3 +#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000008 + +/* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN + + Enable TCP checksum over IPv4 replacement +*/ +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_LSB 4 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000010 + +/* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN + + Enable TCP checksum over IPv6 eplacement +*/ +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_LSB 5 +#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000020 + +/* Description TX_MSDU_EXTENSION_0_RESERVED_0A + + FW will set to 0, MAC will ignore.  +*/ +#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 6 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x00000040 + +/* Description TX_MSDU_EXTENSION_0_TCP_FLAG + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ +#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 + +/* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header + based on the mask, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 + +/* Description TX_MSDU_EXTENSION_0_RESERVED_0B + + FW will set to 0, MAC will ignore.  +*/ +#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 + +/* Description TX_MSDU_EXTENSION_1_L2_LENGTH + + L2 length for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff + +/* Description TX_MSDU_EXTENSION_1_IP_LENGTH + + Ip length for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION + + Ip_identification for the msdu, if tso is enabled +*/ +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff + +/* Description TX_MSDU_EXTENSION_3_UDP_LENGTH + + TXDMA is copies this field into MSDU START TLV +*/ +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff + +/* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN + + Partial Checksum Enable Bit. + + +*/ +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +/* Description TX_MSDU_EXTENSION_4_RESERVED_4A + + +*/ +#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 + +/* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + + +*/ +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +/* Description TX_MSDU_EXTENSION_4_RESERVED_4B + + +*/ +#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 + +/* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + + +*/ +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff + +/* Description TX_MSDU_EXTENSION_5_RESERVED_5A + + +*/ +#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 + +/* Description TX_MSDU_EXTENSION_5_WDS + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by the + OLE during encapsulation. + + Note: there is also global wds tx control in the + TX_PEER_ENTRY + + +*/ +#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_WDS_LSB 16 +#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 + +/* Description TX_MSDU_EXTENSION_5_RESERVED_5B + + +*/ +#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 + +/* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0 + + Lower 32 bits of the first buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32 + + Upper 8 bits of the first buffer pointer +*/ +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_7_RESERVED_7A + + +*/ +#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 +#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_7_BUF0_LEN + + Length of the first buffer +*/ +#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0 + + Lower 32 bits of the second buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32 + + Upper 8 bits of the second buffer pointer +*/ +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_9_RESERVED_9A + + +*/ +#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_9_BUF1_LEN + + Length of the second buffer +*/ +#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0 + + Lower 32 bits of the third buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32 + + Upper 8 bits of the third buffer pointer +*/ +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_11_RESERVED_11A + + +*/ +#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 +#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_11_BUF2_LEN + + Length of the third buffer +*/ +#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0 + + Lower 32 bits of the fourth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32 + + Upper 8 bits of the fourth buffer pointer +*/ +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_13_RESERVED_13A + + +*/ +#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_13_BUF3_LEN + + Length of the fourth buffer +*/ +#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0 + + Lower 32 bits of the fifth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32 + + Upper 8 bits of the fifth buffer pointer +*/ +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_15_RESERVED_15A + + +*/ +#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_15_BUF4_LEN + + Length of the fifth buffer +*/ +#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0 + + Lower 32 bits of the sixth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32 + + Upper 8 bits of the sixth buffer pointer +*/ +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_17_RESERVED_17A + + +*/ +#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_17_BUF5_LEN + + Length of the sixth buffer +*/ +#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 + + +#endif // _TX_MSDU_EXTENSION_H_ diff --git a/hw/qca8074/v1/tx_rate_stats_info.h b/hw/qca8074/v1/tx_rate_stats_info.h new file mode 100644 index 000000000000..d0955884981c --- /dev/null +++ b/hw/qca8074/v1/tx_rate_stats_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28] +// 1 tsf_directly_after_ppdu_transmission[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { + uint32_t tx_rate_stats_info_valid : 1, //[0] + transmit_bw : 2, //[2:1] + transmit_pkt_type : 4, //[6:3] + transmit_stbc : 1, //[7] + transmit_ldpc : 1, //[8] + transmit_sgi : 2, //[10:9] + transmit_mcs : 4, //[14:11] + ofdma_transmission : 1, //[15] + tones_in_ru : 12, //[27:16] + reserved_0a : 4; //[31:28] + uint32_t tsf_directly_after_ppdu_transmission: 32; //[31:0] +}; + +/* + +tx_rate_stats_info_valid + + When set all other fields in this STRUCT contain valid + info. + + + + + + +transmit_bw + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + + +transmit_pkt_type + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + +transmit_stbc + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. + +transmit_ldpc + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates + +transmit_sgi + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + + +transmit_mcs + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + + +ofdma_transmission + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + + +tones_in_ru + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + + + TODO: not clear yet what the number of tones is for RUs + of 160 or 80 + 80 ??? + + For now assumption is that this value for this scenario + will indicate: 0x7FF + + + +reserved_0a + + + +tsf_directly_after_ppdu_transmission + + Field only valid when Tx_rate_stats_info_valid is set + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + +*/ + + +/* Description TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid + info. + + + + + +*/ +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI + + Legacy short GI + + HE related GI + + HE related GI + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800 + +/* Description TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + +*/ +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000 + +/* Description TX_RATE_STATS_INFO_0_TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + + + TODO: not clear yet what the number of tones is for RUs + of 160 or 80 + 80 ??? + + For now assumption is that this value for this scenario + will indicate: 0x7FF + + +*/ +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000 + +/* Description TX_RATE_STATS_INFO_0_RESERVED_0A + + +*/ +#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000 + +/* Description TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + +*/ +#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_LSB 0 +#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_MASK 0xffffffff + + +#endif // _TX_RATE_STATS_INFO_H_ diff --git a/hw/qca8074/v1/uniform_descriptor_header.h b/hw/qca8074/v1/uniform_descriptor_header.h new file mode 100644 index 000000000000..bb0214f6487e --- /dev/null +++ b/hw/qca8074/v1/uniform_descriptor_header.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { + uint32_t owner : 4, //[3:0] + buffer_type : 4, //[7:4] + reserved_0a : 24; //[31:8] +}; + +/* + +owner + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + + +buffer_type + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +reserved_0a + + +*/ + + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 + + +#endif // _UNIFORM_DESCRIPTOR_HEADER_H_ diff --git a/hw/qca8074/v1/uniform_reo_cmd_header.h b/hw/qca8074/v1/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..843fc4735fc1 --- /dev/null +++ b/hw/qca8074/v1/uniform_reo_cmd_header.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { + uint32_t reo_cmd_number : 16, //[15:0] + reo_status_required : 1, //[16] + reserved_0a : 15; //[31:17] +}; + +/* + +reo_cmd_number + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + + +reo_status_required + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + + +reserved_0a + + +*/ + + +/* Description UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description UNIFORM_REO_CMD_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000 + + +#endif // _UNIFORM_REO_CMD_HEADER_H_ diff --git a/hw/qca8074/v1/uniform_reo_status_header.h b/hw/qca8074/v1/uniform_reo_status_header.h new file mode 100644 index 000000000000..6f7fd94b8634 --- /dev/null +++ b/hw/qca8074/v1/uniform_reo_status_header.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28] +// 1 timestamp[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { + uint32_t reo_status_number : 16, //[15:0] + cmd_execution_time : 10, //[25:16] + reo_cmd_execution_status : 2, //[27:26] + reserved_0a : 4; //[31:28] + uint32_t timestamp : 32; //[31:0] +}; + +/* + +reo_status_number + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + + +cmd_execution_time + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + + +reo_cmd_execution_status + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + + +reserved_0a + + + +timestamp + + Timestamp at the moment that this status report is + written. + + + + +*/ + + +/* Description UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000 + +/* Description UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff + + +#endif // _UNIFORM_REO_STATUS_HEADER_H_ diff --git a/hw/qca8074/v1/wbm_buffer_ring.h b/hw/qca8074/v1/wbm_buffer_ring.h new file mode 100644 index 000000000000..eaffc26dca9d --- /dev/null +++ b/hw/qca8074/v1/wbm_buffer_ring.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { + struct buffer_addr_info buf_addr_info; +}; + +/* + +struct buffer_addr_info buf_addr_info + + Consumer: WBM + + Producer: WBM + + + + Details of the physical address of the buffer + source + buffer owner + some SW meta data. + + All modules getting this buffer address info, shall keep + all the 64 bits of info in this descriptor together and + eventually all 64 bits shall be given back to WMB when the + buffer is released. +*/ + +#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000000 +#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 0 +#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff +#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 0 +#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff + + +#endif // _WBM_BUFFER_RING_H_ diff --git a/hw/qca8074/v1/wbm_link_descriptor_ring.h b/hw/qca8074/v1/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..28448c5e24d4 --- /dev/null +++ b/hw/qca8074/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info desc_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { + struct buffer_addr_info desc_addr_info; +}; + +/* + +struct buffer_addr_info desc_addr_info + + Consumer: WBM + + Producer: WBM + + + + Details of the physical address of the buffer + source + buffer owner + some SW meta data + + All modules getting this link descriptor address info, + shall keep all the 64 bits in this descriptor together and + eventually all 64 bits shall be given back to WBM when the + link descriptor is released. +*/ + +#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff +#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff + + +#endif // _WBM_LINK_DESCRIPTOR_RING_H_ diff --git a/hw/qca8074/v1/wbm_reg_seq_hwiobase.h b/hw/qca8074/v1/wbm_reg_seq_hwiobase.h new file mode 100644 index 000000000000..f0d267b67a53 --- /dev/null +++ b/hw/qca8074/v1/wbm_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WBM_REG_SEQ_BASE_H__ +#define __WBM_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/hw/qca8074/v1/wbm_reg_seq_hwioreg.h b/hw/qca8074/v1/wbm_reg_seq_hwioreg.h new file mode 100644 index 000000000000..600376c48c60 --- /dev/null +++ b/hw/qca8074/v1/wbm_reg_seq_hwioreg.h @@ -0,0 +1,12394 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WBM_REG_SEQ_REG_H__ +#define __WBM_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "wbm_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WBM_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WBM_R0_GENERAL_ENABLE //// + +#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) +#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) +#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK 0x000000ff +#define HWIO_WBM_R0_GENERAL_ENABLE_SHFT 0 +#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), HWIO_WBM_R0_GENERAL_ENABLE_RMSK) +#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_GENERAL_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x00000080 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 0x7 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT 0x6 + +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT 0x5 + +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_ENABLE //// + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x) (x+0x00000004) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x) (x+0x00000004) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_SHFT 0x0 + +//// Register WBM_R0_MSDU_BUFFER_RING_ENABLE //// + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x) (x+0x00000008) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x) (x+0x00000008) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_BMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_SHFT 0x0 + +//// Register WBM_R0_LINK_DESC_RING_ENABLE //// + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x) (x+0x0000000c) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x) (x+0x0000000c) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_BMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_SHFT 0x0 + +//// Register WBM_R0_MISC_RING_ENABLE //// + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x) (x+0x00000010) +#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x) (x+0x00000010) +#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK 0x0000001f +#define HWIO_WBM_R0_MISC_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MISC_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_BMSK 0x00000010 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_SHFT 0x4 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW2_BUFFER_RING_BMSK 0x00000008 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW2_BUFFER_RING_SHFT 0x3 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW1_BUFFER_RING_BMSK 0x00000004 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW1_BUFFER_RING_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW0_BUFFER_RING_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW0_BUFFER_RING_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_FW_BUFFER_RING_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_FW_BUFFER_RING_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000014) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000014) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_BMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_MSDU_BUFFER_RING_STATUS //// + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x) (x+0x00000018) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x) (x+0x00000018) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_BMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_LINK_DESC_RING_STATUS //// + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x) (x+0x0000001c) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x) (x+0x0000001c) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_BMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_MISC_RING_STATUS //// + +#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x) (x+0x00000020) +#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x) (x+0x00000020) +#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK 0x000001ff +#define HWIO_WBM_R0_MISC_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), HWIO_WBM_R0_MISC_RING_STATUS_RMSK) +#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MISC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x00000100 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 0x8 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_FLUSH //// + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x) (x+0x00000024) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x) (x+0x00000024) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK 0x00013fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x00010000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 0x10 + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x00002000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 0xd + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x00001000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 0xc + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0x00000fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0x0 + +//// Register WBM_R0_IDLE_STATUS //// + +#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x) (x+0x00000028) +#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x) (x+0x00000028) +#define HWIO_WBM_R0_IDLE_STATUS_RMSK 0x00007fff +#define HWIO_WBM_R0_IDLE_STATUS_SHFT 0 +#define HWIO_WBM_R0_IDLE_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), HWIO_WBM_R0_IDLE_STATUS_RMSK) +#define HWIO_WBM_R0_IDLE_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x00004000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 0xe + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK 0x00002000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT 0xd + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK 0x00001000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT 0xc + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK 0x00000800 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT 0xb + +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000400 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0xa + +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000200 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x9 + +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000100 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x8 + +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT 0x0 + +//// Register WBM_R0_IDLE_SEQUENCE //// + +#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x) (x+0x0000002c) +#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x) (x+0x0000002c) +#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK 0x0000003f +#define HWIO_WBM_R0_IDLE_SEQUENCE_SHFT 0 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), HWIO_WBM_R0_IDLE_SEQUENCE_RMSK) +#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x00000020 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 0x5 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK 0x0000000f +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT 0x0 + +//// Register WBM_R0_MSDU_PARSER_CONTROL //// + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x) (x+0x00000030) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x) (x+0x00000030) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK 0x00000007 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_SHFT 0 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x00000004 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 0x2 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x00000002 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 0x1 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x00000001 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0x0 + +//// Register WBM_R0_MSDU_PARSER_STATUS //// + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) (x+0x00000034) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) (x+0x00000034) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x0007ffff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT 0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x00078000 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 0xf + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x00004000 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 0xe + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_MAIN_STATE_BMSK 0x00003c00 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_MAIN_STATE_SHFT 0xa + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_BMSK 0x000003e0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_SHFT 0x5 + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x0000001f +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0x0 + +//// Register WBM_R0_MISC_CONTROL //// + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) (x+0x00000038) +#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x) (x+0x00000038) +#define HWIO_WBM_R0_MISC_CONTROL_RMSK 0x0000ffff +#define HWIO_WBM_R0_MISC_CONTROL_SHFT 0 +#define HWIO_WBM_R0_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_MISC_CONTROL_RMSK) +#define HWIO_WBM_R0_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0x0000fffc +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT 0x0 + +//// Register WBM_R0_WATCHDOG_TIMEOUT //// + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000003c) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000003c) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_SHFT 0 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), val) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0x00000fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0x0 + +//// Register WBM_R0_INTERRUPT_DATA_CAPTURE //// + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x) (x+0x00000040) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x) (x+0x00000040) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK 0x000001ff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SHFT 0 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), val) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask, val, HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_BMSK 0x000001ff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_SHFT 0x0 + +//// Register WBM_R0_INVALID_APB_ACC_ADDR //// + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x00000044) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x00000044) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK 0x0001ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_SHFT 0 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ + out_dword( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x0001ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0x0 + +//// Register WBM_R0_IDLE_LIST_CONTROL //// + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) (x+0x00000048) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) (x+0x00000048) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x000007ff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SHFT 0 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x000007fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 0x2 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x00000002 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 0x1 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x00000001 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0x0 + +//// Register WBM_R0_IDLE_LIST_SIZE //// + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) (x+0x0000004c) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) (x+0x0000004c) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SHFT 0 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 0x10 + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0x0000ffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_LSB //// + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x) (x+0x00000050) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_PHYS(x) (x+0x00000050) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_MSB //// + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x) (x+0x00000054) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_PHYS(x) (x+0x00000054) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) (x+0x00000058) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) (x+0x00000058) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) (x+0x0000005c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) (x+0x0000005c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000060) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000060) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x00000064) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x00000064) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000068) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000068) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x0000006c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x0000006c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000070) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000070) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x00000074) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x00000074) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000078) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000078) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x0000007c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x0000007c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HP //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x) (x+0x00000080) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_PHYS(x) (x+0x00000080) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HP //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) (x+0x00000084) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) (x+0x00000084) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TP //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x) (x+0x00000088) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_PHYS(x) (x+0x00000088) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TP //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) (x+0x0000008c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) (x+0x0000008c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_CLK_GATE_CTRL //// + +#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000090) +#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000090) +#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK 0x0003ffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_SHFT 0 +#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), HWIO_WBM_R0_CLK_GATE_CTRL_RMSK) +#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), val) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x00020000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 0x11 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x00010000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 0x10 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK 0x0000ffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000094) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000094) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000098) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000098) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000009c) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000009c) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register WBM_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000000a0) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000000a0) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WBM_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000000a4) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000000a4) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000000a8) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000000a8) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000000ac) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000000ac) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000000b0) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000000b0) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000000b4) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000000b4) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000000b8) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000000b8) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000000bc) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000000bc) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000000c0) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000000c0) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000000c4) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000000c4) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000000c8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000000c8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000000cc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000000cc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) (x+0x000000d0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) (x+0x000000d0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x) (x+0x000000d4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_PHYS(x) (x+0x000000d4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x) (x+0x000000d8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_PHYS(x) (x+0x000000d8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000e4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000e4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000e8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000e8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000f8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000f8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000fc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000fc) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000100) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000100) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000104) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000104) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000108) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000108) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000010c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000010c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000011c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000011c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000120) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000120) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000124) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000124) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) (x+0x00000128) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) (x+0x00000128) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) (x+0x0000012c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) (x+0x0000012c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x) (x+0x00000130) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x) (x+0x00000130) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000013c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000013c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000140) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000140) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000150) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000150) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000154) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000154) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000158) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000158) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000015c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000015c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000160) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000160) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000164) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000164) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000174) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000174) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000178) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000178) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x0000017c) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x0000017c) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x00000180) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x00000180) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x00000184) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x00000184) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x00000188) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x00000188) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000194) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000194) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000198) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000198) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001a8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001a8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001ac) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001ac) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001b0) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001b0) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001bc) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001bc) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001cc) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001cc) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000001d0) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000001d0) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000001d4) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000001d4) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) (x+0x000001d8) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) (x+0x000001d8) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) (x+0x000001dc) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) (x+0x000001dc) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) (x+0x000001e0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) (x+0x000001e0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000200) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000200) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000204) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000204) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000208) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000208) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000020c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000020c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000210) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000210) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000214) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000214) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000218) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000218) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000021c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000021c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000220) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000220) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000224) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000224) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000228) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000228) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x0000022c) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x0000022c) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) (x+0x00000230) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) (x+0x00000230) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x) (x+0x00000234) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x) (x+0x00000234) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x) (x+0x00000238) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x) (x+0x00000238) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000244) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000244) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000248) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000248) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000258) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000258) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000025c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000025c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000260) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000260) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000264) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000264) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000268) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000268) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000026c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000026c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000270) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000270) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000274) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000274) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000278) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000278) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000027c) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000027c) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000280) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000280) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000284) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000284) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) (x+0x00000288) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) (x+0x00000288) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x) (x+0x0000028c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x) (x+0x0000028c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x) (x+0x00000290) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x) (x+0x00000290) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000029c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000029c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000002a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000002a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000002b0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000002b0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000002b4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000002b4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000002b8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000002b8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002bc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002bc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000002c0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000002c0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000002c4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000002c4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000002d8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000002d8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000002dc) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000002dc) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x) (x+0x000002e0) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_PHYS(x) (x+0x000002e0) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x) (x+0x000002e4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_PHYS(x) (x+0x000002e4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x) (x+0x000002e8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_PHYS(x) (x+0x000002e8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000002f4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000002f4) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000002f8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000002f8) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000308) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000308) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000030c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000030c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000310) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000310) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000314) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000314) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000318) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000318) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000031c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000031c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000032c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000032c) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000330) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000330) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000334) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000334) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x) (x+0x00000338) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_PHYS(x) (x+0x00000338) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x) (x+0x0000033c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_PHYS(x) (x+0x0000033c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x) (x+0x00000340) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_PHYS(x) (x+0x00000340) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000034c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000034c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000350) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000350) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000360) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000360) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000364) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000364) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000368) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000368) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000036c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000036c) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000370) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000370) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000374) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000374) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000384) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000384) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000388) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000388) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x) (x+0x0000038c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_PHYS(x) (x+0x0000038c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x) (x+0x00000390) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_PHYS(x) (x+0x00000390) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x) (x+0x00000394) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_PHYS(x) (x+0x00000394) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x) (x+0x00000398) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_PHYS(x) (x+0x00000398) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000039c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000039c) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003a0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003a0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003ac) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003ac) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003b0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003b0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003dc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003dc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x) (x+0x000003e0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_PHYS(x) (x+0x000003e0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x) (x+0x000003e4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_PHYS(x) (x+0x000003e4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x) (x+0x000003e8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_PHYS(x) (x+0x000003e8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x) (x+0x000003ec) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_PHYS(x) (x+0x000003ec) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x) (x+0x000003f0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_PHYS(x) (x+0x000003f0) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003f4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003f4) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003f8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003f8) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000404) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000404) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000040c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000040c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000428) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000428) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000042c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000042c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x00000430) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x00000430) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000434) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000434) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000438) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000438) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x) (x+0x0000043c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_PHYS(x) (x+0x0000043c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x) (x+0x00000440) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_PHYS(x) (x+0x00000440) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x) (x+0x00000444) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_PHYS(x) (x+0x00000444) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x) (x+0x00000448) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_PHYS(x) (x+0x00000448) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000044c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000044c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000450) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000450) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000045c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000045c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000460) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000460) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000464) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000464) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000480) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000480) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000484) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000484) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x00000488) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x00000488) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000048c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000048c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000490) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000490) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000494) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000494) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x) (x+0x00000498) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_PHYS(x) (x+0x00000498) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x) (x+0x0000049c) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_PHYS(x) (x+0x0000049c) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x) (x+0x000004a0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_PHYS(x) (x+0x000004a0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004a4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004a4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004a8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004a8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004b4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004b4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004b8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004b8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004bc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004bc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004e4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004e4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x) (x+0x000004e8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_PHYS(x) (x+0x000004e8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x) (x+0x000004ec) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_PHYS(x) (x+0x000004ec) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x) (x+0x000004f0) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_PHYS(x) (x+0x000004f0) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x) (x+0x000004f4) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_PHYS(x) (x+0x000004f4) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x) (x+0x000004f8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_PHYS(x) (x+0x000004f8) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004fc) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004fc) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000500) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000500) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000050c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000050c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000510) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000510) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000514) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000514) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000053c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000053c) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000540) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000540) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000544) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000544) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x) (x+0x00000548) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_PHYS(x) (x+0x00000548) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x) (x+0x0000054c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_PHYS(x) (x+0x0000054c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x) (x+0x00000550) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_PHYS(x) (x+0x00000550) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000554) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000554) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000558) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000558) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000564) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000564) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000568) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000568) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000056c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000056c) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000594) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000594) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000598) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000598) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) (x+0x0000059c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) (x+0x0000059c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) (x+0x000005a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) (x+0x000005a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) (x+0x000005a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) (x+0x000005a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) (x+0x000005a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) (x+0x000005a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000005ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000005ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000005b0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000005b0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000005bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000005bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000005c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000005c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000005c4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000005c4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x000005f0) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x000005f0) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x000005f4) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x000005f4) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x000005f8) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x000005f8) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x000005fc) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x000005fc) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x00000600) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x00000600) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000604) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000604) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000608) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000608) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000614) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000614) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000618) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000618) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000061c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000061c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000644) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000644) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000648) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000648) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) (x+0x0000064c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) (x+0x0000064c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) (x+0x00000650) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) (x+0x00000650) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) (x+0x00000654) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) (x+0x00000654) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) (x+0x00000658) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) (x+0x00000658) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000065c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000065c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000660) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000660) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000066c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000066c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000670) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000670) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000674) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000674) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000690) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000690) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000694) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000694) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x00000698) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x00000698) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000069c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000069c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x) (x+0x000006a0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x) (x+0x000006a0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x) (x+0x000006a4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x) (x+0x000006a4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x) (x+0x000006a8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x) (x+0x000006a8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x) (x+0x000006ac) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x) (x+0x000006ac) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x) (x+0x000006b0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x) (x+0x000006b0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006b4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006b4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006b8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006b8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006c4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006c4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006c8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006c8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006cc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006cc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006e8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006e8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006ec) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006ec) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000006f0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000006f0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006f4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006f4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x) (x+0x000006f8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x) (x+0x000006f8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x) (x+0x000006fc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x) (x+0x000006fc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x) (x+0x00000700) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x) (x+0x00000700) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x) (x+0x00000704) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x) (x+0x00000704) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x) (x+0x00000708) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x) (x+0x00000708) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000070c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000070c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000710) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000710) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000071c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000071c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000720) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000720) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000724) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000724) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000074c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000074c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000750) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000750) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000754) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000754) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x) (x+0x00000758) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_PHYS(x) (x+0x00000758) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x) (x+0x0000075c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_PHYS(x) (x+0x0000075c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x) (x+0x00000760) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_PHYS(x) (x+0x00000760) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000764) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000764) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000768) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000768) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000774) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000774) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000778) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000778) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000077c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000077c) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007a4) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007a4) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x) (x+0x000007a8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_PHYS(x) (x+0x000007a8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x) (x+0x000007ac) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_PHYS(x) (x+0x000007ac) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x) (x+0x000007b0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_PHYS(x) (x+0x000007b0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x) (x+0x000007b4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_PHYS(x) (x+0x000007b4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x) (x+0x000007b8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_PHYS(x) (x+0x000007b8) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000007bc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000007bc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000007c0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000007c0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000007cc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000007cc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007d0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007d0) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007d4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007d4) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007fc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007fc) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000800) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000800) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000804) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000804) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x) (x+0x00000808) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_PHYS(x) (x+0x00000808) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x) (x+0x0000080c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_PHYS(x) (x+0x0000080c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x) (x+0x00000810) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_PHYS(x) (x+0x00000810) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000814) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000814) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000818) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000818) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000081c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000081c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000820) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000820) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000824) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000824) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000828) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000828) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000082c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000082c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000830) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000830) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000834) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000834) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000838) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000838) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000083c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000083c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000840) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000840) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000844) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000844) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000854) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000854) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000858) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000858) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) (x+0x0000085c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) (x+0x0000085c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) (x+0x00000860) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) (x+0x00000860) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) (x+0x00000864) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) (x+0x00000864) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) (x+0x00000868) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) (x+0x00000868) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000086c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000086c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000870) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000870) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000874) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000874) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000878) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000878) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000087c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000087c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000880) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000880) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000884) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000884) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000888) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000888) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000088c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000088c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000890) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000890) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000894) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000894) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000898) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000898) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000089c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000089c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008ac) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008ac) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000008b0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000008b0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000008b4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000008b4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x) (x+0x000008b8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x) (x+0x000008b8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x) (x+0x000008bc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x) (x+0x000008bc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x) (x+0x000008c0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x) (x+0x000008c0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008c4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008c4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008c8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008c8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008d4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008d4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008d8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008d8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008dc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008dc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008f8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008f8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008fc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008fc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000900) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000900) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000904) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000904) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000908) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000908) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x0000090c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x0000090c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) (x+0x00000910) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) (x+0x00000910) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000914) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000914) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) (x+0x00000918) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) (x+0x00000918) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000091c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000091c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000920) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000920) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000092c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000092c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000930) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000930) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000934) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000934) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000950) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000950) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000954) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000954) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000958) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000958) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000095c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000095c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000960) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000960) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000964) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000964) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) (x+0x00000968) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) (x+0x00000968) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) (x+0x0000096c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) (x+0x0000096c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) (x+0x00000970) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) (x+0x00000970) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000974) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000974) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000978) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000978) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000984) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000984) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000988) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000988) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000098c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000098c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000009a8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000009a8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009ac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009ac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000009b0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000009b0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009b4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009b4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000009b8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000009b8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000009bc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000009bc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) (x+0x000009c0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) (x+0x000009c0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) (x+0x000009c4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) (x+0x000009c4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) (x+0x000009c8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) (x+0x000009c8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000009cc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000009cc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000009d0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000009d0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000009dc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000009dc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009e0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009e0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009e4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009e4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000a10) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000a10) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000a14) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000a14) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) (x+0x00000a18) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) (x+0x00000a18) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) (x+0x00000a1c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) (x+0x00000a1c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) (x+0x00000a20) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) (x+0x00000a20) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x0000003f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000a24) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000a24) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000a28) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000a28) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000a34) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000a34) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000a38) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000a38) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a3c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a3c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a5c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a5c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a60) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a60) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a64) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R1_END_OF_TEST_CHECK //// + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_CTRL //// + +#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002004) +#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002004) +#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK 0x00001f3f +#define HWIO_WBM_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), HWIO_WBM_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_BMSK 0x00001f00 +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_SHFT 0x8 + +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK 0x0000003f +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_LOWER //// + +#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002008) +#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002008) +#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R1_TESTBUS_LOWER_RMSK) +#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_HIGHER //// + +#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x) (x+0x0000200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x) (x+0x0000200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK 0x000000ff +#define HWIO_WBM_R1_TESTBUS_HIGHER_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), HWIO_WBM_R1_TESTBUS_HIGHER_RMSK) +#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 + +//// Register WBM_R1_SM_STATES_IX_0 //// + +#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002010) +#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002010) +#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK 0x7fffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_0_RMSK) +#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WBM_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WBM_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 0x1d + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK 0x18000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT 0x1b + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK 0x06000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT 0x19 + +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK 0x01800000 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT 0x17 + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK 0x00600000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT 0x15 + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK 0x00180000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT 0x13 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK 0x00060000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT 0x11 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK 0x00018000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT 0xf + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK 0x00007000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT 0xc + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK 0x00000c00 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT 0xa + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x00000380 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT 0x7 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x00000060 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT 0x5 + +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK 0x0000001c +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT 0x2 + +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK 0x00000003 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT 0x0 + +//// Register WBM_R1_SM_STATES_IX_1 //// + +#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002014) +#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002014) +#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK 0x0000ffff +#define HWIO_WBM_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_1_RMSK) +#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_WBM_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_WBM_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0x0000e000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 0xd + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK 0x00001c00 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT 0xa + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK 0x00000380 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT 0x7 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK 0x00000070 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT 0x4 + +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK 0x0000000c +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT 0x2 + +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK 0x00000003 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_0 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00002018) +#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00002018) +#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_1 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000201c) +#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000201c) +#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_2 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00002020) +#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00002020) +#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_3 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00002024) +#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00002024) +#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_3_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0x0 + +//// Register WBM_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00002028) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00002028) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register WBM_R2_PPE_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x) (x+0x00003000) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_PHYS(x) (x+0x00003000) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_PPE_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x) (x+0x00003004) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_PHYS(x) (x+0x00003004) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_TQM_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x) (x+0x00003008) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x) (x+0x00003008) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_TQM_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x) (x+0x0000300c) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x) (x+0x0000300c) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_REO_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003010) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003010) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_REO_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003014) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003014) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_SW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) (x+0x00003018) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) (x+0x00003018) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_SW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) (x+0x0000301c) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) (x+0x0000301c) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_FW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x) (x+0x00003020) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x) (x+0x00003020) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_FW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x) (x+0x00003024) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x) (x+0x00003024) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA0_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x) (x+0x00003028) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x) (x+0x00003028) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA0_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x) (x+0x0000302c) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x) (x+0x0000302c) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA1_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x) (x+0x00003030) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_PHYS(x) (x+0x00003030) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA1_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x) (x+0x00003034) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_PHYS(x) (x+0x00003034) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA2_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x) (x+0x00003038) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_PHYS(x) (x+0x00003038) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA2_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x) (x+0x0000303c) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_PHYS(x) (x+0x0000303c) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2PPE_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x) (x+0x00003040) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_PHYS(x) (x+0x00003040) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2PPE_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x) (x+0x00003044) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_PHYS(x) (x+0x00003044) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x) (x+0x00003048) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_PHYS(x) (x+0x00003048) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x) (x+0x0000304c) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_PHYS(x) (x+0x0000304c) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x) (x+0x00003050) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_PHYS(x) (x+0x00003050) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x) (x+0x00003054) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_PHYS(x) (x+0x00003054) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x) (x+0x00003058) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_PHYS(x) (x+0x00003058) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x) (x+0x0000305c) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_PHYS(x) (x+0x0000305c) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x) (x+0x00003060) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_PHYS(x) (x+0x00003060) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x) (x+0x00003064) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_PHYS(x) (x+0x00003064) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x) (x+0x00003068) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_PHYS(x) (x+0x00003068) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x) (x+0x0000306c) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_PHYS(x) (x+0x0000306c) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2TQM_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) (x+0x00003070) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) (x+0x00003070) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2TQM_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) (x+0x00003074) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) (x+0x00003074) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2REO_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003078) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003078) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2REO_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000307c) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000307c) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x) (x+0x00003080) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x) (x+0x00003080) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x) (x+0x00003084) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x) (x+0x00003084) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x) (x+0x00003088) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x) (x+0x00003088) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x) (x+0x0000308c) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x) (x+0x0000308c) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x) (x+0x00003090) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x) (x+0x00003090) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x) (x+0x00003094) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x) (x+0x00003094) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x) (x+0x00003098) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_PHYS(x) (x+0x00003098) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA1_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x) (x+0x0000309c) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_PHYS(x) (x+0x0000309c) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x) (x+0x000030a0) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_PHYS(x) (x+0x000030a0) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA2_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x) (x+0x000030a4) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_PHYS(x) (x+0x000030a4) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x) (x+0x000030a8) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_PHYS(x) (x+0x000030a8) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x) (x+0x000030ac) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_PHYS(x) (x+0x000030ac) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) (x+0x000030b0) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) (x+0x000030b0) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) (x+0x000030b4) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) (x+0x000030b4) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x) (x+0x000030b8) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x) (x+0x000030b8) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x) (x+0x000030bc) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x) (x+0x000030bc) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW0_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) (x+0x000030c0) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) (x+0x000030c0) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW0_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) (x+0x000030c4) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) (x+0x000030c4) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW1_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) (x+0x000030c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) (x+0x000030c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW1_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) (x+0x000030cc) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) (x+0x000030cc) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW2_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) (x+0x000030d0) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) (x+0x000030d0) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW2_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) (x+0x000030d4) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) (x+0x000030d4) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW3_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) (x+0x000030d8) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) (x+0x000030d8) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW3_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) (x+0x000030dc) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) (x+0x000030dc) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/hw/qca8074/v1/wbm_release_ring.h b/hw/qca8074/v1/wbm_release_ring.h new file mode 100644 index 000000000000..fb25038ad76f --- /dev/null +++ b/hw/qca8074/v1/wbm_release_ring.h @@ -0,0 +1,1418 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "tx_rate_stats_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info released_buff_or_desc_addr_info; +// 2 release_source_module[2:0], bm_action[5:3], buffer_or_desc_type[8:6], first_msdu_index[12:9], tqm_release_reason[15:13], rxdma_push_reason[17:16], rxdma_error_code[22:18], reo_push_reason[24:23], reo_error_code[29:25], wbm_internal_error[30], reserved_2[31] +// 3 tqm_status_number[23:0], transmit_count[30:24], reserved_3a[31] +// 4 ack_frame_rssi[7:0], sw_release_details_valid[8], first_msdu[9], last_msdu[10], msdu_part_of_amsdu[11], fw_tx_notify_frame[12], buffer_timestamp[31:13] +// 5-6 struct tx_rate_stats_info tx_rate_stats; +// 7 sw_peer_id[15:0], tid[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, //[2:0] + bm_action : 3, //[5:3] + buffer_or_desc_type : 3, //[8:6] + first_msdu_index : 4, //[12:9] + tqm_release_reason : 3, //[15:13] + rxdma_push_reason : 2, //[17:16] + rxdma_error_code : 5, //[22:18] + reo_push_reason : 2, //[24:23] + reo_error_code : 5, //[29:25] + wbm_internal_error : 1, //[30] + reserved_2 : 1; //[31] + uint32_t tqm_status_number : 24, //[23:0] + transmit_count : 7, //[30:24] + reserved_3a : 1; //[31] + uint32_t ack_frame_rssi : 8, //[7:0] + sw_release_details_valid : 1, //[8] + first_msdu : 1, //[9] + last_msdu : 1, //[10] + msdu_part_of_amsdu : 1, //[11] + fw_tx_notify_frame : 1, //[12] + buffer_timestamp : 19; //[31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, //[15:0] + tid : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info released_buff_or_desc_addr_info + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Details of the physical address of the buffer or link + descriptor that is being released. Note that within this + descriptor, WBM will look at the 'owner' of the released + buffer/descriptor and forward it to SW/FW is WBM is not the + owner. + +release_source_module + + Indicates which module initiated the release of this + buffer or descriptor + + + + TQM released this buffer or + descriptor + + RXDMA released this buffer + or descriptor + + REO released this buffer or + descriptor + + FW released this buffer or + descriptor + + SW released this buffer or + descriptor + + + +bm_action + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + + WBM_IDLE_BUF_LIST or + + WBM_IDLE_DESC_LIST + + + + An MSDU extension descriptor shall never be marked as + + + + Put the buffer or descriptor + back in the idle list. In case of MSDU or MDPU link + descriptor, BM does not need to check to release any + individual MSDU buffers + + + + This BM action can only be + used in combination with buffer_or_desc_type being + msdu_link_descriptor. Field first_msdu_index points out + which MSDU pointer in the MSDU link descriptor is the first + of an MPDU that is released. + + BM shall release all the MSDU buffers linked to this + first MSDU buffer pointer. All related MSDU buffer pointer + entries shall be set to value 0, which represents the 'NULL + pointer. When all MSDU buffer pointers in the MSDU link + descriptor are 'NULL', the MSDU link descriptor itself shall + also be released. + + + + CURRENTLY NOT + IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + + + +buffer_or_desc_type + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when WBM is marked as the + return_buffer_manager in the Released_Buffer_address_info + + + + Indicates that type of buffer or descriptor is being + released + + + + The address points to an MSDU + buffer + + The address points to an + TX MSDU link descriptor + + The address points to an + MPDU link descriptor + + The address points to an + MSDU extension descriptor. + + In case BM finds this one in a release ring, it passes + it on to FW... + + The address points to an + TQM queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + + + + +first_msdu_index + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid for the bm_action release_msdu_list. + + + + The index of the first MSDU in an MSDU link descriptor + all belonging to the same MPDU. + + + + + +tqm_release_reason + + Consumer: WBM/SW/FW + + Producer: TQM + + + + Field only valid when Release_source_module is set to + release_source_TQM + + + + (rr = Release Reason) + + frame is removed because an + ACK of BA for it was received + + frame is removed because a + remove command of type Remove_mpdus initiated by SW + + frame is removed because a + remove command of type Remove_transmitted_mpdus initiated by + SW + + frame is removed because a + remove command of type Remove_untransmitted_mpdus initiated + by SW + + frame is removed because a + remove command of type Remove_aged_mpdus or + Remove_aged_msdus initiated by SW + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + + + + +rxdma_push_reason + + Field only valid when Release_source_module is set to + release_source_RXDMA + + + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + + +rxdma_error_code + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + +reo_push_reason + + Field only valid when Release_source_module is set to + release_source_REO + + + + Indicates why REO pushed the frame to this release ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + +reo_error_code + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + + +wbm_internal_error + + Can only be set by WBM. + + + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link + related activity + + OR + + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + + + + +reserved_2 + + + +tqm_status_number + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The value in this field is equal to value of the + 'TQM_CMD_Number' field the TQM command or the + 'TQM_add_cmd_Number' field from the TQM entrance ring + descriptor + + + + This field helps to correlate the statuses with the TQM + commands. + + + + NOTE that SW could program this number to be equal to + the PPDU_ID number in case direct correlation with the PPDU + ID is desired + + + + + +transmit_count + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The number of times this frame has been transmitted + +reserved_3a + + + +ack_frame_rssi + + This field is only valid when the source is TQM. + + + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the + received ACK or BA frame. + + + + When the frame is removed as result of a direct remove + command from the SW, this field is set to 0x0 (which is + never a valid value when real RSSI is available) + + + + + +sw_release_details_valid + + Consumer: SW + + Producer: WBM + + + + When set, some WBM specific release info for SW is + valid. + + This is set when WMB got a 'release_msdu_list' command + from TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + + + + +first_msdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the first MSDU pointed to in the + 'release_msdu_list' command. + + + + + +last_msdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the last MSDU pointed to in the + 'release_msdu_list' command. + + + + + +msdu_part_of_amsdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU was part of an A-MSDU in MPDU + + + +fw_tx_notify_frame + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the FW_tx_notify_frame field from the + + + +buffer_timestamp + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the Buffer_timestamp field from the + + + +struct tx_rate_stats_info tx_rate_stats + + Consumer: TQM + + Producer: SW/SCH(from TXPCU, PDG) + + + + Details for command execution tracking purposes. + +sw_peer_id + + Field only valid when Release_source_module is set to + release_source_TQM + + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or + TX_MPDU_QUEUE descriptor + + + +tid + + Field only valid when Release_source_module is set to + release_source_TQM + + + + TID of the flow or MPDU queue + + + +ring_id + + Consumer: TQM/REO/RXDMA/SW + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + A count value that indicates the number of times the + producer of entries into the Buffer Manager Ring has looped + around the ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + +#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_OFFSET 0x00000000 +#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_LSB 28 +#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_MASK 0xffffffff +#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_LSB 28 +#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_MASK 0xffffffff + +/* Description WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this + buffer or descriptor + + + + TQM released this buffer or + descriptor + + RXDMA released this buffer + or descriptor + + REO released this buffer or + descriptor + + FW released this buffer or + descriptor + + SW released this buffer or + descriptor + + +*/ +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +/* Description WBM_RELEASE_RING_2_BM_ACTION + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + + WBM_IDLE_BUF_LIST or + + WBM_IDLE_DESC_LIST + + + + An MSDU extension descriptor shall never be marked as + + + + Put the buffer or descriptor + back in the idle list. In case of MSDU or MDPU link + descriptor, BM does not need to check to release any + individual MSDU buffers + + + + This BM action can only be + used in combination with buffer_or_desc_type being + msdu_link_descriptor. Field first_msdu_index points out + which MSDU pointer in the MSDU link descriptor is the first + of an MPDU that is released. + + BM shall release all the MSDU buffers linked to this + first MSDU buffer pointer. All related MSDU buffer pointer + entries shall be set to value 0, which represents the 'NULL + pointer. When all MSDU buffer pointers in the MSDU link + descriptor are 'NULL', the MSDU link descriptor itself shall + also be released. + + + + CURRENTLY NOT + IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + + +*/ +#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 + +/* Description WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when WBM is marked as the + return_buffer_manager in the Released_Buffer_address_info + + + + Indicates that type of buffer or descriptor is being + released + + + + The address points to an MSDU + buffer + + The address points to an + TX MSDU link descriptor + + The address points to an + MPDU link descriptor + + The address points to an + MSDU extension descriptor. + + In case BM finds this one in a release ring, it passes + it on to FW... + + The address points to an + TQM queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + + + +*/ +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +/* Description WBM_RELEASE_RING_2_FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid for the bm_action release_msdu_list. + + + + The index of the first MSDU in an MSDU link descriptor + all belonging to the same MPDU. + + + + +*/ +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 + +/* Description WBM_RELEASE_RING_2_TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + + Producer: TQM + + + + Field only valid when Release_source_module is set to + release_source_TQM + + + + (rr = Release Reason) + + frame is removed because an + ACK of BA for it was received + + frame is removed because a + remove command of type Remove_mpdus initiated by SW + + frame is removed because a + remove command of type Remove_transmitted_mpdus initiated by + SW + + frame is removed because a + remove command of type Remove_untransmitted_mpdus initiated + by SW + + frame is removed because a + remove command of type Remove_aged_mpdus or + Remove_aged_msdus initiated by SW + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + + + +*/ +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0000e000 + +/* Description WBM_RELEASE_RING_2_RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to + release_source_RXDMA + + + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + + + +*/ +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 16 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00030000 + +/* Description WBM_RELEASE_RING_2_RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request +*/ +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 18 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x007c0000 + +/* Description WBM_RELEASE_RING_2_REO_PUSH_REASON + + Field only valid when Release_source_module is set to + release_source_REO + + + + Indicates why REO pushed the frame to this release ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + +*/ +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 23 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x01800000 + +/* Description WBM_RELEASE_RING_2_REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + +*/ +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 25 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x3e000000 + +/* Description WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR + + Can only be set by WBM. + + + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link + related activity + + OR + + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + + + +*/ +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 30 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x40000000 + +/* Description WBM_RELEASE_RING_2_RESERVED_2 + + +*/ +#define WBM_RELEASE_RING_2_RESERVED_2_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RESERVED_2_LSB 31 +#define WBM_RELEASE_RING_2_RESERVED_2_MASK 0x80000000 + +/* Description WBM_RELEASE_RING_3_TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The value in this field is equal to value of the + 'TQM_CMD_Number' field the TQM command or the + 'TQM_add_cmd_Number' field from the TQM entrance ring + descriptor + + + + This field helps to correlate the statuses with the TQM + commands. + + + + NOTE that SW could program this number to be equal to + the PPDU_ID number in case direct correlation with the PPDU + ID is desired + + + + +*/ +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff + +/* Description WBM_RELEASE_RING_3_TRANSMIT_COUNT + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The number of times this frame has been transmitted +*/ +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 + +/* Description WBM_RELEASE_RING_3_RESERVED_3A + + +*/ +#define WBM_RELEASE_RING_3_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_RESERVED_3A_LSB 31 +#define WBM_RELEASE_RING_3_RESERVED_3A_MASK 0x80000000 + +/* Description WBM_RELEASE_RING_4_ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the + received ACK or BA frame. + + + + When the frame is removed as result of a direct remove + command from the SW, this field is set to 0x0 (which is + never a valid value when real RSSI is available) + + + + +*/ +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff + +/* Description WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID + + Consumer: SW + + Producer: WBM + + + + When set, some WBM specific release info for SW is + valid. + + This is set when WMB got a 'release_msdu_list' command + from TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + + + +*/ +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 + +/* Description WBM_RELEASE_RING_4_FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the first MSDU pointed to in the + 'release_msdu_list' command. + + + + +*/ +#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 +#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 + +/* Description WBM_RELEASE_RING_4_LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the last MSDU pointed to in the + 'release_msdu_list' command. + + + + +*/ +#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 +#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 + +/* Description WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU was part of an A-MSDU in MPDU + + +*/ +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 + +/* Description WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the FW_tx_notify_frame field from the + + +*/ +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 + +/* Description WBM_RELEASE_RING_4_BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the Buffer_timestamp field from the + + +*/ +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 13 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 0xffffffff +#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 0x00000018 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 13 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 0xffffffff + +/* Description WBM_RELEASE_RING_7_SW_PEER_ID + + Field only valid when Release_source_module is set to + release_source_TQM + + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or + TX_MPDU_QUEUE descriptor + + +*/ +#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff + +/* Description WBM_RELEASE_RING_7_TID + + Field only valid when Release_source_module is set to + release_source_TQM + + + + TID of the flow or MPDU queue + + +*/ +#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_TID_LSB 16 +#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 + +/* Description WBM_RELEASE_RING_7_RING_ID + + Consumer: TQM/REO/RXDMA/SW + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_RING_ID_LSB 20 +#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description WBM_RELEASE_RING_7_LOOPING_COUNT + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + A count value that indicates the number of times the + producer of entries into the Buffer Manager Ring has looped + around the ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _WBM_RELEASE_RING_H_ diff --git a/hw/qca8074/v1/wcss_seq_hwiobase.h b/hw/qca8074/v1/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..8efcab08ecce --- /dev/null +++ b/hw/qca8074/v1/wcss_seq_hwiobase.h @@ -0,0 +1,731 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WCSS_SEQ_BASE_H__ +#define __WCSS_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wcss +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WCSS_ECAHB_OFFSET 0x00008000 +#define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 +#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 +#define SEQ_WCSS_MPSS_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00240000 +#define SEQ_WCSS_MPSS_PCSS_B_REG_MAP_OFFSET 0x00250000 +#define SEQ_WCSS_PHYA0_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 +#define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET 0x00484000 +#define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 +#define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 +#define SEQ_WCSS_PHYA0_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 +#define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 +#define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00530000 +#define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 +#define SEQ_WCSS_PHYA1_OFFSET 0x00600000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00600000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET 0x00680000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00680400 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00680800 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00680c00 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00681000 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00681400 +#define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET 0x00684000 +#define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET 0x00688000 +#define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET 0x00700000 +#define SEQ_WCSS_PHYA1_WFAX_ROBE_REG_MAP_OFFSET 0x00720000 +#define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET 0x00728000 +#define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00730000 +#define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET 0x007a0000 +#define SEQ_WCSS_PHYB_OFFSET 0x00800000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 +#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 +#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 +#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00900000 +#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000 +#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 +#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 +#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 +#define SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 +#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 +#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 +#define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 +#define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 +#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 +#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 +#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 +#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 +#define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000 +#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 +#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 +#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 +#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 +#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 +#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 +#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 +#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 +#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 +#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 +#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 +#define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000 +#define SEQ_WCSS_WMAC1_OFFSET 0x00ac0000 +#define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00ac0000 +#define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00ac3000 +#define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00ac6000 +#define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00ac9000 +#define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00acc000 +#define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00acf000 +#define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00ad2000 +#define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00ad5000 +#define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00ad8000 +#define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00adb000 +#define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00ade000 +#define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00ae1000 +#define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00ae4000 +#define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00ae7000 +#define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00aea000 +#define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00af0000 +#define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00af3000 +#define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00af6000 +#define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00af9000 +#define SEQ_WCSS_WMAC2_OFFSET 0x00b00000 +#define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000 +#define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000 +#define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000 +#define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000 +#define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000 +#define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000 +#define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000 +#define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000 +#define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 +#define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000 +#define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000 +#define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 +#define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000 +#define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000 +#define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000 +#define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000 +#define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000 +#define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000 +#define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000 +#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 +#define SEQ_WCSS_WCMN_OFFSET 0x00b50000 +#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 +#define SEQ_WCSS_PMM_OFFSET 0x00b70000 +#define SEQ_WCSS_ZINC_RFA_CMN_OFFSET 0x00b80000 +#define SEQ_WCSS_ZINC_RFA_CMN_PLL_A_OFFSET 0x00b80000 +#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00b80100 +#define SEQ_WCSS_ZINC_RFA_CMN_PLL_B_OFFSET 0x00b82000 +#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00b82100 +#define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00b84000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00b88000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00b88100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x00b884c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00b88500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00b88600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00b88800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00b88900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88a00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00b88cc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00b88d00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00b88e00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00b89000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00b89100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x00b894c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00b89500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00b89600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00b89800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00b89900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89a00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00b89cc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00b89d00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00b89e00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x00b8a000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x00b8a100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x00b8a4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x00b8a500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x00b8a600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x00b8a800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x00b8a900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8aa00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x00b8acc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x00b8ad00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x00b8ae00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x00b8b000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x00b8b100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x00b8b4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x00b8b500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x00b8b600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x00b8b800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x00b8b900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8ba00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x00b8bcc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x00b8bd00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x00b8be00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x00b8c000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x00b8c100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x00b8c440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x00b8c4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x00b8c500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x00b8c600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x00b8c800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x00b8c900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8ca00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x00b8cc40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x00b8ccc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x00b8cd00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x00b8ce00 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x00b8d000 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x00b8d100 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d200 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x00b8d440 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x00b8d4c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x00b8d500 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x00b8d600 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x00b8d800 +#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x00b8d900 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8da00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x00b8dc40 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x00b8dcc0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x00b8dd00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x00b8de00 +#define SEQ_WCSS_DBG_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 +#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 +#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 +#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 +#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 +#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 +#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 +#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 +#define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 +#define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 +#define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 +#define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000 +#define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 +#define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 +#define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 +#define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYA_CPU1_AHB_AP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 +#define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 +#define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 +#define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET 0x00bce000 +#define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET 0x00bf0000 +#define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 +#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 +#define SEQ_WCSS_CC_OFFSET 0x00c30000 +#define SEQ_WCSS_ACMT_OFFSET 0x00c40000 +#define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 +#define SEQ_WCSS_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00c60000 +#define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 +#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 +#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfax_top +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 +#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 +#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00130000 +#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfax_top_b +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 +#define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 +#define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 +#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 +#define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block umac_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 +#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 +#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 +#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 +#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 +#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 +#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 +#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 +#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 +#define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfss_ce_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 +#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block cxc_top_reg_14lpp +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_CXC_TOP_REG_14LPP_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_14LPP_CXC_PMH_REG_OFFSET 0x0000a000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wmac_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 +#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_cmn +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_CMN_PLL_A_OFFSET 0x00000000 +#define SEQ_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100 +#define SEQ_RFA_CMN_PLL_B_OFFSET 0x00002000 +#define SEQ_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100 +#define SEQ_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008200 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008a00 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009200 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900 +#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009a00 +#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a200 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000aa00 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b200 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800 +#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900 +#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000ba00 +#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c200 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000ca00 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d200 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d300 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600 +#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800 +#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900 +#define SEQ_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000da00 +#define SEQ_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0 +#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00 +#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wcssdbg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 +#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 +#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 +#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 +#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 +#define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 +#define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 +#define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 +#define SEQ_WCSSDBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 +#define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 +#define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 +#define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 +#define SEQ_WCSSDBG_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYA_CPU1_AHB_AP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 +#define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 +#define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 +#define SEQ_WCSSDBG_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000 +#define SEQ_WCSSDBG_UMAC_CPU_AHB_AP_OFFSET 0x00060000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wrapper_acmt +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block qdsp6ss_public +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block qdsp6ss_private +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 +#define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 +#define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 +#define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 +#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 + + +#endif + diff --git a/hw/qca8074/v1/wfss_ce_reg_seq_hwiobase.h b/hw/qca8074/v1/wfss_ce_reg_seq_hwiobase.h new file mode 100644 index 000000000000..a27a10d8aad9 --- /dev/null +++ b/hw/qca8074/v1/wfss_ce_reg_seq_hwiobase.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WFSS_CE_REG_SEQ_BASE_H__ +#define __WFSS_CE_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfss_ce_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 +#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 +#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 +#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 +#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 +#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 +#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 +#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 +#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 +#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 +#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 +#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 +#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 +#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 + + +#endif + diff --git a/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h b/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h new file mode 100644 index 000000000000..b66ae4fffda2 --- /dev/null +++ b/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h @@ -0,0 +1,2361 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// User Name:pgohil +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WFSS_CE_REG_SEQ_REG_H__ +#define __WFSS_CE_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "wfss_ce_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_CHANNEL_DST_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) (x+0x00000064) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) (x+0x00000064) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) (x+0x00000068) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) (x+0x00000068) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000006c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000006c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000070) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000070) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000000a8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000000a8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) (x+0x000000b0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) (x+0x000000b0) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x0001ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) (x+0x000000b4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) (x+0x000000b4) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) (x+0x000000b8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) (x+0x000000b8) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0x0000000f +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) (x+0x00000408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) (x+0x00000408) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP //// + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) (x+0x0000040c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) (x+0x0000040c) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_CHANNEL_SRC_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) (x+0x00000000) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) (x+0x00000004) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) (x+0x0000000c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) (x+0x00000010) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x0000003f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) (x+0x00000050) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) (x+0x00000058) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x0000001f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) (x+0x0000005c) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x0000001f +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x00000010 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x00000002 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x00000001 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) (x+0x00000060) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) (x+0x00000400) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP //// + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) (x+0x00000404) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT 0 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_COMMON_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) (x+0x00000000) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) (x+0x00000000) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) (x+0x00000004) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) (x+0x00000004) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) (x+0x00000008) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) (x+0x00000008) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000000c) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000000c) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000010) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000010) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) (x+0x00000014) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) (x+0x00000014) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) (x+0x00000018) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) (x+0x00000018) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x0000001c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x0000001c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000020) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000020) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) (x+0x00000024) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) (x+0x00000024) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0x007fffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000028) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000028) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) (x+0x0000002c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) (x+0x0000002c) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000030) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000030) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) (x+0x00000034) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) (x+0x00000034) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x01ffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x01000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0x00fff000 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) (x+0x00000038) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) (x+0x00000038) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_SECURITY //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) (x+0x0000003c) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) (x+0x0000003c) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0x00ffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0x00fff000 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) (x+0x00000040) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) (x+0x00000040) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x01ffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x01000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0x00fff000 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) (x+0x00000044) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) (x+0x00000044) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) (x+0x00000048) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) (x+0x00000048) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) (x+0x0000004c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) (x+0x0000004c) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) (x+0x00000050) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) (x+0x00000050) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) (x+0x00000054) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) (x+0x00000054) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) (x+0x00000058) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) (x+0x00000058) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) (x+0x0000005c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) (x+0x0000005c) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x) (x+0x00000060) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x) (x+0x00000060) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK 0xfffdffff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT 0x1f + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK 0x40000000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT 0x1e + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK 0x3ffc0000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT 0x12 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK 0x00010000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT 0x10 + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK 0x0000f000 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT 0xc + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) (x+0x00000400) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 //// + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00000404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00000404) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 //// + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00000408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00000408) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_TESTBUS_LOW //// + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) (x+0x0000040c) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) (x+0x0000040c) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH //// + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) (x+0x00000410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) (x+0x00000410) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00000414) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00000414) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK //// + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00000418) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00000418) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WFSS_CE_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + + +#endif + diff --git a/hw/qca8074/v1/wfss_pmm_base_struct.h b/hw/qca8074/v1/wfss_pmm_base_struct.h new file mode 100644 index 000000000000..f8ef4721273c --- /dev/null +++ b/hw/qca8074/v1/wfss_pmm_base_struct.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +////////////////////////////////////////////////////////////////////////////// +// wfss_pmm_base_struct.h generated by: GenCStruct.pm +////////////////////////////////////////////////////////////////////////////// +// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!! +////////////////////////////////////////////////////////////////////////////// +// RCS File : -USE CVS LOG- +// Revision : -USE CVS LOG- +// Last Check In : -USE CVS LOG- +////////////////////////////////////////////////////////////////////////////// +// Description : Top C Struct file +// +////////////////////////////////////////////////////////////////////////////// + +#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #ifdef _LSB_TO_MSB_REGS + #ifdef _MSB_TO_LSB_REGS + #error You can not define both _LSB_TO_MSB_REGS and _MSB_TO_LSB_REGS! + #endif + + #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #include "wfss_pmm_base_struct_ltm.h" + #endif + + #ifdef _MSB_TO_LSB_REGS + #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #include "wfss_pmm_base_struct_mtl.h" + #endif + + #ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED + #error You have to define _LSB_TO_MSB_REGS or _MSB_TO_LSB_REGS + #endif + +#endif +