From 5ec4e5b567ea8b92bad1c36d515573e0b250a362 Mon Sep 17 00:00:00 2001
From: Melody Olvera <molvera@quicinc.com>
Date: Fri, 14 Aug 2020 09:39:35 -0700
Subject: [PATCH] ARM: dts: msm: Add LLCC for sdxlemur

Added entry for LLCC in sdxlemur tree.

Change-Id: I84bffd2e554a1e4065fcf89098281bc996d42a56
---
 qcom/sdxlemur.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index 78b602a8a669..3a731cd25eb6 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -432,6 +432,15 @@
 		#hwlock-cells = <1>;
 	};
 
+	cache-controller@9200000 {
+		compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
+		reg = <0x9200000 0x50000>;
+		reg-names = "llcc_base";
+		cap-based-alloc-and-pwr-collapse;
+		clocks = <&aopcc QDSS_CLK>;
+		clock-names = "aopcc_closks";
+	};
+
 	smem: qcom,smem {
 		compatible = "qcom,smem";
 		memory-region = <&smem_mem>;