From f29511ee70da6d5e55a47a318ae7d9c7c581c1b4 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 9 Oct 2020 15:00:54 +0530 Subject: [PATCH] msm: kgsl: Correct sequence of FAL register programming PMU expects FAL QACTIVE signal to be asserted first followed by FAL10VETO. Correct this sequence as per latest recommendation. Change-Id: Id9719377b22281830a84f0af534caf6507bfe797 Signed-off-by: Deepak Kumar --- drivers/gpu/msm/adreno_a6xx_gmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index ba3556f8d1ea..4fdc63fe6b8b 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -1316,9 +1316,9 @@ void a6xx_gmu_register_config(struct adreno_device *adreno_dev) /* Vote veto for FAL10 feature if supported*/ if (a6xx_core->veto_fal10) { - gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 0x1); gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 0x1); + gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 0x1); } /* Turn on TCM retention */