mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
irqchip: mips-gic: Use proper iomem accessors
Get rid of the ugly GICREAD/GICWRITE/GICBIS macros and use proper iomem accessors instead. Since the GIC registers are not directly accessed outside of the GIC driver any more, make gic_base static and move all the GIC register manipulation macros out of gic.h, converting them to static inline functions. Signed-off-by: Andrew Bresticker <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Jason Cooper <[email protected]> Cc: Paul Burton <[email protected]> Cc: Qais Yousef <[email protected]> Cc: John Crispin <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/8127/ Patchwork: https://patchwork.linux-mips.org/patch/8229/ Signed-off-by: Ralf Baechle <[email protected]>
This commit is contained in:
Andrew Bresticker
Ralf Baechle
parent
609ead041b
commit
5f68fea09e
2 changed files with 142 additions and 136 deletions
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@ -23,7 +23,6 @@
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unsigned int gic_frequency;
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unsigned int gic_present;
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unsigned long _gic_base;
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struct gic_pcpu_mask {
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DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
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@ -37,6 +36,7 @@ struct gic_intrmask_regs {
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DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
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};
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static void __iomem *gic_base;
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static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static struct gic_pending_regs pending_regs[NR_CPUS];
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static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
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@ -49,15 +49,82 @@ static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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static void __gic_irq_dispatch(void);
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static inline unsigned int gic_read(unsigned int reg)
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{
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return __raw_readl(gic_base + reg);
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}
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static inline void gic_write(unsigned int reg, unsigned int val)
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{
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__raw_writel(val, gic_base + reg);
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}
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static inline void gic_update_bits(unsigned int reg, unsigned int mask,
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unsigned int val)
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{
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unsigned int regval;
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regval = gic_read(reg);
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regval &= ~mask;
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regval |= val;
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gic_write(reg, regval);
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}
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static inline void gic_reset_mask(unsigned int intr)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
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1 << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_mask(unsigned int intr)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
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1 << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
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GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
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pol << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
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GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
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trig << GIC_INTR_BIT(intr));
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}
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static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
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{
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gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
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1 << GIC_INTR_BIT(intr),
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dual << GIC_INTR_BIT(intr));
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}
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static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
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GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
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}
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static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
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{
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gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
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GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
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GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
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}
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#if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
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cycle_t gic_read_count(void)
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{
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unsigned int hi, hi2, lo;
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do {
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
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hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
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hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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@ -67,7 +134,7 @@ unsigned int gic_get_count_width(void)
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{
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unsigned int bits, config;
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GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), config);
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config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
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bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
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GIC_SH_CONFIG_COUNTBITS_SHF);
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@ -76,9 +143,9 @@ unsigned int gic_get_count_width(void)
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void gic_write_compare(cycle_t cnt)
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{
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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}
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@ -88,10 +155,10 @@ void gic_write_cpu_compare(cycle_t cnt, int cpu)
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local_irq_save(flags);
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
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(int)(cnt >> 32));
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
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(int)(cnt & 0xffffffff));
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local_irq_restore(flags);
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@ -101,8 +168,8 @@ cycle_t gic_read_compare(void)
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{
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unsigned int hi, lo;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
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hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
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lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
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return (((cycle_t) hi) << 32) + lo;
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}
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@ -116,7 +183,7 @@ static bool gic_local_irq_is_routable(int intr)
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if (cpu_has_veic)
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return true;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_CTL), vpe_ctl);
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vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
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switch (intr) {
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case GIC_LOCAL_INT_TIMER:
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return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
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@ -136,7 +203,7 @@ unsigned int gic_get_timer_pending(void)
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{
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unsigned int vpe_pending;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), vpe_pending);
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vpe_pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
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return vpe_pending & GIC_VPE_PEND_TIMER_MSK;
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}
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@ -146,12 +213,13 @@ static void gic_bind_eic_interrupt(int irq, int set)
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irq -= GIC_PIN_TO_VEC_OFFSET;
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/* Set irq to use shadow set */
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GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
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GIC_VPE_EIC_SS(irq), set);
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}
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void gic_send_ipi(unsigned int intr)
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{
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GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
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gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
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}
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int gic_get_c0_compare_int(void)
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@ -178,23 +246,21 @@ static unsigned int gic_get_int(void)
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{
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unsigned int i;
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unsigned long *pending, *intrmask, *pcpu_mask;
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unsigned long *pending_abs, *intrmask_abs;
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unsigned long pending_reg, intrmask_reg;
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/* Get per-cpu bitmaps */
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pending = pending_regs[smp_processor_id()].pending;
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intrmask = intrmask_regs[smp_processor_id()].intrmask;
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pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
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pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
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GIC_SH_PEND_31_0_OFS);
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intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
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GIC_SH_MASK_31_0_OFS);
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pending_reg = GIC_REG(SHARED, GIC_SH_PEND_31_0);
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intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK_31_0);
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for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
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GICREAD(*pending_abs, pending[i]);
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GICREAD(*intrmask_abs, intrmask[i]);
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pending_abs++;
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intrmask_abs++;
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pending[i] = gic_read(pending_reg);
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intrmask[i] = gic_read(intrmask_reg);
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pending_reg += 0x4;
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intrmask_reg += 0x4;
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}
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bitmap_and(pending, pending, intrmask, gic_shared_intrs);
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@ -205,19 +271,19 @@ static unsigned int gic_get_int(void)
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static void gic_mask_irq(struct irq_data *d)
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{
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GIC_CLR_INTR_MASK(GIC_HWIRQ_TO_SHARED(d->hwirq));
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gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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GIC_SET_INTR_MASK(GIC_HWIRQ_TO_SHARED(d->hwirq));
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gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
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}
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static void gic_ack_irq(struct irq_data *d)
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{
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unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
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gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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@ -229,34 +295,34 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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spin_lock_irqsave(&gic_lock, flags);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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GIC_SET_POLARITY(irq, GIC_POL_NEG);
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GIC_SET_TRIGGER(irq, GIC_TRIG_EDGE);
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GIC_SET_DUAL(irq, GIC_TRIG_DUAL_DISABLE);
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gic_set_polarity(irq, GIC_POL_NEG);
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gic_set_trigger(irq, GIC_TRIG_EDGE);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = true;
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break;
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case IRQ_TYPE_EDGE_RISING:
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GIC_SET_POLARITY(irq, GIC_POL_POS);
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GIC_SET_TRIGGER(irq, GIC_TRIG_EDGE);
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GIC_SET_DUAL(irq, GIC_TRIG_DUAL_DISABLE);
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gic_set_polarity(irq, GIC_POL_POS);
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gic_set_trigger(irq, GIC_TRIG_EDGE);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = true;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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/* polarity is irrelevant in this case */
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GIC_SET_TRIGGER(irq, GIC_TRIG_EDGE);
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GIC_SET_DUAL(irq, GIC_TRIG_DUAL_ENABLE);
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gic_set_trigger(irq, GIC_TRIG_EDGE);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
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is_edge = true;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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GIC_SET_POLARITY(irq, GIC_POL_NEG);
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GIC_SET_TRIGGER(irq, GIC_TRIG_LEVEL);
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GIC_SET_DUAL(irq, GIC_TRIG_DUAL_DISABLE);
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gic_set_polarity(irq, GIC_POL_NEG);
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gic_set_trigger(irq, GIC_TRIG_LEVEL);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = false;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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default:
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GIC_SET_POLARITY(irq, GIC_POL_POS);
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GIC_SET_TRIGGER(irq, GIC_TRIG_LEVEL);
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GIC_SET_DUAL(irq, GIC_TRIG_DUAL_DISABLE);
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gic_set_polarity(irq, GIC_POL_POS);
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gic_set_trigger(irq, GIC_TRIG_LEVEL);
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gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
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is_edge = false;
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break;
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}
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@ -292,7 +358,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
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spin_lock_irqsave(&gic_lock, flags);
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/* Re-route this IRQ */
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GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
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gic_map_to_vpe(irq, first_cpu(tmp));
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/* Update the pcpu_masks */
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for (i = 0; i < NR_CPUS; i++)
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@ -331,8 +397,8 @@ static unsigned int gic_get_local_int(void)
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{
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unsigned long pending, masked;
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
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GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_MASK), masked);
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pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
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masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
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bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
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@ -343,14 +409,14 @@ static void gic_mask_local_irq(struct irq_data *d)
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{
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int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
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}
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static void gic_unmask_local_irq(struct irq_data *d)
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{
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int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
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}
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static struct irq_chip gic_local_irq_controller = {
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@ -367,8 +433,8 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
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spin_lock_irqsave(&gic_lock, flags);
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for (i = 0; i < gic_vpes; i++) {
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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@ -381,8 +447,8 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
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spin_lock_irqsave(&gic_lock, flags);
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for (i = 0; i < gic_vpes; i++) {
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GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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@ -462,7 +528,7 @@ static __init void gic_ipi_init_one(unsigned int intr, int cpu,
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GIC_SHARED_TO_HWIRQ(intr));
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int i;
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GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
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gic_map_to_vpe(intr, cpu);
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for (i = 0; i < NR_CPUS; i++)
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clear_bit(intr, pcpu_masks[i].pcpu_mask);
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set_bit(intr, pcpu_masks[cpu].pcpu_mask);
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@ -500,19 +566,19 @@ static void __init gic_basic_init(void)
|
|||
|
||||
/* Setup defaults */
|
||||
for (i = 0; i < gic_shared_intrs; i++) {
|
||||
GIC_SET_POLARITY(i, GIC_POL_POS);
|
||||
GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
|
||||
GIC_CLR_INTR_MASK(i);
|
||||
gic_set_polarity(i, GIC_POL_POS);
|
||||
gic_set_trigger(i, GIC_TRIG_LEVEL);
|
||||
gic_reset_mask(i);
|
||||
}
|
||||
|
||||
for (i = 0; i < gic_vpes; i++) {
|
||||
unsigned int j;
|
||||
|
||||
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
||||
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
||||
for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
|
||||
if (!gic_local_irq_is_routable(j))
|
||||
continue;
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -548,29 +614,29 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
|
|||
for (i = 0; i < gic_vpes; i++) {
|
||||
u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
|
||||
|
||||
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
||||
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
|
||||
|
||||
switch (intr) {
|
||||
case GIC_LOCAL_INT_WD:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
|
||||
break;
|
||||
case GIC_LOCAL_INT_COMPARE:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
|
||||
break;
|
||||
case GIC_LOCAL_INT_TIMER:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
|
||||
break;
|
||||
case GIC_LOCAL_INT_PERFCTR:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
|
||||
break;
|
||||
case GIC_LOCAL_INT_SWINT0:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
|
||||
break;
|
||||
case GIC_LOCAL_INT_SWINT1:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
|
||||
break;
|
||||
case GIC_LOCAL_INT_FDC:
|
||||
GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
|
||||
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
|
||||
break;
|
||||
default:
|
||||
pr_err("Invalid local IRQ %d\n", intr);
|
||||
|
|
@ -593,10 +659,9 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
|
|||
handle_level_irq);
|
||||
|
||||
spin_lock_irqsave(&gic_lock, flags);
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
|
||||
GIC_MAP_TO_PIN_MSK | gic_cpu_pin);
|
||||
gic_map_to_pin(intr, gic_cpu_pin);
|
||||
/* Map to VPE 0 by default */
|
||||
GIC_SH_MAP_TO_VPE_SMASK(intr, 0);
|
||||
gic_map_to_vpe(intr, 0);
|
||||
set_bit(intr, pcpu_masks[0].pcpu_mask);
|
||||
spin_unlock_irqrestore(&gic_lock, flags);
|
||||
|
||||
|
|
@ -622,10 +687,9 @@ void __init gic_init(unsigned long gic_base_addr,
|
|||
{
|
||||
unsigned int gicconfig;
|
||||
|
||||
_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
|
||||
gic_addrspace_size);
|
||||
gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
|
||||
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
|
||||
gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
|
||||
gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
|
||||
GIC_SH_CONFIG_NUMINTRS_SHF;
|
||||
gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
|
||||
|
|
|
|||
Loading…
Reference in a new issue