From 87aee0bf556a3934fbf1bc1faef58b71e95e3ae6 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 11 Mar 2020 17:05:00 -0700 Subject: [PATCH] usb: phy: qmp: Perform DP_COM_SW_RESET during portselect In case lane selection is not passed from controller, we can default to using the HW based portselect signal. But in order to ensure the signal is correctly latched from the PMIC, the PHY must be reset using the USB3_DP_COM_SW_RESET register prior to performing initialization. During this time ensure that the default pinctrl configuration is selected which places the pinmux in portselect mode. Change-Id: I0b9ba53a538fad9f731fd1ca0a9d01751d57a063 Signed-off-by: Jack Pham --- drivers/usb/phy/phy-msm-ssusb-qmp.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/usb/phy/phy-msm-ssusb-qmp.c b/drivers/usb/phy/phy-msm-ssusb-qmp.c index 14aab0fef8fd..ecb548624ed1 100644 --- a/drivers/usb/phy/phy-msm-ssusb-qmp.c +++ b/drivers/usb/phy/phy-msm-ssusb-qmp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. */ #include @@ -17,6 +17,8 @@ #include #include #include +#include +#include enum core_ldo_levels { CORE_LEVEL_NONE = 0, @@ -380,6 +382,17 @@ static void usb_qmp_update_portselect_phymode(struct msm_ssphy_qmp *phy) switch (phy->phy_type) { case USB3_AND_DP: + if (phy->phy.dev->pins) { + writel_relaxed(0x01, + phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]); + + pinctrl_select_state(phy->phy.dev->pins->p, + phy->phy.dev->pins->default_state); + + writel_relaxed(0x00, + phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]); + } + /* override hardware control for reset of qmp phy */ writel_relaxed(SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET, @@ -489,11 +502,6 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) return ret; } - /* perform software reset of PHY common logic */ - if (phy->phy_type == USB3_AND_DP) - writel_relaxed(0x00, - phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]); - /* perform software reset of PCS/Serdes */ writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_SW_RESET]); /* start PCS/Serdes to operation mode */