From ada56f0d988f9ca17549204c47c76ff7fd5a03c5 Mon Sep 17 00:00:00 2001
From: Tony Truong <truong@quicinc.com>
Date: Mon, 22 Feb 2021 14:10:55 -0800
Subject: [PATCH 1/2] ARM: dts: msm: expand iommu-map to support PCIe switch on
 sdxlemur CPE

Additional BDF to SID mappings are needed if a switch and
mutliple endpoints are connected to PCIe root complex. Expand
iommu-map for PCIe on sdxprarie CPE to support such a usecase.

Change-Id: Id7643ab574b1472649bb70121da70a40f31c806c
---
 qcom/sdxlemur-mtp-cpe.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi
index 42f218547fd1..f3673cb5ec28 100644
--- a/qcom/sdxlemur-mtp-cpe.dtsi
+++ b/qcom/sdxlemur-mtp-cpe.dtsi
@@ -5,3 +5,14 @@
 
 };
 
+&pcie0 {
+	iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
+		<0x100 &apps_smmu 0x0201 0x1>,
+		<0x208 &apps_smmu 0x0202 0x1>,
+		<0x210 &apps_smmu 0x0203 0x1>,
+		<0x218 &apps_smmu 0x0204 0x1>,
+		<0x300 &apps_smmu 0x0207 0x1>,
+		<0x400 &apps_smmu 0x0208 0x1>,
+		<0x500 &apps_smmu 0x020C 0x1>,
+		<0x501 &apps_smmu 0x020E 0x1>;
+};

From dff71b3b8cf40da0775ee8adea6e6c81a39240a0 Mon Sep 17 00:00:00 2001
From: Tony Truong <truong@quicinc.com>
Date: Mon, 22 Feb 2021 14:13:55 -0800
Subject: [PATCH 2/2] ARM: dts: msm: add pci DT nodes for PCIe switch for
 sdxlemur CPE

If there is a switch connected to PCIe root complex, the
devicetree hierarchy needs to correctly reflect the physical
connection. Add pci DT nodes for each switch device such as
switch upstream and downstream ports for sdxlemur CPE.

Change-Id: I04ddd33adc67f0ec689d014cd00ed5fa26d02a89
---
 qcom/sdxlemur-mtp-cpe.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi
index f3673cb5ec28..e23998921bb7 100644
--- a/qcom/sdxlemur-mtp-cpe.dtsi
+++ b/qcom/sdxlemur-mtp-cpe.dtsi
@@ -16,3 +16,28 @@
 		<0x500 &apps_smmu 0x020C 0x1>,
 		<0x501 &apps_smmu 0x020E 0x1>;
 };
+
+&pcie0_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	/* BDF 1.0.0 */
+	pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 {
+		reg = <0 0 0 0 0>;
+
+		/* BDF 2.1.0 */
+		pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 {
+			reg = <0x800 0x0 0x0 0x0 0x0>;
+		};
+
+		/* BDF 2.2.0 */
+		pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 {
+			reg = <0x1000 0x0 0x0 0x0 0x0>;
+		};
+
+		/* BDF 2.3.0 */
+		pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 {
+			reg = <0x1800 0x0 0x0 0x0 0x0>;
+		};
+	};
+};