From 5fba839bb3ba14c94f6cbac2e5d5087d00c830c5 Mon Sep 17 00:00:00 2001 From: xuwt2 Date: Mon, 21 Oct 2019 18:44:03 +0800 Subject: [PATCH] mmi_pl_chg: clear pmic limit after remove pd power the pmic current would be limit when 45w pd charger connect, and must clear the pmic limit setting after PD power removed. Change-Id: I814e2825ca29c0975542bda0dcc72f6571ea437a Signed-off-by: xuwt2 Reviewed-on: https://gerrit.mot.com/1439744 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Jianqi Yang Submit-Approved: Jira Key Reviewed-on: https://gerrit.mot.com/1893582 Reviewed-by: Wei Xu Reviewed-by: Xiangpo Zhao --- drivers/power/mmi_parallel_charger/mmi_charger_core.c | 1 + drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/power/mmi_parallel_charger/mmi_charger_core.c b/drivers/power/mmi_parallel_charger/mmi_charger_core.c index 4b482a23f9f7..9f572b1e6bc4 100644 --- a/drivers/power/mmi_parallel_charger/mmi_charger_core.c +++ b/drivers/power/mmi_parallel_charger/mmi_charger_core.c @@ -941,6 +941,7 @@ static void cancel_sm(struct mmi_charger_manager *chip) { cancel_delayed_work_sync(&chip->mmi_chrg_sm_work); flush_delayed_work(&chip->mmi_chrg_sm_work); + mmi_chrg_policy_clear(chip); chip->sm_work_running = false; mmi_chrg_dbg(chip, PR_INTERRUPT, "cancel sync and flush mmi chrg sm work\n"); diff --git a/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c b/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c index 177457ee54b6..ca8b3937b453 100644 --- a/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c +++ b/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c @@ -293,9 +293,12 @@ static void chrg_policy_error_recovery(struct mmi_charger_manager *chip, #define PD_CONT_PWR_CNT 5 void mmi_chrg_policy_clear(struct mmi_charger_manager *chip) { + struct mmi_cp_policy_dev *chrg_list = &g_chrg_list; chrg_dev_init(chip, &g_chrg_list); clear_chrg_dev_error_cnt(chip, &g_chrg_list);; clear_chg_manager(chip); + mmi_set_charing_current(chrg_list->chrg_dev[PMIC_SW], + DISABLE_CHRG_LIMIT); sm_state = PM_STATE_DISCONNECT; chip->pps_volt_comp = PPS_INIT_VOLT_COMP; quit_slave_chrg_cnt = 0;