msm: camera: ife: Disable clock gating at top

Clock gating must be disabled at top level initialize
hardware routine as VFE is reset after resource level
initialize hardware routine.

CRs-Fixed: 2590331
Change-Id: I5c51c402a3a6076f056368493b774daa199228aa
Signed-off-by: Venkat Chinta <vchinta@codeaurora.org>
This commit is contained in:
Venkat Chinta 2019-12-19 16:00:05 -08:00 • committed by Gerrit - the friendly Code Review server
commit 5fec859ec6
2 changed files with 15 additions and 14 deletions

View file

@ -298,20 +298,6 @@ static int cam_vfe_camif_ver3_resource_init(
"failed to enable dsp clk, rc = %d", rc);
}
/* All auto clock gating disabled by default */
CAM_INFO(CAM_ISP, "overriding clock gating");
cam_io_w_mb(0xFFFFFFFF, camif_data->mem_base +
camif_data->common_reg->core_cgc_ovd_0);
cam_io_w_mb(0xFF, camif_data->mem_base +
camif_data->common_reg->core_cgc_ovd_1);
cam_io_w_mb(0x1, camif_data->mem_base +
camif_data->common_reg->ahb_cgc_ovd);
cam_io_w_mb(0x1, camif_data->mem_base +
camif_data->common_reg->noc_cgc_ovd);
return rc;
}

View file

@ -222,9 +222,24 @@ int cam_vfe_top_ver3_init_hw(void *device_priv,
void *init_hw_args, uint32_t arg_size)
{
struct cam_vfe_top_ver3_priv *top_priv = device_priv;
struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data;
top_priv->hw_clk_rate = 0;
/* Disable clock gating at IFE top */
CAM_INFO(CAM_ISP, "Disable clock gating at IFE top");
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_1, 0xFF);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->ahb_cgc_ovd, 0x1);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->noc_cgc_ovd, 0x1);
return 0;
}