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msm: camera: ife: Disable clock gating at top
Clock gating must be disabled at top level initialize hardware routine as VFE is reset after resource level initialize hardware routine. CRs-Fixed: 2590331 Change-Id: I5c51c402a3a6076f056368493b774daa199228aa Signed-off-by: Venkat Chinta <vchinta@codeaurora.org>
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2 changed files with 15 additions and 14 deletions
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@ -298,20 +298,6 @@ static int cam_vfe_camif_ver3_resource_init(
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"failed to enable dsp clk, rc = %d", rc);
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}
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/* All auto clock gating disabled by default */
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CAM_INFO(CAM_ISP, "overriding clock gating");
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cam_io_w_mb(0xFFFFFFFF, camif_data->mem_base +
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camif_data->common_reg->core_cgc_ovd_0);
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cam_io_w_mb(0xFF, camif_data->mem_base +
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camif_data->common_reg->core_cgc_ovd_1);
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cam_io_w_mb(0x1, camif_data->mem_base +
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camif_data->common_reg->ahb_cgc_ovd);
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cam_io_w_mb(0x1, camif_data->mem_base +
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camif_data->common_reg->noc_cgc_ovd);
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return rc;
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}
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@ -222,9 +222,24 @@ int cam_vfe_top_ver3_init_hw(void *device_priv,
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void *init_hw_args, uint32_t arg_size)
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{
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struct cam_vfe_top_ver3_priv *top_priv = device_priv;
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struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data;
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top_priv->hw_clk_rate = 0;
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/* Disable clock gating at IFE top */
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CAM_INFO(CAM_ISP, "Disable clock gating at IFE top");
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cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
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common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF);
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cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
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common_data.common_reg->core_cgc_ovd_1, 0xFF);
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cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
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common_data.common_reg->ahb_cgc_ovd, 0x1);
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cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
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common_data.common_reg->noc_cgc_ovd, 0x1);
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return 0;
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}
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