diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 18a7afb2a5b2..89da79d1e357 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -207,6 +207,18 @@ int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
 	if (rocr && !mmc_host_is_spi(host))
 		*rocr = cmd.resp[0];
 
+	/*
+	 * As per design, internal CRC error flag will be cleared after 3
+	 * MCLK once clear command issued. Since the MCLK will be running
+	 * at 400KHz during initialization, design is taking max of 7.5us
+	 * to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled
+	 * before the source is cleared, CRC INTR bit will be set in the 17th
+	 * bit of INTR status register. So it expected to issue the next
+	 * command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay.
+	 */
+	if (!err)
+		udelay(8);
+
 	return err;
 }
 
diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c
index 22bf528294b9..cf9a263390ff 100644
--- a/drivers/mmc/core/sd_ops.c
+++ b/drivers/mmc/core/sd_ops.c
@@ -155,6 +155,18 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
 	if (rocr && !mmc_host_is_spi(host))
 		*rocr = cmd.resp[0];
 
+	/*
+	 * As per design, internal CRC error flag will be cleared after 3
+	 * MCLK once clear command issued. Since the MCLK will be running
+	 * at 400KHz during initialization, design is taking max of 7.5us
+	 * to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled
+	 * before the source is cleared, CRC INTR bit will be set in the 17th
+	 * bit of INTR status register. So it expected to issue the next
+	 * command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay.
+	 */
+	if (!err)
+		udelay(8);
+
 	return err;
 }