From 1367cac7df38f7a4a0dccc8ee330f194f378cdd0 Mon Sep 17 00:00:00 2001 From: Jun Li Date: Mon, 13 Jul 2020 09:17:41 +0800 Subject: [PATCH] mmc: core: Add at least 3 mclk cycle delay before next command after ACMD41 As per design, internal CRC error flag will be cleared only after 3 MCLK once clear command issued. Since the MCLK will be running at 400KHz during initialization, it will take max of 7.5us (2.5us *3 = 7.5us) to clear the status. If the CMD_CRC_CHECK_EN bit is enabled before the source is cleared, CRC INTR bit will be set in the 17th bit of INTR status register. Because the response of ACMD41 in sd and CMD1 in mmc are R3 response that don't have CRC field, so it is expected to give next command after at least 3 MCLK periods. Change-Id: I31b52a767f2212d33cab15251ab5b37a04b25618 Signed-off-by: Jun Li --- drivers/mmc/core/mmc_ops.c | 12 ++++++++++++ drivers/mmc/core/sd_ops.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 18a7afb2a5b2..89da79d1e357 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -207,6 +207,18 @@ int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) if (rocr && !mmc_host_is_spi(host)) *rocr = cmd.resp[0]; + /* + * As per design, internal CRC error flag will be cleared after 3 + * MCLK once clear command issued. Since the MCLK will be running + * at 400KHz during initialization, design is taking max of 7.5us + * to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled + * before the source is cleared, CRC INTR bit will be set in the 17th + * bit of INTR status register. So it expected to issue the next + * command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay. + */ + if (!err) + udelay(8); + return err; } diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index 22bf528294b9..cf9a263390ff 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -155,6 +155,18 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) if (rocr && !mmc_host_is_spi(host)) *rocr = cmd.resp[0]; + /* + * As per design, internal CRC error flag will be cleared after 3 + * MCLK once clear command issued. Since the MCLK will be running + * at 400KHz during initialization, design is taking max of 7.5us + * to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled + * before the source is cleared, CRC INTR bit will be set in the 17th + * bit of INTR status register. So it expected to issue the next + * command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay. + */ + if (!err) + udelay(8); + return err; }