A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-29 11:11:45 -04:00
Code Issues Projects Releases Packages Wiki Activity

parisc: Initialize PCI bridge cache line and default latency

Browse source 
PCI controllers and pci-pci bridges may have not been fully initialized
regarding cache line and defaul latency.

This partly reverts
commit 5f0e9b4 ("parisc: Remove unused pcibios_init_bus()")

Signed-off-by: Helge Deller <[email protected]>
This commit is contained in:
Helge Deller 2015-12-21 10:00:49 +01:00
commit 602c9c9a01
4 changed files with 33 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
drivers/parisc/dino.c
View file

@ -599,8 +599,10 @@ dino_fixup_bus(struct pci_bus *bus)
** P2PB's only have 2 BARs, no IRQs.
** I'd like to just ignore them for now.
*/
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
pcibios_init_bridge(dev);
continue;
}
/* null out the ROM resource if there is one (we don't
* care about an expansion rom on parisc, since it

4
drivers/parisc/lba_pci.c
View file

@ -790,8 +790,10 @@ lba_fixup_bus(struct pci_bus *bus)
/*
** P2PB's have no IRQs. ignore them.
*/
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
pcibios_init_bridge(dev);
continue;
}
/* Adjust INTERRUPT_LINE for this dev */
iosapic_fixup_irq(ldev->iosapic_obj, dev);