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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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pinctrl: Add s5pv210 support to pinctrl-exynos
This patch implements pinctrl support and adds device tree bindings for s5pv210. Signed-off-by: Mateusz Krawczuk <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
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5 changed files with 64 additions and 2 deletions
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@ -252,7 +252,7 @@ config PINCTRL_SAMSUNG
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config PINCTRL_EXYNOS
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bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
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depends on OF && GPIOLIB && ARCH_EXYNOS
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depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
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select PINCTRL_SAMSUNG
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config PINCTRL_EXYNOS5440
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@ -660,6 +660,64 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
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exynos_pinctrl_resume_bank(drvdata, bank);
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}
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/* pin banks of s5pv210 pin-controller */
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static struct samsung_pin_bank s5pv210_pin_bank[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
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EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
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EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
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EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
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EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpe0", 0x1c),
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EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
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EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpf0", 0x24),
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EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
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EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
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EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf3", 0x30),
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EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
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EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
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EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
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EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
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EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
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EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
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EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
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EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
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EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
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EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
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EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
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EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
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EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
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EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
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EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
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EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
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EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
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EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
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};
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struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
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{
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/* pin-controller instance 0 data */
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.pin_banks = s5pv210_pin_bank,
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.nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.weint_con = EXYNOS_WKUP_ECON_OFFSET,
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.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
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.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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.label = "s5pv210-gpio-ctrl0",
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},
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};
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/* pin banks of exynos4210 pin-controller 0 */
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static struct samsung_pin_bank exynos4210_pin_banks0[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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@ -1122,6 +1122,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = (void *)exynos5250_pin_ctrl },
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{ .compatible = "samsung,exynos5420-pinctrl",
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.data = (void *)exynos5420_pin_ctrl },
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{ .compatible = "samsung,s5pv210-pinctrl",
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.data = (void *)s5pv210_pin_ctrl },
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#endif
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#ifdef CONFIG_PINCTRL_S3C64XX
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{ .compatible = "samsung,s3c64xx-pinctrl",
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@ -260,5 +260,6 @@ extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
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extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
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extern struct samsung_pin_ctrl s5pv210_pin_ctrl[];
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#endif /* __PINCTRL_SAMSUNG_H */
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