From 60a6dd19524dc45e4f8dc08db1e5c76d1b4bb644 Mon Sep 17 00:00:00 2001
From: Yogesh Lal <ylal@qti.qualcomm.com>
Date: Thu, 12 Aug 2021 16:49:20 +0530
Subject: [PATCH] ARM: dts: msm: Add BOOT_CONFIG register offset for sdxlemur

Add BOOT_CONFIG to support the EDL over PCIe for sdxlemur.

Change-Id: Ia33b56d3bbb4e4bf4df1f6ac049b5b85d1938c5a
---
 qcom/sdxlemur-v2.dtsi | 5 +++++
 qcom/sdxlemur.dtsi    | 5 ++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi
index f2cadc6e4814..2d9f76145127 100644
--- a/qcom/sdxlemur-v2.dtsi
+++ b/qcom/sdxlemur-v2.dtsi
@@ -173,3 +173,8 @@
 &pil_modem {
 	qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
 };
+
+
+&dload_mode {
+	qcom,boot-config-shift = <1 4>;
+};
diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index 7187570188f5..84615c9ee0ed 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -196,8 +196,11 @@
 		};
 	};
 
-	dload_mode {
+	dload_mode: dload_mode {
 		compatible = "qcom,dload-mode";
+		reg = <0x786070 0x4>;
+		reg-names = "boot-config";
+		qcom,boot-config-shift = <1 3>;
 	};
 
 	dcc: dcc_v2@117f000 {