mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
Merge branch 'pm-cpufreq'
* pm-cpufreq: (22 commits) cpufreq: stats: Handle the case when trans_table goes beyond PAGE_SIZE cpufreq: arm_big_little: make cpufreq_arm_bL_ops structures const cpufreq: arm_big_little: make function arguments and structure pointer const cpufreq: pxa: convert to clock API cpufreq: speedstep-lib: mark expected switch fall-through cpufreq: ti-cpufreq: add missing of_node_put() cpufreq: dt: Remove support for Exynos4212 SoCs cpufreq: imx6q: Move speed grading check to cpufreq driver cpufreq: ti-cpufreq: kfree opp_data when failure cpufreq: SPEAr: pr_err() strings should end with newlines cpufreq: powernow-k8: pr_err() strings should end with newlines cpufreq: dt-platdev: drop socionext,uniphier-ld6b from whitelist arm64: wire cpu-invariant accounting support up to the task scheduler arm64: wire frequency-invariant accounting support up to the task scheduler arm: wire cpu-invariant accounting support up to the task scheduler arm: wire frequency-invariant accounting support up to the task scheduler drivers base/arch_topology: allow inlining cpu-invariant accounting support drivers base/arch_topology: provide frequency-invariant accounting support cpufreq: dt: invoke frequency-invariance setter function cpufreq: arm_big_little: invoke frequency-invariance setter function ...
This commit is contained in:
Rafael J. Wysocki
commit
60af981c78
22 changed files with 214 additions and 286 deletions
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@ -57,7 +57,7 @@ static bool bL_switching_enabled;
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#define VIRT_FREQ(cluster, freq) ((cluster == A7_CLUSTER) ? freq >> 1 : freq)
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static struct thermal_cooling_device *cdev[MAX_CLUSTERS];
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static struct cpufreq_arm_bL_ops *arm_bL_ops;
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static const struct cpufreq_arm_bL_ops *arm_bL_ops;
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static struct clk *clk[MAX_CLUSTERS];
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static struct cpufreq_frequency_table *freq_table[MAX_CLUSTERS + 1];
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static atomic_t cluster_usage[MAX_CLUSTERS + 1];
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@ -213,6 +213,7 @@ static int bL_cpufreq_set_target(struct cpufreq_policy *policy,
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{
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u32 cpu = policy->cpu, cur_cluster, new_cluster, actual_cluster;
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unsigned int freqs_new;
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int ret;
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cur_cluster = cpu_to_cluster(cpu);
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new_cluster = actual_cluster = per_cpu(physical_cluster, cpu);
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@ -229,7 +230,14 @@ static int bL_cpufreq_set_target(struct cpufreq_policy *policy,
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}
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}
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return bL_cpufreq_set_rate(cpu, actual_cluster, new_cluster, freqs_new);
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ret = bL_cpufreq_set_rate(cpu, actual_cluster, new_cluster, freqs_new);
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if (!ret) {
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arch_set_freq_scale(policy->related_cpus, freqs_new,
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policy->cpuinfo.max_freq);
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}
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return ret;
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}
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static inline u32 get_table_count(struct cpufreq_frequency_table *table)
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@ -609,7 +617,7 @@ static int __bLs_register_notifier(void) { return 0; }
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static int __bLs_unregister_notifier(void) { return 0; }
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#endif
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int bL_cpufreq_register(struct cpufreq_arm_bL_ops *ops)
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int bL_cpufreq_register(const struct cpufreq_arm_bL_ops *ops)
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{
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int ret, i;
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@ -653,7 +661,7 @@ int bL_cpufreq_register(struct cpufreq_arm_bL_ops *ops)
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}
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EXPORT_SYMBOL_GPL(bL_cpufreq_register);
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void bL_cpufreq_unregister(struct cpufreq_arm_bL_ops *ops)
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void bL_cpufreq_unregister(const struct cpufreq_arm_bL_ops *ops)
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{
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if (arm_bL_ops != ops) {
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pr_err("%s: Registered with: %s, can't unregister, exiting\n",
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@ -37,7 +37,7 @@ struct cpufreq_arm_bL_ops {
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void (*free_opp_table)(const struct cpumask *cpumask);
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};
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int bL_cpufreq_register(struct cpufreq_arm_bL_ops *ops);
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void bL_cpufreq_unregister(struct cpufreq_arm_bL_ops *ops);
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int bL_cpufreq_register(const struct cpufreq_arm_bL_ops *ops);
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void bL_cpufreq_unregister(const struct cpufreq_arm_bL_ops *ops);
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#endif /* CPUFREQ_ARM_BIG_LITTLE_H */
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@ -61,7 +61,7 @@ static int dt_get_transition_latency(struct device *cpu_dev)
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return transition_latency;
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}
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static struct cpufreq_arm_bL_ops dt_bL_ops = {
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static const struct cpufreq_arm_bL_ops dt_bL_ops = {
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.name = "dt-bl",
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.get_transition_latency = dt_get_transition_latency,
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.init_opp_table = dev_pm_opp_of_cpumask_add_table,
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@ -48,7 +48,6 @@ static const struct of_device_id whitelist[] __initconst = {
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{ .compatible = "samsung,exynos3250", },
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{ .compatible = "samsung,exynos4210", },
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{ .compatible = "samsung,exynos4212", },
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{ .compatible = "samsung,exynos5250", },
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#ifndef CONFIG_BL_SWITCHER
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{ .compatible = "samsung,exynos5800", },
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@ -83,8 +82,6 @@ static const struct of_device_id whitelist[] __initconst = {
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{ .compatible = "rockchip,rk3368", },
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{ .compatible = "rockchip,rk3399", },
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{ .compatible = "socionext,uniphier-ld6b", },
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{ .compatible = "st-ericsson,u8500", },
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{ .compatible = "st-ericsson,u8540", },
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{ .compatible = "st-ericsson,u9500", },
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@ -43,9 +43,17 @@ static struct freq_attr *cpufreq_dt_attr[] = {
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static int set_target(struct cpufreq_policy *policy, unsigned int index)
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{
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struct private_data *priv = policy->driver_data;
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unsigned long freq = policy->freq_table[index].frequency;
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int ret;
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return dev_pm_opp_set_rate(priv->cpu_dev,
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policy->freq_table[index].frequency * 1000);
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ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);
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if (!ret) {
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arch_set_freq_scale(policy->related_cpus, freq,
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policy->cpuinfo.max_freq);
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}
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return ret;
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}
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/*
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@ -161,6 +161,12 @@ u64 get_cpu_idle_time(unsigned int cpu, u64 *wall, int io_busy)
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}
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EXPORT_SYMBOL_GPL(get_cpu_idle_time);
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__weak void arch_set_freq_scale(struct cpumask *cpus, unsigned long cur_freq,
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unsigned long max_freq)
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{
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}
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EXPORT_SYMBOL_GPL(arch_set_freq_scale);
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/*
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* This is a generic cpufreq init() routine which can be used by cpufreq
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* drivers of SMP systems. It will do following:
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@ -118,8 +118,11 @@ static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf)
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break;
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len += snprintf(buf + len, PAGE_SIZE - len, "\n");
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}
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if (len >= PAGE_SIZE)
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return PAGE_SIZE;
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if (len >= PAGE_SIZE) {
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pr_warn_once("cpufreq transition table exceeds PAGE_SIZE. Disabling\n");
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return -EFBIG;
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}
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return len;
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}
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cpufreq_freq_attr_ro(trans_table);
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@ -12,6 +12,7 @@
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_opp.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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@ -191,6 +192,57 @@ static struct cpufreq_driver imx6q_cpufreq_driver = {
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.suspend = cpufreq_generic_suspend,
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};
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#define OCOTP_CFG3 0x440
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#define OCOTP_CFG3_SPEED_SHIFT 16
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#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
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#define OCOTP_CFG3_SPEED_996MHZ 0x2
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#define OCOTP_CFG3_SPEED_852MHZ 0x1
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static void imx6q_opp_check_speed_grading(struct device *dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np)
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return;
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base = of_iomap(np, 0);
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if (!base) {
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dev_err(dev, "failed to map ocotp\n");
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goto put_node;
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}
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/*
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* SPEED_GRADING[1:0] defines the max speed of ARM:
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* 2b'11: 1200000000Hz;
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* 2b'10: 996000000Hz;
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* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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* 2b'00: 792000000Hz;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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val &= 0x3;
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if ((val != OCOTP_CFG3_SPEED_1P2GHZ) &&
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of_machine_is_compatible("fsl,imx6q"))
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if (dev_pm_opp_disable(dev, 1200000000))
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dev_warn(dev, "failed to disable 1.2GHz OPP\n");
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if (val < OCOTP_CFG3_SPEED_996MHZ)
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if (dev_pm_opp_disable(dev, 996000000))
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dev_warn(dev, "failed to disable 996MHz OPP\n");
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if (of_machine_is_compatible("fsl,imx6q")) {
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if (val != OCOTP_CFG3_SPEED_852MHZ)
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if (dev_pm_opp_disable(dev, 852000000))
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dev_warn(dev, "failed to disable 852MHz OPP\n");
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}
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iounmap(base);
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put_node:
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of_node_put(np);
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}
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static int imx6q_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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@ -252,28 +304,21 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
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goto put_reg;
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}
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/*
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* We expect an OPP table supplied by platform.
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* Just, incase the platform did not supply the OPP
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* table, it will try to get it.
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*/
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (ret < 0) {
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dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
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goto put_reg;
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}
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imx6q_opp_check_speed_grading(cpu_dev);
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/* Because we have added the OPPs here, we must free them */
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free_opp = true;
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num = dev_pm_opp_get_opp_count(cpu_dev);
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if (num < 0) {
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (ret < 0) {
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dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
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goto put_reg;
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}
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/* Because we have added the OPPs here, we must free them */
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free_opp = true;
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num = dev_pm_opp_get_opp_count(cpu_dev);
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if (num < 0) {
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ret = num;
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dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
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goto out_free_opp;
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}
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ret = num;
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dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
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goto out_free_opp;
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}
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ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
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@ -1043,7 +1043,7 @@ static int powernowk8_cpu_init(struct cpufreq_policy *pol)
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data) {
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pr_err("unable to alloc powernow_k8_data");
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pr_err("unable to alloc powernow_k8_data\n");
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return -ENOMEM;
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}
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@ -58,56 +58,40 @@ module_param(pxa27x_maxfreq, uint, 0);
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MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
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"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
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struct pxa_cpufreq_data {
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struct clk *clk_core;
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};
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static struct pxa_cpufreq_data pxa_cpufreq_data;
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struct pxa_freqs {
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unsigned int khz;
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unsigned int membus;
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unsigned int cccr;
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unsigned int div2;
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unsigned int cclkcfg;
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int vmin;
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int vmax;
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};
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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static unsigned int sdram_rows;
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define CCLKCFG_HALFTURBO 0x4
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#define CCLKCFG_FASTBUS 0x8
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
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#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
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/*
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* PXA255 definitions
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*/
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/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
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#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
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|
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static const struct pxa_freqs pxa255_run_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
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{132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
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{199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
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{265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
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{331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
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{398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
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/* CPU MEMBUS run turbo PXbus SDRAM */
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{ 99500, -1, -1}, /* 99, 99, 50, 50 */
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{132700, -1, -1}, /* 133, 133, 66, 66 */
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{199100, -1, -1}, /* 199, 199, 99, 99 */
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{265400, -1, -1}, /* 265, 265, 133, 66 */
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{331800, -1, -1}, /* 331, 331, 166, 83 */
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{398100, -1, -1}, /* 398, 398, 196, 99 */
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};
|
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|
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/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
|
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static const struct pxa_freqs pxa255_turbo_freqs[] =
|
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{
|
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
|
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{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
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{199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
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{298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
|
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{298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
|
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{398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
|
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/* CPU run turbo PXbus SDRAM */
|
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{ 99500, -1, -1}, /* 99, 99, 50, 50 */
|
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{199100, -1, -1}, /* 99, 199, 50, 99 */
|
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{298500, -1, -1}, /* 99, 287, 50, 99 */
|
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{298600, -1, -1}, /* 199, 287, 99, 99 */
|
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{398100, -1, -1}, /* 199, 398, 99, 99 */
|
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};
|
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|
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#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
|
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|
|
@ -122,47 +106,14 @@ static unsigned int pxa255_turbo_table;
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module_param(pxa255_turbo_table, uint, 0);
|
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MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
|
||||
|
||||
/*
|
||||
* PXA270 definitions
|
||||
*
|
||||
* For the PXA27x:
|
||||
* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
|
||||
*
|
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* A = 0 => memory controller clock from table 3-7,
|
||||
* A = 1 => memory controller clock = system bus clock
|
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* Run mode frequency = 13 MHz * L
|
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* Turbo mode frequency = 13 MHz * L * N
|
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* System bus frequency = 13 MHz * L / (B + 1)
|
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*
|
||||
* In CCCR:
|
||||
* A = 1
|
||||
* L = 16 oscillator to run mode ratio
|
||||
* 2N = 6 2 * (turbo mode to run mode ratio)
|
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*
|
||||
* In CCLKCFG:
|
||||
* B = 1 Fast bus mode
|
||||
* HT = 0 Half-Turbo mode
|
||||
* T = 1 Turbo mode
|
||||
*
|
||||
* For now, just support some of the combinations in table 3-7 of
|
||||
* PXA27x Processor Family Developer's Manual to simplify frequency
|
||||
* change sequences.
|
||||
*/
|
||||
#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
|
||||
#define CCLKCFG2(B, HT, T) \
|
||||
(CCLKCFG_FCS | \
|
||||
((B) ? CCLKCFG_FASTBUS : 0) | \
|
||||
((HT) ? CCLKCFG_HALFTURBO : 0) | \
|
||||
((T) ? CCLKCFG_TURBO : 0))
|
||||
|
||||
static struct pxa_freqs pxa27x_freqs[] = {
|
||||
{104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
|
||||
{156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
|
||||
{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
|
||||
{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
|
||||
{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
|
||||
{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
|
||||
{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
|
||||
{104000, 900000, 1705000 },
|
||||
{156000, 1000000, 1705000 },
|
||||
{208000, 1180000, 1705000 },
|
||||
{312000, 1250000, 1705000 },
|
||||
{416000, 1350000, 1705000 },
|
||||
{520000, 1450000, 1705000 },
|
||||
{624000, 1550000, 1705000 }
|
||||
};
|
||||
|
||||
#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
|
||||
|
|
@ -241,51 +192,29 @@ static void pxa27x_guess_max_freq(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void init_sdram_rows(void)
|
||||
{
|
||||
uint32_t mdcnfg = __raw_readl(MDCNFG);
|
||||
unsigned int drac2 = 0, drac0 = 0;
|
||||
|
||||
if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
|
||||
drac2 = MDCNFG_DRAC2(mdcnfg);
|
||||
|
||||
if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
|
||||
drac0 = MDCNFG_DRAC0(mdcnfg);
|
||||
|
||||
sdram_rows = 1 << (11 + max(drac0, drac2));
|
||||
}
|
||||
|
||||
static u32 mdrefr_dri(unsigned int freq)
|
||||
{
|
||||
u32 interval = freq * SDRAM_TREF / sdram_rows;
|
||||
|
||||
return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
|
||||
}
|
||||
|
||||
static unsigned int pxa_cpufreq_get(unsigned int cpu)
|
||||
{
|
||||
return get_clk_frequency_khz(0);
|
||||
struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
|
||||
return (unsigned int) clk_get_rate(data->clk_core) / 1000;
|
||||
}
|
||||
|
||||
static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
|
||||
{
|
||||
struct cpufreq_frequency_table *pxa_freqs_table;
|
||||
const struct pxa_freqs *pxa_freq_settings;
|
||||
unsigned long flags;
|
||||
unsigned int new_freq_cpu, new_freq_mem;
|
||||
unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
|
||||
struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
unsigned int new_freq_cpu;
|
||||
int ret = 0;
|
||||
|
||||
/* Get the current policy */
|
||||
find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
|
||||
|
||||
new_freq_cpu = pxa_freq_settings[idx].khz;
|
||||
new_freq_mem = pxa_freq_settings[idx].membus;
|
||||
|
||||
if (freq_debug)
|
||||
pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
|
||||
new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ?
|
||||
(new_freq_mem / 2000) : (new_freq_mem / 1000));
|
||||
pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
|
||||
policy->cur / 1000, new_freq_cpu / 1000);
|
||||
|
||||
if (vcc_core && new_freq_cpu > policy->cur) {
|
||||
ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
|
||||
|
|
@ -293,53 +222,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
|
||||
* we need to preset the smaller DRI before the change. If we're
|
||||
* speeding up we need to set the larger DRI value after the change.
|
||||
*/
|
||||
preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
|
||||
if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
|
||||
preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
|
||||
preset_mdrefr |= mdrefr_dri(new_freq_mem);
|
||||
}
|
||||
postset_mdrefr =
|
||||
(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
|
||||
|
||||
/* If we're dividing the memory clock by two for the SDRAM clock, this
|
||||
* must be set prior to the change. Clearing the divide must be done
|
||||
* after the change.
|
||||
*/
|
||||
if (pxa_freq_settings[idx].div2) {
|
||||
preset_mdrefr |= MDREFR_DB2_MASK;
|
||||
postset_mdrefr |= MDREFR_DB2_MASK;
|
||||
} else {
|
||||
postset_mdrefr &= ~MDREFR_DB2_MASK;
|
||||
}
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* Set new the CCCR and prepare CCLKCFG */
|
||||
writel(pxa_freq_settings[idx].cccr, CCCR);
|
||||
cclkcfg = pxa_freq_settings[idx].cclkcfg;
|
||||
|
||||
asm volatile(" \n\
|
||||
ldr r4, [%1] /* load MDREFR */ \n\
|
||||
b 2f \n\
|
||||
.align 5 \n\
|
||||
1: \n\
|
||||
str %3, [%1] /* preset the MDREFR */ \n\
|
||||
mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
|
||||
str %4, [%1] /* postset the MDREFR */ \n\
|
||||
\n\
|
||||
b 3f \n\
|
||||
2: b 1b \n\
|
||||
3: nop \n\
|
||||
"
|
||||
: "=&r" (unused)
|
||||
: "r" (MDREFR), "r" (cclkcfg),
|
||||
"r" (preset_mdrefr), "r" (postset_mdrefr)
|
||||
: "r4", "r5");
|
||||
local_irq_restore(flags);
|
||||
clk_set_rate(data->clk_core, new_freq_cpu * 1000);
|
||||
|
||||
/*
|
||||
* Even if voltage setting fails, we don't report it, as the frequency
|
||||
|
|
@ -369,8 +252,6 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy)
|
|||
|
||||
pxa_cpufreq_init_voltages();
|
||||
|
||||
init_sdram_rows();
|
||||
|
||||
/* set default policy and cpuinfo */
|
||||
policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
|
||||
|
||||
|
|
@ -429,11 +310,17 @@ static struct cpufreq_driver pxa_cpufreq_driver = {
|
|||
.init = pxa_cpufreq_init,
|
||||
.get = pxa_cpufreq_get,
|
||||
.name = "PXA2xx",
|
||||
.driver_data = &pxa_cpufreq_data,
|
||||
};
|
||||
|
||||
static int __init pxa_cpu_init(void)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
|
||||
pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
|
||||
if (IS_ERR(pxa_cpufreq_data.clk_core))
|
||||
return PTR_ERR(pxa_cpufreq_data.clk_core);
|
||||
|
||||
if (cpu_is_pxa25x() || cpu_is_pxa27x())
|
||||
ret = cpufreq_register_driver(&pxa_cpufreq_driver);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ static int scpi_init_opp_table(const struct cpumask *cpumask)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static struct cpufreq_arm_bL_ops scpi_cpufreq_ops = {
|
||||
static const struct cpufreq_arm_bL_ops scpi_cpufreq_ops = {
|
||||
.name = "scpi",
|
||||
.get_transition_latency = scpi_get_transition_latency,
|
||||
.init_opp_table = scpi_init_opp_table,
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ static int spear_cpufreq_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_cpu_device_node_get(0);
|
||||
if (!np) {
|
||||
pr_err("No cpu node found");
|
||||
pr_err("No cpu node found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
|
@ -187,7 +187,7 @@ static int spear_cpufreq_probe(struct platform_device *pdev)
|
|||
|
||||
prop = of_find_property(np, "cpufreq_tbl", NULL);
|
||||
if (!prop || !prop->value) {
|
||||
pr_err("Invalid cpufreq_tbl");
|
||||
pr_err("Invalid cpufreq_tbl\n");
|
||||
ret = -ENODEV;
|
||||
goto out_put_node;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -367,7 +367,7 @@ unsigned int speedstep_detect_processor(void)
|
|||
} else
|
||||
return SPEEDSTEP_CPU_PIII_C;
|
||||
}
|
||||
|
||||
/* fall through */
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -205,6 +205,7 @@ static int ti_cpufreq_init(void)
|
|||
|
||||
np = of_find_node_by_path("/");
|
||||
match = of_match_node(ti_cpufreq_of_match, np);
|
||||
of_node_put(np);
|
||||
if (!match)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
@ -217,7 +218,8 @@ static int ti_cpufreq_init(void)
|
|||
opp_data->cpu_dev = get_cpu_device(0);
|
||||
if (!opp_data->cpu_dev) {
|
||||
pr_err("%s: Failed to get device for CPU0\n", __func__);
|
||||
return -ENODEV;
|
||||
ret = ENODEV;
|
||||
goto free_opp_data;
|
||||
}
|
||||
|
||||
opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
|
||||
|
|
@ -262,6 +264,8 @@ register_cpufreq_dt:
|
|||
|
||||
fail_put_node:
|
||||
of_node_put(opp_data->opp_node);
|
||||
free_opp_data:
|
||||
kfree(opp_data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static int ve_spc_get_transition_latency(struct device *cpu_dev)
|
|||
return 1000000; /* 1 ms */
|
||||
}
|
||||
|
||||
static struct cpufreq_arm_bL_ops ve_spc_cpufreq_ops = {
|
||||
static const struct cpufreq_arm_bL_ops ve_spc_cpufreq_ops = {
|
||||
.name = "vexpress-spc",
|
||||
.get_transition_latency = ve_spc_get_transition_latency,
|
||||
.init_opp_table = ve_spc_init_opp_table,
|
||||
|
|
|
|||
Loading…
Reference in a new issue