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mmc: sdhci-msm: Remove unneeded device tree entries

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Remove unnecessary device tree properties from the code.

Change-Id: Id6f59c6874acda03c3f2aa93626eb20a9dc2ac00
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
This commit is contained in:
Veerabhadrarao Badiganti 2020-06-29 18:46:02 +05:30 • committed by Sarthak Garg
commit 60ba92dddf
1 changed files with 31 additions and 124 deletions
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155
drivers/mmc/host/sdhci-msm.c
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@ -352,27 +352,13 @@ struct sdhci_msm_reg_data {
* This structure keeps information for all the
* regulators required for a SDCC slot.
*/
struct sdhci_msm_slot_reg_data {
struct sdhci_msm_vreg_data {
/* keeps VDD/VCC regulator info */
struct sdhci_msm_reg_data *vdd_data;
/* keeps VDD IO regulator info */
struct sdhci_msm_reg_data *vdd_io_data;
};
struct sdhci_msm_pltfm_data {
/* Supported UHS-I Modes */
u32 caps;
/* More capabilities */
u32 caps2;
unsigned long mmc_bus_width;
struct sdhci_msm_slot_reg_data *vreg_data;
bool nonremovable;
bool nonhotplug;
bool largeaddressbus;
};
struct sdhci_msm_host {
struct platform_device *pdev;
void __iomem *core_mem; /* MSM SDCC mapped address */
@ -381,7 +367,7 @@ struct sdhci_msm_host {
struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
unsigned long clk_rate;
struct sdhci_msm_pltfm_data *pdata;
struct sdhci_msm_vreg_data *vreg_data;
struct mmc_host *mmc;
bool use_14lpp_dll_reset;
bool tuning_done;
@ -1581,84 +1567,31 @@ skip_hsr:
}
/* Parse platform data */
static
struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev,
static bool sdhci_msm_populate_pdata(struct device *dev,
struct sdhci_msm_host *msm_host)
{
struct sdhci_msm_pltfm_data *pdata = NULL;
struct device_node *np = dev->of_node;
u32 bus_width = 0;
int len, i;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
goto out;
of_property_read_u32(np, "qcom,bus-width", &bus_width);
if (bus_width == 8)
pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA;
else if (bus_width == 4)
pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA;
else {
dev_notice(dev, "invalid bus-width, default to 1-bit mode\n");
pdata->mmc_bus_width = 0;
}
pdata->vreg_data = devm_kzalloc(dev, sizeof(struct
sdhci_msm_slot_reg_data),
msm_host->vreg_data = devm_kzalloc(dev, sizeof(struct
sdhci_msm_vreg_data),
GFP_KERNEL);
if (!pdata->vreg_data) {
if (!msm_host->vreg_data) {
dev_err(dev, "failed to allocate memory for vreg data\n");
goto out;
}
if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data,
if (sdhci_msm_dt_parse_vreg_info(dev, &msm_host->vreg_data->vdd_data,
"vdd")) {
dev_err(dev, "failed parsing vdd data\n");
goto out;
}
if (sdhci_msm_dt_parse_vreg_info(dev,
&pdata->vreg_data->vdd_io_data,
&msm_host->vreg_data->vdd_io_data,
"vdd-io")) {
dev_err(dev, "failed parsing vdd-io data\n");
goto out;
}
len = of_property_count_strings(np, "qcom,bus-speed-mode");
for (i = 0; i < len; i++) {
const char *name = NULL;
of_property_read_string_index(np,
"qcom,bus-speed-mode", i, &name);
if (!name)
continue;
if (!strcmp(name, "HS400_1p8v"))
pdata->caps2 |= MMC_CAP2_HS400_1_8V;
else if (!strcmp(name, "HS400_1p2v"))
pdata->caps2 |= MMC_CAP2_HS400_1_2V;
else if (!strcmp(name, "HS200_1p8v"))
pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
else if (!strcmp(name, "HS200_1p2v"))
pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
else if (!strcmp(name, "DDR_1p8v"))
pdata->caps |= MMC_CAP_1_8V_DDR
| MMC_CAP_UHS_DDR50;
else if (!strcmp(name, "DDR_1p2v"))
pdata->caps |= MMC_CAP_1_2V_DDR
| MMC_CAP_UHS_DDR50;
}
if (of_get_property(np, "qcom,nonremovable", NULL))
pdata->nonremovable = true;
if (of_get_property(np, "qcom,nonhotplug", NULL))
pdata->nonhotplug = true;
pdata->largeaddressbus =
of_property_read_bool(np, "qcom,large-address-bus");
if (of_get_property(np, "qcom,core_3_0v_support", NULL))
msm_host->core_3_0v_support = true;
@ -1668,9 +1601,9 @@ struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev,
if (sdhci_msm_dt_parse_hsr_info(dev, msm_host))
goto out;
return pdata;
return false;
out:
return NULL;
return true;
}
static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
@ -1960,14 +1893,14 @@ out:
return ret;
}
static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata,
static int sdhci_msm_setup_vreg(struct sdhci_msm_host *msm_host,
bool enable, bool is_init)
{
int ret = 0, i;
struct sdhci_msm_slot_reg_data *curr_slot;
struct sdhci_msm_vreg_data *curr_slot;
struct sdhci_msm_reg_data *vreg_table[2];
curr_slot = pdata->vreg_data;
curr_slot = msm_host->vreg_data;
if (!curr_slot) {
pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n",
__func__);
@ -1993,14 +1926,14 @@ out:
/* This init function should be called only once for each SDHC slot */
static int sdhci_msm_vreg_init(struct device *dev,
struct sdhci_msm_pltfm_data *pdata,
struct sdhci_msm_host *msm_host,
bool is_init)
{
int ret = 0;
struct sdhci_msm_slot_reg_data *curr_slot;
struct sdhci_msm_vreg_data *curr_slot;
struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg;
curr_slot = pdata->vreg_data;
curr_slot = msm_host->vreg_data;
if (!curr_slot)
goto out;
@ -2029,7 +1962,7 @@ out:
return ret;
}
static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata,
static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_host *msm_host,
enum vdd_io_level level,
unsigned int voltage_level)
{
@ -2037,10 +1970,10 @@ static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata,
int set_level;
struct sdhci_msm_reg_data *vdd_io_reg;
if (!pdata->vreg_data)
if (!msm_host->vreg_data)
return ret;
vdd_io_reg = pdata->vreg_data->vdd_io_data;
vdd_io_reg = msm_host->vreg_data->vdd_io_data;
if (vdd_io_reg && vdd_io_reg->is_enabled) {
switch (level) {
case VDD_IO_LOW:
@ -2114,9 +2047,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
}
/* Handle BUS ON/OFF*/
if (irq_status & CORE_PWRCTL_BUS_ON) {
ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false);
ret = sdhci_msm_setup_vreg(msm_host, true, false);
if (!ret)
ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata,
ret = sdhci_msm_set_vdd_io_vol(msm_host,
VDD_IO_HIGH, 0);
if (ret)
irq_ack |= CORE_PWRCTL_BUS_FAIL;
@ -2128,10 +2061,10 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
}
if (irq_status & CORE_PWRCTL_BUS_OFF) {
if (msm_host->pltfm_init_done)
ret = sdhci_msm_setup_vreg(msm_host->pdata,
ret = sdhci_msm_setup_vreg(msm_host,
false, false);
if (!ret)
ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata,
ret = sdhci_msm_set_vdd_io_vol(msm_host,
VDD_IO_LOW, 0);
if (ret)
irq_ack |= CORE_PWRCTL_BUS_FAIL;
@ -2144,7 +2077,7 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
/* Handle IO LOW/HIGH */
if (irq_status & CORE_PWRCTL_IO_LOW) {
/* Switch voltage Low */
ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0);
ret = sdhci_msm_set_vdd_io_vol(msm_host, VDD_IO_LOW, 0);
if (ret)
irq_ack |= CORE_PWRCTL_IO_FAIL;
else
@ -2154,7 +2087,7 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
}
if (irq_status & CORE_PWRCTL_IO_HIGH) {
/* Switch voltage High */
ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0);
ret = sdhci_msm_set_vdd_io_vol(msm_host, VDD_IO_HIGH, 0);
if (ret)
irq_ack |= CORE_PWRCTL_IO_FAIL;
else
@ -3095,26 +3028,6 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
/*
* Starting with SDCC 5 controller (core major version = 1)
* controller won't advertise 3.0v, 1.8v and 8-bit features
* except for some targets.
*/
if (major >= 1 && minor != 0x11 && minor != 0x12) {
struct sdhci_msm_reg_data *vdd_io_reg;
/*
* Enable 1.8V support capability on controllers that
* support dual voltage
*/
vdd_io_reg = msm_host->pdata->vreg_data->vdd_io_data;
if (vdd_io_reg && (vdd_io_reg->high_vol_level > 2700000))
caps |= CORE_3_0V_SUPPORT;
if (vdd_io_reg && (vdd_io_reg->low_vol_level < 1950000))
caps |= CORE_1_8V_SUPPORT;
if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA)
caps |= CORE_8_BIT_SUPPORT;
}
/*
* SDCC 5 controller with major version 1, minor version 0x34 and later
* with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
@ -3134,15 +3047,9 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
msm_offset->core_vendor_spec_capabilities0);
}
/*
* Mask 64-bit support for controller with 32-bit address bus so that
* smaller descriptor size will be used and improve memory consumption.
*/
if (!msm_host->pdata->largeaddressbus)
caps &= ~CORE_SYS_BUS_SUPPORT_64_BIT;
writel_relaxed(caps, host->ioaddr +
msm_offset->core_vendor_spec_capabilities0);
/* keep track of the value in SDHCI_CAPABILITIES */
msm_host->caps_0 = caps;
@ -3207,8 +3114,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
msm_host->pdata = sdhci_msm_populate_pdata(dev, msm_host);
if (!msm_host->pdata) {
ret = sdhci_msm_populate_pdata(dev, msm_host);
if (ret) {
dev_err(&pdev->dev, "DT parsing error\n");
goto pltfm_free;
}
@ -3287,7 +3194,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
sdhci_msm_bus_voting(host, true);
/* Setup regulators */
ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true);
ret = sdhci_msm_vreg_init(&pdev->dev, msm_host, true);
if (ret) {
dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret);
goto bus_unregister;
@ -3429,7 +3336,7 @@ pm_runtime_disable:
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
vreg_deinit:
sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false);
sdhci_msm_vreg_init(&pdev->dev, msm_host, false);
bus_unregister:
if (!msm_host->skip_bus_bw_voting) {
sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
@ -3456,7 +3363,7 @@ static int sdhci_msm_remove(struct platform_device *pdev)
sdhci_remove_host(host, dead);
sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false);
sdhci_msm_vreg_init(&pdev->dev, msm_host, false);
pm_runtime_get_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);