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drivers: clk: zynqmp: Allow zero divisor value

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Zero divider is valid and default for some of ZynqMP
clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
for the clock is set.

Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
This commit is contained in:
Rajan Vaja 2019-03-04 15:27:46 -08:00 • committed by Stephen Boyd
commit 60d74e011c
1 changed files with 7 additions and 0 deletions
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7
drivers/clk/zynqmp/divider.c
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@ -76,6 +76,13 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
else
value = div >> 16;
if (!value) {
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
clk_name);
return parent_rate;
}
return DIV_ROUND_UP_ULL(parent_rate, value);
}