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pci-v4.11-changes
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYrvYlAAoJEFmIoMA60/r8FuQQAMDpia3kacyCAJpa+zjmyMNF 1slytaoIvP37dFq9XF1em031lwGNr5sahZ7nP1EKgALz4odZUzait7BUABcfviIn Uesz2E1s/miMo4/0X1j9DqY9xV649DmmSIgk1yn3kvCkH/+Ix27dexu47auGzPEb H/sEfd1RZidjZ5EWaG0ww5FrHcuge+JHtcH6vFQtWsTOspcx++IhaVIGjC0JCpqK DnlQKilsJ38KUkvuDcxWjtFKxAc8De9jvCR4kX96OvbHahfAWwBO4AtUv7U3JpJN 2nyQk+I5kRagbfBucaXZISUtWM7h4peLiL+TGkvKg8eOVlOCedjYlrZW4SWkbAN+ 0qwcHRQ8lwhNmgp3VYq7pmnugIvW4P2Fh3uqaplCAIwlpODxWPDQP7HLM2kyzmvq gPGi0R4Yo2PdIXqfbilrzbFVeyqkIFECr287a6+5PekC0DxsqZvOG0uA1mWKLIaH pRQMT0FO2SCCSOpcxRExeIj+XxhXlDVOrIBP6eMiFXAMgzUAyU8fLSZVMtXAvsTS 02hVDOc/Fq2jKlCSoJRIiRp5aj1QDFS/DjBhOnW7pXuvUTCrfYBXY5NCdT9UV3Q7 W6qHWkizRmRDGxUzqSODRt5aU7VOKbWvZnp10eJyKt5s2Iawe6We5V1NX+u18UIS Scc1nbuPTL6u1n8PsaBG =4Owc -----END PGP SIGNATURE----- Merge tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add ASPM L1 substate support - enable PCIe Extended Tags when supported - configure PCIe MPS settings on iProc, Versatile, X-Gene, and Xilinx - increase VPD access timeout - add ACS quirks for Intel Union Point, Qualcomm QDF2400 and QDF2432 - use new pci_irq_alloc_vectors() in more drivers - fix MSI affinity memory leak - remove unused MSI interfaces and update documentation - remove unused AER .link_reset() callback - avoid pci_lock / p->pi_lock deadlock seen with perf - serialize sysfs enable/disable num_vfs operations - move DesignWare IP from drivers/pci/host/ to drivers/pci/dwc/ and refactor so we can support both hosts and endpoints - add DT ECAM-like support for HiSilicon Hip06/Hip07 controllers - add Rockchip system power management support - add Thunder-X cn81xx and cn83xx support - add Exynos 5440 PCIe PHY support * tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (93 commits) PCI: dwc: Remove dependency of designware on CONFIG_PCI PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host PCI: dwc: Split pcie-designware.c into host and core files PCI: dwc: designware: Fix style errors in pcie-designware.c PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() PCI: dwc: all: Split struct pcie_port into host-only and core structures PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() PCI: dwc: all: Rename cfg_read/cfg_write to read/write PCI: dwc: all: Use platform_set_drvdata() to save private data PCI: dwc: designware: Move register defines to designware header file PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code PCI: dra7xx: Group PHY API invocations PCI: dra7xx: Enable MSI and legacy interrupts simultaneously PCI: dra7xx: Add support to force RC to work in GEN1 mode PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional() PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory PCI: exynos: Support the PHY generic framework Documentation: binding: Modify the exynos5440 PCIe binding phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Documentation: samsung-phy: Add exynos-pcie-phy binding ...
This commit is contained in:
Linus Torvalds
commit
60e8d3e116
74 changed files with 3355 additions and 2265 deletions
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@ -42,3 +42,40 @@ Hip05 Example (note that Hip06 is the same except compatible):
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0x0 0 0 4 &mbigen_pcie 4 13>;
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status = "ok";
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};
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HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
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The properties and their meanings are identical to those described in
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host-generic-pci.txt except as listed below.
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Properties of the host controller node that differ from
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host-generic-pci.txt:
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- compatible : Must be "hisilicon,pcie-almost-ecam"
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- reg : Two entries: First the ECAM configuration space for any
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other bus underneath the root bus. Second, the base
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and size of the HiSilicon host bridge registers include
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the RC's own config space.
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Example:
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pcie0: pcie@a0090000 {
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compatible = "hisilicon,pcie-almost-ecam";
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reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */
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<0 0xa0090000 0 0x10000>; /* host bridge registers */
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bus-range = <0 31>;
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msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
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msi-map-mask = <0xffff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
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0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
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0x0 0 0 2 &mbigen_pcie0 650 4
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0x0 0 0 3 &mbigen_pcie0 650 4
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0x0 0 0 4 &mbigen_pcie0 650 4>;
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status = "ok";
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};
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@ -78,7 +78,8 @@ and the following optional properties:
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multiple lanes. If this property is not found, we assume that the
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value is 0.
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- reset-gpios: optional gpio to PERST#
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- reset-delay-us: delay in us to wait after reset de-assertion
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- reset-delay-us: delay in us to wait after reset de-assertion, if not
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specified will default to 100ms, as required by the PCIe specification.
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Example:
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@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
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"renesas,pcie-r8a7791" for the R8A7791 SoC;
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"renesas,pcie-r8a7793" for the R8A7793 SoC;
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"renesas,pcie-r8a7795" for the R8A7795 SoC;
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"renesas,pcie-r8a7796" for the R8A7796 SoC;
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"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
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"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
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@ -43,6 +43,8 @@ Required properties:
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- interrupt-map-mask and interrupt-map: standard PCI properties
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Optional Property:
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- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
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using 24MHz OSC for RC's PHY.
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- ep-gpios: contain the entry for pre-reset gpio
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- num-lanes: number of lanes to use
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- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
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@ -7,8 +7,19 @@ Required properties:
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- compatible: "samsung,exynos5440-pcie"
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- reg: base addresses and lengths of the pcie controller,
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the phy controller, additional register for the phy controller.
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(Registers for the phy controller are DEPRECATED.
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Use the PHY framework.)
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- reg-names : First name should be set to "elbi".
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And use the "config" instead of getting the confgiruation address space
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from "ranges".
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NOTE: When use the "config" property, reg-names must be set.
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- interrupts: A list of interrupt outputs for level interrupt,
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pulse interrupt, special interrupt.
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- phys: From PHY binding. Phandle for the Generic PHY.
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Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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Other common properties refer to
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Documentation/devicetree/binding/pci/designware-pcie.txt
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Example:
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@ -54,6 +65,24 @@ SoC specific DT Entry:
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num-lanes = <4>;
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};
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With using PHY framework:
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pcie_phy0: pcie-phy@270000 {
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...
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reg = <0x270000 0x1000>, <0x271000 0x40>;
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reg-names = "phy", "block";
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...
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};
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pcie@290000 {
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...
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reg = <0x290000 0x1000>, <0x40000000 0x1000>;
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reg-names = "elbi", "config";
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phys = <&pcie_phy0>;
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ranges = <0x81000000 0 0 0x60001000 0 0x00010000
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
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...
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};
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Board specific DT Entry:
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pcie@290000 {
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@ -191,3 +191,20 @@ Example:
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usbdrdphy0 = &usb3_phy0;
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usbdrdphy1 = &usb3_phy1;
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};
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Samsung Exynos SoC series PCIe PHY controller
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--------------------------------------------------
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Required properties:
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- compatible : Should be set to "samsung,exynos5440-pcie-phy"
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- #phy-cells : Must be zero
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- reg : a register used by phy driver.
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- First is for phy register, second is for block register.
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- reg-names : Must be set to "phy" and "block".
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Example:
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pcie_phy0: pcie-phy@270000 {
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#phy-cells = <0>;
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compatible = "samsung,exynos5440-pcie-phy";
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reg = <0x270000 0x1000>, <0x271000 0x40>;
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reg-names = "phy", "block";
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};
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