A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-13 08:07:32 -04:00
Code Issues Projects Releases Packages Wiki Activity

ARM: dts: msm: add aggre_noc_pcie_*_axi_clk for PCIe on lahaina

Browse source 
Add aggre_noc_pcie_0_axi_clk and aggre_noc_pcie_1_axi_clk for
the corresponding PCIe devicetree node on lahaina.

Change-Id: Ic5940f38b83b54aeb77d310b144a75e15c72b74f
This commit is contained in:
Tony Truong 2020-01-29 21:25:15 -08:00 • committed by Gerrit - the friendly Code Review server
commit 60f5940600
1 changed files with 14 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

20
qcom/lahaina-pcie.dtsi
View file

@ -68,15 +68,20 @@
<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&clock_gcc GCC_PCIE0_PHY_RCHNG_CLK>,
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk";
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk",
"pcie_aggre_noc_1_axi_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>;
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>;
resets = <&clock_gcc GCC_PCIE_0_BCR>,
<&clock_gcc GCC_PCIE_0_PHY_BCR>;
@ -215,15 +220,18 @@
<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&clock_gcc GCC_PCIE1_PHY_RCHNG_CLK>,
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk";
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_1_axi_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>;
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>;
resets = <&clock_gcc GCC_PCIE_1_BCR>,
<&clock_gcc GCC_PCIE_1_PHY_BCR>;