diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 97bc621e80e4..339b6c9b59f5 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -92,6 +92,12 @@ SoCs: - HOLI compatible = "qcom,holi" +- MONACO + compatible = "qcom,monaco" + +- SDXNIGHTJAR + compatible = "qcom,sdxnightjar" + Generic board variants: - CDP device: @@ -251,3 +257,7 @@ compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" compatible = "qcom,scuba-idp" +compatible = "qcom,monaco-rumi" +compatible = "qcom,sdxnightjar-mtp" +compatible = "qcom,sdxnightjar-cdp" +compatible = "qcom,sdxnightjar-qrd" diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index aaa29dc09a63..b9e3105751a5 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -7,6 +7,11 @@ Required properties : "qcom,lahaina-camcc" "qcom,lahaina-camcc-v2" "qcom,shima-camcc" + "qcom,sm8150-camcc" + "qcom,sm8150-camcc-v2" + "qcom,sa8155-camcc" + "qcom,sa8155-camcc-v2" + - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 962376860141..c7d82f90a3c8 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -8,6 +8,7 @@ Required properties : "qcom,shima-debugcc" "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" + "qcom,sm8150-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index feaccf643a45..80bbef3710ec 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -9,6 +9,8 @@ Required properties : "qcom,lahaina-dispcc" "qcom,shima-dispcc" "qcom,holi-dispcc" + "qcom,sm8150-dispcc" + "qcom,sm8150-dispcc-v2" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 617a1a5125dc..f72a8ff537e6 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -24,10 +24,10 @@ Required properties : "qcom,gcc-sdm660" "qcom,gcc-sdm845" "qcom,lahaina-gcc" - "qcom,gcc-sm8150" - "qcom,gcc-sm8150-v2" - "qcom,gcc-sa8155" - "qcom,gcc-sa8155-v2" + "qcom,sm8150-gcc" + "qcom,sm8150-gcc-v2" + "qcom,sa8155-gcc" + "qcom,sa8155-gcc-v2" "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 4b987a3312c1..726c24257d24 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -5,7 +5,10 @@ Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", "qcom,lahaina-gpucc", "qcom,shima-gpucc", - "qcom,holi-gpucc". + "qcom,holi-gpucc", + "qcom,sm8150-gpucc", + "qcom,sa8155-gpucc". + - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Must contain "cc_base". diff --git a/bindings/clock/qcom,npucc.txt b/bindings/clock/qcom,npucc.txt new file mode 100644 index 000000000000..b05c0012dae5 --- /dev/null +++ b/bindings/clock/qcom,npucc.txt @@ -0,0 +1,33 @@ +Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding +---------------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sm8150-npucc" + "qcom,sm8150-npucc-v2" + "qcom,sa8155-npucc" + "qcom,sa8155-npucc-v2" + +- reg : shall contain base register location and length. +- reg-names: names of registers listed in the same order as in + the reg property. +- vdd_cx-supply: phandle to the CX rail that needs to be voted + on behalf of the NPU CC clocks. +- vdd_gdsc-supply: phandle to the NPU core GDSC that needs to be + toggled as part of the CRC sequence. +- #clock-cells : shall contain 1. +- #reset-cells : shall contain 1. + +Optional properties : +- #power-domain-cells : from generic power domain binding, shall contain 1 + +Example: + npucc: qcom,npucc { + compatible = "qcom,npucc-sm8150"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&pm8150l_s6_level>; + vdd_gdsc-supply = <&npu_core_gdsc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/bindings/clock/qcom,scc.txt b/bindings/clock/qcom,scc.txt new file mode 100644 index 000000000000..fce28e82ddb9 --- /dev/null +++ b/bindings/clock/qcom,scc.txt @@ -0,0 +1,23 @@ +Qualcomm Technologies, Inc. Sensor Clock Controller Bindings + +Required properties: +- compatible : shall contain only one of the following: + "qcom,sm8150-scc" + "qcom,sm8150-scc-v2" + "qcom,sa8155-scc" + "qcom,sa8155-scc-v2" + +- reg: shall contain base register location and length. +- vdd_scc_cx-supply: the logic rail supply. +- #clock-cells: shall contain 1. + +Optional properties : +- #power-domain-cells : from generic power domain binding, shall contain 1 + +Example: + qcom,scc@2b10000 { + compatible = "qcom,scc-sm8150"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + }; diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index 9dd9a36d2743..e46fa2db829b 100644 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -7,6 +7,10 @@ Required properties : "qcom,sdm845-videocc" "qcom,lahaina-videocc" "qcom,shima-videocc" + "qcom,sm8150-videocc" + "qcom,sm8150-videocc-v2" + "qcom,sa8155-videocc" + "qcom,sa8155-videocc-v2" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/input/qcom-hv-haptics.txt b/bindings/input/qcom-hv-haptics.txt index 128e9266baac..805b3baedf70 100644 --- a/bindings/input/qcom-hv-haptics.txt +++ b/bindings/input/qcom-hv-haptics.txt @@ -119,6 +119,20 @@ Properties: haptics ISC (short circuit current) config during LRA impedance detection. +- qcom,hpwr-supply: + Usage: optional + Value type: + Definition: Phandle of the regulator device that supplies power for haptics + module. This is needed when haptics module is supplied by + non-HBoost regulator. + +- qcom,hpwr-voltage-mv: + Usage: optional + Value type: + Definition: Specify the voltage level in mv unit requested from the + non-HBoost regulator. When BoB regulator is used, the + requested voltage shouldn't be higher than 4000 mV. + The following properties are only required when LRA actuator is used: - qcom,lra-period-us: diff --git a/bindings/interconnect/qcom,osm-l3.txt b/bindings/interconnect/qcom,osm-l3.txt new file mode 100644 index 000000000000..4d323fd7750b --- /dev/null +++ b/bindings/interconnect/qcom,osm-l3.txt @@ -0,0 +1,25 @@ +Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding +----------------------------------------------------------- + +The EPSS L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdm845-osm-l3", + "qcom,sm8150-osm-l3"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +osm_l3: interconnect@0x18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm8150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; +}; diff --git a/bindings/interconnect/qcom,sm8150.txt b/bindings/interconnect/qcom,sm8150.txt index 247fc9655b8f..a0b636af3c11 100644 --- a/bindings/interconnect/qcom,sm8150.txt +++ b/bindings/interconnect/qcom,sm8150.txt @@ -21,9 +21,6 @@ Required properties : "qcom,sm8150-mc_virt"; "qcom,sm8150-mmss_noc"; "qcom,sm8150-system_noc"; - "qcom,sm8150-gem_noc_display"; - "qcom,sm8150-mc_virt_display"; - "qcom,sm8150-mmss_noc_display"; - #interconnect-cells : should contain 1 Examples: diff --git a/bindings/interrupt-controller/arm,gic.txt b/bindings/interrupt-controller/arm,gic.txt new file mode 100644 index 000000000000..7ac781f6efe9 --- /dev/null +++ b/bindings/interrupt-controller/arm,gic.txt @@ -0,0 +1,171 @@ +* ARM Generic Interrupt Controller + +ARM SMP cores are often associated with a GIC, providing per processor +interrupts (PPI), shared processor interrupts (SPI) and software +generated interrupts (SGI). + +Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. +Secondary GICs are cascaded into the upward interrupt controller and do not +have PPIs or SGIs. + +Main node required properties: + +- compatible : should be one of: + "arm,arm1176jzf-devchip-gic" + "arm,arm11mp-gic" + "arm,cortex-a15-gic" + "arm,cortex-a7-gic" + "arm,cortex-a9-gic" + "arm,eb11mp-gic" + "arm,gic-400" + "arm,pl390" + "arm,tc11mp-gic" + "brcm,brahma-b15-gic" + "nvidia,tegra210-agic" + "qcom,msm-8660-qgic" + "qcom,msm-qgic2" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 3. + + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI + interrupts. + + The 2nd cell contains the interrupt number for the interrupt type. + SPI interrupts are in the range [0-987]. PPI interrupts are in the + range [0-15]. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered (invalid for SPIs) + 4 = active high level-sensitive + 8 = active low level-sensitive (invalid for SPIs). + bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of + the 8 possible cpus attached to the GIC. A bit set to '1' indicated + the interrupt is wired to that CPU. Only valid for PPI interrupts. + Also note that the configurability of PPI interrupts is IMPLEMENTATION + DEFINED and as such not guaranteed to be present (most SoC available + in 2014 seem to ignore the setting of this flag and use the hardware + default value). + +- reg : Specifies base physical address(s) and size of the GIC registers. The + first region is the GIC distributor register base and size. The 2nd region is + the GIC cpu interface register base and size. + +Optional +- interrupts : Interrupt source of the parent interrupt controller on + secondary GICs, or VGIC maintenance interrupt on primary GIC (see + below). + +- cpu-offset : per-cpu offset within the distributor and cpu interface + regions, used when the GIC doesn't have banked registers. The offset is + cpu-offset * cpu-nr. + +- clocks : List of phandle and clock-specific pairs, one for each entry + in clock-names. +- clock-names : List of names for the GIC clock input(s). Valid clock names + depend on the GIC variant: + "ic_clk" (for "arm,arm11mp-gic") + "PERIPHCLKEN" (for "arm,cortex-a15-gic") + "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") + "clk" (for "arm,gic-400" and "nvidia,tegra210") + "gclk" (for "arm,pl390") + +- power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle, used when the GIC + is part of a Power or Clock Domain. + + +Example: + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + +* GIC virtualization extensions (VGIC) + +For ARM cores that support the virtualization extensions, additional +properties must be described (they only exist if the GIC is the +primary interrupt controller). + +Required properties: + +- reg : Additional regions specifying the base physical address and + size of the VGIC registers. The first additional region is the GIC + virtual interface control register base and size. The 2nd additional + region is the GIC virtual cpu interface register base and size. + +- interrupts : VGIC maintenance interrupt. + +Example: + + interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x1000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + +* GICv2m extension for MSI/MSI-x support (Optional) + +Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). +This is enabled by specifying v2m sub-node(s). + +Required properties: + +- compatible : The value here should contain "arm,gic-v2m-frame". + +- msi-controller : Identifies the node as an MSI controller. + +- reg : GICv2m MSI interface register base and size + +Optional properties: + +- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect + value, this property should contain the SPI base of + the MSI frame, overriding the HW value. + +- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect + value, this property should contain the number of + SPIs assigned to the frame, overriding the HW value. + +Example: + + interrupt-controller@e1101000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + interrupts = <1 8 0xf04>; + ranges = <0 0 0 0xe1100000 0 0x100000>; + reg = <0x0 0xe1110000 0 0x01000>, + <0x0 0xe112f000 0 0x02000>, + <0x0 0xe1140000 0 0x10000>, + <0x0 0xe1160000 0 0x10000>; + v2m0: v2m@0x8000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0 0x1000>; + }; + + .... + + v2mN: v2m@0x9000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0 0x1000>; + }; + }; diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 9e3e515e4e96..29e79cddee88 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -182,6 +182,13 @@ conditions. that interconnect votes will be maintained irrespective of the CPUSS' state (awake or asleep). +- qcom,power-always-on: + Boolean property which indicates that votes for power + resources (i.e. regulators, clocks, buses) should + always be maintained. This is required when the latency + for the SMMU's operation is greatly increased by adding and + removing votes for power resources. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : diff --git a/bindings/mailbox/qcom,apcs-kpss-global.txt b/bindings/mailbox/qcom,apcs-kpss-global.txt index 833c68a150c1..49702be69c3d 100644 --- a/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -19,6 +19,7 @@ platforms. "qcom,sdxlemur-apcs-gcc" "qcom,scuba-apcs-hmss-global" "qcom,monaco-apcs-hmss-global" + "qcom,sm8150-spcs-global" - reg: Usage: required diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 8a9fa1e1c6fe..6c6285f4e714 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -346,6 +346,12 @@ interconnects: Definition: The latency(ms) between when PCIe link is up and before any device over the switch is accessed +- qcom,eq-pset-req-vec: + Usage: optional + Definition: EQ preset request vector. Determines which preset is + requested and evauluated during initial part of the EQ master + phase. Default will be 0 if entry is not present. + - qcom,core-preset: Usage: optional Definition: Determines how aggressive the PCIe PHY equalization is for @@ -522,6 +528,7 @@ Example qcom,ep-latency = <20>; qcom,switch-latency = <25>; + qcom,eq-pset-req-vec = <0>; qcom,core-preset = <0x55555555> /* short channel */ qcom,pcie-phy-ver = <0x2101>; /* v2 version 1.01 */ qcom,phy-status-offset = <0x814>; diff --git a/bindings/pinctrl/qcom,monaco-pinctrl.yaml b/bindings/pinctrl/qcom,monaco-pinctrl.yaml new file mode 100644 index 000000000000..861e0e955568 --- /dev/null +++ b/bindings/pinctrl/qcom,monaco-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,monaco-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MONACO TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + MONACO platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,monaco-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@500000 { + compatible = "qcom,monaco-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index d506c20b8a13..84611b5347f5 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -33,6 +33,7 @@ PMIC's from Qualcomm. "qcom,pm6350-gpio" "qcom,pm6150l-gpio" "qcom,pmx65-gpio" + "qcom,pmd9650-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -120,6 +121,7 @@ to specify in a pin configuration subnode: gpio1-gpio9 for pm6350 gpio1-gpio12 for pm6150l gpio1-gpio16 for pmx65 + gpio1-gpio12 for pmd9650 - function: Usage: required diff --git a/bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt b/bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt new file mode 100644 index 000000000000..73b73620978a --- /dev/null +++ b/bindings/pinctrl/qcom,sdxnightjar-pinctrl.txt @@ -0,0 +1,139 @@ +QTI SDXNIGHTJAR TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SDXNIGHTJAR platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdxnightjar-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + +Example: + + tlmm_pinmux: pinctrl@1000000 { + compatible = "qcom,mdm9650-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_console_active: uart1_console_active { + mux { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/bindings/thermal/qti-ddr-cdev.txt b/bindings/thermal/qti-ddr-cdev.txt new file mode 100644 index 000000000000..c081531b11d5 --- /dev/null +++ b/bindings/thermal/qti-ddr-cdev.txt @@ -0,0 +1,42 @@ +QTI DDR cooling device. + +The DDR cooling device will be used to place a DDR frequency vote. This +cooling device will be used in those cases where all the subsystem's are +thermally throttled and DDR has to be operated with a minimum performance +level. This cooling device vote can ensure the same. + +Properties: +- compatible: + Usage: required + Value type: + Definition: should be "qcom,ddr-cooling-device" + +Cooling device node: +- qcom,ddr-freq: + Usage: required + Value type: + Definition: List of available DDR frequencies. + +-#cooling-cells: + Usage: required + Value type: + Definition: Must be 2. Needed for of_thermal as cooling device + identifier. Please refer to + for more + details. +Example: + qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + qcom,ddr-freq = <200000>, + <451000>, + <547000>, + <681000>, + <768000>, + <1017000>, + <1555000>, + <1708000>, + <2092000>, + <2736000>, + <3196000>; + #cooling-cells = <2>; + }; diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index c3db1a85b6e9..c4e221a8c05e 100644 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -16,6 +16,8 @@ Required properties: for sdm845 emulation, "qcom,ufs-phy-qmp-v4-lahaina" for V4 ufs phy present on Lahaina chipset. + "qcom,ufs-phy-qmp-v4" for V4 ufs phy present + on SM8150 chipset. "qcom,ufs-phy-qmp-v3" for V3 ufs phy present on holi chipset. - reg : should contain PHY register address space (mandatory), diff --git a/qcom/Makefile b/qcom/Makefile index 8ddaae69c558..ab69f402e2f2 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -143,6 +143,15 @@ else dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_MONACO) += \ + monaco-rumi-overlay.dtbo + +monaco-rumi-overlay.dtbo-base := monaco.dtb +else +dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SA8155) += \ sa8155-adp-star-overlay.dtbo \ @@ -181,6 +190,7 @@ ifeq ($(CONFIG_ARCH_QTI_VM), y) dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \ lahaina-vm-cdp.dtb \ lahaina-vm-qrd.dtb \ + lahaina-vm-mtp-v2.dtb \ lahaina-vm-mtp-v2.1.dtb endif endif @@ -207,6 +217,10 @@ dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \ endif endif +dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \ + sdxnightjar-cdp.dtb \ + sdxnightjar-qrd.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index 974b08da18ae..92cb1097aa6a 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -295,7 +295,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 238ccb951cd9..d652452eb715 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -11,8 +11,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x0A5640D8>; qcom,va_mclk_mode_muxsel = <0x0A7A0000>; clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 7cbc0ae32d3c..413aed3a2660 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -306,7 +306,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index 4793aaa24948..7c454128af97 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -394,7 +394,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 77dcb6330af0..74fd9e74591b 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -375,7 +375,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 5811c29a8d04..776be0b0286c 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -465,7 +465,7 @@ }; &usb0 { - extcon = <&pm7250b_pdphy>, <&eud>; + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 9b119fb91ea6..6204365a330b 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -448,7 +448,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1 kpti=off"; + bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; }; }; @@ -1499,6 +1499,7 @@ reg = <0x80>; #clock-cells = <1>; }; + scmi_perf_lock: protocol@81 { reg = <0x81>; #clock-cells = <1>; @@ -2481,6 +2482,7 @@ iommus = <&apps_smmu 0x1009 0x0000>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ }; qcom,msm_fastrpc_compute_cb10 { @@ -2527,8 +2529,9 @@ ufshc_mem: ufshc@4804000 { compatible = "qcom,ufshc"; reg = <0x4804000 0x3000>, - <0x4808000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + <0x4808000 0x8000>, + <0x4810000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -2628,8 +2631,10 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; - reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, + <0x04748000 0x8000>, <0x04750000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; @@ -3006,8 +3011,8 @@ qcom_hwkm: hwkm@4440000 { compatible = "qcom,hwkm"; - reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>; - reg-names = "km_master", "ice_slave", "sdcc_ice_slave"; + reg = <0x4440000 0x9000>, <0x04810000 0x9000>; + reg-names = "km_master", "ice_slave"; qcom,enable-hwkm-clk; clock-names = "km_clk_src"; clocks = <&rpmcc RPM_SMD_HWKM_CLK>; diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index 4908e26696d8..1b50e92a9651 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -11,8 +11,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x033240D8>; qcom,wsa_mclk_mode_muxsel = <0x033220D8>; qcom,va_mclk_mode_muxsel = <0x033A0000>; diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 4989e97dd77e..3ef0db6a20c7 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -101,7 +101,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 305d9f3b348f..69b7ad4292ea 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -14,9 +14,10 @@ status = "ok"; reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, <0x3de0000 0x10000>, <0x3d8b000 0x2000>, - <0x06900000 0x80000>; + <0x06900000 0x80000>, <0x0634000 0x1000>, + <0x0636000 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", - "isense_cntl", "qdss_gfx"; + "isense_cntl", "qdss_gfx", "rdpm_cx", "rdpm_mx"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 005e4ff816c5..6af3c39a4c7a 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -184,3 +184,9 @@ }; }; }; + +&pcie1 { + qcom,link-check-max-count = <50>; + qcom,ep-gpio = <&tlmm 6 0>; + qcom,boot-option = <0x0>; +}; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 39f56296aed0..9efb33e86994 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -103,7 +103,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 935146de871d..c5a0bb9fc7ab 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -204,7 +204,7 @@ pinctrl-2 = <&ts_release>; panel = <&dsi_r66451_amoled_cmd - &dsi_r66451_amoled_video>; + &dsi_r66451_amoled_video &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; @@ -347,3 +347,28 @@ &pm8350c_flash { status = "ok"; }; + +&thermal_zones { + gpu-skin-avg-step { + polling-delay-passive = <5000>; + polling-delay = <1000>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 1>, <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + sensor-aggregation = ; + coefficients = <3 7 0>; + trips { + gpuss_skin_config: active-config0 { + temperature = <570000>; + hysteresis = <20000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss_skin_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT 5>; + }; + }; + }; +}; diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 27210b21b047..fb753c87f2dd 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -53,6 +53,25 @@ reg = <0x00635000 0x1000>; interrupts = ; }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,ddr-freq = <762000>, + <1720000>, + <2086000>, + <2597000>, + <2929000>, + <3879000>, + <5161000>, + <5931000>, + <6515000>, + <7980000>, + <8136000>, + <10437000>, + <12191000>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; }; &cpufreq_hw { @@ -751,7 +770,7 @@ thermal-governor = "step_wise"; trips { pop_trip: pop-trip { - temperature = <95000>; + temperature = <90000>; hysteresis = <0>; type = "passive"; }; @@ -764,6 +783,11 @@ <&apc1_cluster THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; + + pop_cdev1 { + trip = <&pop_trip>; + cooling-device = <&ddr_cdev 5 5>; + }; }; }; diff --git a/qcom/lahaina-vm-mtp-v2.dts b/qcom/lahaina-vm-mtp-v2.dts new file mode 100644 index 000000000000..3fbafff1e13b --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm-v2.dtsi" +#include "lahaina-vm-mtp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM MTP v2"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x20008 0>; +}; diff --git a/qcom/lahaina-vm-mtp-v2.dtsi b/qcom/lahaina-vm-mtp-v2.dtsi new file mode 100644 index 000000000000..2a76b5241e44 --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.dtsi @@ -0,0 +1 @@ +#include "lahaina-vm-mtp.dtsi" diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 46d744d95235..f7b2d6708460 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -296,6 +296,7 @@ qcom,gpii-mask = <0x80>; qcom,ev-factor = <2>; qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; status = "ok"; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 504381c5d367..53e480f7cdcd 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -565,6 +565,37 @@ method = "smc"; }; + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + system_pm { + compatible = "qcom,system-pm"; + }; + + clock_rpmh: qcom,rpmhclk { + compatible = "qcom,lahaina-rpmh-clk"; + #clock-cells = <1>; + }; + }; + slim_aud: slim@3ac0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; @@ -2771,37 +2802,6 @@ 0x18040060 0x18050060 0x18060060 0x18070060>; }; - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x18200000 0x10000>, - <0x18210000 0x10000>, - <0x18220000 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - - system_pm { - compatible = "qcom,system-pm"; - }; - - clock_rpmh: qcom,rpmhclk { - compatible = "qcom,lahaina-rpmh-clk"; - #clock-cells = <1>; - }; - }; - aggre1_noc: interconnect@16e0000 { compatible = "qcom,lahaina-aggre1_noc"; reg = <0x016E0000 0x1f180>; @@ -3045,8 +3045,9 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi new file mode 100644 index 000000000000..0008896c79a9 --- /dev/null +++ b/qcom/monaco-pinctrl.dtsi @@ -0,0 +1,11 @@ +&soc { + tlmm: pinctrl@500000 { + compatible = "qcom,monaco-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/qcom/monaco-rumi-overlay.dts b/qcom/monaco-rumi-overlay.dts new file mode 100644 index 000000000000..4f3bb6574696 --- /dev/null +++ b/qcom/monaco-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "monaco-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco RUMI"; + compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi"; + qcom,msm-id = <459 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/monaco-rumi.dts b/qcom/monaco-rumi.dts new file mode 100644 index 000000000000..cb90f9641935 --- /dev/null +++ b/qcom/monaco-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "monaco.dtsi" +#include "monaco-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco RUMI"; + compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi new file mode 100644 index 000000000000..58b95639be9e --- /dev/null +++ b/qcom/monaco-rumi.dtsi @@ -0,0 +1,14 @@ +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@f120000 { + clock-frequency = <500000>; + }; + + wdog: qcom,wdt@f017000 { + status = "disabled"; + }; + +}; diff --git a/qcom/monaco-stub-regulator.dtsi b/qcom/monaco-stub-regulator.dtsi new file mode 100644 index 000000000000..b0eb6737362b --- /dev/null +++ b/qcom/monaco-stub-regulator.dtsi @@ -0,0 +1,336 @@ +#include + +/ { + VDD_CX_LEVEL: + S1A_LEVEL: + pm5100_s1_level: regulator-pm5100-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S1A_LEVEL_AO: + pm5100_s1_level_ao: regulator-pm5100-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s1_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S3A: + pm5100_s3: regulator-pm5100-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <790000>; + regulator-max-microvolt = <1374000>; + }; + + S4A: + pm5100_s4: regulator-pm5100-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + S5A: + pm5100_s5: regulator-pm5100-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_s5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2040000>; + }; + + L1A: + pm5100_l1: regulator-pm5100-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_EBI_LEVEL: + VDD_MXA_LEVEL: + L3A_LEVEL: + pm5100_l3_level: regulator-pm5100-l3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXA_LEVEL_AO: + L3A_LEVEL_AO: + pm5100_l3_level_ao: regulator-pm5100-l3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l3_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_LPI_CX_LEVEL: + L4A_LEVEL: + pm5100_l4_level: regulator-pm5100-l4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_LPI_MX_LEVEL: + L5A_LEVEL: + pm5100_l5_level: regulator-pm5100-l5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXC_LEVEL: + L6A_LEVEL: + pm5100_l6_level: regulator-pm5100-l6-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l6_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXC_LEVEL_AO: + L6A_LEVEL_AO: + pm5100_l6_level_ao: regulator-pm5100-l6-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l6_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L7A: + pm5100_l7: regulator-pm5100-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + L8A: + pm5100_l8: regulator-pm5100-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <968000>; + }; + + L9A: + pm5100_l9: regulator-pm5100-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + L10A: + pm5100_l10: regulator-pm5100-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + }; + + L11A: + pm5100_l11: regulator-pm5100-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + }; + + L12A: + pm5100_l12: regulator-pm5100-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + L13A: + pm5100_l13: regulator-pm5100-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + L14A: + pm5100_l14: regulator-pm5100-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1980000>; + }; + + L15A: + pm5100_l15: regulator-pm5100-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + L16A: + pm5100_l16: regulator-pm5100-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L17A: + pm5100_l17: regulator-pm5100-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1950000>; + }; + + L18A: + pm5100_l18: regulator-pm5100-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L19A: + pm5100_l19: regulator-pm5100-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + L20A: + pm5100_l20: regulator-pm5100-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L21A: + pm5100_l21: regulator-pm5100-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + }; + + L22A: + pm5100_l22: regulator-pm5100-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L23A: + pm5100_l23: regulator-pm5100-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + }; + + L24A: + pm5100_l24: regulator-pm5100-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l24"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <3544000>; + }; + + L25A: + pm5100_l25: regulator-pm5100-l25 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l25"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L26A: + pm5100_l26: regulator-pm5100-l26 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l26"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + L27A: + pm5100_l27: regulator-pm5100-l27 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l27"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + L28A: + pm5100_l28: regulator-pm5100-l28 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l28"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L29A: + pm5100_l29: regulator-pm5100-l29 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm5100_l29"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <3544000>; + }; +}; diff --git a/qcom/monaco.dts b/qcom/monaco.dts new file mode 100644 index 000000000000..c9446f70c99a --- /dev/null +++ b/qcom/monaco.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "monaco.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco SoC"; + compatible = "qcom,monaco"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi new file mode 100644 index 000000000000..f33ea540e53e --- /dev/null +++ b/qcom/monaco.dtsi @@ -0,0 +1,389 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Monaco"; + compatible = "qcom,monaco"; + qcom,msm-id = <459 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + soc: soc { }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + #gpio-cells = <2>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x80000>; /* GICR * 4 */ + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f121000 0x1000>, + <0x0f122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = ; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = ; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = ; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = ; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = ; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = ; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-slepp-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + }; +}; + +#include "monaco-pinctrl.dtsi" diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index 20343e67832b..0b7fb0427195 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -7,6 +7,7 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index de6054d5d612..f373834017d1 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cc_cx_gdsc>; diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index c9c71235d746..4867686e4486 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi index c7125e133d60..f9b8bb82e9a0 100644 --- a/qcom/pm2250.dtsi +++ b/qcom/pm2250.dtsi @@ -146,6 +146,13 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + die_temp_s3 { + reg = ; + label = "die_temp_s3"; + qcom,pre-scaling = <1 3>; + qcom,scale-fn-type = ; + }; }; diff --git a/qcom/pmd9650-rpm-regulator.dtsi b/qcom/pmd9650-rpm-regulator.dtsi new file mode 100644 index 000000000000..d89c52e2a1a8 --- /dev/null +++ b/qcom/pmd9650-rpm-regulator.dtsi @@ -0,0 +1,302 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { /* VDD_CX supply */ + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { /* VDD_MX supply */ + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "9650_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pmd9650.dtsi b/qcom/pmd9650.dtsi new file mode 100644 index 000000000000..83ea13885ee3 --- /dev/null +++ b/qcom/pmd9650.dtsi @@ -0,0 +1,101 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmd9650@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmd9650_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,pon-dbc-delay = <15625>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr"; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pmd9650_gpios: pinctrl@c000 { + compatible = "qcom,pmd9650-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmd9650_vadc: vadc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + ref_1p25 { + reg = ; + label = "ref_1p25"; + qcom,pre-scaling = <1 1>; + }; + }; + + qcom,pmd9650_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + qcom,pmd9650@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmd9650_pwm_1: pwm@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + + pmd9650_pwm_2: pwm@bd00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbd00>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + }; +}; diff --git a/qcom/qg-batterydata-alium-3600mah.dtsi b/qcom/qg-batterydata-alium-3600mah.dtsi index 051f64164fb2..4ade2fcaa7af 100644 --- a/qcom/qg-batterydata-alium-3600mah.dtsi +++ b/qcom/qg-batterydata-alium-3600mah.dtsi @@ -10,7 +10,7 @@ qcom,alium_860_89032_0000_3600mAh { qcom,qg-batt-profile-ver = <100>; qcom,jeita-fcc-ranges = <0 50 2500000 - 51 400 5400000 + 51 400 3600000 401 450 2500000>; qcom,jeita-fv-ranges = <0 50 4250000 51 400 4350000 diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 7ea545d63717..cd431074d371 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -421,6 +421,14 @@ status="disabled"; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + qfprom: qfprom@1b40000 { compatible = "qcom,qfprom"; reg = <0x1b40000 0x7000>; diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi index 997db6b37078..0a9b76bee5c0 100644 --- a/qcom/sdxlemur-blsp.dtsi +++ b/qcom/sdxlemur-blsp.dtsi @@ -294,7 +294,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x82f000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1a_hs>; @@ -330,7 +330,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x82f000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1b_hs>; @@ -366,7 +366,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x830000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2a_hs>; @@ -385,7 +385,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART2_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2a_tx_sleep>, <&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>; @@ -402,7 +402,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x830000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2b_hs>; @@ -421,7 +421,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART2_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2b_tx_sleep>,<&blsp1_uart2b_rx_sleep>, <&blsp1_uart2b_cts_sleep>, <&blsp1_uart2b_rfr_sleep>; @@ -438,7 +438,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x831000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart3_hs>; @@ -457,7 +457,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART3_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_tx_sleep>, <&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>; @@ -474,7 +474,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x832000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart4a_hs>; @@ -493,7 +493,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART4_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4a_tx_sleep>, <&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>; @@ -510,7 +510,7 @@ compatible = "qcom,msm-hsuart-v14"; reg-names = "core_mem", "bam_mem"; reg = <0x832000 0x200>, - <0x80400 0x23000>; + <0x804000 0x23000>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart4b_hs>; @@ -529,7 +529,7 @@ clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_UART1_APPS_CLK>; + <&gcc GCC_BLSP1_UART4_APPS_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart4b_tx_sleep>, <&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>; diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 6b6ff3fc2a0c..b59aa174c58a 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -9,7 +9,7 @@ }; &sdhc_1 { - status = "ok"; + status = "disabled"; vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; @@ -32,4 +32,6 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index c95b7bfa8bba..2e977b84e52b 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -1015,7 +1015,7 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-ipa"; - + status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 768d9aaa521c..3212a1a7041f 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -4,3 +4,19 @@ }; +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + pcie0_generic_ep: pcie0_rp_ep { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&pcie0_generic_ep_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + pcie0_generic_ep_iommu_group: pcie0_generic_ep_iommu_group { + qcom,iommu-dma = "atomic"; + }; + }; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0e02b918f81..cc5ac26327eb 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -12,6 +12,12 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; +}; + +&qnand_1 { + status = "ok"; }; &sdhc_1 { @@ -39,5 +45,5 @@ pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; - status = "ok"; + status = "disabled"; }; diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 35e34a9c4b2d..2ea8fedc36bb 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -43,11 +43,11 @@ &pcie0_wake_default>; gdsc-vdd-supply = <&gcc_pcie_gdsc>; - vreg-1.8-supply = <&pmx65_l1>; - vreg-0.9-supply = <&pmx65_l4>; + vreg-1p8-supply = <&pmx65_l1>; + vreg-0p9-supply = <&pmx65_l4>; vreg-cx-supply = <&VDD_CX_LEVEL>; - qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>; - qcom,vreg-0.9-voltage-level = <912000 912000 132000>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; + qcom,vreg-0p9-voltage-level = <912000 912000 132000>; qcom,vreg-cx-voltage-level = ; qcom,bw-scale = diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 67d96971500f..ea528c0ccbbf 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -208,3 +208,11 @@ }; }; }; + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7e5f6471cab7..0eb9848df6f1 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -12,4 +12,6 @@ &pcie0 { qcom,boot-option = <0x1>; + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f833437c3762..6aa9e75a2eed 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -16,7 +16,7 @@ model = "Qualcomm Technologies, Inc. SDXLEMUR"; compatible = "qcom,sdxlemur"; - qcom,msm-id = <458 0x10000>; + qcom,msm-id = <458 0x10000>, <483 0x10000>; interrupt-parent = <&intc>; aliases { @@ -172,11 +172,8 @@ }; }; - restart_pshold: restart@c264000 { - compatible = "qcom,pshold"; - reg = <0xc264000 0x4>, - <0x1fd3000 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect"; + dload_mode { + compatible = "qcom,dload-mode"; }; dcc: dcc_v2@117f000 { @@ -361,6 +358,18 @@ #clock-cells = <1>; }; + eud: qcom,msm-eud@ff0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xff0000 0x2000>, + <0xff2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + status = "ok"; + }; + serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; @@ -788,14 +797,12 @@ qcom,platform-type = <0>; /* MDM platform */ qcom,ee = <0>; qcom,use-ipa-tethering-bridge; - qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ + qcom,mhi-event-ring-id-limits = <9 15>; /* start and end */ qcom,modem-cfg-emb-pipe-flt; qcom,use-xbl-boot; qcom,arm-smmu; qcom,smmu-fast-map; qcom,ipa-wdi3-over-gsi; - qcom,lan-rx-napi; - qcom,wan-use-skb-page; qcom,tx-wrapper-cache-max-size = <400>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; diff --git a/qcom/sdxnightjar-cdp.dts b/qcom/sdxnightjar-cdp.dts new file mode 100644 index 000000000000..58a5bf7cdc99 --- /dev/null +++ b/qcom/sdxnightjar-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR CDP"; + compatible = "qcom,sdxnightjar-cdp", + "qcom,sdxnightjar", "qcom,cdp"; + qcom,board-id = <0x01 0>; +}; diff --git a/qcom/sdxnightjar-cdp.dtsi b/qcom/sdxnightjar-cdp.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-cdp.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-mtp.dts b/qcom/sdxnightjar-mtp.dts new file mode 100644 index 000000000000..65e7fcd1c964 --- /dev/null +++ b/qcom/sdxnightjar-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP"; + compatible = "qcom,sdxnightjar-mtp", + "qcom,sdxnightjar", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/qcom/sdxnightjar-mtp.dtsi b/qcom/sdxnightjar-mtp.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-mtp.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi new file mode 100644 index 000000000000..fe045ec0167e --- /dev/null +++ b/qcom/sdxnightjar-pinctrl.dtsi @@ -0,0 +1,1363 @@ +#include + +&soc { + tlmm_pinmux: pinctrl@1000000 { + compatible = "qcom,sdxnightjar-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_console_active: uart1_console_active { + mux { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio92"; + function = "qdss_cti"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart2_console_active: uart2_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_active: uart3_console_active { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_sleep: uart3_console_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + bmi160_int1_default: bmi160_int1_default { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + bmi160_int2_default: bmi160_int2_default { + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_sdio_active: cnss_sdio_active { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_sdio_sleep: cnss_sdio_sleep { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SMB CONFIGURATION */ + pmx_smb_stat { + smb_stat_active: smb_stat_active { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio64"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0_mdm2apstatus_default: pcie0_mdm2apstatus_default { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* UART HS CONFIGURATION */ + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_active: blsp1_uart3_active { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_sleep: blsp1_uart3_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_active: blsp1_uart4_active { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_sleep: blsp1_uart4_sleep { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_active: blsp1_uart4b_active { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_sleep: blsp1_uart4b_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + mdss_cs_active: mdss_cs_active { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_cs_sleep: mdss_cs_sleep { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_active: mdss_te_active { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_sleep: mdss_te_sleep { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_active: mdss_rs_active { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_sleep: mdss_rs_sleep { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_active: mdss_ad_active { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_sleep: mdss_ad_sleep { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_bl_active: mdss_bl_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + output-high; + }; + }; + + mdss_bl_sleep: mdss_bl_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + output-low; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio71"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio71"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s_ws_a"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s_ws_a"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s_data1_a"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s_data0_a"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s_ws_a"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s_sck_a"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s_ws_a"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s_sck_a"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s_data1_a"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s_data0_a"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_b_aux { + sec_ws_b_sleep: sec_ws_b_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_b_sleep: sec_sck_b_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_b_sleep: sec_dout_b_sleep { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_b_active_master: sec_ws_b_active_master { + mux { + pins = "gpio20"; + function = "sec_mi2s_ws_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_b_active_master: sec_sck_b_active_master { + mux { + pins = "gpio23"; + function = "sec_mi2s_sck_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_b_active_slave: sec_ws_b_active_slave { + mux { + pins = "gpio20"; + function = "sec_mi2s_ws_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_b_active_slave: sec_sck_b_active_slave { + mux { + pins = "gpio23"; + function = "sec_mi2s_sck_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_b_active: sec_dout_b_active { + mux { + pins = "gpio22"; + function = "sec_mi2s_data1_b"; + }; + + config { + pins = "gpio22"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_b_aux_din { + sec_din_b_sleep: sec_din_b_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_b_active: sec_din_b_active { + mux { + pins = "gpio21"; + function = "sec_mi2s_data0_b"; + }; + + config { + pins = "gpio21"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_wlan_gpio { + sdc1_wlan_gpio_active: sdc1_wlan_gpio_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc1_wlan_gpio_sleep: sdc1_wlan_gpio_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + pinctrl_pps: ppsgrp { + mux { + pins = "gpio39"; + function = "nav_dr"; + }; + + config { + pins = "gpio39"; + bias-pull-down; + }; + }; + + can_reset { + can_rst_on: rst_on { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + }; + }; + + can_rst_off: rst_off { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + output-high; + }; + }; + }; + }; +}; + +&pmd9650_gpios { + gpio@c100 { /* GPIO 2 - VADC */ + /* GPIO should be left off, and in the high + * impedance state when the pin is used with the VADC + */ + pins = "gpio2"; + function = "normal"; + bias-high-impedance; /* DISABLE GPIO */ + }; + + gpio@c200 { /* GPIO 3 - LED */ + pins = "gpio3"; + function = "normal"; + bias-high-impedance; /* DISABLE GPIO */ + }; + + gpio@c400 { /* GPIO 5 - USB_ID */ + pins = "gpio5"; + function = "normal"; + input-enable; /* Digital input */ + bias-pull-up; + qcom,pull-up-strength = ; /* Pull up 1.5 uA */ + power-source = <1>; /* 1.8 V */ + }; +}; diff --git a/qcom/sdxnightjar-qrd.dts b/qcom/sdxnightjar-qrd.dts new file mode 100644 index 000000000000..287997958419 --- /dev/null +++ b/qcom/sdxnightjar-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxnightjar.dtsi" +#include "sdxnightjar-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX NIGHTJAR QRD"; + compatible = "qcom,sdxnightjar-qrd", + "qcom,sdxnightjar", "qcom,qrd"; + qcom,board-id = <0xB 0>; +}; diff --git a/qcom/sdxnightjar-qrd.dtsi b/qcom/sdxnightjar-qrd.dtsi new file mode 100644 index 000000000000..084e2aec6ca1 --- /dev/null +++ b/qcom/sdxnightjar-qrd.dtsi @@ -0,0 +1,6 @@ +&blsp1_uart3 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_console_active>; +}; + diff --git a/qcom/sdxnightjar-regulator.dtsi b/qcom/sdxnightjar-regulator.dtsi new file mode 100644 index 000000000000..32126cb2c986 --- /dev/null +++ b/qcom/sdxnightjar-regulator.dtsi @@ -0,0 +1,258 @@ +#include + +&rpm_bus { + /* PMD9650 S1 = VDD_MSS supply */ + rpm-regulator-smpa1 { + status = "okay"; + pmd9650_s1: regulator-s1 { + regulator-name = "pmd9650_s1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pmd9650_s2: regulator-s2 { + regulator-name = "pmd9650_s2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + qcom,init-voltage = <1256000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pmd9650_s3: regulator-s3 { + regulator-name = "pmd9650_s3"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + qcom,init-voltage = <1024000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pmd9650_s4: regulator-s4 { + regulator-name = "pmd9650_s4"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + qcom,init-voltage = <1856000>; + status = "okay"; + }; + }; + + /* PMD9650 S5 = VDD_CX supply */ + rpm-regulator-smpa5 { + status = "okay"; + pmd9650_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pmd9650_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pmd9650_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pmd9650_l1: regulator-l1 { + regulator-name = "pmd9650_l1"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + qcom,init-voltage = <1224000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pmd9650_l2: regulator-l2 { + regulator-name = "pmd9650_l2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pmd9650_l3: regulator-l3 { + regulator-name = "pmd9650_l3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pmd9650_l4: regulator-l4 { + regulator-name = "pmd9650_l4"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <928000>; + qcom,init-voltage = <928000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pmd9650_l5: regulator-l5 { + regulator-name = "pmd9650_l5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pmd9650_l6: regulator-l6 { + regulator-name = "pmd9650_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pmd9650_l7: regulator-l7 { + regulator-name = "pmd9650_l7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2848000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pmd9650_l8: regulator-l8 { + regulator-name = "pmd9650_l8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + /* PMD9650 L9 = VDD_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + pmd9650_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmd9650_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pmd9650_l10: regulator-l10 { + regulator-name = "pmd9650_l10"; + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <3088000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pmd9650_l11: regulator-l11 { + regulator-name = "pmd9650_l11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2848000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pmd9650_l12: regulator-l12 { + regulator-name = "pmd9650_l12"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pmd9650_l13: regulator-l13 { + regulator-name = "pmd9650_l13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2848000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; +}; + +&soc { + codec_buck_vreg: codec_buck_vreg { + compatible = "regulator-fixed"; + regulator-name = "codec_1.8v"; + regulator-always-on; + }; + + /* Rome 3.3V supply */ + rome_vreg: rome_vreg { + compatible = "regulator-fixed"; + regulator-name = "rome_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmd9650_gpios 6 0>; + }; + + /* SD card 2.95 V supply */ + sdc_vreg: sdc_vreg { + compatible = "regulator-fixed"; + regulator-name = "sdc_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm_pinmux 50 0>; + }; +}; diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi new file mode 100644 index 000000000000..622d46a7c381 --- /dev/null +++ b/qcom/sdxnightjar.dtsi @@ -0,0 +1,432 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. SDXNIGHTJAR"; + compatible = "qcom,sdxnightjar"; + qcom,msm-id = <484 0x10000>; + interrupt-parent = <&intc>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + chosen { }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + peripheral1_mem: peripheral1_region@0x87800000 { + no-map; + reg = <0x87800000 0x400000>; + label = "peripheral1_mem"; + }; + + peripheral2_mem: peripheral2_region@0x87d00000 { + no-map; + reg = <0x87d00000 0x300000>; + label = "peripheral2_mem"; + }; + }; + + aliases { }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x004a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x8600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x8600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + }; + + clock_gcc: qcom,gcc@1800000 { + ompatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + clock_debug: qcom,cc-debug@1874000 { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + clock_cpu: qcom,clock-a7@0b010008 { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + /*TODO: Fix the clock when tree is available*/ + clock-names = "cpu0_clk", "cpu1_clk", + "cpu2_clk", "cpu3_clk"; + qcom,cpufreq-table = + < 200000 >, + < 300000 >, + < 384000 >, + < 600000 >, + < 787200 >, + < 998400 >, + < 1190400 >, + < 1286400 >; + }; + + ahb_clk: qcom,ahb-clk-src { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + /*TODO: Fix the clock when tree is available*/ + governor = "powersave"; + freq-tbl-khz = + < 19200 >, + < 50000 >, + < 100000 >, + < 133330 >; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x0193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb020000 0x1000>; + clock-frequency = <19200000>; + + frame@b021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xb021000 0x1000>, + <0xb022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xb023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xb024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xb025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xb026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xb027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xb028000 0x1000>; + status = "disabled"; + }; + + frame@b029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xb029000 0x1000>; + status = "disabled"; + }; + }; + + + + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + /*TODO: Fix the clock when tree is available*/ + clock-names = "iface_clk"; + }; + + qcom_tzlog: tz-log@08600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; + + qcom,qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 393600>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,ce-opp-freq = <171430000>; + }; + + qcom,qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 393600>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_seecom: qseecom@87800000 { + compatible = "qcom,qseecom"; + reg = <0x87800000 0x200000>; + reg-names = "secapp-region"; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 200000 400000>, + <47 512 300000 800000>, + <47 512 400000 1000000>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "iface_clk", + "bus_clk","core_clk_src"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = <0 107 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b1000 0x200>; + interrupts = <0 109 0>; + /*TODO: Fix the clock when tree is available*/ + clock-names = "core", "iface"; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <1 3 0>, <1 2 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + jtag_mm0: jtagmm@842000 { + compatible = "qcom,jtag-mm"; + reg = <0x842000 0x1000>, + <0x840000 0x1000>; + reg-names = "etm-base","debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + + /*TODO: Fix the clock when tree is available*/ + clock-names = "core_clk", "core_a_clk"; + }; + + qcom,smem@87e80000 { + compatible = "qcom,smem"; + reg = <0x87e80000 0xc0000>, + <0xb011008 0x4>, + <0x60000 0x6000>, + <0x193d000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x0>; + qcom,smd-irq-bitmask = <0x1000>; + interrupts = <0 25 1>; + label = "modem"; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x0>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + qcom,irq-no-suspend; + qcom,not-loadable; + }; + }; + + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */ + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = <0 190 0>; + qcom,pmic-arb-channel = <0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-max-peripherals = <256>; + qcom,pmic-arb-max-periph-interrupts = <256>; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + }; +}; + +#include "pmd9650.dtsi" +#include "pmd9650-rpm-regulator.dtsi" +#include "sdxnightjar-regulator.dtsi" +#include "sdxnightjar-pinctrl.dtsi" diff --git a/qcom/shima-atp.dtsi b/qcom/shima-atp.dtsi index 6ae9ea2b9643..3fc75973a822 100644 --- a/qcom/shima-atp.dtsi +++ b/qcom/shima-atp.dtsi @@ -1,4 +1,212 @@ -#include "shima-idp.dtsi" +#include +#include +#include "shima-pmic-overlay.dtsi" +#include "display/shima-sde-display-idp.dtsi" +#include "shima-thermal-overlay.dtsi" +#include "shima-audio-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 87 0x00>; + qcom,sn-ven = <&tlmm 62 0x00>; + qcom,sn-firm = <&tlmm 86 0x00>; + qcom,sn-clkreq = <&tlmm 63 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <87 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +&sdhc_1 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&S10B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vdd-supply = <&L9C>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6C>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 30000>; + + cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-lahaina"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97100>; + vdda-pll-max-microamp = <19600>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-voltage-level = <2504000 2960000>; + vcc-low-voltage-sup; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + vccq-min-microamp = <10000>; + + vccq2-supply = <&S10B>; + vccq2-voltage-level = <1800000 1800000>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <10000>; + + status = "ok"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&spmi_glink_debug { + status = "ok"; +}; + +&pm8350b_haptics { + status = "ok"; +}; + +&pm8350c_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8350c_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8350c_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8350c_flash { + status = "ok"; +}; + +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + qcom,wireless-fw-name = "idt9412.bin"; +}; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + focaltech,reset-gpio = <&tlmm 22 0x00>; + focaltech,irq-gpio = <&tlmm 23 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L3C>; + vcc_i2c-supply = <&L8C>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + panel = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; + +&dai_mi2s2 { + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; +}; &pm8008i_chip { status = "disabled"; diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 69e699119b63..ca37256988f6 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -10,8 +10,8 @@ #size-cells = <1>; bolero-clk-rsc-mngr { compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; + qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, + <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; qcom,rx_mclk_mode_muxsel = <0x033240D8>; qcom,wsa_mclk_mode_muxsel = <0x033220D8>; qcom,va_mclk_mode_muxsel = <0x033A0000>; diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index f7808d3470d0..9766e11225f9 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -16,10 +16,10 @@ reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, <0x3de0000 0x10000>, <0x3d8b000 0x2000>, - <0x06900000 0x80000>; + <0x06900000 0x80000>, <0x0636000 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", - "isense_cntl", "qdss_gfx"; + "isense_cntl", "qdss_gfx", "rdpm_mx"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 9b4e69e21615..dd34ac6cbd57 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -178,7 +178,6 @@ focaltech,display-coords = <0 0 1080 2340>; vdd-supply = <&L3C>; - vcc_i2c-supply = <&L8C>; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; pinctrl-0 = <&ts_active>; diff --git a/qcom/shima-usb.dtsi b/qcom/shima-usb.dtsi index 6e1d3e73b03a..5e428a4a689c 100644 --- a/qcom/shima-usb.dtsi +++ b/qcom/shima-usb.dtsi @@ -39,6 +39,7 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 8246b5473d9d..44ab78339e3f 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1615,8 +1615,9 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -1752,8 +1753,10 @@ sdhc_1: sdhci@7C4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007c8000 0x8000>, <0x7d0000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; iommus = <&apps_smmu 0xc0 0x0>; dma-coherent; diff --git a/qcom/sm8150-smp2p.dtsi b/qcom/sm8150-smp2p.dtsi new file mode 100644 index 000000000000..999901f99472 --- /dev/null +++ b/qcom/sm8150-smp2p.dtsi @@ -0,0 +1,142 @@ +#include + +&soc { + + qcom,smp2p-modem@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-dsps@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + dsps_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + dsps_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out { + qcom,entry-name = "qvrexternal"; + #qcom,smem-state-cells = <1>; + }; + }; + +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index ca02103037dd..fcb8a87066b1 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -734,6 +734,370 @@ status = "ok"; }; }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm8150-apss-shared"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + sp_scsr: mailbox@188501c { + compatible = "qcom,sm8150-spcs-global"; + reg = <0x188501c 0x4>; + + #mbox-cells = <1>; + }; + + sp_scsr_block: syscon@1880000 { + compatible = "syscon"; + reg = <0x1880000 0x10000>; + }; + + intsp: qcom,qsee_irq { + compatible = "qcom,sm8150-qsee-irq"; + + syscon = <&sp_scsr_block>; + interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, + <0 349 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "sp_ipc0", + "sp_ipc1"; + + interrupt-controller; + #interrupt-cells = <3>; + }; + + qcom,qsee_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,dev-name = "qsee_ipc_irq_spss"; + label = "spss"; + interrupt-parent = <&intsp>; + interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apss_shared 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_slpi>, + <&glink_cdsp>, + <&glink_spss>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apss_shared 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_slpi>, + <&glink_cdsp>; + }; + }; + + glink_slpi: dsps { + qcom,remote-pid = <3>; + transport = "smem"; + mboxes = <&apss_shared 24>; + mbox-names = "dsps_smem"; + interrupts = ; + + label = "slpi"; + qcom,glink-label = "dsps"; + + qcom,slpi_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,slpi_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apss_shared 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + qcom,cdsp-cdsp-l3-gov { + compatible = "qcom,cdsp-l3"; + /* qcom,target-dev = <&cdsp_cdsp_l3_lat>;*/ + }; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + qcom,compute-cx-limit-en; + qcom,compute-priority-mode = <2>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_slpi>; + }; + }; + + glink_spss: spss { + qcom,remote-pid = <8>; + transport = "spss"; + mboxes = <&sp_scsr 0>; + mbox-names = "spss_spss"; + interrupt-parent = <&intsp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + + qcom,spss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; }; &firmware { @@ -747,3 +1111,4 @@ #include "sm8150-regulator.dtsi" #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi" +#include "sm8150-smp2p.dtsi" diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index c10aa1385e0e..a79bbd58abf5 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -15,6 +15,12 @@ reg = ; qcom,ion-heap-type = "SYSTEM_SECURE"; }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index be693f53cd92..cc04ff320e6e 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -322,6 +322,14 @@ reg = <0x0 0xc0000000 0x0 0x5100000>; }; + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool";