From 61d0c902329cdf8cbccc0bb29e64205797a64f0d Mon Sep 17 00:00:00 2001
From: Karthik Anantha Ram <kartanan@quicinc.com>
Date: Mon, 3 Aug 2020 15:30:12 -0700
Subject: [PATCH] ARM: dts: msm: Correct SVS clock level for IPE0 in Lahaina DT

The SVS clock rate for IPE0 is 450MHz as opposed to 475MHz.
This wrong entry resulted in clock being bumped to NOM instead
of SVS level.

CRs-Fixed: 2745429
Change-Id: I759cff68f3811d9f7c44d2fe99bbc0433895945a
---
 lahaina-camera.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lahaina-camera.dtsi b/lahaina-camera.dtsi
index eb80415a1ed9..116baed82f17 100644
--- a/lahaina-camera.dtsi
+++ b/lahaina-camera.dtsi
@@ -1808,7 +1808,7 @@
 
 		clock-rates =
 			<0 0 0 300000000 0>,
-			<0 0 0 475000000 0>,
+			<0 0 0 450000000 0>,
 			<0 0 0 525000000 0>,
 			<0 0 0 700000000 0>,
 			<0 0 0 700000000 0>;