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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
ASoC: aw882xx driver update
This is Awinic official release, the key change is i2c_read function, use i2c_transfer to replace the old one, add thread_lock to protect i2c operation safety, in order to resolve a potential no sound risk after supporting different audio scenarios feature. NO_PROP_NEEDED: aw882xx doesn't use in bq-shm2018 products. Change-Id: I3daeb35c6a349c65bdb723d7f12430634abbf8f2 Signed-off-by: zhouwl <zhouwl@lenovo.com> Reviewed-on: https://gerrit.mot.com/1537490 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Hujun Liao <liaohj@motorola.com> Reviewed-by: Wen Xie <xiewen3@motorola.com> Submit-Approved: Jira Key Reviewed-by: Yunfei Guo <guoyf2@motorola.com>
This commit is contained in:
zhouwl
Wanlong Zhou
parent
36b7510d2c
commit
6204f33cd5
3 changed files with 56 additions and 18 deletions
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@ -173,25 +173,36 @@ static int aw882xx_i2c_writes(struct aw882xx *aw882xx,
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}
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static int aw882xx_i2c_reads(struct aw882xx *aw882xx,
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unsigned char reg_addr, unsigned char *buf, unsigned int len)
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unsigned char reg_addr, unsigned char *data_buf, unsigned int data_len)
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{
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int ret = -1;
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int ret;
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struct i2c_msg msg[] = {
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[0] = {
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.addr = aw882xx->i2c->addr,
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.flags = 0,
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.len = sizeof(uint8_t),
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.buf = ®_addr,
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},
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[1] = {
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.addr = aw882xx->i2c->addr,
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.flags = I2C_M_RD,
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.len = data_len,
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.buf = data_buf,
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},
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};
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ret = i2c_smbus_write_byte(aw882xx->i2c, reg_addr);
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ret = i2c_transfer(aw882xx->i2c->adapter, msg, ARRAY_SIZE(msg));
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if (ret < 0) {
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pr_err("%s: i2c master send error, ret=%d\n",
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__func__, ret);
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return ret;
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}
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ret = i2c_master_recv(aw882xx->i2c, buf, len);
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if (ret != len) {
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} else if (ret != AW882XX_I2C_READ_MSG_NUM) {
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pr_err("%s: couldn't read registers, return %d bytes\n",
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__func__, ret);
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return ret;
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return -ENXIO;
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}
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return ret;
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return 0;
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}
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static int aw882xx_i2c_write(struct aw882xx *aw882xx,
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@ -343,7 +354,7 @@ static int aw882xx_sysst_check(struct aw882xx *aw882xx)
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for (i = 0; i < AW882XX_SYSST_CHECK_MAX; i++) {
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aw882xx_i2c_read(aw882xx, AW882XX_SYSST_REG, ®_val);
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if ((reg_val & (~AW882XX_SYSST_CHECK_MASK)) ==
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if (((reg_val & (~AW882XX_SYSST_CHECK_MASK)) & AW882XX_SYSST_CHECK) ==
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AW882XX_SYSST_CHECK) {
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ret = 0;
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break;
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@ -453,9 +464,11 @@ static int aw882xx_set_vcalb(struct aw882xx *aw882xx)
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static void aw882xx_send_cali_re_to_dsp(struct aw882xx *aw882xx)
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{
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int ret;
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ret = aw_send_afe_cal_apr(AFE_PARAM_ID_AWDSP_RX_RE_L,
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&aw882xx->cali_re, sizeof(int32_t), true);
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int ret = 0;
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if ((aw882xx != NULL) && (aw882xx->cali_re != ERRO_CALI_VALUE)) {
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ret = aw_send_afe_cal_apr(AFE_PARAM_ID_AWDSP_RX_RE_L,
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&aw882xx->cali_re, sizeof(int32_t), true);
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}
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if (ret)
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pr_err("%s : set cali re to dsp failed 0x%x\n",
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__func__ , AFE_PARAM_ID_AWDSP_RX_RE_L);
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@ -469,9 +482,9 @@ static void aw882xx_start(struct aw882xx *aw882xx)
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ret = aw882xx_get_cali_re_form_nv(&cali_re);
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if (ret < 0) {
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cali_re = (DEFAULT_CALI_VALUE << 12);
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cali_re = ERRO_CALI_VALUE;
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pr_err("%s: use default vaule %d",
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__func__ , DEFAULT_CALI_VALUE);
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__func__ , ERRO_CALI_VALUE);
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}
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ret = aw882xx_set_cali_re(aw882xx, cali_re);
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if (ret < 0)
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@ -1223,6 +1236,7 @@ static int aw882xx_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_codec *codec = dai->codec;
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struct aw882xx *aw882xx = snd_soc_codec_get_drvdata(codec);
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unsigned int rate = 0;
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uint32_t cco_mux_value;
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int reg_value = 0;
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int width = 0;
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@ -1240,30 +1254,40 @@ static int aw882xx_hw_params(struct snd_pcm_substream *substream,
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switch (rate) {
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case 8000:
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reg_value = AW882XX_I2SSR_8KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_8_16_32KHZ_VALUE;
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break;
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case 16000:
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reg_value = AW882XX_I2SSR_16KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_8_16_32KHZ_VALUE;
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break;
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case 32000:
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reg_value = AW882XX_I2SSR_32KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_8_16_32KHZ_VALUE;
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break;
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case 44100:
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reg_value = AW882XX_I2SSR_44P1KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE;
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break;
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case 48000:
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reg_value = AW882XX_I2SSR_48KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE;
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break;
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case 96000:
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reg_value = AW882XX_I2SSR_96KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE;
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break;
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case 192000:
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reg_value = AW882XX_I2SSR_192KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE;
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break;
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default:
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reg_value = AW882XX_I2SSR_48KHZ_VALUE;
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cco_mux_value = AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE;
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pr_err("%s: rate can not support\n", __func__);
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break;
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}
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aw882xx_i2c_write_bits(aw882xx, AW882XX_PLLCTRL1_REG,
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AW882XX_I2S_CCO_MUX_MASK, cco_mux_value);
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/* set chip rate */
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if (-1 != reg_value) {
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@ -7,6 +7,7 @@
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* (See Linux kernel documentation: Documentation/i2c/writing-clients)
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*/
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#define MAX_I2C_BUFFER_SIZE 65536
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#define AW882XX_I2C_READ_MSG_NUM 2
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#define AW882XX_FLAG_START_ON_MUTE (1 << 0)
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#define AW882XX_FLAG_SKIP_INTERRUPTS (1 << 1)
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@ -25,6 +26,7 @@
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#define DEFAULT_CALI_VALUE (7)
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#define ERRO_CALI_VALUE (0)
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#define AFE_PARAM_ID_AWDSP_RX_SET_ENABLE (0x10013D11)
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#define AFE_PARAM_ID_AWDSP_RX_PARAMS (0x10013D12)
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#define AFE_PARAM_ID_AWDSP_TX_SET_ENABLE (0x10013D13)
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@ -407,9 +407,7 @@ const unsigned char aw882xx_reg_access[AW882XX_REG_MAX] = {
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AW882XX_PLLS_LOCKED_VALUE))
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#define AW882XX_SYSST_CHECK \
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(AW882XX_BSTS_FINISHED_VALUE | \
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AW882XX_SWS_SWITCHING_VALUE | \
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AW882XX_CLKS_TRIG_VALUE | \
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(AW882XX_CLKS_TRIG_VALUE | \
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AW882XX_PLLS_LOCKED_VALUE)
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#define AW882XX_IIS_CHECK_MASK \
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@ -1176,6 +1174,20 @@ const unsigned char aw882xx_reg_access[AW882XX_REG_MAX] = {
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#define AW882XX_I2SSR_MASK \
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(~(((1<<AW882XX_I2SSR_BITS_LEN)-1)<<AW882XX_I2SSR_START_BIT))
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/* I2S CCO_UMX */
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#define AW882XX_I2S_CCO_MUX_START_BIT (14)
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#define AW882XX_I2S_CCO_MUX_BITS_LEN (1)
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#define AW882XX_I2S_CCO_MUX_MASK \
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(~(((1<<AW882XX_I2S_CCO_MUX_BITS_LEN)-1)<<AW882XX_I2S_CCO_MUX_START_BIT))
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#define AW882XX_I2S_CCO_MUX_8_16_32KHZ_BIT_VALUE (0)
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#define AW882XX_I2S_CCO_MUX_8_16_32KHZ_VALUE \
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(AW882XX_I2S_CCO_MUX_8_16_32KHZ_BIT_VALUE<<AW882XX_I2S_CCO_MUX_START_BIT)
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#define AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_BIT_VALUE (1)
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#define AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE \
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(AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_BIT_VALUE<<AW882XX_I2S_CCO_MUX_START_BIT)
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#define AW882XX_I2SSR_8KHZ (0)
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#define AW882XX_I2SSR_8KHZ_VALUE \
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(AW882XX_I2SSR_8KHZ << AW882XX_I2SSR_START_BIT)
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