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fpga: zynq-fpga: Fix unbalanced clock handling

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This commit fixes the unbalanced clock handling, where
a failed probe would leave the clock with an enable count of -1.

Reported-by: Josh Cartwright <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Moritz Fischer 2015-10-19 13:35:33 -07:00 • committed by Greg Kroah-Hartman
commit 6376931bab
1 changed files with 2 additions and 2 deletions
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4
drivers/fpga/zynq-fpga.c
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@ -487,7 +487,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)
&zynq_fpga_ops, priv);
if (err) {
dev_err(dev, "unable to register FPGA manager");
clk_disable_unprepare(priv->clk);
clk_unprepare(priv->clk);
return err;
}
@ -502,7 +502,7 @@ static int zynq_fpga_remove(struct platform_device *pdev)
priv = platform_get_drvdata(pdev);
clk_disable_unprepare(priv->clk);
clk_unprepare(priv->clk);
return 0;
}