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[media] omap3isp: Calculate vpclk_div for CSI-2

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The video port clock is l3_ick divided by vpclk_div. This clock must be high
enough for the external pixel rate. The video port requires two clock cycles
to process a pixel.

Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
This commit is contained in:
Sakari Ailus 2015-03-25 19:57:32 -03:00 • committed by Mauro Carvalho Chehab
commit 6387b75284
2 changed files with 7 additions and 3 deletions
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include/media/omap3isp.h
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@ -129,11 +129,9 @@ struct isp_ccp2_cfg {
/**
* struct isp_csi2_cfg - CSI2 interface configuration
* @crc: Enable the cyclic redundancy check
* @vpclk_div: Video port output clock control
*/
struct isp_csi2_cfg {
unsigned crc:1;
unsigned vpclk_div:2;
struct isp_csiphy_lanes_cfg lanecfg;
};