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ARM: SoC late changes for v3.12

Browse source 
These are changes that arrived a little late before the merge window,
 or had dependencies on previous branches.
 
 Highlights:
 - ux500: misc. cleanup, fixup I2C devices
 - exynos: DT updates for RTC; PM updates
 - at91: DT updates for NAND; new platforms added to generic defconfig
 - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
 - highbank: LPAE fixes, select necessary ARM errata
 - omap: PM fixes and improvements; OMAP5 mailbox support
 - omap: basic support for new DRA7xx SoCs
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Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late changes from Kevin Hilman:
 "These are changes that arrived a little late before the merge window,
  or had dependencies on previous branches.

  Highlights:
   - ux500: misc.  cleanup, fixup I2C devices
   - exynos: DT updates for RTC; PM updates
   - at91: DT updates for NAND; new platforms added to generic defconfig
   - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
   - highbank: LPAE fixes, select necessary ARM errata
   - omap: PM fixes and improvements; OMAP5 mailbox support
   - omap: basic support for new DRA7xx SoCs"

* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  ARM: dts: vexpress: Add CCI node to TC2 device-tree
  ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
  ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
  ARM: highbank: clean-up some unused includes
  ARM: sun7i: Enable the A20 clocks in the DTSI
  ARM: sun6i: Enable clock support in the DTSI
  ARM: sun5i: dt: Use the A10s gates in the DTSI
  ARM: at91: at91_dt_defconfig: enable rm9200 support
  ARM: dts: add ADC device tree node for exynos5420/5250
  ARM: dts: Add RTC DT node to Exynos5420 SoC
  ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC
  ARM: dts: Fix the RTC DT node name for Exynos5250
  irqchip: mmp: avoid to include irqs head file
  ARM: mmp: avoid to include head file in mach-mmp
  irqchip: mmp: support irqchip
  irqchip: move mmp irq driver
  ARM: OMAP: AM33xx: clock: Add RNG clock data
  ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
  ARM: OMAP4: clock: Lock PLLs in the right sequence
  ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
  ...
This commit is contained in:
Linus Torvalds 2013-09-09 16:35:29 -07:00
commit 6404141718
69 changed files with 6486 additions and 1082 deletions
Download patch file Download diff file Expand all files Collapse all files

23
drivers/dma/amba-pl08x.c
View file

@ -133,6 +133,8 @@ struct pl08x_bus_data {
u8 buswidth;
};
#define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
/**
* struct pl08x_phy_chan - holder for the physical channels
* @id: physical index to this channel
@ -845,10 +847,13 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
dev_vdbg(&pl08x->adev->dev,
"src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
(u64)bd.srcbus.addr,
cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
bd.srcbus.buswidth,
bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
(u64)bd.dstbus.addr,
cctl & PL080_CONTROL_DST_INCR ? "+" : "",
bd.dstbus.buswidth,
bd.remainder);
dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
@ -886,8 +891,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
return 0;
}
if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
(bd.dstbus.addr % bd.dstbus.buswidth)) {
if (!IS_BUS_ALIGNED(&bd.srcbus) ||
!IS_BUS_ALIGNED(&bd.dstbus)) {
dev_err(&pl08x->adev->dev,
"%s src & dst address must be aligned to src"
" & dst width if peripheral is flow controller",
@ -908,9 +913,9 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
*/
if (bd.remainder < mbus->buswidth)
early_bytes = bd.remainder;
else if ((mbus->addr) % (mbus->buswidth)) {
early_bytes = mbus->buswidth - (mbus->addr) %
(mbus->buswidth);
else if (!IS_BUS_ALIGNED(mbus)) {
early_bytes = mbus->buswidth -
(mbus->addr & (mbus->buswidth - 1));
if ((bd.remainder - early_bytes) < mbus->buswidth)
early_bytes = bd.remainder;
}
@ -928,7 +933,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
* Master now aligned
* - if slave is not then we must set its width down
*/
if (sbus->addr % sbus->buswidth) {
if (!IS_BUS_ALIGNED(sbus)) {
dev_dbg(&pl08x->adev->dev,
"%s set down bus width to one byte\n",
__func__);