fw-api: CL 8762856 - update fw common interface files

HTT stats: extend counters to cover MCS 12,13

Change-Id: I8a849fc4661d0854479b23cc97ca7a5eed4cab06
CRs-Fixed: 2262693
This commit is contained in:
spuligil 2019-11-13 06:00:36 -08:00
commit 649fd2f34c
3 changed files with 71 additions and 6 deletions

View file

@ -1216,7 +1216,8 @@ typedef enum {
HTT_STATS_PREAM_COUNT,
} HTT_STATS_PREAM_TYPE;
#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12
#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
#define HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
/* HTT_TX_PEER_STATS_NUM_GI_COUNTERS:
* GI Index 0: WHAL_GI_800
* GI Index 1: WHAL_GI_400
@ -1265,9 +1266,17 @@ typedef struct _htt_tx_peer_rate_stats_tlv {
/* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */
A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
/* Stats for MCS 12/13 */
A_UINT32 tx_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 tx_su_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
} htt_tx_peer_rate_stats_tlv;
#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12
#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
#define HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4
#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5
#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
@ -1319,6 +1328,11 @@ typedef struct _htt_rx_peer_rate_stats_tlv {
A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */
A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */
/* Stats for MCS 12/13 */
A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
} htt_rx_peer_rate_stats_tlv;
typedef enum {
@ -3009,7 +3023,8 @@ typedef struct {
/* == PDEV TX RATE CTRL STATS == */
#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
#define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
@ -3112,6 +3127,15 @@ typedef struct {
A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES];
A_UINT32 tx_11ax_su_ext;
/* Stats for MCS 12/13 */
A_UINT32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
} htt_tx_pdev_rate_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
@ -3130,7 +3154,8 @@ typedef struct {
#define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
#define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
#define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
@ -3261,6 +3286,16 @@ typedef struct {
A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* mpdu level */
A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
/* Stats for MCS 12/13 */
A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_stbc_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ul_ofdma_rx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_11ax_su_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_11ax_mu_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 rx_11ax_dl_ofdma_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
} htt_rx_pdev_rate_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE
@ -3313,6 +3348,9 @@ typedef struct {
A_UINT32 rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */
A_UINT32 rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */
/* Stats for MCS 12/13 */
A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ul_ofdma_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
} htt_rx_pdev_ul_trigger_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
@ -3369,6 +3407,10 @@ typedef struct {
A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
A_UINT32 ul_mumimo_rx_stbc;
A_UINT32 ul_mumimo_rx_ldpc;
/* Stats for MCS 12/13 */
A_UINT32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
A_UINT32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
} htt_rx_pdev_ul_mumimo_trig_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS

View file

@ -2179,6 +2179,20 @@ typedef enum {
*/
#define WMI_HE_MAX_MCS_4_SS_MASK(r,ss) ((3 & (r)) << (((ss) - 1) << 1))
/*
* index ranges from 0 to 15, and is used for checking if MCS 12/13 is enabled
* for a particular NSS.
* The lower 8 bits (indices 0-7) within the 16 bits indicate MCS 12/13
* enablement for BW <= 80MHz; the upper 8 bits (indices 8-15) within
* the 16 bits indicate MCS 12/13 enablement for BW > 80MHz.
* The 16 bits for the index values are within the upper bits (bits 31:16)
* of a 32-bit word.
*/
#define WMI_HE_EXTRA_MCS_SS_GET(he_mcs_map_ext, index) \
WMI_GET_BITS(he_mcs_map_ext, 16 + index, 1)
#define WMI_HE_EXTRA_MCS_SS_SET(he_mcs_map_ext, index, value) \
WMI_SET_BITS(he_mcs_map_ext, 16 + index, 1, value)
/* fragmentation support field value */
enum {
WMI_HE_FRAG_SUPPORT_LEVEL0, /* No Fragmentation support */
@ -12031,7 +12045,16 @@ typedef struct {
* value 1 - MCS 0-9 enabled for this NSS
* value 2 - MCS 0-11 enabled for this NSS
* value 3 - NSS disabled
* - WMI_HE_MAX_MCS_4_SS_MASK macro can be used for encoding this info
* WMI_HE_MAX_MCS_4_SS_MASK macro can be used for encoding this info
*
* - 8 bits x 2 are used for each Nss value for 2 categories of bandwidths,
* to indicate whether MCS 12 and 13 are enabled.
* Bits [16:23] used for checking if MCS 12/13 is enabled for a
* particular NSS (BW <= 80MHz)
* Bits [24:31] used for checking if MCS 12/13 is enabled for a
* particular NSS (BW > 80MHz)
* The WMI_HE_EXTRA_MCS_SS_[GET,SET] macros can be used for accessing
* these bit-fields.
*/
A_UINT32 tx_mcs_set; /* Negotiated TX HE rates(i.e. rate this node can TX to peer) */
} wmi_he_rate_set;

View file

@ -36,7 +36,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
#define __WMI_REVISION_ 738
#define __WMI_REVISION_ 739
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work