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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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fw-api: CL 8762856 - update fw common interface files
HTT stats: extend counters to cover MCS 12,13 Change-Id: I8a849fc4661d0854479b23cc97ca7a5eed4cab06 CRs-Fixed: 2262693
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3 changed files with 71 additions and 6 deletions
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@ -1216,7 +1216,8 @@ typedef enum {
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HTT_STATS_PREAM_COUNT,
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} HTT_STATS_PREAM_TYPE;
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#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12
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#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
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#define HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
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/* HTT_TX_PEER_STATS_NUM_GI_COUNTERS:
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* GI Index 0: WHAL_GI_800
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* GI Index 1: WHAL_GI_400
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@ -1265,9 +1266,17 @@ typedef struct _htt_tx_peer_rate_stats_tlv {
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/* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */
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A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
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/* Stats for MCS 12/13 */
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A_UINT32 tx_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 tx_su_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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} htt_tx_peer_rate_stats_tlv;
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#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12
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#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
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#define HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
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#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4
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#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5
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#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
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@ -1319,6 +1328,11 @@ typedef struct _htt_rx_peer_rate_stats_tlv {
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A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */
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A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */
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/* Stats for MCS 12/13 */
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A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
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} htt_rx_peer_rate_stats_tlv;
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typedef enum {
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@ -3009,7 +3023,8 @@ typedef struct {
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/* == PDEV TX RATE CTRL STATS == */
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#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
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#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
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#define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
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#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
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#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
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#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
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@ -3112,6 +3127,15 @@ typedef struct {
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A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
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A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES];
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A_UINT32 tx_11ax_su_ext;
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/* Stats for MCS 12/13 */
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A_UINT32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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} htt_tx_pdev_rate_stats_tlv;
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/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
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@ -3130,7 +3154,8 @@ typedef struct {
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#define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
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#define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
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#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
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#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
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#define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
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#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
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#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
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#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
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@ -3261,6 +3286,16 @@ typedef struct {
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A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* mpdu level */
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A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
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A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
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/* Stats for MCS 12/13 */
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A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_stbc_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ul_ofdma_rx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_11ax_su_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_11ax_mu_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 rx_11ax_dl_ofdma_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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} htt_rx_pdev_rate_stats_tlv;
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/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE
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@ -3313,6 +3348,9 @@ typedef struct {
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A_UINT32 rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */
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A_UINT32 rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */
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/* Stats for MCS 12/13 */
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A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ul_ofdma_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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} htt_rx_pdev_ul_trigger_stats_tlv;
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/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
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@ -3369,6 +3407,10 @@ typedef struct {
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A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
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A_UINT32 ul_mumimo_rx_stbc;
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A_UINT32 ul_mumimo_rx_ldpc;
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/* Stats for MCS 12/13 */
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A_UINT32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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A_UINT32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
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} htt_rx_pdev_ul_mumimo_trig_stats_tlv;
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/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS
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@ -2179,6 +2179,20 @@ typedef enum {
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*/
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#define WMI_HE_MAX_MCS_4_SS_MASK(r,ss) ((3 & (r)) << (((ss) - 1) << 1))
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/*
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* index ranges from 0 to 15, and is used for checking if MCS 12/13 is enabled
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* for a particular NSS.
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* The lower 8 bits (indices 0-7) within the 16 bits indicate MCS 12/13
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* enablement for BW <= 80MHz; the upper 8 bits (indices 8-15) within
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* the 16 bits indicate MCS 12/13 enablement for BW > 80MHz.
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* The 16 bits for the index values are within the upper bits (bits 31:16)
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* of a 32-bit word.
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*/
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#define WMI_HE_EXTRA_MCS_SS_GET(he_mcs_map_ext, index) \
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WMI_GET_BITS(he_mcs_map_ext, 16 + index, 1)
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#define WMI_HE_EXTRA_MCS_SS_SET(he_mcs_map_ext, index, value) \
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WMI_SET_BITS(he_mcs_map_ext, 16 + index, 1, value)
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/* fragmentation support field value */
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enum {
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WMI_HE_FRAG_SUPPORT_LEVEL0, /* No Fragmentation support */
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@ -12031,7 +12045,16 @@ typedef struct {
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* value 1 - MCS 0-9 enabled for this NSS
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* value 2 - MCS 0-11 enabled for this NSS
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* value 3 - NSS disabled
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* - WMI_HE_MAX_MCS_4_SS_MASK macro can be used for encoding this info
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* WMI_HE_MAX_MCS_4_SS_MASK macro can be used for encoding this info
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*
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* - 8 bits x 2 are used for each Nss value for 2 categories of bandwidths,
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* to indicate whether MCS 12 and 13 are enabled.
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* Bits [16:23] used for checking if MCS 12/13 is enabled for a
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* particular NSS (BW <= 80MHz)
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* Bits [24:31] used for checking if MCS 12/13 is enabled for a
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* particular NSS (BW > 80MHz)
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* The WMI_HE_EXTRA_MCS_SS_[GET,SET] macros can be used for accessing
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* these bit-fields.
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*/
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A_UINT32 tx_mcs_set; /* Negotiated TX HE rates(i.e. rate this node can TX to peer) */
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} wmi_he_rate_set;
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@ -36,7 +36,7 @@
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#define __WMI_VER_MINOR_ 0
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/** WMI revision number has to be incremented when there is a
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* change that may or may not break compatibility. */
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#define __WMI_REVISION_ 738
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#define __WMI_REVISION_ 739
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/** The Version Namespace should not be normally changed. Only
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* host and firmware of the same WMI namespace will work
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