mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
pci: msm: Add support for NTN3 switch i2c client operations
NTN3 switch requires register access over i2c when PCIe link is not up. Add i2c control interface for a i2c client driver. This i2c control interface registers with a i2c client driver and provides client specific callbacks for read, write, reset and register dump operations.i2c control interface can support one i2c client per root port. Change-Id: I9e5f91cab4fd2bb2c6274ad0317fad4279db6958 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
This commit is contained in:
Hemant Kumar
parent
1e80429995
commit
64ca9f61d8
1 changed files with 332 additions and 0 deletions
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@ -9,6 +9,7 @@
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/interconnect.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -20,6 +21,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msm_pcie.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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@ -696,6 +698,36 @@ struct msm_pcie_drv_info {
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struct completion completion;
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};
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/* i2c control interface for a i2c client device */
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struct pcie_i2c_ctrl {
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struct i2c_client *client;
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/* client specific register info */
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u32 gpio_config_reg;
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u32 ep_reset_reg;
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u32 ep_reset_gpio_mask;
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u32 *dump_regs;
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u32 dump_reg_count;
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/* client specific callbacks */
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int (*client_i2c_read)(struct i2c_client *client, u32 reg_addr,
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u32 *val);
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int (*client_i2c_write)(struct i2c_client *client, u32 reg_addr,
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u32 val);
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int (*client_i2c_reset)(struct pcie_i2c_ctrl *i2c_ctrl, bool reset);
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void (*client_i2c_dump_regs)(struct pcie_i2c_ctrl *i2c_ctrl);
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};
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enum i2c_client_id {
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I2C_CLIENT_ID_NTN3,
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I2C_CLIENT_ID_MAX,
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};
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struct i2c_driver_data {
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int rc_index;
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enum i2c_client_id client_id;
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};
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/* msm pcie device structure */
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struct msm_pcie_dev_t {
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struct platform_device *pdev;
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@ -854,6 +886,8 @@ struct msm_pcie_dev_t {
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u32 *filtered_bdfs;
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u32 bdf_count;
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struct pcie_i2c_ctrl i2c_ctrl;
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};
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struct msm_root_dev_t {
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@ -4357,6 +4391,9 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev)
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link_check_count);
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PCIE_INFO(dev, "PCIe RC%d link initialized\n", dev->rc_idx);
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} else {
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if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_dump_regs)
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dev->i2c_ctrl.client_i2c_dump_regs(&dev->i2c_ctrl);
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PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
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dev->rc_idx);
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gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
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@ -4399,6 +4436,170 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev)
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return 0;
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}
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/* write 32-bit value to 24 bit register */
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static int ntn3_i2c_write(struct i2c_client *client, u32 reg_addr,
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u32 reg_val)
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{
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int ret;
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u8 msg_buf[7];
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struct i2c_msg msg;
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msg.addr = client->addr;
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msg.len = 7;
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msg.flags = 0;
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// Big Endian for reg addr
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msg_buf[0] = (u8)(reg_addr >> 16);
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msg_buf[1] = (u8)(reg_addr >> 8);
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msg_buf[2] = (u8)reg_addr;
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// Little Endian for reg val
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msg_buf[3] = (u8)(reg_val);
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msg_buf[4] = (u8)(reg_val >> 8);
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msg_buf[5] = (u8)(reg_val >> 16);
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msg_buf[6] = (u8)(reg_val >> 24);
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msg.buf = msg_buf;
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ret = i2c_transfer(client->adapter, &msg, 1);
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return ret == 1 ? 0 : ret;
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}
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/* read 32 bit value from 24 bit reg addr */
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static int ntn3_i2c_read(struct i2c_client *client, u32 reg_addr,
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u32 *reg_val)
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{
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int ret;
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u8 wr_data[3], rd_data[4];
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struct i2c_msg msg[2];
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msg[0].addr = client->addr;
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msg[0].len = 3;
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msg[0].flags = 0;
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// Big Endian for reg addr
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wr_data[0] = (u8)(reg_addr >> 16);
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wr_data[1] = (u8)(reg_addr >> 8);
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wr_data[2] = (u8)reg_addr;
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msg[0].buf = wr_data;
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msg[1].addr = client->addr;
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msg[1].len = 4;
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msg[1].flags = I2C_M_RD;
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msg[1].buf = rd_data;
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ret = i2c_transfer(client->adapter, &msg[0], 2);
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if (ret != 2)
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return ret;
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*reg_val = (rd_data[3] << 24) | (rd_data[2] << 16) | (rd_data[1] << 8) |
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rd_data[0];
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return 0;
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}
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static int ntn3_ep_reset_ctrl(struct pcie_i2c_ctrl *i2c_ctrl, bool reset)
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{
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int ret, rd_val;
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struct msm_pcie_dev_t *pcie_dev = container_of(i2c_ctrl,
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struct msm_pcie_dev_t,
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i2c_ctrl);
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if (!i2c_ctrl->client_i2c_write || !i2c_ctrl->client_i2c_read)
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return -EOPNOTSUPP;
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/* set NTN3 GPIO as output */
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ret = i2c_ctrl->client_i2c_read(i2c_ctrl->client,
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i2c_ctrl->gpio_config_reg, &rd_val);
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if (ret) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: gpio config reg read failed : %d\n",
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pcie_dev->rc_idx, ret);
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return ret;
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}
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rd_val &= ~i2c_ctrl->ep_reset_gpio_mask;
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i2c_ctrl->client_i2c_write(i2c_ctrl->client, i2c_ctrl->gpio_config_reg,
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rd_val);
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/* read back to flush write - config gpio */
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ret = i2c_ctrl->client_i2c_read(i2c_ctrl->client,
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i2c_ctrl->gpio_config_reg, &rd_val);
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if (ret) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: gpio config reg read failed : %d\n",
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pcie_dev->rc_idx, ret);
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return ret;
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}
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ret = i2c_ctrl->client_i2c_read(i2c_ctrl->client,
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i2c_ctrl->ep_reset_reg, &rd_val);
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if (ret) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: ep_reset_gpio read failed : %d\n",
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pcie_dev->rc_idx, ret);
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return ret;
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}
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rd_val &= ~i2c_ctrl->ep_reset_gpio_mask;
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i2c_ctrl->client_i2c_write(i2c_ctrl->client, i2c_ctrl->ep_reset_reg,
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rd_val);
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/* read back to flush write - reset gpio */
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ret = i2c_ctrl->client_i2c_read(i2c_ctrl->client,
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i2c_ctrl->ep_reset_reg, &rd_val);
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if (ret) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: ep_reset_gpio read failed : %d\n",
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pcie_dev->rc_idx, ret);
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return ret;
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}
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/* ep reset done */
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if (reset)
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return 0;
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/* toggle (0 -> 1) reset gpios to bring eps out of reset */
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rd_val |= i2c_ctrl->ep_reset_gpio_mask;
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i2c_ctrl->client_i2c_write(i2c_ctrl->client, i2c_ctrl->ep_reset_reg,
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rd_val);
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/* read back to flush write - reset gpio */
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ret = i2c_ctrl->client_i2c_read(i2c_ctrl->client,
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i2c_ctrl->ep_reset_reg, &rd_val);
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if (ret) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: ep_reset_gpio read failed : %d\n",
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pcie_dev->rc_idx, ret);
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return ret;
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}
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return 0;
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}
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static void ntn3_dump_regs(struct pcie_i2c_ctrl *i2c_ctrl)
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{
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int i, val;
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struct msm_pcie_dev_t *pcie_dev = container_of(i2c_ctrl,
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struct msm_pcie_dev_t,
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i2c_ctrl);
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if (!i2c_ctrl->client_i2c_read || !i2c_ctrl->dump_reg_count)
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return;
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PCIE_DUMP(pcie_dev, "PCIe: RC%d: NTN3 reg dumps\n", pcie_dev->rc_idx);
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for (i = 0; i < i2c_ctrl->dump_reg_count; i++) {
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i2c_ctrl->client_i2c_read(i2c_ctrl->client,
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i2c_ctrl->dump_regs[i], &val);
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PCIE_DUMP(pcie_dev, "PCIe: RC%d: reg: 0x%04x val: 0x%08x\n",
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pcie_dev->rc_idx, i2c_ctrl->dump_regs[i], val);
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}
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}
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static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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{
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int ret = 0;
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@ -4561,6 +4762,10 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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msm_pcie_config_link_pm(dev, true);
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}
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/* bring eps out of reset */
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if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_reset)
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dev->i2c_ctrl.client_i2c_reset(&dev->i2c_ctrl, false);
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goto out;
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link_fail:
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@ -4607,6 +4812,10 @@ static void msm_pcie_disable(struct msm_pcie_dev_t *dev)
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dev->power_on = false;
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dev->link_turned_off_counter++;
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/* assert reset on eps */
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if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_reset)
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dev->i2c_ctrl.client_i2c_reset(&dev->i2c_ctrl, true);
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PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n",
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dev->rc_idx);
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@ -5946,6 +6155,56 @@ static int msm_pcie_setup_drv(struct msm_pcie_dev_t *pcie_dev,
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return 0;
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}
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static int msm_pcie_i2c_ctrl_init(struct msm_pcie_dev_t *pcie_dev)
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{
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int ret, size;
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struct device_node *of_node, *i2c_client_node;
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struct device *dev = &pcie_dev->pdev->dev;
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struct pcie_i2c_ctrl *i2c_ctrl = &pcie_dev->i2c_ctrl;
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of_node = of_parse_phandle(dev->of_node, "pcie-i2c-phandle", 0);
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if (!of_node) {
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PCIE_DBG(pcie_dev, "PCIe: RC%d: No i2c phandle found\n",
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pcie_dev->rc_idx);
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return 0;
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}
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i2c_client_node = of_get_child_by_name(of_node, "pcie_i2c_ctrl");
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if (!i2c_client_node) {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d: No i2c slave node phandle found\n",
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pcie_dev->rc_idx);
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return 0;
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}
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of_property_read_u32(i2c_client_node, "gpio-config-reg",
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&i2c_ctrl->gpio_config_reg);
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of_property_read_u32(i2c_client_node, "ep-reset-reg",
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&i2c_ctrl->ep_reset_reg);
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of_property_read_u32(i2c_client_node, "ep-reset-gpio-mask",
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&i2c_ctrl->ep_reset_gpio_mask);
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of_get_property(i2c_client_node, "dump-regs", &size);
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if (size) {
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i2c_ctrl->dump_regs = devm_kzalloc(dev, size, GFP_KERNEL);
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if (!i2c_ctrl->dump_regs)
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return -ENOMEM;
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i2c_ctrl->dump_reg_count = size / sizeof(*i2c_ctrl->dump_regs);
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ret = of_property_read_u32_array(i2c_client_node, "dump-regs",
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i2c_ctrl->dump_regs,
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i2c_ctrl->dump_reg_count);
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if (ret)
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i2c_ctrl->dump_reg_count = 0;
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}
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return 0;
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}
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static int msm_pcie_probe(struct platform_device *pdev)
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{
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int ret = 0;
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@ -6258,6 +6517,8 @@ static int msm_pcie_probe(struct platform_device *pdev)
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pcie_dev->rc_idx, ret);
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}
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msm_pcie_i2c_ctrl_init(pcie_dev);
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msm_pcie_sysfs_init(pcie_dev);
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pcie_dev->drv_ready = true;
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@ -6979,6 +7240,72 @@ static void msm_pcie_drv_connect_worker(struct work_struct *work)
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msm_pcie_early_notifier, pcie_drv);
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}
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static const struct i2c_driver_data ntn3_data = {
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.rc_index = 0,
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.client_id = I2C_CLIENT_ID_NTN3,
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};
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static const struct of_device_id of_i2c_id_table[] = {
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{ .compatible = "qcom,pcie0-i2c-ntn3", .data = &ntn3_data },
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{ }
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};
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MODULE_DEVICE_TABLE(of, of_i2c_id_table);
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static int pcie_i2c_ctrl_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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int rc_index = -EINVAL;
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enum i2c_client_id client_id;
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struct pcie_i2c_ctrl *i2c_ctrl;
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const struct of_device_id *match;
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struct i2c_driver_data *data;
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if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
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dev_err(&client->dev, "I2C functionality not supported\n");
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return -EIO;
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}
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if (client->dev.of_node) {
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match = of_match_device(of_match_ptr(of_i2c_id_table),
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&client->dev);
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if (!match) {
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dev_err(&client->dev, "Error: No device match found\n");
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return -ENODEV;
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}
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data = (struct i2c_driver_data *)match->data;
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rc_index = data->rc_index;
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client_id = data->client_id;
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}
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if (rc_index >= MAX_RC_NUM) {
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dev_err(&client->dev, "invalid RC index %d\n", rc_index);
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return -EINVAL;
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}
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if (client_id == I2C_CLIENT_ID_NTN3) {
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i2c_ctrl = &msm_pcie_dev[rc_index].i2c_ctrl;
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i2c_ctrl->client = client;
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i2c_ctrl->client_i2c_read = ntn3_i2c_read;
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i2c_ctrl->client_i2c_write = ntn3_i2c_write;
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i2c_ctrl->client_i2c_reset = ntn3_ep_reset_ctrl;
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i2c_ctrl->client_i2c_dump_regs = ntn3_dump_regs;
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} else {
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dev_err(&client->dev, "invalid client id %d\n", client_id);
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}
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return 0;
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}
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static struct i2c_driver pcie_i2c_ctrl_driver = {
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.driver = {
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.name = "pcie-i2c-ctrl",
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.of_match_table = of_match_ptr(of_i2c_id_table),
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},
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.probe = pcie_i2c_ctrl_probe,
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};
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static int __init pcie_init(void)
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{
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int ret = 0, i;
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@ -7037,6 +7364,9 @@ static int __init pcie_init(void)
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msm_pcie_drv_enable_pc);
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}
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if (i2c_add_driver(&pcie_i2c_ctrl_driver))
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pr_info("Failed to add i2c ctrl driver: %d\n", ret);
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crc8_populate_msb(msm_pcie_crc8_table, MSM_PCIE_CRC8_POLYNOMIAL);
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msm_pcie_debugfs_init();
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@ -7071,6 +7401,8 @@ static void __exit pcie_exit(void)
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pr_info("PCIe: %s\n", __func__);
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||||
|
||||
i2c_del_driver(&pcie_i2c_ctrl_driver);
|
||||
|
||||
if (mpcie_wq)
|
||||
destroy_workqueue(mpcie_wq);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue