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ARM: dts: msm: update clock entries to support CPHY for Lahaina

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Add cphy specific clock entries for both the DSI
controller nodes.

Change-Id: I9694595cc079249ad2e4ed58d353f0cc8e3692e4
This commit is contained in:
Yuan Zhao 2020-04-19 15:41:26 +08:00 • committed by Gerrit - the friendly Code Review server
commit 64d66d8656
1 changed files with 16 additions and 4 deletions
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20
display/lahaina-sde-display.dtsi
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@ -132,10 +132,16 @@
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>;
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1";
"cphy_byte_clk0", "cphy_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@ -163,10 +169,16 @@
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
<&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
<&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>;
<&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
<&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
<&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1";
"cphy_byte_clk0", "cphy_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;