From fc08fb352abb9bc7a58b916325eca6375fc99cc9 Mon Sep 17 00:00:00 2001 From: "Pamidipati, Vijay" Date: Thu, 20 Jul 2017 02:43:33 +0530 Subject: [PATCH 1/2] qcacmn: Disable intrabss forwarding for NAWDS nodes IntraBSS forwarding creates a packet loop when NAWDS mode is enabled. Disable the feature for NAWDS Change-Id: I4d4f5616645b435e1e78c45f9347fa04c91e74ae CRs-Fixed: 2004658 --- dp/wifi3.0/dp_rx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/dp/wifi3.0/dp_rx.c b/dp/wifi3.0/dp_rx.c index 1fa4a3837e58..42b8877d61ad 100644 --- a/dp/wifi3.0/dp_rx.c +++ b/dp/wifi3.0/dp_rx.c @@ -1266,7 +1266,8 @@ done: nbuf); /* Intrabss-fwd */ - if (vdev->opmode != wlan_op_mode_sta) + if ((vdev->opmode != wlan_op_mode_sta) && + !vdev->nawds_enabled) if (dp_rx_intrabss_fwd(soc, peer, rx_tlv_hdr, From 776310a80e3ab901c7c1cf3904b921ee81ae78f4 Mon Sep 17 00:00:00 2001 From: "Pamidipati, Vijay" Date: Fri, 21 Jul 2017 20:37:14 +0530 Subject: [PATCH 2/2] qcacmn: Fix the page mask used for Tx Descriptor Increase the number of bits allocated for page mask to accomodate upto 16K descriptors needed in Tx path Change-Id: I9a1a2757be353c3bd9f78773b87cca7c86041b9c CRs-Fixed: 2004658 --- dp/wifi3.0/dp_tx_desc.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/dp/wifi3.0/dp_tx_desc.h b/dp/wifi3.0/dp_tx_desc.h index ad94bc5e5172..9cbe6ad3b0ab 100644 --- a/dp/wifi3.0/dp_tx_desc.h +++ b/dp/wifi3.0/dp_tx_desc.h @@ -25,16 +25,16 @@ /** * 21 bits cookie - * 3 bits ring id 0 ~ 7, mask 0x1C0000, offset 18 - * 8 bits page id 0 ~ 255, mask 0x03C800, offset 10 - * 10 bits offset id 0 ~ 1023 mask 0x0003FF, offset 0 + * 3 bits ring id 0 ~ 7, + * 8 bits page id 0 ~ 512 + * 5 bits offset id 0 ~ 31 (Desc size = 128, Num descs per page = 4096/128 = 32) */ /* ???Ring ID needed??? */ -#define DP_TX_DESC_ID_POOL_MASK 0x1C0000 -#define DP_TX_DESC_ID_POOL_OS 18 -#define DP_TX_DESC_ID_PAGE_MASK 0x03FC00 -#define DP_TX_DESC_ID_PAGE_OS 10 -#define DP_TX_DESC_ID_OFFSET_MASK 0x0003FF +#define DP_TX_DESC_ID_POOL_MASK 0x01C000 +#define DP_TX_DESC_ID_POOL_OS 14 +#define DP_TX_DESC_ID_PAGE_MASK 0x003FE0 +#define DP_TX_DESC_ID_PAGE_OS 5 +#define DP_TX_DESC_ID_OFFSET_MASK 0x00001F #define DP_TX_DESC_ID_OFFSET_OS 0 #ifdef QCA_LL_TX_FLOW_CONTROL_V2