From 658ad44fed55fd45ef4ef060830e9e36821df02e Mon Sep 17 00:00:00 2001
From: Dhaval Patel <pdhaval@quicinc.com>
Date: Wed, 17 Jun 2020 15:48:15 -0700
Subject: [PATCH] ARM: dts: msm: add clk status register for lahaina target

Add sspp and wb2 clock active status register and
bit offset index for lahaina target. This is required
to check hw blocks' idle vs busy status.

Change-Id: I0834a267e8c4f007a92da0852e33b1e0e02de226
---
 bindings/sde.txt         | 12 ++++++++++--
 display/lahaina-sde.dtsi |  4 ++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/bindings/sde.txt b/bindings/sde.txt
index a29dc87f2b61..93e968a01ab9 100644
--- a/bindings/sde.txt
+++ b/bindings/sde.txt
@@ -178,10 +178,10 @@ Optional properties:
 				match the number of offsets defined in
 				property: qcom,sde-sspp-off
 - qcom,sde-sspp-clk-status:	Array of offsets describing clk status
-				offsets for dynamic clock gating. 1st value
+				offsets for clock active state. 1st value
 				in the array represents offset of the status
 				register. 2nd value represents bit offset within
-				control register. Number of offsets defined should
+				status register. Number of offsets defined should
 				match the number of offsets defined in
 				property: qcom,sde-sspp-off.
 - qcom,sde-sspp-excl-rect:	Array of u32 values indicating exclusion rectangle
@@ -359,6 +359,13 @@ Optional properties:
 				control register. Number of offsets defined should
 				match the number of offsets defined in
 				property: qcom,sde-wb-off
+- qcom,sde-wb-clk-status:	Array of 2 cell property describing clk status
+				offsets for clock active state. 1st value
+				in the array represents offset of the status
+				register. 2nd value represents bit offset within
+				status register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-wb-off
 - qcom,sde-reg-dma-off:         Array of u32 offset addresses of the dma hardware blocks,
 				relative to "regdma_phys" defined in reg property.
 - qcom,sde-reg-dma-id:		Array of u32 DMA block type ids corresponding to the
@@ -724,6 +731,7 @@ Example:
 
     qcom,sde-wb-id = <2>;
     qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+    qcom,sde-wb-clk-status = <0x3bc 20>;
 
     qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
 		0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi
index 90de1c6c2365..e7d0bc65d019 100644
--- a/display/lahaina-sde.dtsi
+++ b/display/lahaina-sde.dtsi
@@ -79,6 +79,7 @@
 		qcom,sde-wb-xin-id = <6>;
 		qcom,sde-wb-id = <2>;
 		qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+		qcom,sde-wb-clk-status = <0x3bc 20>;
 
 		qcom,sde-intf-off = <0x35000 0x36000
 					0x37000 0x38000>;
@@ -155,6 +156,9 @@
 		qcom,sde-sspp-clk-ctrl =
 				<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
 				 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
+		qcom,sde-sspp-clk-status =
+				<0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>,
+				 <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>;
 		qcom,sde-sspp-csc-off = <0x1a00>;
 		qcom,sde-csc-type = "csc-10bit";
 		qcom,sde-qseed-sw-lib-rev = "qseedv3lite";