From 65b8a22ac0bb71d3d0c673da8e2e9e70d8d78b59 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 13 Feb 2019 12:00:11 -0700 Subject: [PATCH] dt-bindings: pdc: Add SPI config register In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface. Change-Id: I89ba52ded2451071973b81c83a53964d7ec2e486 --- bindings/interrupt-controller/qcom,pdc.txt | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/bindings/interrupt-controller/qcom,pdc.txt b/bindings/interrupt-controller/qcom,pdc.txt index 8e0797cb1487..ee7c295b6c51 100644 --- a/bindings/interrupt-controller/qcom,pdc.txt +++ b/bindings/interrupt-controller/qcom,pdc.txt @@ -23,7 +23,8 @@ Properties: - reg: Usage: required Value type: - Definition: Specifies the base physical address for PDC hardware. + Definition: Specifies the base physical address for PDC hardware and + the interrupt type configuration register. - interrupt-cells: Usage: required @@ -50,15 +51,22 @@ Properties: The second element is the GIC hwirq number for the PDC port. The third element is the number of interrupts in sequence. +- qcom,scm-spi-cfg: + Usage: optional + Value type: + Definition: Specifies if the SPI configuration registers have to be + written from the firmware. + Example: pdc: interrupt-controller@b220000 { compatible = "qcom,sdm845-pdc"; - reg = <0xb220000 0x30000>; + reg = <0xb220000 0x30000>, <0x179900f0 0x60>; qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; + qcom,scm-spi-cfg; }; DT binding of a device that wants to use the GIC SPI 514 as a wakeup