From a309519fe0c353594fa7f90784b8090343e710ec Mon Sep 17 00:00:00 2001
From: Lijuan Gao <lijuang@qti.qualcomm.com>
Date: Thu, 4 Feb 2021 18:08:42 +0800
Subject: [PATCH] ARM: dts: msm: Add irq type for uart, watchdog and pinctrl
 for sdxnightjar

Add irq type for uart, watchdog and pinctrl to avoid excessive warning
log for sdxnightjar.

Change-Id: I3fa817c2f334da5939b1976fedbb5208f58a88de
---
 qcom/sdxnightjar-pinctrl.dtsi | 2 +-
 qcom/sdxnightjar.dtsi         | 9 +++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/qcom/sdxnightjar-pinctrl.dtsi b/qcom/sdxnightjar-pinctrl.dtsi
index f5a916ea293e..53260f855864 100644
--- a/qcom/sdxnightjar-pinctrl.dtsi
+++ b/qcom/sdxnightjar-pinctrl.dtsi
@@ -4,7 +4,7 @@
 	tlmm_pinmux: pinctrl@1000000 {
 		compatible = "qcom,sdxnightjar-pinctrl";
 		reg = <0x1000000 0x300000>;
-		interrupts = <0 208 0>;
+		interrupts = <0 208 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		interrupt-controller;
diff --git a/qcom/sdxnightjar.dtsi b/qcom/sdxnightjar.dtsi
index 00ea3f6a2f57..676c8a2c807f 100644
--- a/qcom/sdxnightjar.dtsi
+++ b/qcom/sdxnightjar.dtsi
@@ -584,7 +584,7 @@
 	blsp1_uart1: serial@78af000 {
 		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 		reg = <0x78af000 0x200>;
-		interrupts = <0 107 0>;
+		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 			 <&gcc  GCC_BLSP1_AHB_CLK>;
 		clock-names = "core", "iface";
@@ -594,7 +594,7 @@
 	blsp1_uart2: serial@78b0000 {
 		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 		reg = <0x78b0000 0x200>;
-		interrupts = <0 108 0>;
+		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&gcc  GCC_BLSP1_UART2_APPS_CLK>,
 			 <&gcc  GCC_BLSP1_AHB_CLK>;
 		clock-names = "core", "iface";
@@ -604,7 +604,7 @@
 	blsp1_uart3: serial@78b1000 {
 		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 		reg = <0x78b1000 0x200>;
-		interrupts = <0 109 0>;
+		interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&gcc  GCC_BLSP1_UART3_APPS_CLK>,
 			 <&gcc  GCC_BLSP1_AHB_CLK>;
 		clock-names = "core", "iface";
@@ -622,7 +622,8 @@
 		compatible = "qcom,msm-watchdog";
 		reg = <0xb017000 0x1000>;
 		reg-names = "wdt-base";
-		interrupts = <1 3 0>, <1 2 0>;
+		interrupts = <1 3 IRQ_TYPE_EDGE_RISING>,
+			<1 2 IRQ_TYPE_EDGE_RISING>;
 		qcom,bark-time = <11000>;
 		qcom,pet-time = <10000>;
 	};