mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-15 01:01:56 -04:00
Merge "clk: qcom: lahaina: Add runtime_pm support"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
65d212e2e0
9 changed files with 245 additions and 106 deletions
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@ -10,6 +10,7 @@
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/clock/qcom,camcc-lahaina.h>
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@ -1931,24 +1932,6 @@ static struct clk_branch cam_cc_csiphy5_clk = {
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},
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};
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static struct clk_branch cam_cc_gdsc_clk = {
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.halt_reg = 0xc148,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0xc148,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_gdsc_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &cam_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_cc_icp_ahb_clk = {
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.halt_reg = 0xc094,
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.halt_check = BRANCH_HALT,
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@ -2866,7 +2849,6 @@ static struct clk_regmap *cam_cc_lahaina_clocks[] = {
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[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
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[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
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[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
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[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
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[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
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[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
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[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
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@ -2972,7 +2954,7 @@ static const struct regmap_config cam_cc_lahaina_regmap_config = {
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.fast_io = true,
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};
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static const struct qcom_cc_desc cam_cc_lahaina_desc = {
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static struct qcom_cc_desc cam_cc_lahaina_desc = {
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.config = &cam_cc_lahaina_regmap_config,
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.clks = cam_cc_lahaina_clocks,
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.num_clks = ARRAY_SIZE(cam_cc_lahaina_clocks),
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@ -3014,23 +2996,22 @@ static int cam_cc_lahaina_fixup(struct platform_device *pdev,
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static int cam_cc_lahaina_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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struct clk *clk;
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int ret;
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clk = devm_clk_get(&pdev->dev, "cfg_ahb_clk");
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
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return PTR_ERR(clk);
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}
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devm_clk_put(&pdev->dev, clk);
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regmap = qcom_cc_map(pdev, &cam_cc_lahaina_desc);
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if (IS_ERR(regmap)) {
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dev_err(&pdev->dev, "Failed to map cam CC registers\n");
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return PTR_ERR(regmap);
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}
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ret = qcom_cc_runtime_init(pdev, &cam_cc_lahaina_desc);
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if (ret)
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return ret;
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ret = pm_runtime_get_sync(&pdev->dev);
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if (ret)
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return ret;
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clk_lucid_5lpe_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
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clk_lucid_5lpe_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
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clk_zonda_5lpe_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
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@ -3043,12 +3024,19 @@ static int cam_cc_lahaina_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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/*
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* Keep clocks always enabled:
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* cam_cc_gdsc_clk
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*/
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regmap_update_bits(regmap, 0xc148, BIT(0), BIT(0));
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ret = qcom_cc_really_probe(pdev, &cam_cc_lahaina_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
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return ret;
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}
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pm_runtime_put_sync(&pdev->dev);
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dev_info(&pdev->dev, "Registered CAM CC clocks\n");
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return ret;
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@ -3059,12 +3047,17 @@ static void cam_cc_lahaina_sync_state(struct device *dev)
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qcom_cc_sync_state(dev, &cam_cc_lahaina_desc);
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}
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static const struct dev_pm_ops cam_cc_lahaina_pm_ops = {
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SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
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};
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static struct platform_driver cam_cc_lahaina_driver = {
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.probe = cam_cc_lahaina_probe,
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.driver = {
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.name = "lahaina-cam_cc",
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.of_match_table = cam_cc_lahaina_match_table,
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.sync_state = cam_cc_lahaina_sync_state,
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.pm = &cam_cc_lahaina_pm_ops,
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},
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};
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@ -266,12 +266,22 @@ static u32 get_mux_divs(struct clk_hw *mux)
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static int clk_debug_measure_get(void *data, u64 *val)
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{
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struct clk_regmap *rclk = NULL;
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struct clk_debug_mux *mux;
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struct clk_hw *hw = data;
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struct clk_hw *parent;
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int ret = 0;
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u32 regval;
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if (clk_is_regmap_clk(hw))
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rclk = to_clk_regmap(hw);
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if (rclk) {
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ret = clk_runtime_get_regmap(rclk);
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if (ret)
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return ret;
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}
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mutex_lock(&clk_debug_lock);
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ret = clk_find_and_set_parent(measure, hw);
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@ -306,6 +316,8 @@ static int clk_debug_measure_get(void *data, u64 *val)
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}
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exit:
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mutex_unlock(&clk_debug_lock);
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if (rclk)
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clk_runtime_put_regmap(rclk);
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return ret;
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}
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@ -501,8 +513,14 @@ static void clk_debug_print_hw(struct clk_hw *hw, struct seq_file *f)
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if (clk_is_regmap_clk(hw)) {
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rclk = to_clk_regmap(hw);
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if (clk_runtime_get_regmap(rclk))
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return;
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if (rclk->ops && rclk->ops->list_registers)
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rclk->ops->list_registers(f, hw);
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clk_runtime_put_regmap(rclk);
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}
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}
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@ -7,6 +7,7 @@
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/export.h>
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#include <linux/pm_runtime.h>
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#include "clk-regmap.h"
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@ -270,6 +271,8 @@ int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk)
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{
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int ret;
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rclk->dev = dev;
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if (dev && dev_get_regmap(dev, NULL))
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rclk->regmap = dev_get_regmap(dev, NULL);
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else if (dev && dev->parent)
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@ -282,3 +285,24 @@ int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk)
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return ret;
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}
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EXPORT_SYMBOL_GPL(devm_clk_register_regmap);
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int clk_runtime_get_regmap(struct clk_regmap *rclk)
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{
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int ret;
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if (pm_runtime_enabled(rclk->dev)) {
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ret = pm_runtime_get_sync(rclk->dev);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(clk_runtime_get_regmap);
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void clk_runtime_put_regmap(struct clk_regmap *rclk)
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{
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if (pm_runtime_enabled(rclk->dev))
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pm_runtime_put_sync(rclk->dev);
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}
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EXPORT_SYMBOL(clk_runtime_put_regmap);
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@ -50,6 +50,7 @@ struct clk_regmap {
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struct clk_vdd_class_data vdd_data;
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struct clk_regmap_ops *ops;
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struct list_head list_node;
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struct device *dev;
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};
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#define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw)
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@ -71,4 +72,7 @@ struct clk_register_data {
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u32 offset;
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};
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int clk_runtime_get_regmap(struct clk_regmap *rclk);
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void clk_runtime_put_regmap(struct clk_regmap *rclk);
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#endif
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@ -12,6 +12,10 @@
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#include <linux/reset-controller.h>
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#include <linux/of.h>
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#include <linux/clk/qcom.h>
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#include <linux/clk.h>
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#include <linux/interconnect.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include "common.h"
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#include "clk-opp.h"
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@ -394,4 +398,123 @@ int qcom_clk_get_voltage(struct clk *clk, unsigned long rate)
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}
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EXPORT_SYMBOL(qcom_clk_get_voltage);
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int qcom_cc_runtime_init(struct platform_device *pdev,
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struct qcom_cc_desc *desc)
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{
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struct device *dev = &pdev->dev;
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struct clk *clk;
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int ret;
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clk = clk_get_optional(dev, "iface");
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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dev_err(dev, "unable to get iface clock\n");
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return PTR_ERR(clk);
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}
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clk_put(clk);
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ret = clk_regulator_init(dev, desc);
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if (ret)
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return ret;
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desc->path = of_icc_get(dev, NULL);
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if (IS_ERR(desc->path)) {
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if (PTR_ERR(desc->path) != -EPROBE_DEFER)
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dev_err(dev, "error getting path\n");
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return PTR_ERR(desc->path);
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}
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platform_set_drvdata(pdev, desc);
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pm_runtime_enable(dev);
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ret = pm_clk_create(dev);
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if (ret)
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goto disable_pm_runtime;
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ret = pm_clk_add(dev, "iface");
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if (ret < 0) {
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dev_err(dev, "failed to acquire iface clock\n");
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goto destroy_pm_clk;
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}
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return 0;
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destroy_pm_clk:
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pm_clk_destroy(dev);
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disable_pm_runtime:
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pm_runtime_disable(dev);
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icc_put(desc->path);
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return ret;
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}
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EXPORT_SYMBOL(qcom_cc_runtime_init);
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int qcom_cc_runtime_resume(struct device *dev)
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{
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struct qcom_cc_desc *desc = dev_get_drvdata(dev);
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struct clk_vdd_class_data vdd_data = {0};
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int ret;
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int i;
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for (i = 0; i < desc->num_clk_regulators; i++) {
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vdd_data.vdd_class = desc->clk_regulators[i];
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if (!vdd_data.vdd_class)
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continue;
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ret = clk_vote_vdd_level(&vdd_data, 1);
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if (ret) {
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dev_warn(dev, "%s: failed to vote voltage\n", __func__);
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return ret;
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}
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}
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if (desc->path) {
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ret = icc_set_bw(desc->path, 0, 1);
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if (ret) {
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dev_warn(dev, "%s: failed to vote bw\n", __func__);
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return ret;
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}
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}
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ret = pm_clk_resume(dev);
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if (ret)
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dev_warn(dev, "%s: failed to enable clocks\n", __func__);
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return ret;
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}
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EXPORT_SYMBOL(qcom_cc_runtime_resume);
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int qcom_cc_runtime_suspend(struct device *dev)
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{
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struct qcom_cc_desc *desc = dev_get_drvdata(dev);
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struct clk_vdd_class_data vdd_data = {0};
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int ret;
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int i;
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ret = pm_clk_suspend(dev);
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if (ret)
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dev_warn(dev, "%s: failed to disable clocks\n", __func__);
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if (desc->path) {
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ret = icc_set_bw(desc->path, 0, 0);
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if (ret)
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dev_warn(dev, "%s: failed to unvote bw\n", __func__);
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}
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for (i = 0; i < desc->num_clk_regulators; i++) {
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vdd_data.vdd_class = desc->clk_regulators[i];
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if (!vdd_data.vdd_class)
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continue;
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ret = clk_unvote_vdd_level(&vdd_data, 1);
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if (ret)
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dev_warn(dev, "%s: failed to unvote voltage\n",
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__func__);
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}
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return 0;
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}
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EXPORT_SYMBOL(qcom_cc_runtime_suspend);
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MODULE_LICENSE("GPL v2");
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|
|
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@ -33,6 +33,7 @@ struct qcom_cc_desc {
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size_t num_clk_hws;
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struct clk_vdd_class **clk_regulators;
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size_t num_clk_regulators;
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struct icc_path *path;
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};
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/**
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@ -77,4 +78,10 @@ extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
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const struct qcom_cc_desc *desc);
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extern const struct clk_ops clk_dummy_ops;
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void qcom_cc_sync_state(struct device *dev, const struct qcom_cc_desc *desc);
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|
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int qcom_cc_runtime_init(struct platform_device *pdev,
|
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struct qcom_cc_desc *desc);
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int qcom_cc_runtime_suspend(struct device *dev);
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int qcom_cc_runtime_resume(struct device *dev);
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#endif
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|
|
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|
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@ -10,6 +10,7 @@
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#include <linux/of_device.h>
|
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#include <linux/of.h>
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#include <linux/regmap.h>
|
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#include <linux/pm_runtime.h>
|
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|
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#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
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|
|
@ -1422,24 +1423,6 @@ static struct clk_branch disp_cc_sleep_clk = {
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},
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};
|
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|
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static struct clk_branch disp_cc_xo_clk = {
|
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.halt_reg = 0x605c,
|
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.halt_check = BRANCH_HALT,
|
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.clkr = {
|
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.enable_reg = 0x605c,
|
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.enable_mask = BIT(0),
|
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.hw.init = &(struct clk_init_data){
|
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.name = "disp_cc_xo_clk",
|
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.parent_data = &(const struct clk_parent_data){
|
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.hw = &disp_cc_xo_clk_src.clkr.hw,
|
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},
|
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.num_parents = 1,
|
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
|
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.ops = &clk_branch2_ops,
|
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},
|
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},
|
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};
|
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|
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static struct clk_regmap *disp_cc_lahaina_clocks[] = {
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[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
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[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
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|
|
@ -1502,7 +1485,6 @@ static struct clk_regmap *disp_cc_lahaina_clocks[] = {
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[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
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[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
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[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
|
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[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
|
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[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
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};
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|
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|
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@ -1519,7 +1501,7 @@ static const struct regmap_config disp_cc_lahaina_regmap_config = {
|
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.fast_io = true,
|
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};
|
||||
|
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static const struct qcom_cc_desc disp_cc_lahaina_desc = {
|
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static struct qcom_cc_desc disp_cc_lahaina_desc = {
|
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.config = &disp_cc_lahaina_regmap_config,
|
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.clks = disp_cc_lahaina_clocks,
|
||||
.num_clks = ARRAY_SIZE(disp_cc_lahaina_clocks),
|
||||
|
|
@ -1538,20 +1520,19 @@ MODULE_DEVICE_TABLE(of, disp_cc_lahaina_match_table);
|
|||
static int disp_cc_lahaina_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &disp_cc_lahaina_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, "cfg_ahb_clk");
|
||||
if (IS_ERR(clk)) {
|
||||
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
devm_clk_put(&pdev->dev, clk);
|
||||
ret = qcom_cc_runtime_init(pdev, &disp_cc_lahaina_desc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap,
|
||||
&disp_cc_pll0_config);
|
||||
|
|
@ -1561,12 +1542,19 @@ static int disp_cc_lahaina_probe(struct platform_device *pdev)
|
|||
/* Enable clock gating for MDP clocks */
|
||||
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* disp_cc_xo_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &disp_cc_lahaina_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
dev_info(&pdev->dev, "Registered DISP CC clocks\n");
|
||||
|
||||
return ret;
|
||||
|
|
@ -1577,12 +1565,17 @@ static void disp_cc_lahaina_sync_state(struct device *dev)
|
|||
qcom_cc_sync_state(dev, &disp_cc_lahaina_desc);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops disp_cc_lahaina_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver disp_cc_lahaina_driver = {
|
||||
.probe = disp_cc_lahaina_probe,
|
||||
.driver = {
|
||||
.name = "disp_cc-lahaina",
|
||||
.of_match_table = disp_cc_lahaina_match_table,
|
||||
.sync_state = disp_cc_lahaina_sync_state,
|
||||
.pm = &disp_cc_lahaina_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -197,6 +197,9 @@ int clk_regulator_init(struct device *dev, const struct qcom_cc_desc *desc)
|
|||
vdd_class = desc->clk_regulators[i];
|
||||
|
||||
for (cnt = 0; cnt < vdd_class->num_regulators; cnt++) {
|
||||
if (vdd_class->regulator[cnt])
|
||||
continue;
|
||||
|
||||
name = vdd_class->regulator_names[cnt];
|
||||
regulator = devm_regulator_get(dev, name);
|
||||
if (IS_ERR(regulator)) {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,videocc-lahaina.h>
|
||||
|
||||
|
|
@ -361,26 +362,6 @@ static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_ahb_clk = {
|
||||
.halt_reg = 0xe58,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.hwcg_reg = 0xe58,
|
||||
.hwcg_bit = 1,
|
||||
.clkr = {
|
||||
.enable_reg = 0xe58,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &video_cc_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_mvs0_clk = {
|
||||
.halt_reg = 0xd34,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
|
|
@ -495,26 +476,7 @@ static struct clk_branch video_cc_sleep_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch video_cc_xo_clk = {
|
||||
.halt_reg = 0xeec,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0xeec,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_xo_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &video_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_lahaina_clocks[] = {
|
||||
[VIDEO_CC_AHB_CLK] = &video_cc_ahb_clk.clkr,
|
||||
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
||||
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
||||
|
|
@ -531,7 +493,6 @@ static struct clk_regmap *video_cc_lahaina_clocks[] = {
|
|||
&video_cc_mvs1c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
|
||||
[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
|
||||
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
|
||||
[VIDEO_PLL0] = &video_pll0.clkr,
|
||||
[VIDEO_PLL1] = &video_pll1.clkr,
|
||||
|
|
@ -555,7 +516,7 @@ static const struct regmap_config video_cc_lahaina_regmap_config = {
|
|||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc video_cc_lahaina_desc = {
|
||||
static struct qcom_cc_desc video_cc_lahaina_desc = {
|
||||
.config = &video_cc_lahaina_regmap_config,
|
||||
.clks = video_cc_lahaina_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_lahaina_clocks),
|
||||
|
|
@ -574,30 +535,38 @@ MODULE_DEVICE_TABLE(of, video_cc_lahaina_match_table);
|
|||
static int video_cc_lahaina_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
regmap = qcom_cc_map(pdev, &video_cc_lahaina_desc);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, "cfg_ahb_clk");
|
||||
if (IS_ERR(clk)) {
|
||||
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
devm_clk_put(&pdev->dev, clk);
|
||||
ret = qcom_cc_runtime_init(pdev, &video_cc_lahaina_desc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config);
|
||||
clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config);
|
||||
|
||||
/*
|
||||
* Keep clocks always enabled:
|
||||
* video_cc_ahb_clk
|
||||
* video_cc_xo_clk
|
||||
*/
|
||||
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
|
||||
regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
|
||||
|
||||
ret = qcom_cc_really_probe(pdev, &video_cc_lahaina_desc, regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
|
||||
|
||||
return ret;
|
||||
|
|
@ -608,12 +577,17 @@ static void video_cc_lahaina_sync_state(struct device *dev)
|
|||
qcom_cc_sync_state(dev, &video_cc_lahaina_desc);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops video_cc_lahaina_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver video_cc_lahaina_driver = {
|
||||
.probe = video_cc_lahaina_probe,
|
||||
.driver = {
|
||||
.name = "video_cc-lahaina",
|
||||
.of_match_table = video_cc_lahaina_match_table,
|
||||
.sync_state = video_cc_lahaina_sync_state,
|
||||
.pm = &video_cc_lahaina_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue