From 00841dbe6db1fa35cdd6cb8f38e52458346e39ca Mon Sep 17 00:00:00 2001
From: Ram Chandrasekar <rkumbako@quicinc.com>
Date: Tue, 8 Sep 2020 15:39:49 -0700
Subject: [PATCH 1/2] ARM: dts: msm: Add CX SDPM configuration for lahaina

Add CX SDPM configuration to monitor Camera, CPU and other misc clocks
for lahaina.

Change-Id: I936d4ecc6af78a30abad97e402fe6c1e6c0fcf5d
---
 qcom/lahaina-thermal.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi
index 561b0db16801..ea3307042725 100644
--- a/qcom/lahaina-thermal.dtsi
+++ b/qcom/lahaina-thermal.dtsi
@@ -30,6 +30,17 @@
 		csr-id = <1 3 5>;
 	};
 
+	cx_sdpm@0x00634000 {
+		compatible = "qcom,sdpm";
+		reg = <0x00634000 0x1000>;
+		clock-names = "cam_cc_csi0phytiimer", "ufs_phy";
+		clocks = <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+			<&clock_gcc GCC_UFS_PHY_AXI_CLK_SRC>;
+		cam_cc_csi0phytiimer-supply = <&cam_cc_ipe_0_gdsc>;
+		cpu = <&CPU7>;
+		csr-id = <5 7 4>;
+	};
+
 	mx_pe: mx_rdpm_pe@0x00637000 {
 		compatible = "qcom,policy-engine";
 		#thermal-sensor-cells = <0>;

From a100f21bab63c2851136898f596a519f5184536e Mon Sep 17 00:00:00 2001
From: Ram Chandrasekar <rkumbako@quicinc.com>
Date: Tue, 8 Sep 2020 15:42:11 -0700
Subject: [PATCH 2/2] ARM: dts: msm: Configure Policy engine for CX rail in
 lahaina

Enable policy engine sensor driver for CX rail policy engine
hardware for lahaina. policy engine will recommend mitigation for all
CX clients based on operating level.

Change-Id: I3896c78a6cdd80b0511719d8707b42ac5478eb4c
---
 qcom/lahaina-thermal.dtsi | 61 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi
index ea3307042725..58f5763c1df1 100644
--- a/qcom/lahaina-thermal.dtsi
+++ b/qcom/lahaina-thermal.dtsi
@@ -47,6 +47,13 @@
 		reg = <0x00637000 0x1000>;
 		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	cx_pe: cx_rdpm_pe@0x00635000 {
+		compatible = "qcom,policy-engine";
+		#thermal-sensor-cells = <0>;
+		reg = <0x00635000 0x1000>;
+		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+	};
 };
 
 &cpufreq_hw {
@@ -1183,5 +1190,59 @@
 			};
 		};
 	};
+
+	cx-pe-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&cx_pe>;
+		thermal-governor = "step_wise";
+		trips {
+			cx_pe_config1: cx-pe-config1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+
+			cx_pe_config2: cx-pe-config2 {
+				temperature = <2>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+
+			cx_pe_config3: cx-pe-config3 {
+				temperature = <3>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+
+			cx_pe_config4: cx-pe-config4 {
+				temperature = <5>;
+				hysteresis = <2>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cx_pe_cdev_1 {
+				trip = <&cx_pe_config1>;
+				cooling-device = <&cdsp_sw 1 1>;
+			};
+
+			cx_pe_cdev_2 {
+				trip = <&cx_pe_config2>;
+				cooling-device = <&cdsp_sw 2 2>;
+			};
+
+			cx_pe_cdev_3 {
+				trip = <&cx_pe_config3>;
+				cooling-device = <&cdsp_sw 3 3>;
+			};
+
+			cx_pe_cdev_4 {
+				trip = <&cx_pe_config4>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+		};
+	};
 };