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msm: kgsl: Clean up adreno_spin_idle_debug

Browse source 
Make the debug function target specific since
it was anyways used in only two places and it also
simplifies a bunch of indirect register reads
we had to do because of ADRENO_REG enum.

Change-Id: I20fcd91339639d999d475dae60f95a357721b71d
Signed-off-by: Urvashi Agrawal <urvaagra@codeaurora.org>
This commit is contained in:
Urvashi Agrawal 2020-08-12 16:11:09 -07:00
commit 65dc7023e6
4 changed files with 92 additions and 67 deletions
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50
drivers/gpu/msm/adreno.c
View file

@ -1788,28 +1788,6 @@ static bool regulators_left_on(struct kgsl_device *device)
return false;
}
int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb)
{
unsigned int *cmds;
int ret;
cmds = adreno_ringbuffer_allocspace(rb, 2);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
if (cmds == NULL)
return -ENOSPC;
cmds += cp_secure_mode(adreno_dev, cmds, 0);
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
"Switch to unsecure failed to idle\n");
return ret;
}
void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)
{
int i;
@ -2787,34 +2765,6 @@ static bool adreno_isidle(struct adreno_device *adreno_dev)
return gpudev->hw_isidle(adreno_dev);
}
/* Print some key registers if a spin-for-idle times out */
void adreno_spin_idle_debug(struct adreno_device *adreno_dev,
const char *str)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int rptr, wptr;
unsigned int status, status3, intstatus;
unsigned int hwfault;
dev_err(device->dev, str);
adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &rptr);
adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr);
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS, &status);
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS3, &status3);
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &intstatus);
adreno_readreg(adreno_dev, ADRENO_REG_CP_HW_FAULT, &hwfault);
dev_err(device->dev,
"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",
adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);
dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
kgsl_device_snapshot(device, NULL, false);
}
/**
* adreno_spin_idle() - Spin wait for the GPU to idle
* @adreno_dev: Pointer to an adreno device

2
drivers/gpu/msm/adreno.h
View file

@ -658,7 +658,6 @@ enum adreno_regs {
ADRENO_REG_CP_ROQ_DATA,
ADRENO_REG_CP_MEQ_ADDR,
ADRENO_REG_CP_MEQ_DATA,
ADRENO_REG_CP_HW_FAULT,
ADRENO_REG_CP_PROTECT_STATUS,
ADRENO_REG_CP_PREEMPT,
ADRENO_REG_CP_PREEMPT_DEBUG,
@ -923,7 +922,6 @@ long adreno_ioctl_helper(struct kgsl_device_private *dev_priv,
int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb);
void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str);
int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);
int adreno_idle(struct kgsl_device *device);

56
drivers/gpu/msm/adreno_a5xx.c
View file

@ -629,6 +629,34 @@ err:
return ret;
}
static void a5xx_spin_idle_debug(struct adreno_device *adreno_dev,
const char *str)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int rptr, wptr;
unsigned int status, status3, intstatus;
unsigned int hwfault;
dev_err(device->dev, str);
kgsl_regread(device, A5XX_CP_RB_RPTR, &rptr);
kgsl_regread(device, A5XX_CP_RB_WPTR, &wptr);
kgsl_regread(device, A5XX_RBBM_STATUS, &status);
kgsl_regread(device, A5XX_RBBM_STATUS3, &status3);
kgsl_regread(device, A5XX_RBBM_INT_0_STATUS, &intstatus);
kgsl_regread(device, A5XX_CP_HW_FAULT, &hwfault);
dev_err(device->dev,
"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",
adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);
dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
kgsl_device_snapshot(device, NULL, false);
}
static int _gpmu_send_init_cmds(struct adreno_device *adreno_dev)
{
struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
@ -650,7 +678,7 @@ static int _gpmu_send_init_cmds(struct adreno_device *adreno_dev)
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret != 0)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"gpmu initialization failed to idle\n");
return ret;
@ -1628,7 +1656,7 @@ static int a5xx_post_start(struct adreno_device *adreno_dev)
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"hw initialization failed to idle\n");
return ret;
@ -1767,7 +1795,7 @@ static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,
ret = adreno_ringbuffer_submit_spin(rb, NULL, 20);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"Critical packet submission failed to idle\n");
return ret;
@ -1843,7 +1871,7 @@ static int a5xx_send_me_init(struct adreno_device *adreno_dev,
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a5xx_spin_idle_debug(adreno_dev,
"CP initialization failed to idle\n");
return ret;
@ -1858,6 +1886,7 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev)
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_ringbuffer *rb;
uint64_t addr;
unsigned int *cmds;
int ret, i;
/* Clear all the ringbuffers */
@ -1918,11 +1947,21 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev)
*/
if (!adreno_dev->zap_loaded)
kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0);
else
ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);
else {
cmds = adreno_ringbuffer_allocspace(rb, 2);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
if (ret)
return ret;
*cmds++ = cp_packet(adreno_dev, CP_SET_SECURE_MODE, 1);
*cmds++ = 0;
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret) {
a5xx_spin_idle_debug(adreno_dev,
"Switch to unsecure failed to idle\n");
return ret;
}
}
ret = a5xx_gpmu_init(adreno_dev);
if (ret)
@ -2395,7 +2434,6 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A5XX_CP_MEQ_DBG_ADDR),
ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A5XX_CP_MEQ_DBG_DATA),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_REG_0, A5XX_CP_PROTECT_REG_0),
ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A5XX_CP_HW_FAULT),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT, A5XX_CP_CONTEXT_SWITCH_CNTL),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_DEBUG, ADRENO_REG_SKIP),
ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_DISABLE, ADRENO_REG_SKIP),

49
drivers/gpu/msm/adreno_a6xx.c
View file

@ -778,6 +778,35 @@ static int a6xx_get_cp_init_cmds(struct adreno_device *adreno_dev)
return 0;
}
static void a6xx_spin_idle_debug(struct adreno_device *adreno_dev,
const char *str)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int rptr, wptr;
unsigned int status, status3, intstatus;
unsigned int hwfault;
dev_err(device->dev, str);
kgsl_regread(device, A6XX_CP_RB_RPTR, &rptr);
kgsl_regread(device, A6XX_CP_RB_WPTR, &wptr);
kgsl_regread(device, A6XX_RBBM_STATUS, &status);
kgsl_regread(device, A6XX_RBBM_STATUS3, &status3);
kgsl_regread(device, A6XX_RBBM_INT_0_STATUS, &intstatus);
kgsl_regread(device, A6XX_CP_HW_FAULT, &hwfault);
dev_err(device->dev,
"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",
adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);
dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
kgsl_device_snapshot(device, NULL, false);
}
/*
* a6xx_send_cp_init() - Initialize ringbuffer
* @adreno_dev: Pointer to adreno device
@ -800,7 +829,7 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev,
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret) {
adreno_spin_idle_debug(adreno_dev,
a6xx_spin_idle_debug(adreno_dev,
"CP initialization failed to idle\n");
kgsl_sharedmem_writel(device->scratch,
@ -872,7 +901,7 @@ static int a6xx_post_start(struct adreno_device *adreno_dev)
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret)
adreno_spin_idle_debug(adreno_dev,
a6xx_spin_idle_debug(adreno_dev,
"hw preemption initialization failed to idle\n");
return ret;
@ -886,6 +915,7 @@ int a6xx_rb_start(struct adreno_device *adreno_dev)
struct adreno_ringbuffer *rb;
uint64_t addr;
int ret, i;
unsigned int *cmds;
/* Clear all the ringbuffers */
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
@ -945,9 +975,19 @@ int a6xx_rb_start(struct adreno_device *adreno_dev)
if (!adreno_dev->zap_loaded)
kgsl_regwrite(device, A6XX_RBBM_SECVID_TRUST_CNTL, 0);
else {
ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);
if (ret)
cmds = adreno_ringbuffer_allocspace(rb, 2);
if (IS_ERR(cmds))
return PTR_ERR(cmds);
*cmds++ = cp_packet(adreno_dev, CP_SET_SECURE_MODE, 1);
*cmds++ = 0;
ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
if (ret) {
a6xx_spin_idle_debug(adreno_dev,
"Switch to unsecure failed to idle\n");
return ret;
}
}
return a6xx_post_start(adreno_dev);
@ -2495,7 +2535,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A6XX_CP_RB_WPTR),
ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A6XX_CP_RB_CNTL),
ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A6XX_CP_SQE_CNTL),
ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A6XX_CP_HW_FAULT),
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A6XX_CP_IB1_BASE),
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE_HI, A6XX_CP_IB1_BASE_HI),
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BUFSZ, A6XX_CP_IB1_REM_SIZE),