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ARM: socfpga: initial support for Altera's SOCFPGA platform

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Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <[email protected]>
Reviewed-by: Pavel Machek <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
This commit is contained in:
Dinh Nguyen 2012-07-18 16:07:18 -06:00 • committed by Arnd Bergmann
commit 66314223aa
16 changed files with 460 additions and 0 deletions
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1
drivers/clk/Makefile
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@ -4,4 +4,5 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
clk-mux.o clk-divider.o clk-fixed-factor.o
# SoCs specific
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/

1
drivers/clk/socfpga/Makefile Normal file
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@ -0,0 +1 @@
obj-y += clk.o

51
drivers/clk/socfpga/clk.c Normal file
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@ -0,0 +1,51 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#define SOCFPGA_OSC1_CLK 10000000
#define SOCFPGA_MPU_CLK 800000000
#define SOCFPGA_MAIN_QSPI_CLK 432000000
#define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000
#define SOCFPGA_S2F_USR_CLK 125000000
void __init socfpga_init_clocks(void)
{
struct clk *clk;
clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
clk_register_clkdev(clk, "osc1_clk", NULL);
clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
clk_register_clkdev(clk, "mpu_clk", NULL);
clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
clk_register_clkdev(clk, "main_clk", NULL);
clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
clk_register_clkdev(clk, "dbg_base_clk", NULL);
clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
clk_register_clkdev(clk, "main_qspi_clk", NULL);
clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
clk_register_clkdev(clk, "s2f_usr_clk", NULL);
}