From 66b82d2ac58fe2fbcf0fcd7d5309046f052505d7 Mon Sep 17 00:00:00 2001
From: Raghavendra Rao Ananta <rananta@quicinc.com>
Date: Fri, 26 Jul 2019 09:19:47 -0700
Subject: [PATCH] ARM: dts: msm: Add support for SCM PAS

The PIL drivers need to vote for bandwidth across DDR and
crypto subsytem, such that the secure world can perform
initialization and authorization of the firmware blobs.
Hence add a device-tree node indicating the corresponding
interconnect.

Change-Id: If5626ad20638434e39a7d4aa0f02149a72bdaf12
---
 qcom/lahaina.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index a1fb72c58381..c23667d53f59 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -556,6 +556,11 @@
 		#interconnect-cells = <1>;
 	};
 
+	pil_scm_pas {
+		compatible = "qcom,pil-tz-scm-pas";
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+	};
+
 	ufsphy_mem: ufsphy_mem@1d87000 {
 		reg = <0x1d8700 0xe10>;
 		reg-names = "phy_mem";