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Merge "ARM: dts: msm: add trusted vm display dtsi files for yupik target"

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qctecmdr 2021-02-04 23:26:21 -08:00 • committed by Gerrit - the friendly Code Review server
commit 66f3793873
2 changed files with 81 additions and 0 deletions
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26
display/trustedvm-yupik-sde-display.dtsi Normal file
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#include "yupik-sde-display-common.dtsi"
&sde_dsi {
clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>,
<&clock_cpucc PCLK_MUX_0_CLK>,
<&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>,
<&clock_cpucc CPHY_PCLK_SRC_0_CLK>,
<&clock_cpucc BYTECLK_SRC_0_CLK>,
<&clock_cpucc PCLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_PCLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_CPHY_PCLK_SRC_0_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
qcom,panel-te-source = <0>;
qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>;
};
&mdss_mdp {
connectors = <&sde_dsi>;
};

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display/trustedvm-yupik-sde.dtsi Normal file
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#include "yupik-sde-common.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
&soc {
/* dummy display clock provider */
clock_cpucc: qcom,cpucc {
compatible = "qcom,dummycc";
clock-output-names = "cpucc_clocks";
#clock-cells = <1>;
};
};
&mdss_mdp {
reg = <0x0ae00000 0x84000>,
<0x0aeb0000 0x2008>,
<0x0aeac000 0x800>,
<0x0ae8f000 0x02c>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"sid_phys";
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,sde-hw-version = <0x70020000>;
clocks =
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
<&clock_cpucc GCC_DISP_SF_AXI_CLK>,
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>,
<&clock_cpucc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_bus", "gcc_nrt_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
qcom,sde-trusted-vm-env;
qcom,vram-size = <0x200000>;
};
&mdss_dsi0 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
qcom,dsi-pll-in-trusted-vm;
};