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ARM: dts: msm: Update GPUCC clock node and GDSC for YUPIK

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Update GPUCC clock node and corresponding GDSC's for YUPIK.

Change-Id: Ib5c4e21fa3e8da086689c16a3f766a869d459969
This commit is contained in:
Jagadeesh Kona 2020-10-27 10:35:49 +05:30
commit 6719abb50e
2 changed files with 25 additions and 4 deletions
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7
qcom/yupik-rumi.dtsi
View file

@ -1,3 +1,5 @@
#include <dt-bindings/clock/qcom,gcc-yupik.h>
&soc {
timer {
clock-frequency = <5000000>;
@ -79,3 +81,8 @@
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>;
};
&gpucc {
clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
};

22
qcom/yupik.dtsi
View file

@ -625,8 +625,15 @@
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
compatible = "qcom,yupik-gpucc", "syscon";
reg = <0x3d90000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -1392,12 +1399,19 @@
};
&gpu_cx_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&gpu_gx_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
qcom,skip-disable-before-sw-enable;
status = "ok"
};