A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-08 21:22:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

msm: camera: csiphy: Update csiphy-v1.2.3 CPHY sequences

Browse source 
Update the CPHY sequences to align to HPG rev X.

Data rate:   <=1.9Gsps  1.9Gsps->3Gsps  >3Gsps
144/344/544  0x22       0xA2            0xA2
988/A88/B88  0          5               5
980/A80/B80  0          0x61            0x61
9B4/AB4/BB4  8          8               4.

CRs-Fixed: 3000765
Change-Id: I6cda0471399c5724a6b9e50a175fc5b69a72b025
Signed-off-by: Shravan Nevatia <snevatia@codeaurora.org>
This commit is contained in:
Shravan Nevatia 2021-07-15 12:22:32 +05:30
commit 672b8abdde
2 changed files with 96 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h
View file

@ -34,7 +34,7 @@
#define MAX_LANES 5
#define MAX_SETTINGS_PER_LANE 43
#define MAX_DATA_RATES 3
#define MAX_DATA_RATES 4
#define MAX_DATA_RATE_REGS 30
#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"

111
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h
View file

@ -16,7 +16,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
.csiphy_common_array_size = 5,
.csiphy_reset_array_size = 2,
.csiphy_2ph_config_array_size = 16,
.csiphy_3ph_config_array_size = 31,
.csiphy_3ph_config_array_size = 28,
.csiphy_2ph_3ph_config_array_size = 0,
.csiphy_2ph_clock_lane = 0x1,
.csiphy_2ph_combo_ck_ln = 0x10,
@ -261,14 +261,11 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0980, 0x61, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
},
@ -294,14 +291,11 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A80, 0x61, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
},
@ -327,30 +321,29 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B80, 0x61, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
},
};
struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
.num_data_rate_settings = 3,
.num_data_rate_settings = 4,
.data_rate_settings = {
{
/* (2.5 * 10**3 * 2.28) rounded value*/
.bandwidth = 5700000000,
.data_rate_reg_array_size = 1,
/* (1.9 * 10**3 * 2.28) rounded value*/
.bandwidth = 4332000000,
.data_rate_reg_array_size = 2,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x144, 0x22, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x9B4, 0x08, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -358,6 +351,8 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x344, 0x22, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xAB4, 0x08, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -365,6 +360,54 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x544, 0x22, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xBB4, 0x08, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* (3 * 10**3 * 2.28) rounded value */
.bandwidth = 6840000000,
.data_rate_reg_array_size = 4,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x144, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x988, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x980, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x9B4, 0x08, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x344, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xA88, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xA80, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xAB4, 0x08, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x544, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xB88, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xB80, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xBB4, 0x08, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -374,11 +417,17 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
/* (3.5 * 10**3 * 2.28) rounded value */
.bandwidth = 7980000000,
.data_rate_reg_array_size = 1,
.data_rate_reg_array_size = 4,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x144, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x988, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x980, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x9B4, 0x04, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -386,6 +435,12 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x344, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xA88, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xA80, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xAB4, 0x04, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -393,6 +448,12 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x544, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xB88, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xB80, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xBB4, 0x04, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -402,11 +463,17 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
/* (4.5 * 10**3 * 2.28) rounded value */
.bandwidth = 10260000000,
.data_rate_reg_array_size = 1,
.data_rate_reg_array_size = 4,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x144, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x988, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x980, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0x9B4, 0x04, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -414,6 +481,12 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x344, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xA88, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xA80, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xAB4, 0x04, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},
@ -421,6 +494,12 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x544, 0xA2, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xB88, 0x05, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xB80, 0x61, 0x00,
CSIPHY_DEFAULT_PARAMS},
{0xBB4, 0x04, 0x0A,
CSIPHY_DEFAULT_PARAMS},
},