From 6756b1a5aab1b93b77a95dc541cdff89b2060c00 Mon Sep 17 00:00:00 2001 From: Pavankumar Nandeshwar Date: Mon, 24 Aug 2020 23:53:46 +0530 Subject: [PATCH] qcacmn: Data path changes for QCN9100 bringup Initial changes made for bring up of QCN9100 in data path and hal Change-Id: I6cbe90428b552b6ff5733bc0f60bfb9f7933bc9a --- dp/inc/cdp_txrx_cmn_reg.h | 1 + dp/wifi3.0/dp_main.c | 2 + hal/wifi3.0/hal_generic_api.h | 1 + hal/wifi3.0/hal_srng.c | 15 + hal/wifi3.0/qcn9100/hal_qcn9100.c | 925 ++++++++++++++++++------- hal/wifi3.0/qcn9100/hal_qcn9100_rx.h | 997 ++++++++------------------- hal/wifi3.0/qcn9100/hal_qcn9100_tx.h | 42 +- 7 files changed, 1012 insertions(+), 971 deletions(-) diff --git a/dp/inc/cdp_txrx_cmn_reg.h b/dp/inc/cdp_txrx_cmn_reg.h index f63a5e21c178..5e79d5cc087f 100644 --- a/dp/inc/cdp_txrx_cmn_reg.h +++ b/dp/inc/cdp_txrx_cmn_reg.h @@ -115,6 +115,7 @@ ol_txrx_soc_handle cdp_soc_attach(u_int16_t devid, case QCA5018_DEVICE_ID: case QCA6290_DEVICE_ID: case QCN9000_DEVICE_ID: + case QCN9100_DEVICE_ID: case QCA6390_DEVICE_ID: case QCA6490_DEVICE_ID: case QCA6750_DEVICE_ID: diff --git a/dp/wifi3.0/dp_main.c b/dp/wifi3.0/dp_main.c index 20739a441eff..f0fdec14df3f 100644 --- a/dp/wifi3.0/dp_main.c +++ b/dp/wifi3.0/dp_main.c @@ -12919,6 +12919,7 @@ static void dp_soc_cfg_init(struct dp_soc *soc) dp_config_full_mon_mode((struct cdp_soc_t *)soc, 1); break; case TARGET_TYPE_QCA5018: + case TARGET_TYPE_QCN9100: wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx, REO_DST_RING_SIZE_QCA8074); soc->ast_override_support = 1; @@ -12968,6 +12969,7 @@ static void dp_soc_cfg_attach(struct dp_soc *soc) break; case TARGET_TYPE_QCA8074V2: case TARGET_TYPE_QCA6018: + case TARGET_TYPE_QCN9100: case TARGET_TYPE_QCA5018: wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1); wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx, diff --git a/hal/wifi3.0/hal_generic_api.h b/hal/wifi3.0/hal_generic_api.h index 8b5acd4461c2..38d44dc0ef27 100644 --- a/hal/wifi3.0/hal_generic_api.h +++ b/hal/wifi3.0/hal_generic_api.h @@ -903,6 +903,7 @@ hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, case TARGET_TYPE_QCA6018: case TARGET_TYPE_QCA5018: case TARGET_TYPE_QCN9000: + case TARGET_TYPE_QCN9100: #ifdef QCA_WIFI_QCA6390 case TARGET_TYPE_QCA6390: #endif diff --git a/hal/wifi3.0/hal_srng.c b/hal/wifi3.0/hal_srng.c index 8cb491954fe9..51519c1dbc41 100644 --- a/hal/wifi3.0/hal_srng.c +++ b/hal/wifi3.0/hal_srng.c @@ -40,6 +40,9 @@ void hal_qca6490_attach(struct hal_soc *hal); #ifdef QCA_WIFI_QCN9000 void hal_qcn9000_attach(struct hal_soc *hal); #endif +#ifdef QCA_WIFI_QCN9100 +void hal_qcn9100_attach(struct hal_soc *hal); +#endif #ifdef QCA_WIFI_QCA6750 void hal_qca6750_attach(struct hal_soc *hal); #endif @@ -324,6 +327,18 @@ static void hal_target_based_configure(struct hal_soc *hal) break; #endif +#if defined(QCA_WIFI_QCN9100) + case TARGET_TYPE_QCN9100: + hal->use_register_windowing = true; + /* + * Static window map is enabled for qcn9000 to use 2mb bar + * size and use multiple windows to write into registers. + */ + hal->static_window_map = true; + hal_qcn9100_attach(hal); + break; +#endif + #ifdef QCA_WIFI_QCN9000 case TARGET_TYPE_QCN9000: hal->use_register_windowing = true; diff --git a/hal/wifi3.0/qcn9100/hal_qcn9100.c b/hal/wifi3.0/qcn9100/hal_qcn9100.c index 8d55a37adc6b..12a1bf0462c0 100644 --- a/hal/wifi3.0/qcn9100/hal_qcn9100.c +++ b/hal/wifi3.0/qcn9100/hal_qcn9100.c @@ -20,6 +20,8 @@ #include "target_type.h" #include "wcss_version.h" #include "qdf_module.h" +#include "hal_9100_rx.h" +#include "hal_api_mon.h" #include "hal_flow.h" #include "rx_flow_search_entry.h" #include "hal_rx_flow_info.h" @@ -53,7 +55,7 @@ #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ - RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET + RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ @@ -102,38 +104,459 @@ WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB -#include "hal_8074v2_tx.h" -#include "hal_8074v2_rx.h" + +#define CE_WINDOW_ADDRESS_9100 \ + ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) + +#define UMAC_WINDOW_ADDRESS_9100 \ + ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) + +#define WINDOW_CONFIGURATION_VALUE_9100 \ + ((CE_WINDOW_ADDRESS_9100 << 6) |\ + (UMAC_WINDOW_ADDRESS_9100 << 12) | \ + WINDOW_ENABLE_BIT) + +#include +#include #include #include /** - * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve - * rx fragment number + * hal_rx_sw_mon_desc_info_get_9100(): API to read the + * sw monitor ring descriptor + * + * @rxdma_dst_ring_desc: sw monitor ring descriptor + * @desc_info_buf: Descriptor info buffer to which + * sw monitor ring descriptor is populated to + * + * Return: void + */ +static void +hal_rx_sw_mon_desc_info_get_9100(hal_ring_desc_t rxdma_dst_ring_desc, + hal_rx_mon_desc_info_t desc_info_buf) +{ + struct sw_monitor_ring *sw_mon_ring = + (struct sw_monitor_ring *)rxdma_dst_ring_desc; + struct buffer_addr_info *buf_addr_info; + uint32_t *mpdu_info; + uint32_t loop_cnt; + struct hal_rx_mon_desc_info *desc_info; + + desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; + mpdu_info = (uint32_t *)&sw_mon_ring-> + reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; + + loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); + desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); + + /* Get msdu link descriptor buf_addr_info */ + buf_addr_info = &sw_mon_ring-> + reo_level_mpdu_frame_info.msdu_link_desc_addr_info; + desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) + | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( + buf_addr_info)) << 32); + desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); + buf_addr_info = &sw_mon_ring->status_buff_addr_info; + desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) + | ((uint64_t) + (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); + desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); + desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, + SW_MONITOR_RING_6, + END_OF_PPDU); + desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, + SW_MONITOR_RING_6, + STATUS_BUF_COUNT); + desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, + SW_MONITOR_RING_6, + RXDMA_PUSH_REASON); + desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, + SW_MONITOR_RING_7, + PHY_PPDU_ID); +} + +/** + * hal_rx_msdu_start_nss_get_9100(): API to get the NSS + * Interval from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(nss) + */ +static uint32_t hal_rx_msdu_start_nss_get_9100(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint8_t mimo_ss_bitmap; + + mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); + + return qdf_get_hweight8(mimo_ss_bitmap); +} + +/** + * hal_rx_mon_hw_desc_get_mpdu_status_9100(): Retrieve MPDU status + * + * @ hw_desc_addr: Start address of Rx HW TLVs + * @ rs: Status for monitor mode + * + * Return: void + */ +static void hal_rx_mon_hw_desc_get_mpdu_status_9100(void *hw_desc_addr, + struct mon_rx_status *rs) +{ + struct rx_msdu_start *rx_msdu_start; + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; + uint32_t reg_value; + const uint32_t sgi_hw_to_cdp[] = { + CDP_SGI_0_8_US, + CDP_SGI_0_4_US, + CDP_SGI_1_6_US, + CDP_SGI_3_2_US, + }; + + rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; + + HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); + + rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, + RX_MSDU_START_5, USER_RSSI); + rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); + + reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); + rs->sgi = sgi_hw_to_cdp[reg_value]; + reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); + rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; + /* TODO: rs->beamformed should be set for SU beamforming also */ +} + +#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) +/** + * hal_get_link_desc_size_9100(): API to get the link desc size + * + * Return: uint32_t + */ +static uint32_t hal_get_link_desc_size_9100(void) +{ + return LINK_DESC_SIZE; +} + +/** + * hal_rx_get_tlv_9100(): API to get the tlv + * + * @rx_tlv: TLV data extracted from the rx packet + * Return: uint8_t + */ +static uint8_t hal_rx_get_tlv_9100(void *rx_tlv) +{ + return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); +} + +/** + * hal_rx_mpdu_start_tlv_tag_valid_9100 () - API to check if RX_MPDU_START + * tlv tag is valid + * + *@rx_tlv_hdr: start address of rx_pkt_tlvs + * + * Return: true if RX_MPDU_START is valied, else false. + */ +uint8_t hal_rx_mpdu_start_tlv_tag_valid_9100(void *rx_tlv_hdr) +{ + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; + uint32_t tlv_tag; + + tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); + + return tlv_tag == WIFIRX_MPDU_START_E ? true : false; +} + +/** + * hal_rx_wbm_err_msdu_continuation_get_9100 () - API to check if WBM + * msdu continuation bit is set + * + *@wbm_desc: wbm release ring descriptor + * + * Return: true if msdu continuation bit is set. + */ +uint8_t hal_rx_wbm_err_msdu_continuation_get_9100(void *wbm_desc) +{ + uint32_t comp_desc = + *(uint32_t *)(((uint8_t *)wbm_desc) + + WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); + + return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> + WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; +} + +/** + * hal_rx_proc_phyrx_other_receive_info_tlv_9100(): API to get tlv info + * + * Return: uint32_t + */ +static inline +void hal_rx_proc_phyrx_other_receive_info_tlv_9100(void *rx_tlv_hdr, + void *ppdu_info_hdl) +{ +} + +/** + * hal_rx_dump_msdu_start_tlv_9100() : dump RX msdu_start TLV in structured + * human readable format. + * @ msdu_start: pointer the msdu_start TLV in pkt. + * @ dbg_level: log level. + * + * Return: void + */ +static void hal_rx_dump_msdu_start_tlv_9100(void *msdustart, + uint8_t dbg_level) +{ + struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; + + QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, + "rx_msdu_start tlv - " + "rxpcu_mpdu_filter_in_category: %d " + "sw_frame_group_id: %d " + "phy_ppdu_id: %d " + "msdu_length: %d " + "ipsec_esp: %d " + "l3_offset: %d " + "ipsec_ah: %d " + "l4_offset: %d " + "msdu_number: %d " + "decap_format: %d " + "ipv4_proto: %d " + "ipv6_proto: %d " + "tcp_proto: %d " + "udp_proto: %d " + "ip_frag: %d " + "tcp_only_ack: %d " + "da_is_bcast_mcast: %d " + "ip4_protocol_ip6_next_header: %d " + "toeplitz_hash_2_or_4: %d " + "flow_id_toeplitz: %d " + "user_rssi: %d " + "pkt_type: %d " + "stbc: %d " + "sgi: %d " + "rate_mcs: %d " + "receive_bandwidth: %d " + "reception_type: %d " + "ppdu_start_timestamp: %d " + "sw_phy_meta_data: %d ", + msdu_start->rxpcu_mpdu_filter_in_category, + msdu_start->sw_frame_group_id, + msdu_start->phy_ppdu_id, + msdu_start->msdu_length, + msdu_start->ipsec_esp, + msdu_start->l3_offset, + msdu_start->ipsec_ah, + msdu_start->l4_offset, + msdu_start->msdu_number, + msdu_start->decap_format, + msdu_start->ipv4_proto, + msdu_start->ipv6_proto, + msdu_start->tcp_proto, + msdu_start->udp_proto, + msdu_start->ip_frag, + msdu_start->tcp_only_ack, + msdu_start->da_is_bcast_mcast, + msdu_start->ip4_protocol_ip6_next_header, + msdu_start->toeplitz_hash_2_or_4, + msdu_start->flow_id_toeplitz, + msdu_start->user_rssi, + msdu_start->pkt_type, + msdu_start->stbc, + msdu_start->sgi, + msdu_start->rate_mcs, + msdu_start->receive_bandwidth, + msdu_start->reception_type, + msdu_start->ppdu_start_timestamp, + msdu_start->sw_phy_meta_data); +} + +/** + * hal_rx_dump_msdu_end_tlv_9100: dump RX msdu_end TLV in structured + * human readable format. + * @ msdu_end: pointer the msdu_end TLV in pkt. + * @ dbg_level: log level. + * + * Return: void + */ +static void hal_rx_dump_msdu_end_tlv_9100(void *msduend, + uint8_t dbg_level) +{ + struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; + + QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, + "rx_msdu_end tlv - " + "rxpcu_mpdu_filter_in_category: %d " + "sw_frame_group_id: %d " + "phy_ppdu_id: %d " + "ip_hdr_chksum: %d " + "reported_mpdu_length: %d " + "key_id_octet: %d " + "cce_super_rule: %d " + "cce_classify_not_done_truncat: %d " + "cce_classify_not_done_cce_dis: %d " + "rule_indication_31_0: %d " + "rule_indication_63_32: %d " + "da_offset: %d " + "sa_offset: %d " + "da_offset_valid: %d " + "sa_offset_valid: %d " + "ipv6_options_crc: %d " + "tcp_seq_number: %d " + "tcp_ack_number: %d " + "tcp_flag: %d " + "lro_eligible: %d " + "window_size: %d " + "tcp_udp_chksum: %d " + "sa_idx_timeout: %d " + "da_idx_timeout: %d " + "msdu_limit_error: %d " + "flow_idx_timeout: %d " + "flow_idx_invalid: %d " + "wifi_parser_error: %d " + "amsdu_parser_error: %d " + "sa_is_valid: %d " + "da_is_valid: %d " + "da_is_mcbc: %d " + "l3_header_padding: %d " + "first_msdu: %d " + "last_msdu: %d " + "sa_idx: %d " + "msdu_drop: %d " + "reo_destination_indication: %d " + "flow_idx: %d " + "fse_metadata: %d " + "cce_metadata: %d " + "sa_sw_peer_id: %d ", + msdu_end->rxpcu_mpdu_filter_in_category, + msdu_end->sw_frame_group_id, + msdu_end->phy_ppdu_id, + msdu_end->ip_hdr_chksum, + msdu_end->reported_mpdu_length, + msdu_end->key_id_octet, + msdu_end->cce_super_rule, + msdu_end->cce_classify_not_done_truncate, + msdu_end->cce_classify_not_done_cce_dis, + msdu_end->rule_indication_31_0, + msdu_end->rule_indication_63_32, + msdu_end->da_offset, + msdu_end->sa_offset, + msdu_end->da_offset_valid, + msdu_end->sa_offset_valid, + msdu_end->ipv6_options_crc, + msdu_end->tcp_seq_number, + msdu_end->tcp_ack_number, + msdu_end->tcp_flag, + msdu_end->lro_eligible, + msdu_end->window_size, + msdu_end->tcp_udp_chksum, + msdu_end->sa_idx_timeout, + msdu_end->da_idx_timeout, + msdu_end->msdu_limit_error, + msdu_end->flow_idx_timeout, + msdu_end->flow_idx_invalid, + msdu_end->wifi_parser_error, + msdu_end->amsdu_parser_error, + msdu_end->sa_is_valid, + msdu_end->da_is_valid, + msdu_end->da_is_mcbc, + msdu_end->l3_header_padding, + msdu_end->first_msdu, + msdu_end->last_msdu, + msdu_end->sa_idx, + msdu_end->msdu_drop, + msdu_end->reo_destination_indication, + msdu_end->flow_idx, + msdu_end->fse_metadata, + msdu_end->cce_metadata, + msdu_end->sa_sw_peer_id); +} + +/** + * hal_rx_mpdu_start_tid_get_9100(): API to get tid + * from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(tid value) + */ +static uint32_t hal_rx_mpdu_start_tid_get_9100(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + uint32_t tid; + + tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); + + return tid; +} + +/** + * hal_rx_msdu_start_reception_type_get(): API to get the reception type + * Interval from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(reception_type) + */ +static uint32_t hal_rx_msdu_start_reception_type_get_9100(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t reception_type; + + reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); + + return reception_type; +} + +/** + * hal_rx_msdu_end_da_idx_get_9100: API to get da_idx + * from rx_msdu_end TLV + * + * @ buf: pointer to the start of RX PKT TLV headers + * Return: da index + */ +static uint16_t hal_rx_msdu_end_da_idx_get_9100(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint16_t da_idx; + + da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); + + return da_idx; +} + +/** + * hal_rx_get_rx_fragment_number_9100(): Function to retrieve rx fragment number * * @nbuf: Network buffer * Returns: rx fragment number */ static -uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) +uint8_t hal_rx_get_rx_fragment_number_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); /* Return first 4 bits as fragment number */ - return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & - DOT11_SEQ_FRAG_MASK; + return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & + DOT11_SEQ_FRAG_MASK); } /** - * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC + * hal_rx_msdu_end_da_is_mcbc_get_9100(): API to check if pkt is MCBC * from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: da_is_mcbc */ static uint8_t -hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) +hal_rx_msdu_end_da_is_mcbc_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -142,14 +565,14 @@ hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the + * hal_rx_msdu_end_sa_is_valid_get_9100(): API to get_9100 the * sa_is_valid bit from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: sa_is_valid bit */ static uint8_t -hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) +hal_rx_msdu_end_sa_is_valid_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -161,13 +584,13 @@ hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the + * hal_rx_msdu_end_sa_idx_get_9100(): API to get_9100 the * sa_idx from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: sa_idx (SA AST index) */ -static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) +static uint16_t hal_rx_msdu_end_sa_idx_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -179,29 +602,29 @@ static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) } /** - * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu + * hal_rx_desc_is_first_msdu_9100() - Check if first msdu * * @hal_soc_hdl: hal_soc handle * @hw_desc_addr: hardware descriptor address * * Return: 0 - success/ non-zero failure */ -static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) +static uint32_t hal_rx_desc_is_first_msdu_9100(void *hw_desc_addr) { struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; - return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); + return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); } /** - * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the + * hal_rx_msdu_end_l3_hdr_padding_get_9100(): API to get_9100 the * l3_header padding from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: number of l3 header padding bytes */ -static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) +static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -212,13 +635,13 @@ static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) return l3_header_padding; } -/* - * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. +/** + * @ hal_rx_encryption_info_valid_9100: Returns encryption type. * * @ buf: rx_tlv_hdr of the received packet * @ Return: encryption type */ -static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) +inline uint32_t hal_rx_encryption_info_valid_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -230,12 +653,12 @@ static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) } /* - * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. + * @ hal_rx_print_pn_9100: Prints the PN of rx packet. * * @ buf: rx_tlv_hdr of the received packet * @ Return: void */ -static void hal_rx_print_pn_8074v2(uint8_t *buf) +static void hal_rx_print_pn_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -252,13 +675,13 @@ static void hal_rx_print_pn_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status + * hal_rx_msdu_end_first_msdu_get_9100: API to get first msdu status * from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: first_msdu */ -static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) +static uint8_t hal_rx_msdu_end_first_msdu_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -270,13 +693,13 @@ static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid + * hal_rx_msdu_end_da_is_valid_get_9100: API to check if da is valid * from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: da_is_valid */ -static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) +static uint8_t hal_rx_msdu_end_da_is_valid_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -288,13 +711,13 @@ static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status + * hal_rx_msdu_end_last_msdu_get_9100: API to get last msdu status * from rx_msdu_end TLV * * @ buf: pointer to the start of RX PKT TLV headers * Return: last_msdu */ -static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) +static uint8_t hal_rx_msdu_end_last_msdu_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -306,29 +729,29 @@ static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) } /* - * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid + * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid * * @nbuf: Network buffer * Returns: value of mpdu 4th address valid field */ -static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) +inline bool hal_rx_get_mpdu_mac_ad4_valid_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); bool ad4_valid = 0; - ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); + ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); return ad4_valid; } /** - * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id + * hal_rx_mpdu_start_sw_peer_id_get_9100: Retrieve sw peer_id * @buf: network buffer * * Return: sw peer_id */ -static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) +static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -339,13 +762,13 @@ static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) } /* - * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info + * hal_rx_mpdu_get_to_ds_9100(): API to get the tods info * from rx_mpdu_start * * @buf: pointer to the start of RX PKT TLV header * Return: uint32_t(to_ds) */ -static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) +static uint32_t hal_rx_mpdu_get_to_ds_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -357,13 +780,13 @@ static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) } /* - * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info + * hal_rx_mpdu_get_fr_ds_9100(): API to get the from ds info * from rx_mpdu_start * * @buf: pointer to the start of RX PKT TLV header * Return: uint32_t(fr_ds) */ -static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) +static uint32_t hal_rx_mpdu_get_fr_ds_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -375,13 +798,13 @@ static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) } /* - * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu + * hal_rx_get_mpdu_frame_control_valid_9100(): Retrieves mpdu * frame control valid * * @nbuf: Network buffer * Returns: value of frame control valid field */ -static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) +static uint8_t hal_rx_get_mpdu_frame_control_valid_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); @@ -390,13 +813,14 @@ static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) } /* - * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu + * hal_rx_mpdu_get_addr1_9100(): API to check get address1 of the mpdu * * @buf: pointer to the start of RX PKT TLV headera * @mac_addr: pointer to mac address * Return: success/failure */ -static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) +static QDF_STATUS hal_rx_mpdu_get_addr1_9100(uint8_t *buf, + uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr1 { uint32_t ad1_31_0; @@ -423,14 +847,14 @@ static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) } /* - * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu + * hal_rx_mpdu_get_addr2_9100(): API to check get address2 of the mpdu * in the packet * * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address * Return: success/failure */ -static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) +static QDF_STATUS hal_rx_mpdu_get_addr2_9100(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr2 { uint16_t ad2_15_0; @@ -457,14 +881,14 @@ static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) } /* - * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu + * hal_rx_mpdu_get_addr3_9100(): API to get address3 of the mpdu * in the packet * * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address * Return: success/failure */ -static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) +static QDF_STATUS hal_rx_mpdu_get_addr3_9100(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr3 { uint32_t ad3_31_0; @@ -491,14 +915,14 @@ static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) } /* - * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu + * hal_rx_mpdu_get_addr4_9100(): API to get address4 of the mpdu * in the packet * * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address * Return: success/failure */ -static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) +static QDF_STATUS hal_rx_mpdu_get_addr4_9100(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr4 { uint32_t ad4_31_0; @@ -525,13 +949,13 @@ static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) } /* - * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu + * hal_rx_get_mpdu_sequence_control_valid_9100(): Get mpdu * sequence control valid * * @nbuf: Network buffer * Returns: value of sequence control valid field */ -static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) +static uint8_t hal_rx_get_mpdu_sequence_control_valid_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); @@ -540,13 +964,13 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) } /** - * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. + * hal_rx_is_unicast_9100: check packet is unicast frame or not. * * @ buf: pointer to rx pkt TLV. * * Return: true on unicast. */ -static bool hal_rx_is_unicast_8074v2(uint8_t *buf) +static bool hal_rx_is_unicast_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -555,22 +979,21 @@ static bool hal_rx_is_unicast_8074v2(uint8_t *buf) uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), - RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), - RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, - RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); + RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), + RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, + RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; } /** - * hal_rx_tid_get_8074v2: get tid based on qos control valid. + * hal_rx_tid_get_9100: get tid based on qos control valid. * @hal_soc_hdl: hal soc handle * @buf: pointer to rx pkt TLV. * * Return: tid */ -static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, - uint8_t *buf) +static uint32_t hal_rx_tid_get_9100(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -578,37 +1001,33 @@ static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; uint8_t qos_control_valid = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), - RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), - RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, - RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); + RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), + RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, + RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); if (qos_control_valid) - return hal_rx_mpdu_start_tid_get_8074v2(buf); + return hal_rx_mpdu_start_tid_get_9100(buf); return HAL_RX_NON_QOS_TID; } /** - * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id - * @rx_tlv_hdr: packtet rx tlv header + * hal_rx_hw_desc_get_ppduid_get_9100(): retrieve ppdu id + * @rx_tlv_hdr: rx tlv header * @rxdma_dst_ring_desc: rxdma HW descriptor * * Return: ppdu id */ -static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, - void *rxdma_dst_ring_desc) +static uint32_t hal_rx_hw_desc_get_ppduid_get_9100(void *rx_tlv_hdr, + void *rxdma_dst_ring_desc) { - struct rx_mpdu_info *rx_mpdu_info; - struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; + struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; - rx_mpdu_info = - &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; - - return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); + return reo_ent->phy_ppdu_id; } /** - * hal_reo_status_get_header_8074v2 - Process reo desc info + * hal_reo_status_get_header_9100 - Process reo desc info * @d - Pointer to reo descriptior * @b - tlv type info * @h1 - Pointer to hal_reo_status_header where info to be stored @@ -616,7 +1035,7 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, * Return - none. * */ -static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1) +static void hal_reo_status_get_header_9100(uint32_t *d, int b, void *h1) { uint32_t val1 = 0; struct hal_reo_status_header *h = @@ -705,14 +1124,14 @@ static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1) } /** - * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): + * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9100(): * Retrieve qos control valid bit from the tlv. * @buf: pointer to rx pkt TLV. * * Return: qos control value. */ static inline uint32_t -hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) +hal_rx_mpdu_start_mpdu_qos_control_valid_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = @@ -723,14 +1142,14 @@ hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the + * hal_rx_msdu_end_sa_sw_peer_id_get_9100(): API to get the * sa_sw_peer_id from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: sa_sw_peer_id index */ static inline uint32_t -hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) +hal_rx_msdu_end_sa_sw_peer_id_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -739,7 +1158,7 @@ hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) } /** - * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor + * hal_tx_desc_set_mesh_en_9100 - Set mesh_enable flag in Tx descriptor * @desc: Handle to Tx Descriptor * @en: For raw WiFi frames, this indicates transmission to a mesh STA, * enabling the interpretation of the 'Mesh Control Present' bit @@ -750,59 +1169,59 @@ hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) * Return: void */ static inline -void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) +void hal_tx_desc_set_mesh_en_9100(void *desc, uint8_t en) { - HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= - HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); + HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= + HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); } static -void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) +void *hal_rx_msdu0_buffer_addr_lsb_9100(void *link_desc_va) { return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); } static -void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) +void *hal_rx_msdu_desc_info_ptr_get_9100(void *msdu0) { return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); } static -void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) +void *hal_ent_mpdu_desc_info_9100(void *ent_ring_desc) { return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); } static -void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) +void *hal_dst_mpdu_desc_info_9100(void *dst_ring_desc) { return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); } static -uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) +uint8_t hal_rx_get_fc_valid_9100(uint8_t *buf) { return HAL_RX_GET_FC_VALID(buf); } -static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) +static uint8_t hal_rx_get_to_ds_flag_9100(uint8_t *buf) { return HAL_RX_GET_TO_DS_FLAG(buf); } -static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) +static uint8_t hal_rx_get_mac_addr2_valid_9100(uint8_t *buf) { return HAL_RX_GET_MAC_ADDR2_VALID(buf); } -static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) +static uint8_t hal_rx_get_filter_category_9100(uint8_t *buf) { return HAL_RX_GET_FILTER_CATEGORY(buf); } static uint32_t -hal_rx_get_ppdu_id_8074v2(uint8_t *buf) +hal_rx_get_ppdu_id_9100(uint8_t *buf) { struct rx_mpdu_info *rx_mpdu_info; struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; @@ -814,7 +1233,7 @@ hal_rx_get_ppdu_id_8074v2(uint8_t *buf) } /** - * hal_reo_config_8074v2(): Set reo config parameters + * hal_reo_config_9100(): Set reo config parameters * @soc: hal soc handle * @reg_val: value to be set * @reo_params: reo parameters @@ -822,45 +1241,45 @@ hal_rx_get_ppdu_id_8074v2(uint8_t *buf) * Return: void */ static void -hal_reo_config_8074v2(struct hal_soc *soc, - uint32_t reg_val, - struct hal_reo_params *reo_params) +hal_reo_config_9100(struct hal_soc *soc, + uint32_t reg_val, + struct hal_reo_params *reo_params) { HAL_REO_R0_CONFIG(soc, reg_val, reo_params); } /** - * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr + * hal_rx_msdu_desc_info_get_ptr_9100() - Get msdu desc info ptr * @msdu_details_ptr - Pointer to msdu_details_ptr * * Return - Pointer to rx_msdu_desc_info structure. * */ -static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) +static void *hal_rx_msdu_desc_info_get_ptr_9100(void *msdu_details_ptr) { return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); } /** - * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details + * hal_rx_link_desc_msdu0_ptr_9100 - Get pointer to rx_msdu details * @link_desc - Pointer to link desc * * Return - Pointer to rx_msdu_details structure * */ -static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) +static void *hal_rx_link_desc_msdu0_ptr_9100(void *link_desc) { return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); } /** - * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index + * hal_rx_msdu_flow_idx_get_9100: API to get flow index * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index value from MSDU END TLV */ -static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) +static inline uint32_t hal_rx_msdu_flow_idx_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -869,13 +1288,13 @@ static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid + * hal_rx_msdu_flow_idx_invalid_9100: API to get flow index invalid * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index invalid value from MSDU END TLV */ -static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) +static bool hal_rx_msdu_flow_idx_invalid_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -884,13 +1303,13 @@ static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout + * hal_rx_msdu_flow_idx_timeout_9100: API to get flow index timeout * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index timeout value from MSDU END TLV */ -static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) +static bool hal_rx_msdu_flow_idx_timeout_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -899,13 +1318,13 @@ static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata + * hal_rx_msdu_fse_metadata_get_9100: API to get FSE metadata * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: fse metadata value from MSDU END TLV */ -static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) +static uint32_t hal_rx_msdu_fse_metadata_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -914,14 +1333,14 @@ static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata + * hal_rx_msdu_cce_metadata_get_9100: API to get CCE metadata * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: cce_metadata */ static uint16_t -hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) +hal_rx_msdu_cce_metadata_get_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -930,7 +1349,7 @@ hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) } /** - * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid + * hal_rx_msdu_get_flow_params_9100: API to get flow index, flow index invalid * and flow index timeout from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * @flow_invalid: pointer to return value of flow_idx_valid @@ -940,10 +1359,10 @@ hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) * Return: none */ static inline void -hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, - bool *flow_invalid, - bool *flow_timeout, - uint32_t *flow_index) +hal_rx_msdu_get_flow_params_9100(uint8_t *buf, + bool *flow_invalid, + bool *flow_timeout, + uint32_t *flow_index) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; @@ -954,25 +1373,25 @@ hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, } /** - * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum + * hal_rx_tlv_get_tcp_chksum_9100() - API to get tcp checksum * @buf: rx_tlv_hdr * * Return: tcp checksum */ static uint16_t -hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) +hal_rx_tlv_get_tcp_chksum_9100(uint8_t *buf) { return HAL_RX_TLV_GET_TCP_CHKSUM(buf); } /** - * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number + * hal_rx_get_rx_sequence_9100(): Function to retrieve rx sequence number * * @nbuf: Network buffer * Returns: rx sequence number */ static -uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) +uint16_t hal_rx_get_rx_sequence_9100(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); @@ -981,38 +1400,76 @@ uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) } /** - * hal_get_window_address_8074v2(): Function to get hp/tp address + * hal_get_window_address_9100(): Function to get hp/tp address * @hal_soc: Pointer to hal_soc * @addr: address offset of register * * Return: modified address offset of register */ -static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, - qdf_iomem_t addr) +#define SPRUCE_SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SPRUCE_CE_WFSS_CE_REG_BASE 0x3B80000 +static inline qdf_iomem_t hal_get_window_address_9100(struct hal_soc *hal_soc, + qdf_iomem_t addr) { - return addr; + uint32_t offset = addr - hal_soc->dev_base_addr; + qdf_iomem_t new_offset; + + /* + * If offset lies within DP register range, use 3rd window to write + * into DP region. + */ + if ((offset ^ SPRUCE_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { + new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + + (offset & WINDOW_RANGE_MASK)); + /* + * If offset lies within CE register range, use 2nd window to write + * into CE region. + */ + } else if ((offset ^ SPRUCE_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { + new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + + (offset & WINDOW_RANGE_MASK)); + } else { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, + "%s: ERROR: Accessing Wrong register\n", __func__); + qdf_assert_always(0); + return 0; + } + return new_offset; +} + +static inline void hal_write_window_register(struct hal_soc *hal_soc) +{ + /* Write value into window configuration register */ + qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, + WINDOW_CONFIGURATION_VALUE_9100); } /** - * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START - * tlv tag is valid + * hal_rx_msdu_packet_metadata_get_9100(): API to get the + * msdu information from rx_msdu_end TLV * - * @rx_tlv_hdr: start address of rx_pkt_tlvs - * - * Return: true if RX_MPDU_START is valied, else false. + * @ buf: pointer to the start of RX PKT TLV headers + * @ hal_rx_msdu_metadata: pointer to the msdu info structure */ -uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) +static void +hal_rx_msdu_packet_metadata_get_9100(uint8_t *buf, + void *msdu_pkt_metadata) { - struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; - uint32_t tlv_tag; + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + struct hal_rx_msdu_metadata *msdu_metadata = + (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; - tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); - - return tlv_tag == WIFIRX_MPDU_START_E ? true : false; + msdu_metadata->l3_hdr_pad = + HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); + msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); + msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); + msdu_metadata->sa_sw_peer_id = + HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); } /** - * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST + * hal_rx_flow_setup_fse_9100() - Setup a flow search entry in HW FST * @fst: Pointer to the Rx Flow Search Table * @table_offset: offset into the table where the flow is to be setup * @flow: Flow Parameters @@ -1020,8 +1477,8 @@ uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) * Return: Success/Failure */ static void * -hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, - uint8_t *rx_flow) +hal_rx_flow_setup_fse_9100(uint8_t *rx_fst, uint32_t table_offset, + uint8_t *rx_flow) { struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; @@ -1107,16 +1564,15 @@ hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, flow->fse_metadata); - HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); - HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= - HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION, flow->reo_destination_indication); /* Reset all the other fields in FSE */ HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); - HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); - HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); @@ -1124,9 +1580,8 @@ hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, return fse; } -static -void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, - uint32_t *remap1, uint32_t *remap2) +void hal_compute_reo_remap_ix2_ix3_9100(uint32_t *ring, uint32_t num_rings, + uint32_t *remap1, uint32_t *remap2) { switch (num_rings) { case 1: @@ -1208,7 +1663,7 @@ void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, } } -struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { +struct hal_hw_txrx_ops qcn9100_hal_hw_txrx_ops = { /* init and setup */ hal_srng_dst_hw_init_generic, @@ -1216,14 +1671,14 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { hal_get_hw_hptp_generic, hal_reo_setup_generic, hal_setup_link_idle_list_generic, - hal_get_window_address_8074v2, + hal_get_window_address_9100, NULL, /* tx */ - hal_tx_desc_set_dscp_tid_table_id_8074v2, - hal_tx_set_dscp_tid_map_8074v2, - hal_tx_update_dscp_tid_8074v2, - hal_tx_desc_set_lmac_id_8074v2, + hal_tx_desc_set_dscp_tid_table_id_9100, + hal_tx_set_dscp_tid_map_9100, + hal_tx_update_dscp_tid_9100, + hal_tx_desc_set_lmac_id_9100, hal_tx_desc_set_buf_addr_generic, hal_tx_desc_set_search_type_generic, hal_tx_desc_set_search_index_generic, @@ -1231,23 +1686,23 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { hal_tx_comp_get_status_generic, hal_tx_comp_get_release_reason_generic, hal_get_wbm_internal_error_generic, - hal_tx_desc_set_mesh_en_8074v2, - hal_tx_init_cmd_credit_ring_8074v2, + hal_tx_desc_set_mesh_en_9100, + hal_tx_init_cmd_credit_ring_9100, /* rx */ - hal_rx_msdu_start_nss_get_8074v2, - hal_rx_mon_hw_desc_get_mpdu_status_8074v2, - hal_rx_get_tlv_8074v2, - hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, - hal_rx_dump_msdu_start_tlv_8074v2, - hal_rx_dump_msdu_end_tlv_8074v2, - hal_get_link_desc_size_8074v2, - hal_rx_mpdu_start_tid_get_8074v2, - hal_rx_msdu_start_reception_type_get_8074v2, - hal_rx_msdu_end_da_idx_get_8074v2, - hal_rx_msdu_desc_info_get_ptr_8074v2, - hal_rx_link_desc_msdu0_ptr_8074v2, - hal_reo_status_get_header_8074v2, + hal_rx_msdu_start_nss_get_9100, + hal_rx_mon_hw_desc_get_mpdu_status_9100, + hal_rx_get_tlv_9100, + hal_rx_proc_phyrx_other_receive_info_tlv_9100, + hal_rx_dump_msdu_start_tlv_9100, + hal_rx_dump_msdu_end_tlv_9100, + hal_get_link_desc_size_9100, + hal_rx_mpdu_start_tid_get_9100, + hal_rx_msdu_start_reception_type_get_9100, + hal_rx_msdu_end_da_idx_get_9100, + hal_rx_msdu_desc_info_get_ptr_9100, + hal_rx_link_desc_msdu0_ptr_9100, + hal_reo_status_get_header_9100, hal_rx_status_get_tlv_info_generic, hal_rx_wbm_err_info_get_generic, hal_rx_dump_mpdu_start_tlv_generic, @@ -1255,69 +1710,63 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { hal_tx_set_pcp_tid_map_generic, hal_tx_update_pcp_tid_generic, hal_tx_update_tidmap_prty_generic, - hal_rx_get_rx_fragment_number_8074v2, - hal_rx_msdu_end_da_is_mcbc_get_8074v2, - hal_rx_msdu_end_sa_is_valid_get_8074v2, - hal_rx_msdu_end_sa_idx_get_8074v2, - hal_rx_desc_is_first_msdu_8074v2, - hal_rx_msdu_end_l3_hdr_padding_get_8074v2, - hal_rx_encryption_info_valid_8074v2, - hal_rx_print_pn_8074v2, - hal_rx_msdu_end_first_msdu_get_8074v2, - hal_rx_msdu_end_da_is_valid_get_8074v2, - hal_rx_msdu_end_last_msdu_get_8074v2, - hal_rx_get_mpdu_mac_ad4_valid_8074v2, - hal_rx_mpdu_start_sw_peer_id_get_8074v2, - hal_rx_mpdu_get_to_ds_8074v2, - hal_rx_mpdu_get_fr_ds_8074v2, - hal_rx_get_mpdu_frame_control_valid_8074v2, - hal_rx_mpdu_get_addr1_8074v2, - hal_rx_mpdu_get_addr2_8074v2, - hal_rx_mpdu_get_addr3_8074v2, - hal_rx_mpdu_get_addr4_8074v2, - hal_rx_get_mpdu_sequence_control_valid_8074v2, - hal_rx_is_unicast_8074v2, - hal_rx_tid_get_8074v2, - hal_rx_hw_desc_get_ppduid_get_8074v2, - hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2, - hal_rx_msdu_end_sa_sw_peer_id_get_8074v2, - hal_rx_msdu0_buffer_addr_lsb_8074v2, - hal_rx_msdu_desc_info_ptr_get_8074v2, - hal_ent_mpdu_desc_info_8074v2, - hal_dst_mpdu_desc_info_8074v2, - hal_rx_get_fc_valid_8074v2, - hal_rx_get_to_ds_flag_8074v2, - hal_rx_get_mac_addr2_valid_8074v2, - hal_rx_get_filter_category_8074v2, - hal_rx_get_ppdu_id_8074v2, - hal_reo_config_8074v2, - hal_rx_msdu_flow_idx_get_8074v2, - hal_rx_msdu_flow_idx_invalid_8074v2, - hal_rx_msdu_flow_idx_timeout_8074v2, - hal_rx_msdu_fse_metadata_get_8074v2, - hal_rx_msdu_cce_metadata_get_8074v2, - hal_rx_msdu_get_flow_params_8074v2, - hal_rx_tlv_get_tcp_chksum_8074v2, - hal_rx_get_rx_sequence_8074v2, -#if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ - defined(WLAN_ENH_CFR_ENABLE) - hal_rx_get_bb_info_8074v2, - hal_rx_get_rtt_info_8074v2, -#else + hal_rx_get_rx_fragment_number_9100, + hal_rx_msdu_end_da_is_mcbc_get_9100, + hal_rx_msdu_end_sa_is_valid_get_9100, + hal_rx_msdu_end_sa_idx_get_9100, + hal_rx_desc_is_first_msdu_9100, + hal_rx_msdu_end_l3_hdr_padding_get_9100, + hal_rx_encryption_info_valid_9100, + hal_rx_print_pn_9100, + hal_rx_msdu_end_first_msdu_get_9100, + hal_rx_msdu_end_da_is_valid_get_9100, + hal_rx_msdu_end_last_msdu_get_9100, + hal_rx_get_mpdu_mac_ad4_valid_9100, + hal_rx_mpdu_start_sw_peer_id_get_9100, + hal_rx_mpdu_get_to_ds_9100, + hal_rx_mpdu_get_fr_ds_9100, + hal_rx_get_mpdu_frame_control_valid_9100, + hal_rx_mpdu_get_addr1_9100, + hal_rx_mpdu_get_addr2_9100, + hal_rx_mpdu_get_addr3_9100, + hal_rx_mpdu_get_addr4_9100, + hal_rx_get_mpdu_sequence_control_valid_9100, + hal_rx_is_unicast_9100, + hal_rx_tid_get_9100, + hal_rx_hw_desc_get_ppduid_get_9100, + hal_rx_mpdu_start_mpdu_qos_control_valid_get_9100, + hal_rx_msdu_end_sa_sw_peer_id_get_9100, + hal_rx_msdu0_buffer_addr_lsb_9100, + hal_rx_msdu_desc_info_ptr_get_9100, + hal_ent_mpdu_desc_info_9100, + hal_dst_mpdu_desc_info_9100, + hal_rx_get_fc_valid_9100, + hal_rx_get_to_ds_flag_9100, + hal_rx_get_mac_addr2_valid_9100, + hal_rx_get_filter_category_9100, + hal_rx_get_ppdu_id_9100, + hal_reo_config_9100, + hal_rx_msdu_flow_idx_get_9100, + hal_rx_msdu_flow_idx_invalid_9100, + hal_rx_msdu_flow_idx_timeout_9100, + hal_rx_msdu_fse_metadata_get_9100, + hal_rx_msdu_cce_metadata_get_9100, + hal_rx_msdu_get_flow_params_9100, + hal_rx_tlv_get_tcp_chksum_9100, + hal_rx_get_rx_sequence_9100, NULL, NULL, -#endif /* rx - msdu fast path info fields */ - hal_rx_msdu_packet_metadata_get_generic, + hal_rx_msdu_packet_metadata_get_9100, NULL, NULL, NULL, NULL, NULL, NULL, - hal_rx_mpdu_start_tlv_tag_valid_8074v2, - NULL, - NULL, + hal_rx_mpdu_start_tlv_tag_valid_9100, + hal_rx_sw_mon_desc_info_get_9100, + hal_rx_wbm_err_msdu_continuation_get_9100, /* rx - TLV struct offsets */ hal_rx_msdu_end_offset_get_generic, @@ -1325,11 +1774,11 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { hal_rx_msdu_start_offset_get_generic, hal_rx_mpdu_start_offset_get_generic, hal_rx_mpdu_end_offset_get_generic, - hal_rx_flow_setup_fse_8074v2, - hal_compute_reo_remap_ix2_ix3_8074v2 + hal_rx_flow_setup_fse_9100, + hal_compute_reo_remap_ix2_ix3_9100, }; -struct hal_hw_srng_config hw_srng_table_8074v2[] = { +struct hal_hw_srng_config hw_srng_table_9100[] = { /* TODO: max_rings can populated by querying HW capabilities */ { /* REO_DST */ .start_ring_id = HAL_SRNG_REO2SW1, @@ -1460,8 +1909,8 @@ struct hal_hw_srng_config hw_srng_table_8074v2[] = { HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, }, - { /* TCL_CMD */ - /* qca8074v2 and qcn9000 uses this ring for data commands */ + { /* TCL_CMD/CREDIT */ + /* qca8074v2 and qcn9100 uses this ring for data commands */ .start_ring_id = HAL_SRNG_SW2TCL_CMD, .max_rings = 1, .entry_size = (sizeof(struct tlv_32_hdr) + @@ -1469,9 +1918,9 @@ struct hal_hw_srng_config hw_srng_table_8074v2[] = { .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { - HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( + HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), - HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( + HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this @@ -1479,8 +1928,8 @@ struct hal_hw_srng_config hw_srng_table_8074v2[] = { */ .reg_size = {}, .max_size = - HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, + HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> + HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* TCL_STATUS */ .start_ring_id = HAL_SRNG_TCL_STATUS, @@ -1689,7 +2138,7 @@ struct hal_hw_srng_config hw_srng_table_8074v2[] = { { /* RXDMA_MONITOR_DST */ .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, .max_rings = 1, - .entry_size = sizeof(struct reo_entrance_ring) >> 2, + .entry_size = sizeof(struct sw_monitor_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_DST_RING, /* reg_start is not set because LMAC rings are not accessed @@ -1743,7 +2192,7 @@ struct hal_hw_srng_config hw_srng_table_8074v2[] = { #endif }; -int32_t hal_hw_reg_offset_qca8074v2[] = { +int32_t hal_hw_reg_offset_qcn9100[] = { /* dst */ REG_OFFSET(DST, HP), REG_OFFSET(DST, TP), @@ -1773,14 +2222,16 @@ int32_t hal_hw_reg_offset_qca8074v2[] = { REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), }; - /** - * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, + * hal_qcn9100_attach()- Attach 9100 target specific hal_soc ops, * offset and srng table + * Return: void */ -void hal_qca8074v2_attach(struct hal_soc *hal_soc) +void hal_qcn9100_attach(struct hal_soc *hal_soc) { - hal_soc->hw_srng_table = hw_srng_table_8074v2; - hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; - hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; + hal_soc->hw_srng_table = hw_srng_table_9100; + hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9100; + hal_soc->ops = &qcn9100_hal_hw_txrx_ops; + if (hal_soc->static_window_map) + hal_write_window_register(hal_soc); } diff --git a/hal/wifi3.0/qcn9100/hal_qcn9100_rx.h b/hal/wifi3.0/qcn9100/hal_qcn9100_rx.h index 2182424aa983..fb4376f407bd 100644 --- a/hal/wifi3.0/qcn9100/hal_qcn9100_rx.h +++ b/hal/wifi3.0/qcn9100/hal_qcn9100_rx.h @@ -18,263 +18,55 @@ #include "hal_internal.h" #include "cdp_txrx_mon_struct.h" #include "qdf_trace.h" +#include "sw_monitor_ring.h" #include "hal_rx.h" -#include "hal_tx.h" -#include "dp_types.h" #include "hal_api_mon.h" -#ifndef QCA_WIFI_QCA6018 -#include "phyrx_other_receive_info_su_evm_details.h" -#endif - -#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ - RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ - RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) - -#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ - RX_MSDU_END_5_DA_IS_MCBC_MASK, \ - RX_MSDU_END_5_DA_IS_MCBC_LSB)) - -#define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ - RX_MSDU_END_5_SA_IS_VALID_MASK, \ - RX_MSDU_END_5_SA_IS_VALID_LSB)) - -#define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_13_SA_IDX_OFFSET)), \ - RX_MSDU_END_13_SA_IDX_MASK, \ - RX_MSDU_END_13_SA_IDX_LSB)) - -#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ - RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ - RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) - -#define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ - RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ - RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) - -#define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ - RX_MPDU_INFO_4_PN_31_0_MASK, \ - RX_MPDU_INFO_4_PN_31_0_LSB)) - -#define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ - RX_MPDU_INFO_5_PN_63_32_MASK, \ - RX_MPDU_INFO_5_PN_63_32_LSB)) - -#define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ - RX_MPDU_INFO_6_PN_95_64_MASK, \ - RX_MPDU_INFO_6_PN_95_64_LSB)) - -#define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ - RX_MPDU_INFO_7_PN_127_96_MASK, \ - RX_MPDU_INFO_7_PN_127_96_LSB)) - -#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ - RX_MSDU_END_5_FIRST_MSDU_MASK, \ - RX_MSDU_END_5_FIRST_MSDU_LSB)) - -#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ - RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ - RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ - RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) - -#define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ - RX_MSDU_END_5_DA_IS_VALID_MASK, \ - RX_MSDU_END_5_DA_IS_VALID_LSB)) - -#define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ - RX_MSDU_END_5_LAST_MSDU_MASK, \ - RX_MSDU_END_5_LAST_MSDU_LSB)) - -#define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ - RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) - -#define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ - RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ - RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ - RX_MPDU_INFO_1_SW_PEER_ID_LSB)) - -#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_TO_DS_OFFSET)), \ - RX_MPDU_INFO_2_TO_DS_MASK, \ - RX_MPDU_INFO_2_TO_DS_LSB)) - -#define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_FR_DS_OFFSET)), \ - RX_MPDU_INFO_2_FR_DS_MASK, \ - RX_MPDU_INFO_2_FR_DS_LSB)) - -#define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ - RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) - -#define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ - RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) - -#define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ - RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ - RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) - -#define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ - RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ - RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) - -#define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ - RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) - -#define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ - RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ - RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) - -#define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ - RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ - RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) - -#define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ - RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) - -#define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ - RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ - RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) - -#define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ - RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ - RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) - -#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ - RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) - -#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ - RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ - RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) - -#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ - RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ - RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) - -#define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ - RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ - RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) - -#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ - RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ - RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ - RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) - -#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ - RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ - RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ - (uint8_t *)(link_desc_va) + \ - RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET + ((uint8_t *)(link_desc_va) + \ + RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET) #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ - (uint8_t *)(msdu0) + \ - RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET + ((uint8_t *)(msdu0) + \ + RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET) #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ - (uint8_t *)(ent_ring_desc) + \ - RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET + ((uint8_t *)(ent_ring_desc) + \ + RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ - (uint8_t *)(dst_ring_desc) + \ - REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET + ((uint8_t *)(dst_ring_desc) + \ + REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ - HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ do { \ reg_val &= \ - ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ - HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ + ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK | \ + HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ reg_val |= \ - HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ + HAL_SM(HWIO_REO_R0_MISC_CTL, \ FRAGMENT_DEST_RING, \ (reo_params)->frag_dst_ring) | \ HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ @@ -290,512 +82,293 @@ #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ ((struct rx_msdu_desc_info *) \ _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ -UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) + UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ ((struct rx_msdu_details *) \ _OFFSET_TO_BYTE_PTR((link_desc),\ UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) -#define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ - RX_MSDU_END_14_FLOW_IDX_MASK, \ - RX_MSDU_END_14_FLOW_IDX_LSB)) - -#define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ - RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ - RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) - -#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ - RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ - RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) - -#define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ - RX_MSDU_END_15_FSE_METADATA_MASK, \ - RX_MSDU_END_15_FSE_METADATA_LSB)) - -#define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ - RX_MSDU_END_16_CCE_METADATA_MASK, \ - RX_MSDU_END_16_CCE_METADATA_LSB)) - #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ (_HAL_MS( \ (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ msdu_end_tlv.rx_msdu_end), \ - RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ - RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ - RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) + RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ + RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ + RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) -/* - * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS - * Interval from rx_msdu_start - * - * @buf: pointer to the start of RX PKT TLV header - * Return: uint32_t(nss) - */ -static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_msdu_start *msdu_start = - &pkt_tlvs->msdu_start_tlv.rx_msdu_start; - uint8_t mimo_ss_bitmap; +#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ + RX_MSDU_END_10_FIRST_MSDU_MASK, \ + RX_MSDU_END_10_FIRST_MSDU_LSB)) - mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); +#define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ + RX_MSDU_END_10_LAST_MSDU_MASK, \ + RX_MSDU_END_10_LAST_MSDU_LSB)) - return qdf_get_hweight8(mimo_ss_bitmap); -} +#define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ + RX_MSDU_END_10_SA_IS_VALID_MASK, \ + RX_MSDU_END_10_SA_IS_VALID_LSB)) -/** - * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status - * - * @ hw_desc_addr: Start address of Rx HW TLVs - * @ rs: Status for monitor mode - * - * Return: void - */ -static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr, - struct mon_rx_status *rs) -{ - struct rx_msdu_start *rx_msdu_start; - struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; - uint32_t reg_value; - const uint32_t sgi_hw_to_cdp[] = { - CDP_SGI_0_8_US, - CDP_SGI_0_4_US, - CDP_SGI_1_6_US, - CDP_SGI_3_2_US, - }; +#define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ + RX_MSDU_END_10_DA_IS_VALID_MASK, \ + RX_MSDU_END_10_DA_IS_VALID_LSB)) - rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; +#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ + RX_MSDU_END_10_DA_IS_MCBC_MASK, \ + RX_MSDU_END_10_DA_IS_MCBC_LSB)) - HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); +#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ + RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ + RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) - rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, - RX_MSDU_START_5, USER_RSSI); - rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); +#define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_11_SA_IDX_OFFSET)), \ + RX_MSDU_END_11_SA_IDX_MASK, \ + RX_MSDU_END_11_SA_IDX_LSB)) - reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); - rs->sgi = sgi_hw_to_cdp[reg_value]; - reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); - rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; - /* TODO: rs->beamformed should be set for SU beamforming also */ -} +#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ + RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ + RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) -#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) -static uint32_t hal_get_link_desc_size_8074v2(void) -{ - return LINK_DESC_SIZE; -} +#define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ + RX_MSDU_END_14_CCE_METADATA_MASK, \ + RX_MSDU_END_14_CCE_METADATA_LSB)) -/* - * hal_rx_get_tlv_8074v2(): API to get the tlv - * - * @rx_tlv: TLV data extracted from the rx packet - * Return: uint8_t - */ -static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv) -{ - return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); -} - -#ifndef QCA_WIFI_QCA6018 -#define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ - (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ - PHYRX_OTHER_RECEIVE_INFO, \ - SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) - -static inline void -hal_rx_update_su_evm_info(void *rx_tlv, - void *ppdu_info_hdl) -{ - struct hal_rx_ppdu_info *ppdu_info = - (struct hal_rx_ppdu_info *)ppdu_info_hdl; - - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); - HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); -} -/** - * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2() - * -process other receive info TLV - * @rx_tlv_hdr: pointer to TLV header - * @ppdu_info: pointer to ppdu_info - * - * Return: None - */ -static -void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, - void *ppdu_info_hdl) -{ - uint16_t tlv_tag; - void *rx_tlv; - struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; - - /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the - * embedded TLVs inside - */ - rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; - tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); - - switch (tlv_tag) { - case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E: - - /* Skip TLV length to get TLV content */ - rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; - - ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, - PHYRX_OTHER_RECEIVE_INFO, - SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); - ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, - PHYRX_OTHER_RECEIVE_INFO, - SU_EVM_DETAILS_0_PILOT_COUNT); - ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, - PHYRX_OTHER_RECEIVE_INFO, - SU_EVM_DETAILS_0_NSS_COUNT); - hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); - break; - } -} -#else -static inline -void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, - void *ppdu_info_hdl) -{ -} -#endif - -#if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ - defined(WLAN_ENH_CFR_ENABLE) -static inline -void hal_rx_get_bb_info_8074v2(void *rx_tlv, - void *ppdu_info_hdl) -{ - struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; - - ppdu_info->cfr_info.bb_captured_channel = - HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); - - ppdu_info->cfr_info.bb_captured_timeout = - HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); - - ppdu_info->cfr_info.bb_captured_reason = - HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); -} - -static inline -void hal_rx_get_rtt_info_8074v2(void *rx_tlv, - void *ppdu_info_hdl) -{ - struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; - - ppdu_info->cfr_info.rx_location_info_valid = - HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, - RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); - - ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = - HAL_RX_GET(rx_tlv, - PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, - RTT_CHE_BUFFER_POINTER_LOW32); - - ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = - HAL_RX_GET(rx_tlv, - PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, - RTT_CHE_BUFFER_POINTER_HIGH8); - - ppdu_info->cfr_info.chan_capture_status = - HAL_RX_GET(rx_tlv, - PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, - RESERVED_8); -} -#endif - -/** - * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured - * human readable format. - * @ msdu_start: pointer the msdu_start TLV in pkt. - * @ dbg_level: log level. - * - * Return: void - */ -static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart, - uint8_t dbg_level) -{ - struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; - - QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, - "rx_msdu_start tlv - " - "rxpcu_mpdu_filter_in_category: %d " - "sw_frame_group_id: %d " - "phy_ppdu_id: %d " - "msdu_length: %d " - "ipsec_esp: %d " - "l3_offset: %d " - "ipsec_ah: %d " - "l4_offset: %d " - "msdu_number: %d " - "decap_format: %d " - "ipv4_proto: %d " - "ipv6_proto: %d " - "tcp_proto: %d " - "udp_proto: %d " - "ip_frag: %d " - "tcp_only_ack: %d " - "da_is_bcast_mcast: %d " - "ip4_protocol_ip6_next_header: %d " - "toeplitz_hash_2_or_4: %d " - "flow_id_toeplitz: %d " - "user_rssi: %d " - "pkt_type: %d " - "stbc: %d " - "sgi: %d " - "rate_mcs: %d " - "receive_bandwidth: %d " - "reception_type: %d " - "ppdu_start_timestamp: %d " - "sw_phy_meta_data: %d ", - msdu_start->rxpcu_mpdu_filter_in_category, - msdu_start->sw_frame_group_id, - msdu_start->phy_ppdu_id, - msdu_start->msdu_length, - msdu_start->ipsec_esp, - msdu_start->l3_offset, - msdu_start->ipsec_ah, - msdu_start->l4_offset, - msdu_start->msdu_number, - msdu_start->decap_format, - msdu_start->ipv4_proto, - msdu_start->ipv6_proto, - msdu_start->tcp_proto, - msdu_start->udp_proto, - msdu_start->ip_frag, - msdu_start->tcp_only_ack, - msdu_start->da_is_bcast_mcast, - msdu_start->ip4_protocol_ip6_next_header, - msdu_start->toeplitz_hash_2_or_4, - msdu_start->flow_id_toeplitz, - msdu_start->user_rssi, - msdu_start->pkt_type, - msdu_start->stbc, - msdu_start->sgi, - msdu_start->rate_mcs, - msdu_start->receive_bandwidth, - msdu_start->reception_type, - msdu_start->ppdu_start_timestamp, - msdu_start->sw_phy_meta_data); -} - -/** - * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured - * human readable format. - * @ msdu_end: pointer the msdu_end TLV in pkt. - * @ dbg_level: log level. - * - * Return: void - */ -static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend, - uint8_t dbg_level) -{ - struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; - - QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, - "rx_msdu_end tlv - " - "rxpcu_mpdu_filter_in_category: %d " - "sw_frame_group_id: %d " - "phy_ppdu_id: %d " - "ip_hdr_chksum: %d " - "tcp_udp_chksum: %d " - "key_id_octet: %d " - "cce_super_rule: %d " - "cce_classify_not_done_truncat: %d " - "cce_classify_not_done_cce_dis: %d " - "ext_wapi_pn_63_48: %d " - "ext_wapi_pn_95_64: %d " - "ext_wapi_pn_127_96: %d " - "reported_mpdu_length: %d " - "first_msdu: %d " - "last_msdu: %d " - "sa_idx_timeout: %d " - "da_idx_timeout: %d " - "msdu_limit_error: %d " - "flow_idx_timeout: %d " - "flow_idx_invalid: %d " - "wifi_parser_error: %d " - "amsdu_parser_error: %d " - "sa_is_valid: %d " - "da_is_valid: %d " - "da_is_mcbc: %d " - "l3_header_padding: %d " - "ipv6_options_crc: %d " - "tcp_seq_number: %d " - "tcp_ack_number: %d " - "tcp_flag: %d " - "lro_eligible: %d " - "window_size: %d " - "da_offset: %d " - "sa_offset: %d " - "da_offset_valid: %d " - "sa_offset_valid: %d " - "rule_indication_31_0: %d " - "rule_indication_63_32: %d " - "sa_idx: %d " - "msdu_drop: %d " - "reo_destination_indication: %d " - "flow_idx: %d " - "fse_metadata: %d " - "cce_metadata: %d " - "sa_sw_peer_id: %d ", - msdu_end->rxpcu_mpdu_filter_in_category, - msdu_end->sw_frame_group_id, - msdu_end->phy_ppdu_id, - msdu_end->ip_hdr_chksum, - msdu_end->tcp_udp_chksum, - msdu_end->key_id_octet, - msdu_end->cce_super_rule, - msdu_end->cce_classify_not_done_truncate, - msdu_end->cce_classify_not_done_cce_dis, - msdu_end->ext_wapi_pn_63_48, - msdu_end->ext_wapi_pn_95_64, - msdu_end->ext_wapi_pn_127_96, - msdu_end->reported_mpdu_length, - msdu_end->first_msdu, - msdu_end->last_msdu, - msdu_end->sa_idx_timeout, - msdu_end->da_idx_timeout, - msdu_end->msdu_limit_error, - msdu_end->flow_idx_timeout, - msdu_end->flow_idx_invalid, - msdu_end->wifi_parser_error, - msdu_end->amsdu_parser_error, - msdu_end->sa_is_valid, - msdu_end->da_is_valid, - msdu_end->da_is_mcbc, - msdu_end->l3_header_padding, - msdu_end->ipv6_options_crc, - msdu_end->tcp_seq_number, - msdu_end->tcp_ack_number, - msdu_end->tcp_flag, - msdu_end->lro_eligible, - msdu_end->window_size, - msdu_end->da_offset, - msdu_end->sa_offset, - msdu_end->da_offset_valid, - msdu_end->sa_offset_valid, - msdu_end->rule_indication_31_0, - msdu_end->rule_indication_63_32, - msdu_end->sa_idx, - msdu_end->msdu_drop, - msdu_end->reo_destination_indication, - msdu_end->flow_idx, - msdu_end->fse_metadata, - msdu_end->cce_metadata, - msdu_end->sa_sw_peer_id); -} - - -/* - * Get tid from RX_MPDU_START - */ -#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ - RX_MPDU_INFO_3_TID_OFFSET)), \ - RX_MPDU_INFO_3_TID_MASK, \ - RX_MPDU_INFO_3_TID_LSB)) - -static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_mpdu_start *mpdu_start = - &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; - uint32_t tid; - - tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); - - return tid; -} - -#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ - (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ - RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ - RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ - RX_MSDU_START_5_RECEPTION_TYPE_LSB)) - -/* - * hal_rx_msdu_start_reception_type_get(): API to get the reception type - * Interval from rx_msdu_start - * - * @buf: pointer to the start of RX PKT TLV header - * Return: uint32_t(reception_type) - */ -static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_msdu_start *msdu_start = - &pkt_tlvs->msdu_start_tlv.rx_msdu_start; - uint32_t reception_type; - - reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); - - return reception_type; -} - -/* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ - RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ - RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ - RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) - /** - * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx - * from rx_msdu_end TLV - * - * @ buf: pointer to the start of RX PKT TLV headers - * Return: da index - */ -static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf) -{ - struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; - struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; - uint16_t da_idx; + RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ + RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ + RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) - da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); +#define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), \ + RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, \ + RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)) \ - return da_idx; -} +#define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ + RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ + RX_MPDU_INFO_10_SW_PEER_ID_LSB)) + +#define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ + RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) + +#define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ + RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ + RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) + +#define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ + RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ + RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) + +#define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ + RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ + RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) + +#define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ + RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ + RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) + +#define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ + RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ + RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) + +#define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ + RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ + RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) + +#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) + +#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) + +#define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) + +#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) + +#define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ + RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ + RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) + +#define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_FR_DS_OFFSET)), \ + RX_MPDU_INFO_11_FR_DS_MASK, \ + RX_MPDU_INFO_11_FR_DS_LSB)) + +#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_TO_DS_OFFSET)), \ + RX_MPDU_INFO_11_TO_DS_MASK, \ + RX_MPDU_INFO_11_TO_DS_LSB)) + +#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) + +#define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ + RX_MPDU_INFO_3_PN_31_0_MASK, \ + RX_MPDU_INFO_3_PN_31_0_LSB)) + +#define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ + RX_MPDU_INFO_4_PN_63_32_MASK, \ + RX_MPDU_INFO_4_PN_63_32_LSB)) + +#define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ + RX_MPDU_INFO_5_PN_95_64_MASK, \ + RX_MPDU_INFO_5_PN_95_64_LSB)) + +#define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ + RX_MPDU_INFO_6_PN_127_96_MASK, \ + RX_MPDU_INFO_6_PN_127_96_LSB)) + +#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ + RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ + RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) + +#define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ + RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ + RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) + +#define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ + RX_MSDU_END_12_FLOW_IDX_MASK, \ + RX_MSDU_END_12_FLOW_IDX_LSB)) + +#define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ + RX_MSDU_END_13_FSE_METADATA_MASK, \ + RX_MSDU_END_13_FSE_METADATA_LSB)) + +#define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)), \ + RX_MPDU_INFO_9_PHY_PPDU_ID_MASK, \ + RX_MPDU_INFO_9_PHY_PPDU_ID_LSB)) \ + +#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ + RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ + RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ + RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) + +#ifdef GET_MSDU_AGGREGATION +#define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ +{\ + struct rx_msdu_end *rx_msdu_end;\ + bool first_msdu, last_msdu; \ + rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ + first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\ + last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\ + if (first_msdu && last_msdu)\ + rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ + else\ + rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ +} \ + +#else +#define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) +#endif + +#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_7_TID_OFFSET)), \ + RX_MPDU_INFO_7_TID_MASK, \ + RX_MPDU_INFO_7_TID_LSB)) + +#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ + RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ + RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ + RX_MSDU_START_5_RECEPTION_TYPE_LSB)) diff --git a/hal/wifi3.0/qcn9100/hal_qcn9100_tx.h b/hal/wifi3.0/qcn9100/hal_qcn9100_tx.h index 3957c37c17cf..786961d3df7d 100644 --- a/hal/wifi3.0/qcn9100/hal_qcn9100_tx.h +++ b/hal/wifi3.0/qcn9100/hal_qcn9100_tx.h @@ -24,28 +24,26 @@ #include "hal_api_mon.h" /** - * hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion + * hal_tx_desc_set_dscp_tid_table_id_9100() - Sets DSCP to TID conversion * table ID * @desc: Handle to Tx Descriptor * @id: DSCP to tid conversion table to be used for this frame * * Return: void */ - -static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id) +static void hal_tx_desc_set_dscp_tid_table_id_9100(void *desc, uint8_t id) { HAL_SET_FLD(desc, TCL_DATA_CMD_5, - DSCP_TID_TABLE_NUM) |= - HAL_TX_SM(TCL_DATA_CMD_5, - DSCP_TID_TABLE_NUM, id); + DSCP_TID_TABLE_NUM) |= + HAL_TX_SM(TCL_DATA_CMD_5, DSCP_TID_TABLE_NUM, id); } - #define DSCP_TID_TABLE_SIZE 24 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 + /** - * hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table + * hal_tx_set_dscp_tid_map_9100() - Configure default DSCP to TID map table * @soc: HAL SoC context * @map: DSCP-TID mapping table * @id: mapping table ID - 0,1 @@ -57,10 +55,8 @@ static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id) * * Return: none */ - -static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc, - uint8_t *map, - uint8_t id) +static void hal_tx_set_dscp_tid_map_9100(struct hal_soc *soc, + uint8_t *map, uint8_t id) { int i; uint32_t addr, cmn_reg_addr; @@ -115,7 +111,7 @@ static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc, } /** - * hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as + * hal_tx_update_dscp_tid_9100() - Update the dscp tid map table as updated by user * @soc: HAL SoC context * @map: DSCP-TID mapping table @@ -124,15 +120,16 @@ static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc, * * Return: void */ -static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid, - uint8_t id, uint8_t dscp) +static void hal_tx_update_dscp_tid_9100(struct hal_soc *soc, uint8_t tid, + uint8_t id, uint8_t dscp) { - uint32_t addr, addr1, cmn_reg_addr, regmask = 0xFFFFFFFF; + uint32_t addr, addr1, cmn_reg_addr; uint32_t start_value = 0, end_value = 0; uint32_t regval; uint8_t end_bits = 0; uint8_t start_bits = 0; uint32_t start_index, end_index; + cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); @@ -169,7 +166,7 @@ static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid, regval = HAL_REG_READ(soc, addr); if (end_index < start_index) - regval &= (regmask >> start_bits); + regval &= (~0) >> start_bits; else regval &= ~(7 << start_index); @@ -194,7 +191,7 @@ static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid, } /** - * hal_tx_desc_set_lmac_id - Set the lmac_id value + * hal_tx_desc_set_lmac_id_9100 - Set the lmac_id value * @desc: Handle to Tx Descriptor * @lmac_id: mac Id to ast matching * b00 – mac 0 @@ -204,21 +201,22 @@ static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid, * * Return: void */ -static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id) +static void hal_tx_desc_set_lmac_id_9100(void *desc, uint8_t lmac_id) { HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); } /** - * hal_tx_init_cmd_credit_ring_8074v2() - Initialize command/credit SRNG + * hal_tx_init_cmd_credit_ring_9100() - Initialize TCL command/credit SRNG * @hal_soc_hdl: Handle to HAL SoC structure * @hal_srng: Handle to HAL SRNG structure * * Return: none */ -static inline void hal_tx_init_cmd_credit_ring_8074v2(hal_soc_handle_t hal_soc_hdl, - hal_ring_handle_t hal_ring_hdl) +static inline void +hal_tx_init_cmd_credit_ring_9100(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl) { uint8_t *desc_addr; struct hal_srng_params srng_params;