mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
arm/dts: Rhodep/panel: update tianma nt37701 6.55 inch panel code
1. update tianma nt37701 v1 panel dc code 2. add SOE code for tianma nt37701 6.55 inch v1 panel 3.add tianma nt37701 6.55 inch v2 panel code Change-Id: If3a5d9778a557dfe058f6d6a33ebdf26750ed2e1 Signed-off-by: houdz1 <houdz1@lenovo.com> Reviewed-on: https://gerrit.mot.com/2162253 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Yeqing Wang <wangyq13@motorola.com> Reviewed-by: Guobin Zhang <zhanggb@motorola.com> Submit-Approved: Jira Key
This commit is contained in:
houdz1
panyq6
parent
ef3f48ff9c
commit
67af48ce6a
4 changed files with 1844 additions and 923 deletions
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/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&mdss_mdp {
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mot_tm_nt37701_655_1080x2400_dsc_cmd_v2: qcom,mdss_dsi_mot_tm_nt37701_655_1080x2400_dsc_cmd_v2 {
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compatible = "qcom,mdss-dsi-panel";
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qcom,mdss-dsi-panel-name = "mipi_mot_cmd_tm_1080p_dsc_655";
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qcom,mdss-dsi-panel-supplier = "tianma";
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qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
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qcom,mdss-dsi-virtual-channel-id = <0>;
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qcom,mdss-dsi-stream = <0>;
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qcom,mdss-pan-physical-width-dimension = <68>;
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qcom,mdss-pan-physical-height-dimension = <152>;
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qcom,mdss-dsi-bpp = <30>;
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qcom,mdss-dsi-underflow-color = <0xff>;
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qcom,mdss-dsi-border-color = <0>;
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qcom,mdss-dsi-panel-param-verision = <121201>;
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qcom,mdss-dsi-panel-param-num = <5>;
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qcom,dsi-ctrl-num = <0>;
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qcom,dsi-phy-num = <0>;
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qcom,mdss-dsi-traffic-mode = "burst_mode";
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qcom,mdss-dsi-bllp-eof-power-mode;
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qcom,mdss-dsi-bllp-power-mode;
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qcom,mdss-dsi-lane-0-state;
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qcom,mdss-dsi-lane-1-state;
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qcom,mdss-dsi-lane-2-state;
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qcom,mdss-dsi-lane-3-state;
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qcom,mdss-dsi-dma-trigger = "trigger_sw";
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qcom,mdss-dsi-mdp-trigger = "none";
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qcom,mdss-dsi-reset-sequence = <0 11>, <1 1>, <0 1>, <1 11>;
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qcom,mdss-dsi-lp11-init;
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qcom,mdss-dsi-tx-eot-append;
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qcom,mdss-dsi-te-pin-select = <1>;
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qcom,mdss-dsi-te-dcs-command = <1>;
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qcom,mdss-dsi-te-using-te-pin;
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qcom,bklt-dcs-2bytes-enabled;
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qcom,mdss-dsi-bl-min-level = <3>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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/*qcom,mdss-dsi-panel-hdr-enabled;
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qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
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17000 15500 30000 8000 3000>;
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qcom,mdss-dsi-panel-peak-brightness = <4200000>;
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qcom,mdss-dsi-panel-blackness-level = <3230>;*/
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qcom,mdss-dsi-hbm-on-command = [
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39 01 00 00 00 00 03 51 0F FF];
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qcom,mdss-dsi-hbm-off-command = [
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39 01 00 00 00 00 03 51 0D BA];
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qcom,mdss-dsi-hbm-fod;
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qcom,mdss-dsi-hbm-fod-on-command = [
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39 01 00 00 00 00 03 51 0F FF];
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//qcom,mdss-dsi-acl-on-command = [
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// 39 01 00 00 00 00 06 F0 55 AA 52 08 00
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// 15 00 00 00 00 00 02 B0 0C
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// 15 01 00 00 00 00 02 55 05];
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//qcom,mdss-dsi-acl-off-command = [
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// 15 01 00 00 00 00 02 55 00];
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qcom,mdss-dsi-dc-off-command = [
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 B2 51
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15 00 00 00 00 00 02 6F 0F
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39 00 00 00 00 00 07 B2 60 50 66 91 86 91
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39 00 00 00 00 00 0D B3 00 08 01 5F 01 5F 02 A4 02 A4 03 BB
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15 00 00 00 00 00 02 6F 0C
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39 00 00 00 00 00 0D B3 03 BB 05 2F 05 2F 06 91 06 91 06 92
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15 00 00 00 00 00 02 6F 18
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39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
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15 01 00 00 00 00 02 58 00];
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qcom,mdss-dsi-dc-off-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-dc-on-command = [
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 B2 81
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15 00 00 00 00 00 02 6F 0F
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39 00 00 00 00 00 07 B2 00 00 06 91 06 91
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39 00 00 00 00 00 0D B3 00 00 00 00 00 00 00 00 00 00 00 00
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15 00 00 00 00 00 02 6F 0C
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39 00 00 00 00 00 0D B3 00 00 00 00 00 00 00 00 00 00 00 00
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15 00 00 00 00 00 02 6F 18
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39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
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15 01 00 00 00 00 02 58 01];
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qcom,mdss-dsi-dc-on-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-display-timings {
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timing@0{
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qcom,mdss-dsi-cmd-mode;
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qcom,mdss-dsi-panel-framerate = <48>;
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qcom,mdss-dsi-panel-width = <1080>;
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qcom,mdss-dsi-panel-height = <2400>;
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qcom,mdss-dsi-h-front-porch = <32>;
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qcom,mdss-dsi-h-back-porch = <32>;
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qcom,mdss-dsi-h-pulse-width = <16>;
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qcom,mdss-dsi-h-sync-skew = <0>;
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qcom,mdss-dsi-h-sync-pulse = <0>;
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qcom,mdss-dsi-v-back-porch = <4>;
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qcom,mdss-dsi-v-front-porch = <12>;
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qcom,mdss-dsi-v-pulse-width = <4>;
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qcom,mdss-dsi-h-left-border = <0>;
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qcom,mdss-dsi-h-right-border = <0>;
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qcom,mdss-dsi-v-top-border = <0>;
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qcom,mdss-dsi-v-bottom-border = <0>;
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qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
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qcom,mdss-dsi-timing-switch-command = [
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15 01 00 00 14 00 02 2F 08 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
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// FFD2.0 RGB OFS CTRL
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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39 00 00 00 00 00 06 E1 00 03 03 03 00
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39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
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39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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//FFD SPR Pixel Type Setting
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15 00 00 00 00 00 02 6F 04
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15 00 00 00 00 00 02 C1 00
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//FFD RAM Setting, RAMOFF_IDLE_DMR
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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39 00 00 00 00 00 04 C0 0E B3 20
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//ODS part
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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15 00 00 00 00 00 02 6F 03
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15 00 00 00 00 00 02 C1 03
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39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
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qcom,mdss-dsi-on-command = [
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 6F 06
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39 01 00 00 00 00 04 B5 00 18 50 //swire pulse
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 B2 51
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15 00 00 00 00 00 02 6F 0F
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39 00 00 00 00 00 07 B2 60 50 66 91 86 91
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39 00 00 00 00 00 0D B3 00 08 01 5F 01 5F 02 A4 02 A4 03 BB
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15 00 00 00 00 00 02 6F 0C
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39 00 00 00 00 00 0D B3 03 BB 05 2F 05 2F 06 91 06 91 06 92
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15 00 00 00 00 00 02 6F 18
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39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
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15 01 00 00 00 00 02 58 00 //DC off
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 6F 02
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39 01 00 00 00 00 03 C1 00 60
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15 00 00 00 00 00 02 6F 08
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15 00 00 00 00 00 02 C3 04
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39 00 00 00 00 00 06 F0 55 AA 52 08 03
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39 00 00 00 00 00 05 BC 11 00 09 51
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15 00 00 00 00 00 02 6F 04
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39 00 00 00 00 00 0A BC 00 09 51 00 09 51 00 0B 41
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15 00 00 00 00 00 02 6F 0D
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39 01 00 00 00 00 04 BC 00 11 51
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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39 00 00 00 00 00 0D C6 66 66 66 66 66 66 66 66 66 66 66 66
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 6F 1C
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39 00 00 00 00 00 06 C0 15 0A 38 27 49
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15 00 00 00 00 00 02 03 01
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15 00 00 00 00 00 02 90 01
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39 00 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
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15 00 00 00 00 00 02 2C 00 //dsc config 10bit
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15 00 00 00 00 00 02 6F 01
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39 01 00 00 00 00 05 88 02 1C 08 73 //Local HBM X/Y
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15 01 00 00 00 00 02 5F 00
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39 01 00 00 00 00 03 51 00 00
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15 01 00 00 00 00 02 53 20
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15 01 00 00 00 00 02 35 00 //te enable
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39 01 00 00 00 00 05 2A 00 00 04 37
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39 01 00 00 00 00 05 2B 00 00 09 5F
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15 01 00 00 00 00 02 2F 08 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
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// FFD2.0 RGB OFS CTRL
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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39 00 00 00 00 00 06 E1 00 03 03 03 00
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39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
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39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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//FFD SPR Pixel Type Setting
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15 00 00 00 00 00 02 6F 04
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15 00 00 00 00 00 02 C1 00
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//FFD RAM Setting, RAMOFF_IDLE_DMR
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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39 00 00 00 00 00 04 C0 0E B3 20
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//ODS part
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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15 00 00 00 00 00 02 6F 03
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15 00 00 00 00 00 02 C1 03
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39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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05 01 00 00 78 00 01 11
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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15 00 00 00 00 00 02 E1 A1
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05 01 00 00 00 00 01 29]; /* display on */
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qcom,mdss-dsi-off-command = [
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05 01 00 00 00 00 01 28 /* display_off */
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05 01 00 00 78 00 01 10]; /* enter sleep mode */
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qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-timing-switch-command-state =
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"dsi_lp_mode";
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qcom,compression-mode = "dsc";
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/* Why QCOM doesn't use this, even it used 2 encoder
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* as for that dsi_sw43404_amoled_cmd, for ex */
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/* qcom,mdss-dsc-encoders = <2>; */
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qcom,mdss-dsc-version = <0x11>;
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qcom,mdss-dsc-slice-height = <12>;
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qcom,mdss-dsc-slice-width = <1080>;
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qcom,mdss-dsc-slice-per-pkt = <1>;
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qcom,mdss-dsc-bit-per-component = <10>;
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qcom,mdss-dsc-bit-per-pixel = <8>;
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qcom,mdss-dsc-block-prediction-enable;
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};
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timing@1{
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qcom,mdss-dsi-cmd-mode;
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qcom,mdss-dsi-panel-framerate = <60>;
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qcom,mdss-dsi-panel-width = <1080>;
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qcom,mdss-dsi-panel-height = <2400>;
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qcom,mdss-dsi-h-front-porch = <32>;
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qcom,mdss-dsi-h-back-porch = <32>;
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qcom,mdss-dsi-h-pulse-width = <16>;
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qcom,mdss-dsi-h-sync-skew = <0>;
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qcom,mdss-dsi-h-sync-pulse = <0>;
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qcom,mdss-dsi-v-back-porch = <4>;
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qcom,mdss-dsi-v-front-porch = <12>;
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qcom,mdss-dsi-v-pulse-width = <4>;
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qcom,mdss-dsi-h-left-border = <0>;
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qcom,mdss-dsi-h-right-border = <0>;
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qcom,mdss-dsi-v-top-border = <0>;
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qcom,mdss-dsi-v-bottom-border = <0>;
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qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
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qcom,mdss-dsi-timing-switch-command = [
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15 01 00 00 10 00 02 2F 03 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
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// FFD2.0 RGB OFS CTRL
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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39 00 00 00 00 00 06 E1 00 03 03 03 00
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39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
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39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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//FFD SPR Pixel Type Setting
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15 00 00 00 00 00 02 6F 04
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15 00 00 00 00 00 02 C1 00
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//FFD RAM Setting, RAMOFF_IDLE_DMR
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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39 00 00 00 00 00 04 C0 0E B3 20
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//ODS part
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39 00 00 00 00 00 06 F0 55 AA 52 08 08
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15 00 00 00 00 00 02 6F 03
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15 00 00 00 00 00 02 C1 03
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39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
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qcom,mdss-dsi-on-command = [
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 6F 06
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39 01 00 00 00 00 04 B5 00 18 50 //swire pulse
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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15 00 00 00 00 00 02 B2 51
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15 00 00 00 00 00 02 6F 0F
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39 00 00 00 00 00 07 B2 60 50 66 91 86 91
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39 00 00 00 00 00 0D B3 00 08 01 5F 01 5F 02 A4 02 A4 03 BB
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||||
15 00 00 00 00 00 02 6F 0C
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||||
39 00 00 00 00 00 0D B3 03 BB 05 2F 05 2F 06 91 06 91 06 92
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||||
15 00 00 00 00 00 02 6F 18
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||||
39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
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||||
15 01 00 00 00 00 02 58 00 //DC off
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||||
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39 00 00 00 00 00 06 F0 55 AA 52 08 00
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||||
15 00 00 00 00 00 02 6F 02
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||||
39 01 00 00 00 00 03 C1 00 60
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||||
15 00 00 00 00 00 02 6F 08
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||||
15 00 00 00 00 00 02 C3 04
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||||
39 00 00 00 00 00 06 F0 55 AA 52 08 03
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||||
39 00 00 00 00 00 05 BC 11 00 09 51
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||||
15 00 00 00 00 00 02 6F 04
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||||
39 00 00 00 00 00 0A BC 00 09 51 00 09 51 00 0B 41
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||||
15 00 00 00 00 00 02 6F 0D
|
||||
39 01 00 00 00 00 04 BC 00 11 51
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||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 0D C6 66 66 66 66 66 66 66 66 66 66 66 66
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||||
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||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 1C
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||||
39 00 00 00 00 00 06 C0 15 0A 38 27 49
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||||
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||||
15 00 00 00 00 00 02 03 01
|
||||
15 00 00 00 00 00 02 90 01
|
||||
39 00 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 00 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 00 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 05 88 02 1C 08 73 //Local HBM X/Y
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
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||||
15 01 00 00 00 00 02 35 00 //te enable
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||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 03 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@2{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 0b 00 02 2F 07 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 04 B5 00 18 50 //swire pulse
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 B2 51
|
||||
15 00 00 00 00 00 02 6F 0F
|
||||
39 00 00 00 00 00 07 B2 60 50 66 91 86 91
|
||||
39 00 00 00 00 00 0D B3 00 08 01 5F 01 5F 02 A4 02 A4 03 BB
|
||||
15 00 00 00 00 00 02 6F 0C
|
||||
39 00 00 00 00 00 0D B3 03 BB 05 2F 05 2F 06 91 06 91 06 92
|
||||
15 00 00 00 00 00 02 6F 18
|
||||
39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
|
||||
15 01 00 00 00 00 02 58 00 //DC off
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 03 C1 00 60
|
||||
15 00 00 00 00 00 02 6F 08
|
||||
15 00 00 00 00 00 02 C3 04
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 00 00 00 00 00 05 BC 11 00 09 51
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
39 00 00 00 00 00 0A BC 00 09 51 00 09 51 00 0B 41
|
||||
15 00 00 00 00 00 02 6F 0D
|
||||
39 01 00 00 00 00 04 BC 00 11 51
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 0D C6 66 66 66 66 66 66 66 66 66 66 66 66
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 1C
|
||||
39 00 00 00 00 00 06 C0 15 0A 38 27 49
|
||||
|
||||
15 00 00 00 00 00 02 03 01
|
||||
15 00 00 00 00 00 02 90 01
|
||||
39 00 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 00 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 00 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 05 88 02 1C 08 73 //Local HBM X/Y
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 07 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@3{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 08 00 02 2F 02 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 06 00 02 6F 04
|
||||
15 00 00 00 06 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 06 00 02 6F 03
|
||||
15 00 00 00 06 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 04 B5 00 18 50 //swire pulse
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 B2 51
|
||||
15 00 00 00 00 00 02 6F 0F
|
||||
39 00 00 00 00 00 07 B2 60 50 66 91 86 91
|
||||
39 00 00 00 00 00 0D B3 00 08 01 5F 01 5F 02 A4 02 A4 03 BB
|
||||
15 00 00 00 00 00 02 6F 0C
|
||||
39 00 00 00 00 00 0D B3 03 BB 05 2F 05 2F 06 91 06 91 06 92
|
||||
15 00 00 00 00 00 02 6F 18
|
||||
39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
|
||||
15 01 00 00 00 00 02 58 00 //DC off
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 03 C1 00 60
|
||||
15 00 00 00 00 00 02 6F 08
|
||||
15 00 00 00 00 00 02 C3 04
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 00 00 00 00 00 05 BC 11 00 09 51
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
39 00 00 00 00 00 0A BC 00 09 51 00 09 51 00 0B 41
|
||||
15 00 00 00 00 00 02 6F 0D
|
||||
39 01 00 00 00 00 04 BC 00 11 51
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 0D C6 66 66 66 66 66 66 66 66 66 66 66 66
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 1C
|
||||
39 00 00 00 00 00 06 C0 15 0A 38 27 49
|
||||
|
||||
15 00 00 00 00 00 02 03 01
|
||||
15 00 00 00 00 00 02 90 01
|
||||
39 00 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 00 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 00 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 05 88 02 1C 08 73 //Local HBM X/Y
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 02 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 06 00 02 6F 04
|
||||
15 00 00 00 06 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 06 00 02 6F 03
|
||||
15 00 00 00 06 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
/*timing@4{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; // 90fps +/- 2
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 06 00 02 2F 04 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 86 86 06 F8 54 34 33 12 01 11 51 00 00 03 00 04 40 00 BC
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 06 00 02 6F 04
|
||||
15 00 00 00 06 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 06 00 02 6F 03
|
||||
15 00 00 00 06 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 04 B5 00 18 50 //swire pulse
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 B2 51
|
||||
15 00 00 00 00 00 02 6F 0F
|
||||
39 00 00 00 00 00 07 B2 60 50 66 91 86 91
|
||||
39 00 00 00 00 00 0D B3 00 08 01 5F 01 5F 02 A4 02 A4 03 BB
|
||||
15 00 00 00 00 00 02 6F 0C
|
||||
39 00 00 00 00 00 0D B3 03 BB 05 2F 05 2F 06 91 06 91 06 92
|
||||
15 00 00 00 00 00 02 6F 18
|
||||
39 00 00 00 00 00 0D B3 06 92 0A 2F 0A 2F 0D B9 0D B9 0F FF
|
||||
15 01 00 00 00 00 02 58 00 //DC off
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 03 C1 00 60
|
||||
15 00 00 00 00 00 02 6F 08
|
||||
15 00 00 00 00 00 02 C3 04
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 00 00 00 00 00 05 BC 11 00 09 51
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
39 00 00 00 00 00 0A BC 00 09 51 00 09 51 00 0B 41
|
||||
15 00 00 00 00 00 02 6F 0D
|
||||
39 01 00 00 00 00 04 BC 00 11 51
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 0D C6 66 66 66 66 66 66 66 66 66 66 66 66
|
||||
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 00 00 00 00 00 02 6F 1C
|
||||
39 00 00 00 00 00 06 C0 15 0A 38 27 49
|
||||
|
||||
15 00 00 00 00 00 02 03 01
|
||||
15 00 00 00 00 00 02 90 01
|
||||
39 00 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 00 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 00 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 05 88 02 1C 08 73 //Local HBM X/Y
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 04 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 06 E1 00 03 03 03 00
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 86 86 06 F8 54 34 33 12 01 11 51 00 00 03 00 04 40 00 BC
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 06 00 02 6F 04
|
||||
15 00 00 00 06 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 06 00 02 6F 03
|
||||
15 00 00 00 06 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; // display on
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 // display_off
|
||||
05 01 00 00 78 00 01 10]; // enter sleep mode
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
// Why QCOM doesn't use this, even it used 2 encoder
|
||||
// as for that dsi_sw43404_amoled_cmd, for ex
|
||||
// qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};*/
|
||||
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -10,419 +10,416 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
&mdss_mdp {
|
||||
mot_tm_nt37701_655_1080x2400_dsc_cmd_v0: qcom,mdss_dsi_mot_tm_nt37701_655_1080x2400_dsc_cmd_v0 {
|
||||
compatible = "qcom,mdss-dsi-panel";
|
||||
qcom,mdss-dsi-panel-name = "mipi_mot_cmd_tm_1080p_dsc_655";
|
||||
qcom,mdss-dsi-panel-supplier = "tianma";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-pan-physical-width-dimension = <68>;
|
||||
qcom,mdss-pan-physical-height-dimension = <152>;
|
||||
qcom,mdss-dsi-bpp = <30>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-panel-param-verision = <121201>;
|
||||
qcom,mdss-dsi-panel-param-num = <5>;
|
||||
mot_tm_nt37701_655_1080x2400_dsc_cmd_v0: qcom,mdss_dsi_mot_tm_nt37701_655_1080x2400_dsc_cmd_v0 {
|
||||
compatible = "qcom,mdss-dsi-panel";
|
||||
qcom,mdss-dsi-panel-name = "mipi_mot_cmd_tm_1080p_dsc_655";
|
||||
qcom,mdss-dsi-panel-supplier = "tianma";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-pan-physical-width-dimension = <68>;
|
||||
qcom,mdss-pan-physical-height-dimension = <152>;
|
||||
qcom,mdss-dsi-bpp = <30>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-panel-param-verision = <121201>;
|
||||
qcom,mdss-dsi-panel-param-num = <5>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <0 11>, <1 1>, <0 1>, <1 11>;
|
||||
qcom,mdss-dsi-lp11-init;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <0 11>, <1 1>, <0 1>, <1 11>;
|
||||
qcom,mdss-dsi-lp11-init;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
|
||||
qcom,bklt-dcs-2bytes-enabled;
|
||||
qcom,mdss-dsi-bl-min-level = <3>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bklt-dcs-2bytes-enabled;
|
||||
qcom,mdss-dsi-bl-min-level = <3>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
|
||||
/*qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
/*qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;*/
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;*/
|
||||
|
||||
qcom,mdss-dsi-hbm-on-command = [
|
||||
39 01 00 00 00 00 03 51 0F FF];
|
||||
qcom,mdss-dsi-hbm-off-command = [
|
||||
39 01 00 00 00 00 03 51 07 FF];
|
||||
qcom,mdss-dsi-hbm-on-command = [
|
||||
39 01 00 00 00 00 03 51 0F FF];
|
||||
qcom,mdss-dsi-hbm-off-command = [
|
||||
39 01 00 00 00 00 03 51 07 FF];
|
||||
|
||||
qcom,mdss-dsi-hbm-fod;
|
||||
qcom,mdss-dsi-hbm-fod-on-command = [
|
||||
39 01 00 00 00 00 03 51 0F FF];
|
||||
qcom,mdss-dsi-hbm-fod;
|
||||
qcom,mdss-dsi-hbm-fod-on-command = [
|
||||
39 01 00 00 00 00 03 51 0F FF];
|
||||
|
||||
//qcom,mdss-dsi-acl-on-command = [
|
||||
// 39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
// 15 00 00 00 00 00 02 B0 0C
|
||||
// 15 01 00 00 00 00 02 55 05];
|
||||
//qcom,mdss-dsi-acl-off-command = [
|
||||
// 15 01 00 00 00 00 02 55 00];
|
||||
//qcom,mdss-dsi-acl-on-command = [
|
||||
// 39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
// 15 00 00 00 00 00 02 B0 0C
|
||||
// 15 01 00 00 00 00 02 55 05];
|
||||
//qcom,mdss-dsi-acl-off-command = [
|
||||
// 15 01 00 00 00 00 02 55 00];
|
||||
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <48>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 14 00 02 2F 08 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <48>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 14 00 02 2F 08 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
39 01 00 00 00 00 05 3B 00 10 00 20
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 08 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
15 01 00 00 00 00 02 2F 08 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@1{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 10 00 02 2F 01 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
39 01 00 00 00 00 05 3B 00 10 00 20
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 01 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@2{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 0b 00 02 2F 03 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
39 01 00 00 00 00 05 3B 00 10 00 20
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 03 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@3{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 08 00 02 2F 02 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
39 01 00 00 00 00 05 3B 00 10 00 04
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 02 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
/*timing@4{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; // 90fps +/- 2
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 06 00 02 2F 04 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
39 01 00 00 00 00 05 3B 00 10 00 04
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 04 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; // display on
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 // display_off
|
||||
05 01 00 00 78 00 01 10]; // enter sleep mode
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
// Why QCOM doesn't use this, even it used 2 encoder
|
||||
// as for that dsi_sw43404_amoled_cmd, for ex
|
||||
// qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};*/
|
||||
};
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@1{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 10 00 02 2F 01 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 01 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@2{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 0b 00 02 2F 03 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 03 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
timing@3{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 08 00 02 2F 02 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 02 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
05 01 00 00 78 00 01 10]; /* enter sleep mode */
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
/* Why QCOM doesn't use this, even it used 2 encoder
|
||||
* as for that dsi_sw43404_amoled_cmd, for ex */
|
||||
/* qcom,mdss-dsc-encoders = <2>; */
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
/*timing@4{
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <32>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; // 90fps +/- 2
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 06 00 02 2F 04 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
15 01 00 00 00 00 02 6F 1C
|
||||
39 01 00 00 00 00 06 C0 15 27 38 49 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 04
|
||||
15 01 00 00 00 00 02 CB 86
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 03 CD 05 62
|
||||
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 90 01
|
||||
39 01 00 00 00 00 13 91 AB 28 00 0C C2 00 03 1C 01 7E 00 0F 08 BB 04 3D 10 F0
|
||||
15 01 00 00 00 00 02 2C 00 //dsc config 10bit
|
||||
|
||||
15 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
15 01 00 00 00 00 02 53 20
|
||||
15 01 00 00 00 00 02 35 00 //te enable
|
||||
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 04 //08:49Hz 01:60Hz 03:90Hz 02:120Hz 04:144Hz
|
||||
|
||||
05 01 00 00 C8 00 01 11
|
||||
05 01 00 00 00 00 01 29]; // display on
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 // display_off
|
||||
05 01 00 00 78 00 01 10]; // enter sleep mode
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,compression-mode = "dsc";
|
||||
// Why QCOM doesn't use this, even it used 2 encoder
|
||||
// as for that dsi_sw43404_amoled_cmd, for ex
|
||||
// qcom,mdss-dsc-encoders = <2>;
|
||||
qcom,mdss-dsc-version = <0x11>;
|
||||
qcom,mdss-dsc-slice-height = <12>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};*/
|
||||
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
#include "dsi-panel-mot-csot-nt37701-655-1080x2400-dsc-cmd-common-v1.dtsi"
|
||||
#include "dsi-panel-mot-tianma-nt37701-655-1080x2400-dsc-cmd-common.dtsi"
|
||||
#include "dsi-panel-mot-tianma-nt37701-655-1080x2400-dsc-cmd-common-v1.dtsi"
|
||||
#include "dsi-panel-mot-tianma-nt37701-655-1080x2400-dsc-cmd-common-v2.dtsi"
|
||||
#include "dsi-panel-mot-dummy-qhd-video.dtsi"
|
||||
|
||||
&display_panel_avdd {
|
||||
|
|
@ -174,6 +175,72 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mot_tm_nt37701_655_1080x2400_dsc_cmd_v2 {
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "te_chk_reg_rd";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>;
|
||||
qcom,mdss-dsi-no-panel-on-read-support;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <9>;
|
||||
qcom,mdss-dsi-bl-max-level = <3514>;
|
||||
qcom,mdss-dsi-bl-default-level = <1757>;
|
||||
qcom,mdss-brightness-max-level = <3514>;
|
||||
qcom,platform-te-gpio = <&tlmm 23 0>;
|
||||
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
|
||||
qcom,bl-dsc-cmd-state = "dsi_hs_mode";
|
||||
|
||||
/*qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14950 15750 34000
|
||||
16000 13000 35500 7000 2500>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <5000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <100>;*/
|
||||
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
//qcom,mdss-dsi-panel-clockrate = <320000000>;
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0D 03 03 10 1D 04
|
||||
03 02 02 04 00 0C 08];
|
||||
};
|
||||
timing@1 {
|
||||
//qcom,mdss-dsi-panel-clockrate = <400000000>;
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1E 04
|
||||
04 03 02 04 00 0E 08];
|
||||
};
|
||||
timing@2 {
|
||||
//qcom,mdss-dsi-panel-clockrate = <601000000>;
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1F 06
|
||||
06 06 02 04 00 13 0A];
|
||||
};
|
||||
timing@3 {
|
||||
//qcom,mdss-dsi-panel-clockrate = <801000000>;
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 17 15 07
|
||||
07 08 02 04 00 18 0C];
|
||||
};
|
||||
/*timing@4 {
|
||||
//qcom,mdss-dsi-panel-clockrate = <961000000>;
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 19 17 08
|
||||
08 09 02 04 00 1C 0D];
|
||||
};*/
|
||||
};
|
||||
};
|
||||
|
||||
&mot_tm_nt37701_655_1080x2400_dsc_cmd_v1 {
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "te_chk_reg_rd";
|
||||
|
|
|
|||
Loading…
Reference in a new issue