From 66265b505b6ea8e3380c1601c3c5c380328c87d0 Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Wed, 28 Oct 2020 19:39:42 +0530 Subject: [PATCH 1/4] msm: vidc: yupik: Add platform data Add driver platform data for yupik yupik_v0: 4k@60 Dec, 4k@30 Enc Concurrency: 4k@30 Dec + 1080p@30 Enc yupik_v1: 4k@30 Dec/Enc Concurrency: UHD@30 Dec + 1080p@30 Enc DDR5 UBWC3.0 HBB value: 15 DDR4 UBWC3.0 HBB value: 14 Change-Id: Ia33befb5eb9694fe7eded7b0bed662c0c406c6e9 Signed-off-by: Priyanka Gujjula --- msm/vidc/msm_vidc_platform.c | 590 +++++++++++++++++++++++++++++++++-- 1 file changed, 564 insertions(+), 26 deletions(-) diff --git a/msm/vidc/msm_vidc_platform.c b/msm/vidc/msm_vidc_platform.c index be9fad4f1300..583a63a5e16c 100644 --- a/msm/vidc/msm_vidc_platform.c +++ b/msm/vidc/msm_vidc_platform.c @@ -88,6 +88,15 @@ static struct msm_vidc_codec_data holi_codec_data[] = { CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 440, 440), }; +static struct msm_vidc_codec_data yupik_codec_data[] = { + CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 25, 675, 320), + CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 25, 675, 320), + CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 25, 200, 200), + CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 25, 200, 200), + CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 25, 200, 200), + CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 60, 200, 200), +}; + #define ENC HAL_VIDEO_DOMAIN_ENCODER #define DEC HAL_VIDEO_DOMAIN_DECODER #define H264 HAL_VIDEO_CODEC_H264 @@ -429,6 +438,229 @@ static struct msm_vidc_codec_capability lahaina_capabilities[] = { V4L2_MPEG_VIDEO_HEVC_LEVEL_5}, }; +static struct msm_vidc_codec_capability yupik_capabilities_v0[] = { + /* {cap_type, domains, codecs, min, max, step_size, default_value,} */ + /* Decode spec */ + {CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 5760, 1, 1920}, + {CAP_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 5760, 1, 1080}, + /* (5760 * 2880) / 256 */ + {CAP_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 64800, 1, 8160}, + /* ((4096 * 2176) / 256) * 60 fps */ + {CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 36, 2088960, 1, 244800}, + {CAP_FRAMERATE, DEC, CODECS_ALL, 1, 480, 1, 30}, + + /* Encode spec */ + {CAP_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 2, 1920}, + {CAP_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 2, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160}, + /* ((4096 * 2176) / 256) * 30 fps */ + {CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 1044480, 1, 244800}, + {CAP_FRAMERATE, ENC, CODECS_ALL, 1, 240, 1, 30}, + + {CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 100000000, 1, 20000000}, + {CAP_CABAC_BITRATE, ENC, H264, 1, 100000000, 1, 20000000}, + {CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192}, + {CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192}, + {CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536}, + {CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536}, + {CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0}, + {CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0}, + {CAP_LTR_COUNT, ENC, H264|HEVC, 0, 2, 1, 0}, + /* ((1920 * 1088) / 256) * 30 fps */ + {CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL, + 0, 244800, 1, 244800}, + {CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10}, + {CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20}, + {CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20}, + {CAP_I_FRAME_QP, DEC, VP9, 0, 127, 1, 20}, + {CAP_P_FRAME_QP, DEC, VP9, 0, 127, 1, 40}, + {CAP_B_FRAME_QP, DEC, VP9, 0, 127, 1, 40}, + /* 10 slices */ + {CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10}, + {CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10}, + {CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1}, + + /* Mpeg2 decoder specific */ + {CAP_FRAME_WIDTH, DEC, MPEG2, 96, 1920, 1, 1920}, + {CAP_FRAME_HEIGHT, DEC, MPEG2, 96, 1920, 1, 1088}, + /* (1920 * 1088) / 256 */ + {CAP_MBS_PER_FRAME, DEC, MPEG2, 36, 8160, 1, 8160}, + /* ((1920 * 1088) / 256) * 30*/ + {CAP_MBS_PER_SECOND, DEC, MPEG2, 36, 244800, 1, 244800}, + {CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30}, + {CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000}, + + /* Vp9 specific */ + {CAP_FRAME_WIDTH, DEC, VP9, 96, 4096, 1, 1920}, + {CAP_FRAME_HEIGHT, DEC, VP9, 96, 4096, 1, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_MBS_PER_FRAME, DEC, VP9, 36, 34816, 1, 8160}, + /* ((4096 * 2176) / 256) * 60*/ + {CAP_MBS_PER_SECOND, DEC, VP9, 36, 2088960, 1, 244800}, + {CAP_FRAMERATE, DEC, VP9, 1, 60, 1, 60}, + {CAP_BITRATE, DEC, VP9, 1, 100000000, 1, 20000000}, + + /* Secure usecase specific */ + {CAP_SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920}, + {CAP_SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080}, + {CAP_SECURE_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 2, 1920}, + {CAP_SECURE_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 2, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_SECURE_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160}, + {CAP_SECURE_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160}, + {CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000}, + + /* Batch Mode Decode */ + {CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 36, 8160, 1, 8160}, + /* (1920 * 1088) / 256 */ + {CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 30, 1, 30}, + + /* Lossless encoding usecase specific */ + {CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 4096, 2, 1920}, + {CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 4096, 2, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 34816, 1, 8160}, + + /* All intra encoding usecase specific */ + {CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30}, + + /* Image specific */ + {CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 2, 512}, + {CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 2, 512}, + {CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16834, 2, 16834}, + {CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16834, 2, 16834}, + + /* Level for AVC and HEVC encoder specific. + * Default for levels is UNKNOWN value. But if we use unknown + * value here to set as default, max value needs to be set to + * unknown as well, which creates a problem of allowing client + * to set higher level than supported + */ + {CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0}, + {CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_4}, + + /* Level for AVC and HEVC decoder specific */ + {CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_5_2, 1, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0}, + {CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_4}, +}; + +static struct msm_vidc_codec_capability yupik_capabilities_v1[] = { + /* {cap_type, domains, codecs, min, max, step_size, default_value,} */ + {CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920}, + {CAP_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080}, + {CAP_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 2, 1920}, + {CAP_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 2, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160}, + {CAP_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160}, + /* ((4096 * 2176) / 256) * 30 fps */ + {CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 36, 1044480, 1, 244800}, + {CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 1044480, 1, 244800}, + {CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 240, 1, 30}, + {CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 100000000, 1, 20000000}, + {CAP_CABAC_BITRATE, ENC, H264, 1, 100000000, 1, 20000000}, + {CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192}, + {CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192}, + {CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536}, + {CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536}, + {CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0}, + {CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0}, + {CAP_LTR_COUNT, ENC, H264|HEVC, 0, 2, 1, 0}, + /* ((1920 * 1088) / 256) * 30 fps */ + {CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL, + 0, 244800, 1, 244800}, + {CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10}, + {CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20}, + {CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20}, + {CAP_I_FRAME_QP, DEC, VP9, 0, 127, 1, 20}, + {CAP_P_FRAME_QP, DEC, VP9, 0, 127, 1, 40}, + {CAP_B_FRAME_QP, DEC, VP9, 0, 127, 1, 40}, + /* 10 slices */ + {CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10}, + {CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10}, + {CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1}, + + /* Mpeg2 decoder specific */ + {CAP_FRAME_WIDTH, DEC, MPEG2, 96, 1920, 1, 1920}, + {CAP_FRAME_HEIGHT, DEC, MPEG2, 96, 1920, 1, 1088}, + /* (1920 * 1088) / 256 */ + {CAP_MBS_PER_FRAME, DEC, MPEG2, 36, 8160, 1, 8160}, + /* ((1920 * 1088) / 256) * 30*/ + {CAP_MBS_PER_SECOND, DEC, MPEG2, 36, 244800, 1, 244800}, + {CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30}, + {CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000}, + + /* Vp9 specific */ + {CAP_FRAME_WIDTH, DEC, VP9, 96, 4096, 1, 1920}, + {CAP_FRAME_HEIGHT, DEC, VP9, 96, 4096, 1, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_MBS_PER_FRAME, DEC, VP9, 36, 34816, 1, 8160}, + /* ((4096 * 2176) / 256) * 30*/ + {CAP_MBS_PER_SECOND, DEC, VP9, 36, 1044480, 1, 244800}, + {CAP_FRAMERATE, DEC, VP9, 1, 60, 1, 60}, + {CAP_BITRATE, DEC, VP9, 1, 100000000, 1, 20000000}, + + /* Secure usecase specific */ + {CAP_SECURE_FRAME_WIDTH, DEC, CODECS_ALL, 96, 4096, 1, 1920}, + {CAP_SECURE_FRAME_HEIGHT, DEC, CODECS_ALL, 96, 4096, 1, 1080}, + {CAP_SECURE_FRAME_WIDTH, ENC, CODECS_ALL, 128, 4096, 1, 1920}, + {CAP_SECURE_FRAME_HEIGHT, ENC, CODECS_ALL, 128, 4096, 1, 1080}, + /* (4096 * 2176) / 256 */ + {CAP_SECURE_MBS_PER_FRAME, DEC, CODECS_ALL, 36, 34816, 1, 8160}, + {CAP_SECURE_MBS_PER_FRAME, ENC, CODECS_ALL, 64, 34816, 1, 8160}, + {CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000}, + + /* Batch Mode Decode */ + {CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 36, 8160, 1, 8160}, + /* (1920 * 1088) / 256 */ + {CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 30, 1, 30}, + + /* Lossless encoding usecase specific */ + {CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 4096, 2, 1920}, + {CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 4096, 2, 1080}, + /* (4096 * 2176)/ 256 */ + {CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 34816, 1, 8160}, + + /* All intra encoding usecase specific */ + {CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30}, + + /* Image specific */ + {CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 2, 512}, + {CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 2, 512}, + {CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16834, 2, 16834}, + {CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16834, 2, 16834}, + + /* Level for AVC and HEVC encoder specific. + * Default for levels is UNKNOWN value. But if we use unknown + * value here to set as default, max value needs to be set to + * unknown as well, which creates a problem of allowing client + * to set higher level than supported + */ + {CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0}, + {CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_4}, + + /* Level for AVC and HEVC decoder specific */ + {CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0}, + {CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1, + V4L2_MPEG_VIDEO_HEVC_LEVEL_4}, +}; + static struct msm_vidc_codec_capability shima_capabilities_v0[] = { /* {cap_type, domains, codecs, min, max, step_size, default_value,} */ {CAP_FRAME_WIDTH, DEC, CODECS_ALL, 96, 8192, 1, 1920}, @@ -785,6 +1017,10 @@ static u32 vpe_csc_custom_limit_coeff[HAL_MAX_LIMIT_COEFFS] = { 16, 235, 16, 240, 16, 240 }; +struct allowed_clock_rates_table yupik_clock_data_v1[] = { + {133330000}, {240000000}, {335000000}, {380000000} +}; + struct allowed_clock_rates_table shima_clock_data_v0[] = { {240000000}, {338000000}, {366000000}, {444000000} }; @@ -934,6 +1170,262 @@ static struct msm_vidc_common_data lahaina_common_data[] = { }, }; +static struct msm_vidc_common_data yupik_common_data_v0[] = { + { + .key = "qcom,never-unload-fw", + .value = 1, + }, + { + .key = "qcom,fw-unload-delay", + .value = 1000, + }, + { + .key = "qcom,sw-power-collapse", + .value = 1, + }, + { + .key = "qcom,domain-attr-non-fatal-faults", + .value = 1, + }, + { + .key = "qcom,max-secure-instances", + .value = 3, + }, + { + .key = "qcom,max-hw-load", + .value = 2088960, + /* ((4096x2176)/256)@60 + * 4k@30 decode + 1080p@30 encode + */ + }, + { + .key = "qcom,max-image-load", + .value = 1048576, /* ((16384x16384)/256)@1fps */ + }, + { + .key = "qcom,max-mbpf", + .value = 139264, /* ((4096x2176)/256) x 4 */ + }, + { + .key = "qcom,max-hq-mbs-per-frame", + .value = 8160, /* ((1920x1088)/256) */ + }, + { + .key = "qcom,max-hq-mbs-per-sec", + .value = 244800, /* ((1920x1088)/256)@30fps */ + }, + { + .key = "qcom,max-b-frame-mbs-per-frame", + .value = 8160, /* ((1920x1088)/256) */ + }, + { + .key = "qcom,max-b-frame-mbs-per-sec", + .value = 489600, /* ((1920x1088)/256) MBs@60fps */ + }, + { + .key = "qcom,power-collapse-delay", + .value = 1500, + }, + { + .key = "qcom,hw-resp-timeout", + .value = 1000, + }, + { + .key = "qcom,debug-timeout", + .value = 0, + }, + { + .key = "qcom,decode-batching", + .value = 1, + }, + { + .key = "qcom,batch-timeout", + .value = 200, + }, + { + .key = "qcom,dcvs", + .value = 1, + }, + { + .key = "qcom,fw-cycles", + .value = 436000, + }, + { + .key = "qcom,fw-vpp-cycles", + .value = 166667, + }, + { + .key = "qcom,avsync-window-size", + .value = 40, + }, + { + .key = "qcom,prefetch_non_pix_buf_count", + .value = 1, + }, + { + .key = "qcom,prefetch_non_pix_buf_size", + /* + * Internal buffer size is calculated for secure decode session + * of resolution 4k (4096x2160) + * Internal buf size = calculate_scratch_size() + + * calculate_scratch1_size() + calculate_persist1_size() + * Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure + * decoder sessions + */ + .value = 209715200, + }, + { + .key = "qcom,prefetch_pix_buf_count", + .value = 18, + }, + { + .key = "qcom,prefetch_pix_buf_size", + /* + * Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC + */ + .value = 13434880, + }, + { + .key = "qcom,ubwc_stats_in_fbd", + .value = 0, + }, + { + .key = "qcom,vpp_delay_supported", + .value = 0, + }, + { + .key = "qcom,enc_auto_dynamic_fps", + .value = 0, + }, +}; + +static struct msm_vidc_common_data yupik_common_data_v1[] = { + { + .key = "qcom,never-unload-fw", + .value = 1, + }, + { + .key = "qcom,fw-unload-delay", + .value = 1000, + }, + { + .key = "qcom,sw-power-collapse", + .value = 1, + }, + { + .key = "qcom,domain-attr-non-fatal-faults", + .value = 1, + }, + { + .key = "qcom,max-secure-instances", + .value = 3, + }, + { + .key = "qcom,max-hw-load", + .value = 1224000, + /* UHD@30 decode + 1080p@30 encode */ + }, + { + .key = "qcom,max-image-load", + .value = 1048576, /* ((16384x16384)/256)@1fps */ + }, + { + .key = "qcom,max-mbpf", + .value = 139264, /* ((4096x2176)/256) x 4 */ + }, + { + .key = "qcom,max-hq-mbs-per-frame", + .value = 8160, /* ((1920x1088)/256) */ + }, + { + .key = "qcom,max-hq-mbs-per-sec", + .value = 244800, /* ((1920x1088)/256)@30fps */ + }, + { + .key = "qcom,max-b-frame-mbs-per-frame", + .value = 8160, /* ((1920x1088)/256) */ + }, + { + .key = "qcom,max-b-frame-mbs-per-sec", + .value = 489600, /* ((1920x1088)/256) MBs@60fps */ + }, + { + .key = "qcom,power-collapse-delay", + .value = 1500, + }, + { + .key = "qcom,hw-resp-timeout", + .value = 1000, + }, + { + .key = "qcom,debug-timeout", + .value = 0, + }, + { + .key = "qcom,decode-batching", + .value = 1, + }, + { + .key = "qcom,batch-timeout", + .value = 200, + }, + { + .key = "qcom,dcvs", + .value = 1, + }, + { + .key = "qcom,fw-cycles", + .value = 436000, + }, + { + .key = "qcom,fw-vpp-cycles", + .value = 166667, + }, + { + .key = "qcom,avsync-window-size", + .value = 40, + }, + { + .key = "qcom,prefetch_non_pix_buf_count", + .value = 1, + }, + { + .key = "qcom,prefetch_non_pix_buf_size", + /* + * Internal buffer size is calculated for secure decode session + * of resolution 4k (4096x2160) + * Internal buf size = calculate_scratch_size() + + * calculate_scratch1_size() + calculate_persist1_size() + * Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure + * decoder sessions + */ + .value = 209715200, + }, + { + .key = "qcom,prefetch_pix_buf_count", + .value = 18, + }, + { + .key = "qcom,prefetch_pix_buf_size", + /* + * Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC + */ + .value = 13434880, + }, + { + .key = "qcom,ubwc_stats_in_fbd", + .value = 0, + }, + { + .key = "qcom,vpp_delay_supported", + .value = 0, + }, + { + .key = "qcom,enc_auto_dynamic_fps", + .value = 0, + }, +}; + static struct msm_vidc_common_data bengal_common_data_v0[] = { { .key = "qcom,never-unload-fw", @@ -1479,6 +1971,11 @@ static struct msm_vidc_common_data holi_common_data[] = { }, }; +static struct msm_vidc_efuse_data yupik_efuse_data[] = { + /* IRIS_4K60_FMAX_LIMIT_EFUSE - max 4K@60 */ + EFUSE_ENTRY(0x007801E8, 4, 0x00004000, 0x0E, SKU_VERSION), +}; + static struct msm_vidc_efuse_data shima_efuse_data[] = { /* IRIS_4K60_FMAX_LIMIT_EFUSE - max 4K@60 */ EFUSE_ENTRY(0x007801E0, 4, 0x00200000, 0x15, SKU_VERSION), @@ -1491,6 +1988,11 @@ static struct msm_vidc_ubwc_config_data lahaina_ubwc_data[] = { UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0), }; +/* Default UBWC config for LPDDR5 */ +static struct msm_vidc_ubwc_config_data yupik_ubwc_data[] = { + UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 15, 0, 0), +}; + /* Default UBWC config for LPDDR5 */ static struct msm_vidc_ubwc_config_data shima_ubwc_data[] = { UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 15, 0, 0), @@ -1536,6 +2038,30 @@ static struct msm_vidc_platform_data lahaina_data = { .vpss_caps_count = ARRAY_SIZE(vpss_capabilities), }; +static struct msm_vidc_platform_data yupik_data = { + .codec_data = yupik_codec_data, + .codec_data_length = ARRAY_SIZE(yupik_codec_data), + .clock_data = NULL, + .clock_data_length = 0, + .common_data = yupik_common_data_v0, + .common_data_length = ARRAY_SIZE(yupik_common_data_v0), + .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, + .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, + .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, + .efuse_data = yupik_efuse_data, + .efuse_data_length = ARRAY_SIZE(yupik_efuse_data), + .sku_version = 0, + .vpu_ver = VPU_VERSION_IRIS2_1, + .num_vpp_pipes = 0x1, + .ubwc_config = yupik_ubwc_data, + .codecs = default_codecs, + .codecs_count = ARRAY_SIZE(default_codecs), + .codec_caps = yupik_capabilities_v0, + .codec_caps_count = ARRAY_SIZE(yupik_capabilities_v0), + .vpss_caps = vpss_capabilities, + .vpss_caps_count = ARRAY_SIZE(vpss_capabilities), +}; + static struct msm_vidc_platform_data bengal_data = { .codec_data = bengal_codec_data, .codec_data_length = ARRAY_SIZE(bengal_codec_data), @@ -1625,6 +2151,10 @@ static const struct of_device_id msm_vidc_dt_device[] = { .compatible = "qcom,holi-vidc", .data = &holi_data, }, + { + .compatible = "qcom,yupik-vidc", + .data = &yupik_data, + }, {}, }; @@ -1686,11 +2216,30 @@ static int msm_vidc_read_rank( return 0; } +static inline void msm_vidc_ddr_ubwc_config( + struct msm_vidc_platform_data *driver_data, u32 hbb_override_val) +{ + uint32_t ddr_type = DDR_TYPE_LPDDR5; + + ddr_type = of_fdt_get_ddrtype(); + if (ddr_type == -ENOENT) { + d_vpr_e("Failed to get ddr type, use LPDDR5\n"); + } + + if (driver_data->ubwc_config && + (ddr_type == DDR_TYPE_LPDDR4 || + ddr_type == DDR_TYPE_LPDDR4X)) + driver_data->ubwc_config->highest_bank_bit = hbb_override_val; + + d_vpr_h("DDR Type 0x%x hbb 0x%x\n", + ddr_type, driver_data->ubwc_config ? + driver_data->ubwc_config->highest_bank_bit : -1); +} + void *vidc_get_drv_data(struct device *dev) { struct msm_vidc_platform_data *driver_data = NULL; const struct of_device_id *match; - uint32_t ddr_type = DDR_TYPE_LPDDR5; int rc = 0; if (!IS_ENABLED(CONFIG_OF) || !dev->of_node) { @@ -1713,19 +2262,7 @@ void *vidc_get_drv_data(struct device *dev) goto exit; if (!strcmp(match->compatible, "qcom,lahaina-vidc")) { - ddr_type = of_fdt_get_ddrtype(); - if (ddr_type == -ENOENT) { - d_vpr_e("Failed to get ddr type, use LPDDR5\n"); - } - - if (driver_data->ubwc_config && - (ddr_type == DDR_TYPE_LPDDR4 || - ddr_type == DDR_TYPE_LPDDR4X)) - driver_data->ubwc_config->highest_bank_bit = 0xf; - - d_vpr_h("DDR Type 0x%x hbb 0x%x\n", - ddr_type, driver_data->ubwc_config ? - driver_data->ubwc_config->highest_bank_bit : -1); + msm_vidc_ddr_ubwc_config(driver_data, 0xf); } else if (!strcmp(match->compatible, "qcom,bengal-vidc")) { rc = msm_vidc_read_rank(driver_data, dev); if (rc) { @@ -1761,19 +2298,20 @@ void *vidc_get_drv_data(struct device *dev) driver_data->codec_caps_count = ARRAY_SIZE(shima_capabilities_v2); } - ddr_type = of_fdt_get_ddrtype(); - if (ddr_type == -ENOENT) { - d_vpr_e("Failed to get ddr type, use LPDDR5\n"); + msm_vidc_ddr_ubwc_config(driver_data, 0xe); + } else if (!strcmp(match->compatible, "qcom,yupik-vidc")) { + if (driver_data->sku_version == SKU_VERSION_1) { + driver_data->clock_data = yupik_clock_data_v1; + driver_data->clock_data_length = + ARRAY_SIZE(yupik_clock_data_v1);; + driver_data->common_data = yupik_common_data_v1; + driver_data->common_data_length = + ARRAY_SIZE(yupik_common_data_v1); + driver_data->codec_caps = yupik_capabilities_v1; + driver_data->codec_caps_count = + ARRAY_SIZE(yupik_capabilities_v1); } - - if (driver_data->ubwc_config && - (ddr_type == DDR_TYPE_LPDDR4 || - ddr_type == DDR_TYPE_LPDDR4X)) - driver_data->ubwc_config->highest_bank_bit = 0xe; - - d_vpr_h("DDR Type 0x%x hbb 0x%x\n", - ddr_type, driver_data->ubwc_config ? - driver_data->ubwc_config->highest_bank_bit : -1); + msm_vidc_ddr_ubwc_config(driver_data, 0xe); } exit: return driver_data; From 83b35fa14a82065dc9d67dd2ee58535563e783f5 Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Wed, 6 Jan 2021 11:19:04 +0530 Subject: [PATCH 2/4] msm: vidc: Update offset for yupik FMAX fuse Update offset from 14 to 21 for yupik fmax fuse. IRIS_PLL_FMAX: Limits the enc/dec capability to 4k@30. Change-Id: I60dc110e85a5aa7d4427424b401b759e49d345ac Signed-off-by: Priyanka Gujjula --- msm/vidc/msm_vidc_platform.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/msm/vidc/msm_vidc_platform.c b/msm/vidc/msm_vidc_platform.c index 583a63a5e16c..75259c34c5c0 100644 --- a/msm/vidc/msm_vidc_platform.c +++ b/msm/vidc/msm_vidc_platform.c @@ -1972,8 +1972,8 @@ static struct msm_vidc_common_data holi_common_data[] = { }; static struct msm_vidc_efuse_data yupik_efuse_data[] = { - /* IRIS_4K60_FMAX_LIMIT_EFUSE - max 4K@60 */ - EFUSE_ENTRY(0x007801E8, 4, 0x00004000, 0x0E, SKU_VERSION), + /* IRIS_PLL_FMAX - max 4K@30 */ + EFUSE_ENTRY(0x007801E8, 4, 0x00200000, 0x15, SKU_VERSION), }; static struct msm_vidc_efuse_data shima_efuse_data[] = { From 76cae5a345ced8afef26ffd435b44c44befcf279 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 7 Jan 2021 12:44:31 +0530 Subject: [PATCH 3/4] msm: vidc: Amend DCVS handling for encoder For DCVS, there are mainly 3 buffer count watermarks i.e low, normal, high. When the buffers held with firmware goes above high or below low, DCVS changes the clock to high or low respectively. At this state, to come back to normal clock, it needs the buffer in firmware to come back to normal count. For cases, when DCVS decides to decrease the clock, the clock remains lowered till the buffer count in firmware is back to normal. During this phase, the clock remains low and impacts performance. Since encode usecase always desire more clock, keeping low for them leads to measurable impact. The fix considers a case for encoder to bring back to normal clock when the buffer count is more than low watermark. CRs-Fixed: 2845570 Change-Id: I426a17f7b16db544ea09ec072c77e95198634c84 Signed-off-by: Vikash Garodia --- msm/vidc/msm_vidc_clocks.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/msm/vidc/msm_vidc_clocks.c b/msm/vidc/msm_vidc_clocks.c index aa8825caa007..271178a1e1a0 100644 --- a/msm/vidc/msm_vidc_clocks.c +++ b/msm/vidc/msm_vidc_clocks.c @@ -525,7 +525,10 @@ static int msm_dcvs_scale_clocks(struct msm_vidc_inst *inst, } else if ((dcvs->dcvs_flags & MSM_VIDC_DCVS_DECR && bufs_with_fw >= dcvs->nom_threshold) || (dcvs->dcvs_flags & MSM_VIDC_DCVS_INCR && - bufs_with_fw <= dcvs->nom_threshold)) + bufs_with_fw <= dcvs->nom_threshold) || + (inst->session_type == MSM_VIDC_ENCODER && + dcvs->dcvs_flags & MSM_VIDC_DCVS_DECR && + bufs_with_fw >= dcvs->min_threshold)) dcvs->dcvs_flags = 0; s_vpr_p(inst->sid, "DCVS: bufs_with_fw %d Th[%d %d %d] Flag %#x\n", From 5bf127b94f38f9ec179e767f84716845365e719a Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Fri, 8 Jan 2021 13:40:50 +0530 Subject: [PATCH 4/4] msm: vidc: Increase 10-bit enc o/p buffer size for <=360p Increase 10-bit enc bistream buffer size for <=360p. For 8-bit YUV size : w x h x 1.5 For 10-bit YUV size : w x h x 1.5 x 2 Change-Id: I6fddcf960b8b06fe6edbe4b8262374303a045530 Signed-off-by: Priyanka Gujjula --- msm/vidc/msm_vidc_buffer_calculations.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/msm/vidc/msm_vidc_buffer_calculations.c b/msm/vidc/msm_vidc_buffer_calculations.c index 3052801b9589..2db5696313c7 100644 --- a/msm/vidc/msm_vidc_buffer_calculations.c +++ b/msm/vidc/msm_vidc_buffer_calculations.c @@ -1005,7 +1005,7 @@ u32 msm_vidc_calculate_enc_output_frame_size(struct msm_vidc_inst *inst) goto calc_done; if (mbs_per_frame <= NUM_MBS_360P) - goto calc_done; /* Default frame_size = YUVsize * 2 */ + (void)frame_size; /* Default frame_size = YUVsize * 2 */ else if (mbs_per_frame <= NUM_MBS_4k) frame_size = frame_size >> 2; else