clk: si5351: Fix clkout rate computation.

Rate was incorrectly computed because we read from wrong divider register.

Signed-off-by: Marek Belisko <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Cc: [email protected]
This commit is contained in:
Marek Belisko 2013-05-03 07:53:22 +02:00 • committed by Mike Turquette
commit 67e1e2268e

View file

@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
unsigned char reg;
unsigned char rdiv;
if (hwdata->num > 5)
if (hwdata->num <= 5)
reg = si5351_msynth_params_address(hwdata->num) + 2;
else
reg = SI5351_CLK6_7_OUTPUT_DIVIDER;